Classic Timing Analyzer report for double_selector_8b
Mon Mar 07 11:22:47 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Parallel Compilation
  5. tpd
  6. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                               ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 14.785 ns   ; b6   ; Y6 ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;    ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2C8Q208C8        ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                   ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                   ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                          ; Near End           ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2-4 processors         ;   0.0%      ;
+----------------------------+-------------+


+---------------------------------------------------------+
; tpd                                                     ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A   ; None              ; 14.785 ns       ; b6   ; Y6 ;
; N/A   ; None              ; 14.732 ns       ; b5   ; Y5 ;
; N/A   ; None              ; 14.623 ns       ; b0   ; Y0 ;
; N/A   ; None              ; 14.408 ns       ; b4   ; Y4 ;
; N/A   ; None              ; 14.174 ns       ; b1   ; Y1 ;
; N/A   ; None              ; 14.155 ns       ; b7   ; Y7 ;
; N/A   ; None              ; 14.070 ns       ; b2   ; Y2 ;
; N/A   ; None              ; 14.007 ns       ; b3   ; Y3 ;
; N/A   ; None              ; 13.636 ns       ; a0   ; Y0 ;
; N/A   ; None              ; 13.392 ns       ; a6   ; Y6 ;
; N/A   ; None              ; 13.327 ns       ; a5   ; Y5 ;
; N/A   ; None              ; 13.142 ns       ; a3   ; Y3 ;
; N/A   ; None              ; 13.132 ns       ; a2   ; Y2 ;
; N/A   ; None              ; 12.984 ns       ; a7   ; Y7 ;
; N/A   ; None              ; 12.917 ns       ; a4   ; Y4 ;
; N/A   ; None              ; 12.863 ns       ; a1   ; Y1 ;
; N/A   ; None              ; 10.926 ns       ; AY   ; Y6 ;
; N/A   ; None              ; 10.880 ns       ; AY   ; Y5 ;
; N/A   ; None              ; 10.740 ns       ; BY   ; Y6 ;
; N/A   ; None              ; 10.694 ns       ; BY   ; Y5 ;
; N/A   ; None              ; 10.632 ns       ; BY   ; Y3 ;
; N/A   ; None              ; 10.630 ns       ; BY   ; Y2 ;
; N/A   ; None              ; 10.571 ns       ; BY   ; Y1 ;
; N/A   ; None              ; 10.534 ns       ; AY   ; Y7 ;
; N/A   ; None              ; 10.528 ns       ; AY   ; Y3 ;
; N/A   ; None              ; 10.506 ns       ; AY   ; Y2 ;
; N/A   ; None              ; 10.484 ns       ; AY   ; Y0 ;
; N/A   ; None              ; 10.463 ns       ; AY   ; Y4 ;
; N/A   ; None              ; 10.459 ns       ; AY   ; Y1 ;
; N/A   ; None              ; 10.346 ns       ; BY   ; Y7 ;
; N/A   ; None              ; 10.288 ns       ; BY   ; Y4 ;
; N/A   ; None              ; 10.285 ns       ; BY   ; Y0 ;
+-------+-------------------+-----------------+------+----+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
    Info: Processing started: Mon Mar 07 11:22:47 2022
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b --timing_analysis_only
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Info: Longest tpd from source pin "b6" to destination pin "Y6" is 14.785 ns
    Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_75; Fanout = 1; PIN Node = 'b6'
    Info: 2: + IC(6.679 ns) + CELL(0.651 ns) = 8.304 ns; Loc. = LCCOMB_X25_Y2_N12; Fanout = 1; COMB Node = 'inst7'
    Info: 3: + IC(3.365 ns) + CELL(3.116 ns) = 14.785 ns; Loc. = PIN_149; Fanout = 0; PIN Node = 'Y6'
    Info: Total cell delay = 4.741 ns ( 32.07 % )
    Info: Total interconnect delay = 10.044 ns ( 67.93 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 212 megabytes
    Info: Processing ended: Mon Mar 07 11:22:47 2022
    Info: Elapsed time: 00:00:00
    Info: Total CPU time (on all processors): 00:00:00


