Classic Timing Analyzer report for data_selector
Sat Mar 05 20:41:36 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Parallel Compilation
  5. tpd
  6. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                               ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 12.694 ns   ; b5   ; Y5 ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;    ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2C8Q208C8        ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                   ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                   ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                          ; Near End           ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2-4 processors         ;   0.0%      ;
+----------------------------+-------------+


+---------------------------------------------------------+
; tpd                                                     ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A   ; None              ; 12.694 ns       ; b5   ; Y5 ;
; N/A   ; None              ; 12.565 ns       ; BY   ; Y7 ;
; N/A   ; None              ; 12.553 ns       ; BY   ; Y0 ;
; N/A   ; None              ; 12.543 ns       ; a7   ; Y7 ;
; N/A   ; None              ; 12.522 ns       ; AY   ; Y0 ;
; N/A   ; None              ; 12.477 ns       ; BY   ; Y5 ;
; N/A   ; None              ; 12.469 ns       ; a4   ; Y4 ;
; N/A   ; None              ; 12.451 ns       ; AY   ; Y5 ;
; N/A   ; None              ; 12.396 ns       ; b3   ; Y3 ;
; N/A   ; None              ; 12.360 ns       ; a0   ; Y0 ;
; N/A   ; None              ; 12.298 ns       ; b0   ; Y0 ;
; N/A   ; None              ; 12.293 ns       ; AY   ; Y7 ;
; N/A   ; None              ; 12.239 ns       ; a5   ; Y5 ;
; N/A   ; None              ; 12.214 ns       ; b4   ; Y4 ;
; N/A   ; None              ; 12.099 ns       ; AY   ; Y1 ;
; N/A   ; None              ; 12.083 ns       ; b7   ; Y7 ;
; N/A   ; None              ; 12.036 ns       ; BY   ; Y2 ;
; N/A   ; None              ; 12.035 ns       ; BY   ; Y4 ;
; N/A   ; None              ; 12.030 ns       ; BY   ; Y3 ;
; N/A   ; None              ; 12.014 ns       ; AY   ; Y4 ;
; N/A   ; None              ; 12.010 ns       ; AY   ; Y2 ;
; N/A   ; None              ; 11.998 ns       ; AY   ; Y3 ;
; N/A   ; None              ; 11.941 ns       ; b6   ; Y6 ;
; N/A   ; None              ; 11.823 ns       ; a1   ; Y1 ;
; N/A   ; None              ; 11.701 ns       ; BY   ; Y1 ;
; N/A   ; None              ; 11.697 ns       ; BY   ; Y6 ;
; N/A   ; None              ; 11.670 ns       ; AY   ; Y6 ;
; N/A   ; None              ; 11.480 ns       ; a6   ; Y6 ;
; N/A   ; None              ; 6.818 ns        ; a3   ; Y3 ;
; N/A   ; None              ; 6.817 ns        ; b2   ; Y2 ;
; N/A   ; None              ; 6.775 ns        ; a2   ; Y2 ;
; N/A   ; None              ; 6.079 ns        ; b1   ; Y1 ;
+-------+-------------------+-----------------+------+----+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
    Info: Processing started: Sat Mar 05 20:41:36 2022
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off data_selector -c data_selector --timing_analysis_only
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Info: Longest tpd from source pin "b5" to destination pin "Y5" is 12.694 ns
    Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_45; Fanout = 1; PIN Node = 'b5'
    Info: 2: + IC(6.147 ns) + CELL(0.624 ns) = 7.766 ns; Loc. = LCCOMB_X1_Y9_N26; Fanout = 1; COMB Node = 'inst6'
    Info: 3: + IC(1.642 ns) + CELL(3.286 ns) = 12.694 ns; Loc. = PIN_208; Fanout = 0; PIN Node = 'Y5'
    Info: Total cell delay = 4.905 ns ( 38.64 % )
    Info: Total interconnect delay = 7.789 ns ( 61.36 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 212 megabytes
    Info: Processing ended: Sat Mar 05 20:41:36 2022
    Info: Elapsed time: 00:00:00
    Info: Total CPU time (on all processors): 00:00:00


