Classic Timing Analyzer report for 38_decoder
Tue Mar 08 15:12:42 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Parallel Compilation
  5. tpd
  6. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                               ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 13.172 ns   ; I2   ; Y4 ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;    ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2C8Q208C8        ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                   ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                   ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                          ; Near End           ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2-4 processors         ;   0.0%      ;
+----------------------------+-------------+


+---------------------------------------------------------+
; tpd                                                     ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A   ; None              ; 13.172 ns       ; I2   ; Y4 ;
; N/A   ; None              ; 13.161 ns       ; I2   ; Y6 ;
; N/A   ; None              ; 13.141 ns       ; I2   ; Y5 ;
; N/A   ; None              ; 13.095 ns       ; I2   ; Y7 ;
; N/A   ; None              ; 13.009 ns       ; I2   ; Y3 ;
; N/A   ; None              ; 12.995 ns       ; I2   ; Y0 ;
; N/A   ; None              ; 12.674 ns       ; I1   ; Y6 ;
; N/A   ; None              ; 12.658 ns       ; I0   ; Y5 ;
; N/A   ; None              ; 12.658 ns       ; I1   ; Y4 ;
; N/A   ; None              ; 12.648 ns       ; I1   ; Y3 ;
; N/A   ; None              ; 12.647 ns       ; I2   ; Y1 ;
; N/A   ; None              ; 12.636 ns       ; I0   ; Y3 ;
; N/A   ; None              ; 12.623 ns       ; I1   ; Y7 ;
; N/A   ; None              ; 12.619 ns       ; I0   ; Y7 ;
; N/A   ; None              ; 12.614 ns       ; I0   ; Y4 ;
; N/A   ; None              ; 12.612 ns       ; I1   ; Y5 ;
; N/A   ; None              ; 12.594 ns       ; I0   ; Y6 ;
; N/A   ; None              ; 12.580 ns       ; I1   ; Y0 ;
; N/A   ; None              ; 12.560 ns       ; I2   ; Y2 ;
; N/A   ; None              ; 12.535 ns       ; I0   ; Y0 ;
; N/A   ; None              ; 12.270 ns       ; I0   ; Y1 ;
; N/A   ; None              ; 12.241 ns       ; I1   ; Y1 ;
; N/A   ; None              ; 12.201 ns       ; I1   ; Y2 ;
; N/A   ; None              ; 12.104 ns       ; I0   ; Y2 ;
+-------+-------------------+-----------------+------+----+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
    Info: Processing started: Tue Mar 08 15:12:42 2022
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder --timing_analysis_only
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Info: Longest tpd from source pin "I2" to destination pin "Y4" is 13.172 ns
    Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_81; Fanout = 8; PIN Node = 'I2'
    Info: 2: + IC(7.387 ns) + CELL(0.651 ns) = 9.012 ns; Loc. = LCCOMB_X33_Y13_N2; Fanout = 1; COMB Node = 'inst10~5'
    Info: 3: + IC(1.054 ns) + CELL(3.106 ns) = 13.172 ns; Loc. = PIN_146; Fanout = 0; PIN Node = 'Y4'
    Info: Total cell delay = 4.731 ns ( 35.92 % )
    Info: Total interconnect delay = 8.441 ns ( 64.08 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 212 megabytes
    Info: Processing ended: Tue Mar 08 15:12:42 2022
    Info: Elapsed time: 00:00:00
    Info: Total CPU time (on all processors): 00:00:00


