Classic Timing Analyzer report for shifter_8b
Tue Mar 08 15:17:19 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Parallel Compilation
  5. tpd
  6. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                               ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 15.661 ns   ; LM   ; Y5 ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;    ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2C8Q208C8        ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                   ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                   ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                          ; Near End           ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2-4 processors         ;   0.0%      ;
+----------------------------+-------------+


+---------------------------------------------------------+
; tpd                                                     ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A   ; None              ; 15.661 ns       ; LM   ; Y5 ;
; N/A   ; None              ; 15.651 ns       ; DM   ; Y5 ;
; N/A   ; None              ; 15.610 ns       ; LM   ; Y3 ;
; N/A   ; None              ; 15.606 ns       ; DM   ; Y3 ;
; N/A   ; None              ; 15.297 ns       ; DM   ; Y1 ;
; N/A   ; None              ; 15.251 ns       ; DM   ; Y6 ;
; N/A   ; None              ; 15.189 ns       ; LM   ; Y4 ;
; N/A   ; None              ; 15.186 ns       ; DM   ; Y4 ;
; N/A   ; None              ; 14.807 ns       ; LM   ; Y1 ;
; N/A   ; None              ; 14.796 ns       ; DM   ; Y2 ;
; N/A   ; None              ; 14.768 ns       ; LM   ; Y6 ;
; N/A   ; None              ; 14.737 ns       ; RM   ; Y6 ;
; N/A   ; None              ; 14.714 ns       ; RM   ; Y5 ;
; N/A   ; None              ; 14.662 ns       ; RM   ; Y3 ;
; N/A   ; None              ; 14.654 ns       ; RM   ; Y4 ;
; N/A   ; None              ; 14.633 ns       ; DM   ; Y7 ;
; N/A   ; None              ; 14.630 ns       ; LM   ; Y7 ;
; N/A   ; None              ; 14.582 ns       ; A0   ; Y1 ;
; N/A   ; None              ; 14.517 ns       ; A3   ; Y3 ;
; N/A   ; None              ; 14.509 ns       ; A1   ; Y1 ;
; N/A   ; None              ; 14.410 ns       ; A2   ; Y3 ;
; N/A   ; None              ; 14.345 ns       ; RM   ; Y1 ;
; N/A   ; None              ; 14.328 ns       ; LM   ; Y2 ;
; N/A   ; None              ; 14.284 ns       ; RM   ; Y2 ;
; N/A   ; None              ; 14.272 ns       ; RM   ; Y0 ;
; N/A   ; None              ; 14.232 ns       ; A5   ; Y5 ;
; N/A   ; None              ; 14.231 ns       ; DM   ; Y0 ;
; N/A   ; None              ; 14.156 ns       ; A6   ; Y6 ;
; N/A   ; None              ; 14.096 ns       ; A3   ; Y4 ;
; N/A   ; None              ; 14.080 ns       ; A2   ; Y2 ;
; N/A   ; None              ; 14.078 ns       ; A4   ; Y5 ;
; N/A   ; None              ; 13.824 ns       ; A5   ; Y6 ;
; N/A   ; None              ; 13.706 ns       ; A1   ; Y2 ;
; N/A   ; None              ; 13.606 ns       ; A4   ; Y4 ;
; N/A   ; None              ; 13.309 ns       ; A0   ; Y0 ;
; N/A   ; None              ; 13.231 ns       ; A7   ; Y6 ;
; N/A   ; None              ; 13.196 ns       ; A5   ; Y4 ;
; N/A   ; None              ; 13.181 ns       ; A7   ; Y7 ;
; N/A   ; None              ; 13.141 ns       ; A1   ; Y0 ;
; N/A   ; None              ; 13.137 ns       ; A3   ; Y2 ;
; N/A   ; None              ; 13.099 ns       ; A2   ; Y1 ;
; N/A   ; None              ; 13.098 ns       ; A6   ; Y5 ;
; N/A   ; None              ; 13.064 ns       ; A6   ; Y7 ;
; N/A   ; None              ; 13.036 ns       ; A4   ; Y3 ;
+-------+-------------------+-----------------+------+----+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
    Info: Processing started: Tue Mar 08 15:17:19 2022
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Info: Longest tpd from source pin "LM" to destination pin "Y5" is 15.661 ns
    Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_69; Fanout = 7; PIN Node = 'LM'
    Info: 2: + IC(6.879 ns) + CELL(0.650 ns) = 8.523 ns; Loc. = LCCOMB_X26_Y1_N18; Fanout = 1; COMB Node = 'triple_selector_8b:inst|inst23~0'
    Info: 3: + IC(0.370 ns) + CELL(0.624 ns) = 9.517 ns; Loc. = LCCOMB_X26_Y1_N20; Fanout = 1; COMB Node = 'triple_selector_8b:inst|inst23'
    Info: 4: + IC(3.028 ns) + CELL(3.116 ns) = 15.661 ns; Loc. = PIN_147; Fanout = 0; PIN Node = 'Y5'
    Info: Total cell delay = 5.384 ns ( 34.38 % )
    Info: Total interconnect delay = 10.277 ns ( 65.62 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 212 megabytes
    Info: Processing ended: Tue Mar 08 15:17:19 2022
    Info: Elapsed time: 00:00:00
    Info: Total CPU time (on all processors): 00:00:00


