Classic Timing Analyzer report for shifter_8b
Mon Mar 07 11:15:57 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Parallel Compilation
  5. tpd
  6. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                               ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 13.413 ns   ; A6   ; Y7 ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;    ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2C8Q208C8        ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                   ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                   ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                          ; Near End           ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 6           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2-6 processors         ;   0.0%      ;
+----------------------------+-------------+


+---------------------------------------------------------+
; tpd                                                     ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A   ; None              ; 13.413 ns       ; A6   ; Y7 ;
; N/A   ; None              ; 13.008 ns       ; A7   ; Y7 ;
; N/A   ; None              ; 12.993 ns       ; DM   ; Y3 ;
; N/A   ; None              ; 12.852 ns       ; A1   ; Y2 ;
; N/A   ; None              ; 12.792 ns       ; A6   ; Y6 ;
; N/A   ; None              ; 12.781 ns       ; DM   ; Y4 ;
; N/A   ; None              ; 12.737 ns       ; DM   ; Y5 ;
; N/A   ; None              ; 12.544 ns       ; LM   ; Y3 ;
; N/A   ; None              ; 12.476 ns       ; DM   ; Y7 ;
; N/A   ; None              ; 12.455 ns       ; A1   ; Y0 ;
; N/A   ; None              ; 12.428 ns       ; A1   ; Y1 ;
; N/A   ; None              ; 12.419 ns       ; A0   ; Y0 ;
; N/A   ; None              ; 12.394 ns       ; A0   ; Y1 ;
; N/A   ; None              ; 12.311 ns       ; DM   ; Y2 ;
; N/A   ; None              ; 12.292 ns       ; LM   ; Y5 ;
; N/A   ; None              ; 12.248 ns       ; A6   ; Y5 ;
; N/A   ; None              ; 12.029 ns       ; LM   ; Y7 ;
; N/A   ; None              ; 11.943 ns       ; RM   ; Y3 ;
; N/A   ; None              ; 11.911 ns       ; DM   ; Y0 ;
; N/A   ; None              ; 11.884 ns       ; DM   ; Y1 ;
; N/A   ; None              ; 11.864 ns       ; LM   ; Y2 ;
; N/A   ; None              ; 11.859 ns       ; LM   ; Y4 ;
; N/A   ; None              ; 11.855 ns       ; DM   ; Y6 ;
; N/A   ; None              ; 11.827 ns       ; A7   ; Y6 ;
; N/A   ; None              ; 11.433 ns       ; LM   ; Y1 ;
; N/A   ; None              ; 11.432 ns       ; RM   ; Y0 ;
; N/A   ; None              ; 11.404 ns       ; LM   ; Y6 ;
; N/A   ; None              ; 11.258 ns       ; RM   ; Y2 ;
; N/A   ; None              ; 11.254 ns       ; RM   ; Y5 ;
; N/A   ; None              ; 11.249 ns       ; RM   ; Y4 ;
; N/A   ; None              ; 10.823 ns       ; RM   ; Y1 ;
; N/A   ; None              ; 10.804 ns       ; RM   ; Y6 ;
; N/A   ; None              ; 8.265 ns        ; A2   ; Y3 ;
; N/A   ; None              ; 8.237 ns        ; A3   ; Y3 ;
; N/A   ; None              ; 8.014 ns        ; A5   ; Y5 ;
; N/A   ; None              ; 7.942 ns        ; A4   ; Y5 ;
; N/A   ; None              ; 7.635 ns        ; A4   ; Y3 ;
; N/A   ; None              ; 7.583 ns        ; A2   ; Y2 ;
; N/A   ; None              ; 7.551 ns        ; A3   ; Y4 ;
; N/A   ; None              ; 7.136 ns        ; A5   ; Y6 ;
; N/A   ; None              ; 7.085 ns        ; A4   ; Y4 ;
; N/A   ; None              ; 7.014 ns        ; A5   ; Y4 ;
; N/A   ; None              ; 6.993 ns        ; A3   ; Y2 ;
; N/A   ; None              ; 6.585 ns        ; A2   ; Y1 ;
+-------+-------------------+-----------------+------+----+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
    Info: Processing started: Mon Mar 07 11:15:57 2022
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only
Info: Parallel compilation is enabled and will use 4 of the 6 processors detected
Info: Longest tpd from source pin "A6" to destination pin "Y7" is 13.413 ns
    Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 3; PIN Node = 'A6'
    Info: 2: + IC(6.895 ns) + CELL(0.624 ns) = 8.513 ns; Loc. = LCCOMB_X1_Y5_N10; Fanout = 1; COMB Node = 'triple_selector_8b:inst|inst31'
    Info: 3: + IC(1.604 ns) + CELL(3.296 ns) = 13.413 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'Y7'
    Info: Total cell delay = 4.914 ns ( 36.64 % )
    Info: Total interconnect delay = 8.499 ns ( 63.36 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 191 megabytes
    Info: Processing ended: Mon Mar 07 11:15:58 2022
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:00


