From e32d73391a8a8719cc0c5c4c771794c6bef17e04 Mon Sep 17 00:00:00 2001 From: juzeon <812312770@qq.com> Date: Mon, 7 Mar 2022 08:54:33 +0800 Subject: [PATCH 1/7] =?UTF-8?q?add=208=E4=BD=8D=E5=8A=A0=E6=B3=95=E5=99=A8?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- adder/adder.asm.rpt | 129 + adder/adder.bdf | 2906 +++++++++++++++++ adder/adder.bsf | 211 ++ adder/adder.done | 1 + adder/adder.fit.rpt | 1040 ++++++ adder/adder.fit.smsg | 6 + adder/adder.fit.summary | 16 + adder/adder.flow.rpt | 120 + adder/adder.map.rpt | 240 ++ adder/adder.map.summary | 14 + adder/adder.pin | 278 ++ adder/adder.pof | Bin 0 -> 524488 bytes adder/adder.qpf | 30 + adder/adder.qsf | 53 + adder/adder.sof | Bin 0 -> 240789 bytes adder/adder.tan.rpt | 228 ++ adder/adder.tan.summary | 26 + adder/db/adder.(0).cnf.cdb | Bin 0 -> 1879 bytes adder/db/adder.(0).cnf.hdb | Bin 0 -> 1270 bytes adder/db/adder.(1).cnf.cdb | Bin 0 -> 519 bytes adder/db/adder.(1).cnf.hdb | Bin 0 -> 465 bytes adder/db/adder.(2).cnf.cdb | Bin 0 -> 521 bytes adder/db/adder.(2).cnf.hdb | Bin 0 -> 464 bytes adder/db/adder.asm.qmsg | 7 + adder/db/adder.asm_labs.ddb | Bin 0 -> 4100 bytes adder/db/adder.cbx.xml | 5 + adder/db/adder.cmp.bpm | Bin 0 -> 673 bytes adder/db/adder.cmp.cdb | Bin 0 -> 6286 bytes adder/db/adder.cmp.ecobp | Bin 0 -> 28 bytes adder/db/adder.cmp.hdb | Bin 0 -> 8241 bytes adder/db/adder.cmp.kpt | 10 + adder/db/adder.cmp.logdb | 1 + adder/db/adder.cmp.rdb | Bin 0 -> 17244 bytes adder/db/adder.cmp.tdb | Bin 0 -> 5803 bytes adder/db/adder.cmp0.ddb | Bin 0 -> 59317 bytes adder/db/adder.cmp2.ddb | Bin 0 -> 42886 bytes adder/db/adder.cmp_merge.kpt | 10 + adder/db/adder.db_info | 3 + adder/db/adder.eco.cdb | Bin 0 -> 175 bytes adder/db/adder.fit.qmsg | 39 + adder/db/adder.hier_info | 286 ++ adder/db/adder.hif | 120 + adder/db/adder.lpc.html | 18 + adder/db/adder.lpc.rdb | Bin 0 -> 399 bytes adder/db/adder.lpc.txt | 5 + adder/db/adder.map.bpm | Bin 0 -> 656 bytes adder/db/adder.map.cdb | Bin 0 -> 2132 bytes adder/db/adder.map.ecobp | Bin 0 -> 28 bytes adder/db/adder.map.hdb | Bin 0 -> 7920 bytes adder/db/adder.map.kpt | 10 + adder/db/adder.map.logdb | 1 + adder/db/adder.map.qmsg | 11 + adder/db/adder.map_bb.cdb | Bin 0 -> 743 bytes adder/db/adder.map_bb.hdb | Bin 0 -> 7177 bytes adder/db/adder.map_bb.logdb | 1 + adder/db/adder.pre_map.cdb | Bin 0 -> 2341 bytes adder/db/adder.pre_map.hdb | Bin 0 -> 7950 bytes adder/db/adder.rtlv.hdb | Bin 0 -> 7966 bytes adder/db/adder.rtlv_sg.cdb | Bin 0 -> 1992 bytes adder/db/adder.rtlv_sg_swap.cdb | Bin 0 -> 851 bytes adder/db/adder.sgdiff.cdb | Bin 0 -> 1696 bytes adder/db/adder.sgdiff.hdb | Bin 0 -> 7979 bytes adder/db/adder.sld_design_entry.sci | Bin 0 -> 168 bytes adder/db/adder.sld_design_entry_dsc.sci | Bin 0 -> 168 bytes adder/db/adder.syn_hier_info | 0 adder/db/adder.tan.qmsg | 6 + adder/db/adder.tis_db_list.ddb | Bin 0 -> 188 bytes adder/incremental_db/README | 11 + .../adder.root_partition.cmp.atm | Bin 0 -> 8870 bytes .../adder.root_partition.cmp.dfp | Bin 0 -> 33 bytes .../adder.root_partition.cmp.hdbx | Bin 0 -> 3314 bytes .../adder.root_partition.cmp.kpt | 10 + .../adder.root_partition.cmp.logdb | 1 + .../adder.root_partition.cmp.rcf | Bin 0 -> 1605 bytes .../adder.root_partition.map.atm | Bin 0 -> 6004 bytes .../adder.root_partition.map.dpi | Bin 0 -> 1311 bytes .../adder.root_partition.map.hdbx | Bin 0 -> 3202 bytes .../adder.root_partition.map.kpt | 10 + 78 files changed, 5863 insertions(+) create mode 100644 adder/adder.asm.rpt create mode 100644 adder/adder.bdf create mode 100644 adder/adder.bsf create mode 100644 adder/adder.done create mode 100644 adder/adder.fit.rpt create mode 100644 adder/adder.fit.smsg create mode 100644 adder/adder.fit.summary create mode 100644 adder/adder.flow.rpt create mode 100644 adder/adder.map.rpt create mode 100644 adder/adder.map.summary create mode 100644 adder/adder.pin create mode 100644 adder/adder.pof create mode 100644 adder/adder.qpf create mode 100644 adder/adder.qsf create mode 100644 adder/adder.sof create mode 100644 adder/adder.tan.rpt create mode 100644 adder/adder.tan.summary create mode 100644 adder/db/adder.(0).cnf.cdb create mode 100644 adder/db/adder.(0).cnf.hdb create mode 100644 adder/db/adder.(1).cnf.cdb create mode 100644 adder/db/adder.(1).cnf.hdb create mode 100644 adder/db/adder.(2).cnf.cdb create mode 100644 adder/db/adder.(2).cnf.hdb create mode 100644 adder/db/adder.asm.qmsg create mode 100644 adder/db/adder.asm_labs.ddb create mode 100644 adder/db/adder.cbx.xml create mode 100644 adder/db/adder.cmp.bpm create mode 100644 adder/db/adder.cmp.cdb create mode 100644 adder/db/adder.cmp.ecobp create mode 100644 adder/db/adder.cmp.hdb create mode 100644 adder/db/adder.cmp.kpt create mode 100644 adder/db/adder.cmp.logdb create mode 100644 adder/db/adder.cmp.rdb create mode 100644 adder/db/adder.cmp.tdb create mode 100644 adder/db/adder.cmp0.ddb create mode 100644 adder/db/adder.cmp2.ddb create mode 100644 adder/db/adder.cmp_merge.kpt create mode 100644 adder/db/adder.db_info create mode 100644 adder/db/adder.eco.cdb create mode 100644 adder/db/adder.fit.qmsg create mode 100644 adder/db/adder.hier_info create mode 100644 adder/db/adder.hif create mode 100644 adder/db/adder.lpc.html create mode 100644 adder/db/adder.lpc.rdb create mode 100644 adder/db/adder.lpc.txt create mode 100644 adder/db/adder.map.bpm create mode 100644 adder/db/adder.map.cdb create mode 100644 adder/db/adder.map.ecobp create mode 100644 adder/db/adder.map.hdb create mode 100644 adder/db/adder.map.kpt create mode 100644 adder/db/adder.map.logdb create mode 100644 adder/db/adder.map.qmsg create mode 100644 adder/db/adder.map_bb.cdb create mode 100644 adder/db/adder.map_bb.hdb create mode 100644 adder/db/adder.map_bb.logdb create mode 100644 adder/db/adder.pre_map.cdb create mode 100644 adder/db/adder.pre_map.hdb create mode 100644 adder/db/adder.rtlv.hdb create mode 100644 adder/db/adder.rtlv_sg.cdb create mode 100644 adder/db/adder.rtlv_sg_swap.cdb create mode 100644 adder/db/adder.sgdiff.cdb create mode 100644 adder/db/adder.sgdiff.hdb create mode 100644 adder/db/adder.sld_design_entry.sci create mode 100644 adder/db/adder.sld_design_entry_dsc.sci create mode 100644 adder/db/adder.syn_hier_info create mode 100644 adder/db/adder.tan.qmsg create mode 100644 adder/db/adder.tis_db_list.ddb create mode 100644 adder/incremental_db/README create mode 100644 adder/incremental_db/compiled_partitions/adder.root_partition.cmp.atm create mode 100644 adder/incremental_db/compiled_partitions/adder.root_partition.cmp.dfp create mode 100644 adder/incremental_db/compiled_partitions/adder.root_partition.cmp.hdbx create mode 100644 adder/incremental_db/compiled_partitions/adder.root_partition.cmp.kpt create mode 100644 adder/incremental_db/compiled_partitions/adder.root_partition.cmp.logdb create mode 100644 adder/incremental_db/compiled_partitions/adder.root_partition.cmp.rcf create mode 100644 adder/incremental_db/compiled_partitions/adder.root_partition.map.atm create mode 100644 adder/incremental_db/compiled_partitions/adder.root_partition.map.dpi create mode 100644 adder/incremental_db/compiled_partitions/adder.root_partition.map.hdbx create mode 100644 adder/incremental_db/compiled_partitions/adder.root_partition.map.kpt diff --git a/adder/adder.asm.rpt b/adder/adder.asm.rpt new file mode 100644 index 0000000..dc2646b --- /dev/null +++ b/adder/adder.asm.rpt @@ -0,0 +1,129 @@ +Assembler report for adder +Mon Mar 07 08:49:26 2022 +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: D:/projects/quartus/adder/adder.sof + 6. Assembler Device Options: D:/projects/quartus/adder/adder.pof + 7. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Mon Mar 07 08:49:26 2022 ; +; Revision Name ; adder ; +; Top-level Entity Name ; adder ; +; Family ; Cyclone II ; +; Device ; EP2C8Q208C8 ; ++-----------------------+---------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Option ; Setting ; Default Value ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Use smart compilation ; Off ; Off ; +; Generate compressed bitstreams ; On ; On ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; Auto user code ; Off ; Off ; +; Use configuration device ; On ; On ; +; Configuration device ; Auto ; Auto ; +; Configuration device auto user code ; Off ; Off ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File start address ; 0 ; 0 ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Release clears before tri-states ; Off ; Off ; +; Auto-restart configuration after error ; On ; On ; +; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; ++-----------------------------------------------------------------------------+----------+---------------+ + + ++-------------------------------------+ +; Assembler Generated Files ; ++-------------------------------------+ +; File Name ; ++-------------------------------------+ +; D:/projects/quartus/adder/adder.sof ; +; D:/projects/quartus/adder/adder.pof ; ++-------------------------------------+ + + ++---------------------------------------------------------------+ +; Assembler Device Options: D:/projects/quartus/adder/adder.sof ; ++----------------+----------------------------------------------+ +; Option ; Setting ; ++----------------+----------------------------------------------+ +; Device ; EP2C8Q208C8 ; +; JTAG usercode ; 0xFFFFFFFF ; +; Checksum ; 0x000C8655 ; ++----------------+----------------------------------------------+ + + ++---------------------------------------------------------------+ +; Assembler Device Options: D:/projects/quartus/adder/adder.pof ; ++--------------------+------------------------------------------+ +; Option ; Setting ; ++--------------------+------------------------------------------+ +; Device ; EPCS4 ; +; JTAG usercode ; 0x00000000 ; +; Checksum ; 0x06F061B0 ; +; Compression Ratio ; 3 ; ++--------------------+------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II Assembler + Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + Info: Processing started: Mon Mar 07 08:49:25 2022 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off adder -c adder +Info: Writing out detailed assembly data for power analysis +Info: Assembler is generating device programming files +Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled +Info: Quartus II Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 242 megabytes + Info: Processing ended: Mon Mar 07 08:49:26 2022 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:00 + + diff --git a/adder/adder.bdf b/adder/adder.bdf new file mode 100644 index 0000000..6d769db --- /dev/null +++ b/adder/adder.bdf @@ -0,0 +1,2906 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. 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File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. 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Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Input Pins + 11. Output Pins + 12. I/O Bank Usage + 13. All Package Pins + 14. Output Pin Default Load For Reported TCO + 15. Fitter Resource Utilization by Entity + 16. Delay Chain Summary + 17. Pad To Core Delay Chain Fanout + 18. Non-Global High Fan-Out Signals + 19. Interconnect Usage Summary + 20. LAB Logic Elements + 21. LAB Signals Sourced + 22. LAB Signals Sourced Out + 23. LAB Distinct Inputs + 24. Fitter Device Options + 25. Operating Settings and Conditions + 26. Estimated Delay Added for Hold Timing + 27. Advanced Data - General + 28. Advanced Data - Placement Preparation + 29. Advanced Data - Placement + 30. Advanced Data - Routing + 31. Fitter Messages + 32. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+----------------------------------------------+ +; Fitter Status ; Successful - Mon Mar 07 08:49:24 2022 ; +; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; +; Revision Name ; adder ; +; Top-level Entity Name ; adder ; +; Family ; Cyclone II ; +; Device ; EP2C8Q208C8 ; +; Timing Models ; Final ; +; Total logic elements ; 21 / 8,256 ( < 1 % ) ; +; Total combinational functions ; 21 / 8,256 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 26 / 138 ( 19 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 165,888 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; +; Total PLLs ; 0 / 2 ( 0 % ) ; ++------------------------------------+----------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Device ; EP2C8Q208C8 ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Use TimeQuest Timing Analyzer ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Always Enable Input Buffers ; Off ; Off ; +; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; +; Optimize Multi-Corner Timing ; Off ; Off ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; On ; On ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Global Memory Control Signals ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Merge PLLs ; On ; On ; +; Ignore PLL Mode When Merging PLLs ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Stop After Congestion Map Generation ; Off ; Off ; +; Save Intermediate Fitting Results ; Off ; Off ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; 1 processor ; 100.0% ; +; 2-4 processors ; < 0.1% ; ++----------------------------+-------------+ + + ++----------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++-------------------------+--------------------+ +; Type ; Value ; ++-------------------------+--------------------+ +; Placement ; ; +; -- Requested ; 0 / 47 ( 0.00 % ) ; +; -- Achieved ; 0 / 47 ( 0.00 % ) ; +; ; ; +; Routing (by Connection) ; ; +; -- Requested ; 0 / 0 ( 0.00 % ) ; +; -- Achieved ; 0 / 0 ( 0.00 % ) ; ++-------------------------+--------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ + + ++--------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++----------------+---------+-------------------+-------------------------+-------------------+ +; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; ++----------------+---------+-------------------+-------------------------+-------------------+ +; Top ; 47 ; 0 ; N/A ; Source File ; ++----------------+---------+-------------------+-------------------------+-------------------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in D:/projects/quartus/adder/adder.pin. + + ++--------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+----------------------+ +; Resource ; Usage ; ++---------------------------------------------+----------------------+ +; Total logic elements ; 21 / 8,256 ( < 1 % ) ; +; -- Combinational with no register ; 21 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 0 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 9 ; +; -- 3 input functions ; 9 ; +; -- <=2 input functions ; 3 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 21 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 0 / 8,646 ( 0 % ) ; +; -- Dedicated logic registers ; 0 / 8,256 ( 0 % ) ; +; -- I/O registers ; 0 / 390 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 2 / 516 ( < 1 % ) ; +; User inserted logic elements ; 0 ; +; Virtual pins ; 0 ; +; I/O pins ; 26 / 138 ( 19 % ) ; +; -- Clock pins ; 2 / 4 ( 50 % ) ; +; Global signals ; 0 ; +; M4Ks ; 0 / 36 ( 0 % ) ; +; Total block memory bits ; 0 / 165,888 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 165,888 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; +; PLLs ; 0 / 2 ( 0 % ) ; +; Global clocks ; 0 / 8 ( 0 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Maximum fan-out node ; 7400:inst8|4~0 ; +; Maximum fan-out ; 4 ; +; Highest non-global fan-out signal ; 7400:inst8|4~0 ; +; Highest non-global fan-out ; 4 ; +; Total fan-out ; 78 ; +; Average fan-out ; 1.56 ; ++---------------------------------------------+----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ; ++------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; A0 ; 24 ; 1 ; 0 ; 9 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; A1 ; 57 ; 4 ; 1 ; 0 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; A2 ; 23 ; 1 ; 0 ; 9 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; A3 ; 40 ; 1 ; 0 ; 5 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; A4 ; 41 ; 1 ; 0 ; 4 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; A5 ; 150 ; 3 ; 34 ; 16 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; A6 ; 13 ; 1 ; 0 ; 16 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; A7 ; 5 ; 1 ; 0 ; 17 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; B0 ; 28 ; 1 ; 0 ; 9 ; 3 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; B1 ; 60 ; 4 ; 3 ; 0 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; B2 ; 30 ; 1 ; 0 ; 8 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; B3 ; 39 ; 1 ; 0 ; 5 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; B4 ; 207 ; 2 ; 1 ; 19 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; B5 ; 14 ; 1 ; 0 ; 14 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; B6 ; 10 ; 1 ; 0 ; 17 ; 3 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; B7 ; 11 ; 1 ; 0 ; 16 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; CI ; 27 ; 1 ; 0 ; 9 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; ++------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; ++------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ +; CO ; 58 ; 4 ; 1 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; S0 ; 102 ; 4 ; 32 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; S1 ; 34 ; 1 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; S2 ; 118 ; 3 ; 34 ; 7 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; S3 ; 31 ; 1 ; 0 ; 8 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; S4 ; 37 ; 1 ; 0 ; 6 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; S5 ; 35 ; 1 ; 0 ; 7 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; S6 ; 12 ; 1 ; 0 ; 16 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; S7 ; 6 ; 1 ; 0 ; 17 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; ++------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1 ; 21 / 32 ( 66 % ) ; 3.3V ; -- ; +; 2 ; 1 / 35 ( 3 % ) ; 3.3V ; -- ; +; 3 ; 3 / 35 ( 9 % ) ; 3.3V ; -- ; +; 4 ; 4 / 36 ( 11 % ) ; 3.3V ; -- ; ++----------+------------------+---------------+--------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; 1 ; 0 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; 2 ; 1 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; 3 ; 2 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 4 ; 3 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 5 ; 4 ; 1 ; A7 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 6 ; 5 ; 1 ; S7 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 8 ; 6 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 10 ; 7 ; 1 ; B6 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 11 ; 8 ; 1 ; B7 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 12 ; 9 ; 1 ; S6 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 13 ; 10 ; 1 ; A6 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 14 ; 18 ; 1 ; B5 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 15 ; 19 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; 18 ; 22 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; 19 ; 23 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; 20 ; 24 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ; +; 21 ; 25 ; 1 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ; +; 22 ; 26 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; 23 ; 27 ; 1 ; A2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 24 ; 28 ; 1 ; A0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 26 ; 29 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; 27 ; 30 ; 1 ; CI ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 28 ; 31 ; 1 ; B0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 30 ; 32 ; 1 ; B2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 31 ; 33 ; 1 ; S3 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 33 ; 35 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 34 ; 36 ; 1 ; S1 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 35 ; 37 ; 1 ; S5 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 37 ; 39 ; 1 ; S4 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 39 ; 43 ; 1 ; B3 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 40 ; 44 ; 1 ; A3 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 41 ; 45 ; 1 ; A4 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 42 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 43 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 44 ; 49 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 45 ; 50 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 46 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 47 ; 52 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 48 ; 53 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 49 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 50 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; 51 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 52 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; 53 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 54 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; 55 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 56 ; 54 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 57 ; 55 ; 4 ; A1 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 58 ; 56 ; 4 ; CO ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 59 ; 57 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 60 ; 58 ; 4 ; B1 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 61 ; 59 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 63 ; 60 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 64 ; 61 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 67 ; 69 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 68 ; 70 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 69 ; 71 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 70 ; 74 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 71 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 72 ; 75 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 74 ; 76 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 75 ; 77 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 76 ; 78 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 77 ; 79 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 80 ; 82 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 81 ; 83 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 82 ; 84 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 83 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 84 ; 85 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 85 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 86 ; 86 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 87 ; 87 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 88 ; 88 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 89 ; 89 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 90 ; 90 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 91 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 92 ; 91 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 94 ; 92 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 95 ; 93 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 96 ; 94 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 97 ; 95 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 98 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 99 ; 96 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 100 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 101 ; 97 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 102 ; 98 ; 4 ; S0 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 103 ; 99 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 104 ; 100 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 105 ; 101 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 106 ; 102 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 107 ; 105 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 108 ; 106 ; 3 ; ~LVDS54p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 109 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 110 ; 107 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 111 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 112 ; 108 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 113 ; 109 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 114 ; 110 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 115 ; 112 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 116 ; 113 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 117 ; 114 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 118 ; 117 ; 3 ; S2 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 119 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 120 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 121 ; 121 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; 122 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 123 ; 122 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; 124 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 125 ; 123 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; 126 ; 124 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; 127 ; 125 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 128 ; 126 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 129 ; 127 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 130 ; 128 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 131 ; 129 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 132 ; 130 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 133 ; 131 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 134 ; 132 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 135 ; 133 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 136 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 137 ; 134 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 138 ; 135 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 139 ; 136 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 141 ; 137 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 142 ; 138 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 143 ; 141 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 144 ; 142 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 145 ; 143 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 146 ; 149 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 147 ; 150 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 148 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 149 ; 151 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 150 ; 152 ; 3 ; A5 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 151 ; 153 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 152 ; 154 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 153 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 154 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; 155 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 156 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; 157 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 158 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; 159 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 160 ; 155 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 161 ; 156 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 162 ; 157 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 163 ; 158 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 164 ; 159 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 165 ; 160 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 166 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 167 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 168 ; 161 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 169 ; 162 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 170 ; 163 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 171 ; 164 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 172 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 173 ; 165 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 174 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 175 ; 168 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 176 ; 169 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 177 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 178 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 179 ; 173 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 180 ; 174 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 181 ; 175 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 182 ; 176 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 183 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 184 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 185 ; 180 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 186 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 187 ; 181 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 188 ; 182 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 189 ; 183 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 190 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 191 ; 184 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 192 ; 185 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 193 ; 186 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 194 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 195 ; 187 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 196 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 197 ; 191 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 198 ; 192 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 199 ; 195 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 200 ; 196 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 201 ; 197 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 202 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 203 ; 198 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 204 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 205 ; 199 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 206 ; 200 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 207 ; 201 ; 2 ; B4 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 208 ; 202 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-------------------------------------------------------------------------------+ +; Output Pin Default Load For Reported TCO ; ++----------------------------------+-------+------------------------------------+ +; I/O Standard ; Load ; Termination Resistance ; ++----------------------------------+-------+------------------------------------+ +; 3.3-V LVTTL ; 0 pF ; Not Available ; +; 3.3-V LVCMOS ; 0 pF ; Not Available ; +; 2.5 V ; 0 pF ; Not Available ; +; 1.8 V ; 0 pF ; Not Available ; +; 1.5 V ; 0 pF ; Not Available ; +; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ; +; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ; +; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ; +; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ; +; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ; +; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ; +; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ; +; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ; +; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ; +; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ; +; LVDS ; 0 pF ; 100 Ohm (Differential) ; +; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ; +; RSDS ; 0 pF ; 100 Ohm (Differential) ; +; Simple RSDS ; 0 pF ; Not Available ; +; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ; ++----------------------------------+-------+------------------------------------+ +Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ +; |adder ; 21 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 26 ; 0 ; 21 (0) ; 0 (0) ; 0 (0) ; |adder ; work ; +; |7400:inst13| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |adder|7400:inst13 ; work ; +; |7400:inst18| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder|7400:inst18 ; work ; +; |7400:inst23| ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 0 (0) ; |adder|7400:inst23 ; work ; +; |7400:inst28| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder|7400:inst28 ; work ; +; |7400:inst33| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |adder|7400:inst33 ; work ; +; |7400:inst38| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder|7400:inst38 ; work ; +; |7400:inst3| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |adder|7400:inst3 ; work ; +; |7400:inst8| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder|7400:inst8 ; work ; +; |7486:inst10| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder|7486:inst10 ; work ; +; |7486:inst15| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder|7486:inst15 ; work ; +; |7486:inst20| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder|7486:inst20 ; work ; +; |7486:inst25| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder|7486:inst25 ; work ; +; |7486:inst30| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder|7486:inst30 ; work ; +; |7486:inst35| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder|7486:inst35 ; work ; +; |7486:inst40| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder|7486:inst40 ; work ; +; |7486:inst5| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder|7486:inst5 ; work ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++------+----------+---------------+---------------+-----------------------+-----+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; ++------+----------+---------------+---------------+-----------------------+-----+ +; CO ; Output ; -- ; -- ; -- ; -- ; +; S7 ; Output ; -- ; -- ; -- ; -- ; +; S0 ; Output ; -- ; -- ; -- ; -- ; +; S1 ; Output ; -- ; -- ; -- ; -- ; +; S2 ; Output ; -- ; -- ; -- ; -- ; +; S3 ; Output ; -- ; -- ; -- ; -- ; +; S4 ; Output ; -- ; -- ; -- ; -- ; +; S5 ; Output ; -- ; -- ; -- ; -- ; +; S6 ; Output ; -- ; -- ; -- ; -- ; +; A6 ; Input ; 6 ; 6 ; -- ; -- ; +; A3 ; Input ; 6 ; 6 ; -- ; -- ; +; B3 ; Input ; 6 ; 6 ; -- ; -- ; +; A4 ; Input ; 6 ; 6 ; -- ; -- ; +; A2 ; Input ; 0 ; 0 ; -- ; -- ; +; A0 ; Input ; 0 ; 0 ; -- ; -- ; +; CI ; Input ; 0 ; 0 ; -- ; -- ; +; B0 ; Input ; 0 ; 0 ; -- ; -- ; +; A1 ; Input ; 6 ; 6 ; -- ; -- ; +; B1 ; Input ; 6 ; 6 ; -- ; -- ; +; B2 ; Input ; 6 ; 6 ; -- ; -- ; +; B4 ; Input ; 6 ; 6 ; -- ; -- ; +; A5 ; Input ; 6 ; 6 ; -- ; -- ; +; B5 ; Input ; 6 ; 6 ; -- ; -- ; +; B6 ; Input ; 6 ; 6 ; -- ; -- ; +; A7 ; Input ; 6 ; 6 ; -- ; -- ; +; B7 ; Input ; 6 ; 6 ; -- ; -- ; ++------+----------+---------------+---------------+-----------------------+-----+ + + ++-------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++-------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++-------------------------+-------------------+---------+ +; A6 ; ; ; +; - 7400:inst33|4~0 ; 1 ; 6 ; +; - 7400:inst33|4~1 ; 1 ; 6 ; +; - 7486:inst35|4~0 ; 1 ; 6 ; +; A3 ; ; ; +; - 7400:inst23|4~8 ; 0 ; 6 ; +; - 7400:inst18|4~0 ; 0 ; 6 ; +; - 7486:inst20|4 ; 0 ; 6 ; +; B3 ; ; ; +; - 7400:inst23|4~8 ; 1 ; 6 ; +; - 7400:inst18|4~0 ; 1 ; 6 ; +; - 7486:inst20|4 ; 1 ; 6 ; +; A4 ; ; ; +; - 7400:inst23|4~8 ; 0 ; 6 ; +; - 7400:inst23|4~9 ; 0 ; 6 ; +; - 7486:inst25|4~0 ; 0 ; 6 ; +; A2 ; ; ; +; A0 ; ; ; +; CI ; ; ; +; B0 ; ; ; +; A1 ; ; ; +; - 7400:inst8|4~0 ; 0 ; 6 ; +; - 7486:inst10|4 ; 0 ; 6 ; +; B1 ; ; ; +; - 7400:inst8|4~0 ; 0 ; 6 ; +; - 7486:inst10|4 ; 0 ; 6 ; +; B2 ; ; ; +; - 7400:inst13|4~1 ; 1 ; 6 ; +; - 7486:inst15|4~0 ; 1 ; 6 ; +; - 7400:inst23|4~10 ; 1 ; 6 ; +; B4 ; ; ; +; - 7400:inst23|4~9 ; 0 ; 6 ; +; - 7486:inst25|4~0 ; 0 ; 6 ; +; A5 ; ; ; +; - 7400:inst28|4~0 ; 0 ; 6 ; +; - 7486:inst30|4 ; 0 ; 6 ; +; B5 ; ; ; +; - 7400:inst28|4~0 ; 1 ; 6 ; +; - 7486:inst30|4 ; 1 ; 6 ; +; B6 ; ; ; +; - 7400:inst33|4~1 ; 1 ; 6 ; +; - 7486:inst35|4~0 ; 1 ; 6 ; +; A7 ; ; ; +; - 7400:inst38|4~0 ; 0 ; 6 ; +; - 7486:inst40|4 ; 0 ; 6 ; +; B7 ; ; ; +; - 7400:inst38|4~0 ; 1 ; 6 ; +; - 7486:inst40|4 ; 1 ; 6 ; ++-------------------------+-------------------+---------+ + + ++---------------------------------+ +; Non-Global High Fan-Out Signals ; ++------------------+--------------+ +; Name ; Fan-Out ; ++------------------+--------------+ +; A2 ; 4 ; +; 7400:inst8|4~0 ; 4 ; +; B2 ; 3 ; +; CI ; 3 ; +; A0 ; 3 ; +; A4 ; 3 ; +; B3 ; 3 ; +; A3 ; 3 ; +; A6 ; 3 ; +; 7400:inst28|4~0 ; 3 ; +; B7 ; 2 ; +; A7 ; 2 ; +; B6 ; 2 ; +; B5 ; 2 ; +; A5 ; 2 ; +; B4 ; 2 ; +; B1 ; 2 ; +; A1 ; 2 ; +; B0 ; 2 ; +; 7400:inst33|4~1 ; 2 ; +; 7400:inst33|4~0 ; 2 ; +; 7400:inst23|4~9 ; 2 ; +; 7400:inst18|4~0 ; 2 ; +; 7400:inst23|4~8 ; 2 ; +; 7400:inst13|4~1 ; 2 ; +; 7400:inst13|4~0 ; 2 ; +; 7400:inst3|4~1 ; 2 ; +; 7400:inst3|4~0 ; 2 ; +; 7400:inst23|4~10 ; 1 ; +; 7486:inst35|4~0 ; 1 ; +; 7486:inst30|4 ; 1 ; +; 7486:inst25|4~0 ; 1 ; +; 7486:inst20|4 ; 1 ; +; 7486:inst15|4~0 ; 1 ; +; 7486:inst10|4 ; 1 ; +; 7486:inst5|4~0 ; 1 ; +; 7486:inst40|4 ; 1 ; +; 7400:inst38|4~0 ; 1 ; ++------------------+--------------+ + + ++----------------------------------------------------+ +; Interconnect Usage Summary ; ++----------------------------+-----------------------+ +; Interconnect Resource Type ; Usage ; ++----------------------------+-----------------------+ +; Block interconnects ; 29 / 26,052 ( < 1 % ) ; +; C16 interconnects ; 2 / 1,156 ( < 1 % ) ; +; C4 interconnects ; 31 / 17,952 ( < 1 % ) ; +; Direct links ; 2 / 26,052 ( < 1 % ) ; +; Global clocks ; 0 / 8 ( 0 % ) ; +; Local interconnects ; 10 / 8,256 ( < 1 % ) ; +; R24 interconnects ; 3 / 1,020 ( < 1 % ) ; +; R4 interconnects ; 18 / 22,440 ( < 1 % ) ; ++----------------------------+-----------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Logic Elements ; ++---------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 10.50) ; Number of LABs (Total = 2) ; ++---------------------------------------------+-----------------------------+ +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 1 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 10.50) ; Number of LABs (Total = 2) ; ++----------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 1 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 1 ; ++----------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 5.00) ; Number of LABs (Total = 2) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 1 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 9.00) ; Number of LABs (Total = 2) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 1 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------+ +; Fitter Device Options ; ++----------------------------------------------+--------------------------+ +; Option ; Setting ; ++----------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; nCEO ; As output driving ground ; +; ASDO,nCSO ; As input tri-stated ; +; Reserve all unused pins ; As output driving ground ; +; Base pin-out file on sameframe device ; Off ; ++----------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing ; ++-----------------+----------------------+-------------------+ +; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; ++-----------------+----------------------+-------------------+ + + ++----------------------------+ +; Advanced Data - General ; ++--------------------+-------+ +; Name ; Value ; ++--------------------+-------+ +; Status Code ; 0 ; +; Desired User Slack ; 0 ; +; Fit Attempts ; 1 ; ++--------------------+-------+ + + ++---------------------------------------------------------------------------------+ +; Advanced Data - Placement Preparation ; ++------------------------------------------------------------------+--------------+ +; Name ; Value ; ++------------------------------------------------------------------+--------------+ +; Auto Fit Point 1 - Fit Attempt 1 ; ff ; +; Mid Wire Use - Fit Attempt 1 ; 0 ; +; Mid Slack - Fit Attempt 1 ; 2147483639 ; +; Internal Atom Count - Fit Attempt 1 ; 22 ; +; LE/ALM Count - Fit Attempt 1 ; 22 ; +; LAB Count - Fit Attempt 1 ; 3 ; +; Outputs per Lab - Fit Attempt 1 ; 3.333 ; +; Inputs per LAB - Fit Attempt 1 ; 6.000 ; +; Global Inputs per LAB - Fit Attempt 1 ; 0.000 ; +; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:3 ; +; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:3 ; +; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:3 ; +; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:3 ; +; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:3 ; +; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:3 ; +; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:3 ; +; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:3 ; +; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:3 ; +; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:3 ; +; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:3 ; +; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:3 ; +; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;4:1;12:1 ; +; LEs in Chains - Fit Attempt 1 ; 0 ; +; LEs in Long Chains - Fit Attempt 1 ; 0 ; +; LABs with Chains - Fit Attempt 1 ; 0 ; +; LABs with Multiple Chains - Fit Attempt 1 ; 0 ; +; Time - Fit Attempt 1 ; 0 ; ++------------------------------------------------------------------+--------------+ + + ++-------------------------------------------------+ +; Advanced Data - Placement ; ++------------------------------------+------------+ +; Name ; Value ; ++------------------------------------+------------+ +; Auto Fit Point 2 - Fit Attempt 1 ; ff ; +; Auto Fit Point 5 - Fit Attempt 1 ; ff ; +; Mid Wire Use - Fit Attempt 1 ; 0 ; +; Mid Slack - Fit Attempt 1 ; 2147483639 ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Auto Fit Point 5 - Fit Attempt 1 ; ff ; +; Mid Wire Use - Fit Attempt 1 ; 0 ; +; Mid Slack - Fit Attempt 1 ; 2147483639 ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Late Wire Use - Fit Attempt 1 ; 0 ; +; Late Slack - Fit Attempt 1 ; 2147483639 ; +; Peak Regional Wire - Fit Attempt 1 ; 0.000 ; +; Auto Fit Point 7 - Fit Attempt 1 ; ff ; +; Time - Fit Attempt 1 ; 0 ; ++------------------------------------+------------+ + + ++--------------------------------------------------+ +; Advanced Data - Routing ; ++------------------------------------+-------------+ +; Name ; Value ; ++------------------------------------+-------------+ +; Early Slack - Fit Attempt 1 ; 2147483639 ; +; Early Wire Use - Fit Attempt 1 ; 0 ; +; Peak Regional Wire - Fit Attempt 1 ; 0 ; +; Mid Slack - Fit Attempt 1 ; 2147483639 ; +; Late Slack - Fit Attempt 1 ; -2147483648 ; +; Late Wire Use - Fit Attempt 1 ; 0 ; +; Time - Fit Attempt 1 ; 0 ; ++------------------------------------+-------------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Info: ******************************************************************* +Info: Running Quartus II Fitter + Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + Info: Processing started: Mon Mar 07 08:49:23 2022 +Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off adder -c adder +Info: Parallel compilation is enabled and will use 4 of the 4 processors detected +Info: Selected device EP2C8Q208C8 for design "adder" +Info: Low junction temperature is 0 degrees C +Info: High junction temperature is 85 degrees C +Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info: Device EP2C5Q208C8 is compatible + Info: Device EP2C5Q208I8 is compatible + Info: Device EP2C8Q208I8 is compatible +Info: Fitter converted 3 user pins into dedicated programming pins + Info: Pin ~ASDO~ is reserved at location 1 + Info: Pin ~nCSO~ is reserved at location 2 + Info: Pin ~LVDS54p/nCEO~ is reserved at location 108 +Warning: No exact pin location assignment(s) for 26 pins of 26 total pins + Info: Pin CO not assigned to an exact location on the device + Info: Pin S7 not assigned to an exact location on the device + Info: Pin S0 not assigned to an exact location on the device + Info: Pin S1 not assigned to an exact location on the device + Info: Pin S2 not assigned to an exact location on the device + Info: Pin S3 not assigned to an exact location on the device + Info: Pin S4 not assigned to an exact location on the device + Info: Pin S5 not assigned to an exact location on the device + Info: Pin S6 not assigned to an exact location on the device + Info: Pin A6 not assigned to an exact location on the device + Info: Pin A3 not assigned to an exact location on the device + Info: Pin B3 not assigned to an exact location on the device + Info: Pin A4 not assigned to an exact location on the device + Info: Pin A2 not assigned to an exact location on the device + Info: Pin A0 not assigned to an exact location on the device + Info: Pin CI not assigned to an exact location on the device + Info: Pin B0 not assigned to an exact location on the device + Info: Pin A1 not assigned to an exact location on the device + Info: Pin B1 not assigned to an exact location on the device + Info: Pin B2 not assigned to an exact location on the device + Info: Pin B4 not assigned to an exact location on the device + Info: Pin A5 not assigned to an exact location on the device + Info: Pin B5 not assigned to an exact location on the device + Info: Pin B6 not assigned to an exact location on the device + Info: Pin A7 not assigned to an exact location on the device + Info: Pin B7 not assigned to an exact location on the device +Info: Fitter is using the Classic Timing Analyzer +Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time. +Info: Starting register packing +Info: Finished register packing + Extra Info: No registers were packed into other blocks +Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info: Number of I/O pins in group: 26 (unused VREF, 3.3V VCCIO, 17 input, 9 output, 0 bidirectional) + Info: I/O standards used: 3.3-V LVTTL. +Info: I/O bank details before I/O pin placement + Info: Statistics of I/O banks + Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available + Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available + Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available + Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available +Info: Fitter preparation operations ending: elapsed time is 00:00:00 +Info: Fitter placement preparation operations beginning +Info: Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info: Fitter placement operations beginning +Info: Fitter placement was successful +Info: Fitter placement operations ending: elapsed time is 00:00:00 +Info: Fitter routing operations beginning +Info: Average interconnect usage is 0% of the available device resources + Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9 +Info: Fitter routing operations ending: elapsed time is 00:00:00 +Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info: Optimizations that may affect the design's routability were skipped + Info: Optimizations that may affect the design's timing were skipped +Info: Started post-fitting delay annotation +Warning: Found 9 output pins without output pin load capacitance assignment + Info: Pin "CO" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "S7" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "S0" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "S1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "S2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "S3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "S4" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "S5" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "S6" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis +Info: Delay annotation completed successfully +Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. +Info: Generated suppressed messages file D:/projects/quartus/adder/adder.fit.smsg +Info: Quartus II Fitter was successful. 0 errors, 3 warnings + Info: Peak virtual memory: 305 megabytes + Info: Processing ended: Mon Mar 07 08:49:24 2022 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in D:/projects/quartus/adder/adder.fit.smsg. + + diff --git a/adder/adder.fit.smsg b/adder/adder.fit.smsg new file mode 100644 index 0000000..14764e7 --- /dev/null +++ b/adder/adder.fit.smsg @@ -0,0 +1,6 @@ +Extra Info: Performing register packing on registers with non-logic cell location assignments +Extra Info: Completed register packing on registers with non-logic cell location assignments +Extra Info: Started Fast Input/Output/OE register processing +Extra Info: Finished Fast Input/Output/OE register processing +Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/adder/adder.fit.summary b/adder/adder.fit.summary new file mode 100644 index 0000000..25f7342 --- /dev/null +++ b/adder/adder.fit.summary @@ -0,0 +1,16 @@ +Fitter Status : Successful - Mon Mar 07 08:49:24 2022 +Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +Revision Name : adder +Top-level Entity Name : adder +Family : Cyclone II +Device : EP2C8Q208C8 +Timing Models : Final +Total logic elements : 21 / 8,256 ( < 1 % ) + Total combinational functions : 21 / 8,256 ( < 1 % ) + Dedicated logic registers : 0 / 8,256 ( 0 % ) +Total registers : 0 +Total pins : 26 / 138 ( 19 % ) +Total virtual pins : 0 +Total memory bits : 0 / 165,888 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % ) +Total PLLs : 0 / 2 ( 0 % ) diff --git a/adder/adder.flow.rpt b/adder/adder.flow.rpt new file mode 100644 index 0000000..169a9be --- /dev/null +++ b/adder/adder.flow.rpt @@ -0,0 +1,120 @@ +Flow report for adder +Mon Mar 07 08:49:27 2022 +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+----------------------------------------------+ +; Flow Status ; Successful - Mon Mar 07 08:49:27 2022 ; +; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; +; Revision Name ; adder ; +; Top-level Entity Name ; adder ; +; Family ; Cyclone II ; +; Device ; EP2C8Q208C8 ; +; Timing Models ; Final ; +; Met timing requirements ; Yes ; +; Total logic elements ; 21 / 8,256 ( < 1 % ) ; +; Total combinational functions ; 21 / 8,256 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 26 / 138 ( 19 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 165,888 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; +; Total PLLs ; 0 / 2 ( 0 % ) ; ++------------------------------------+----------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 03/07/2022 08:49:22 ; +; Main task ; Compilation ; +; Revision Name ; adder ; ++-------------------+---------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++------------------------------------+---------------------------------+---------------+-------------+----------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++------------------------------------+---------------------------------+---------------+-------------+----------------+ +; COMPILER_SIGNATURE_ID ; 220283517943889.164661416219416 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; +; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ; ++------------------------------------+---------------------------------+---------------+-------------+----------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 245 MB ; 00:00:00 ; +; Fitter ; 00:00:01 ; 1.0 ; 305 MB ; 00:00:01 ; +; Assembler ; 00:00:01 ; 1.0 ; 242 MB ; 00:00:00 ; +; Classic Timing Analyzer ; 00:00:01 ; 1.0 ; 198 MB ; 00:00:00 ; +; Total ; 00:00:04 ; -- ; -- ; 00:00:01 ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++------------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++-------------------------+------------------+---------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++-------------------------+------------------+---------------+------------+----------------+ +; Analysis & Synthesis ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; +; Fitter ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; +; Assembler ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; +; Classic Timing Analyzer ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; ++-------------------------+------------------+---------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off adder -c adder +quartus_fit --read_settings_files=off --write_settings_files=off adder -c adder +quartus_asm --read_settings_files=off --write_settings_files=off adder -c adder +quartus_tan --read_settings_files=off --write_settings_files=off adder -c adder --timing_analysis_only + + + diff --git a/adder/adder.map.rpt b/adder/adder.map.rpt new file mode 100644 index 0000000..fc3c724 --- /dev/null +++ b/adder/adder.map.rpt @@ -0,0 +1,240 @@ +Analysis & Synthesis report for adder +Mon Mar 07 08:49:22 2022 +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Analysis & Synthesis Source Files Read + 5. Analysis & Synthesis Resource Usage Summary + 6. Analysis & Synthesis Resource Utilization by Entity + 7. General Register Statistics + 8. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+----------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Mon Mar 07 08:49:22 2022 ; +; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; +; Revision Name ; adder ; +; Top-level Entity Name ; adder ; +; Family ; Cyclone II ; +; Total logic elements ; 21 ; +; Total combinational functions ; 21 ; +; Dedicated logic registers ; 0 ; +; Total registers ; 0 ; +; Total pins ; 26 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; ++------------------------------------+----------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++--------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP2C8Q208C8 ; ; +; Top-level entity name ; adder ; adder ; +; Family name ; Cyclone II ; Stratix II ; +; Use Generated Physical Constraints File ; Off ; ; +; Use smart compilation ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL93 ; VHDL93 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Parallel Synthesis ; Off ; Off ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; Off ; Off ; +; Show Parameter Settings Tables in Synthesis Report ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; ++--------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------+------------------------------------------------------------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; ++----------------------------------+-----------------+------------------------------------+------------------------------------------------------------+ +; adder.bdf ; yes ; User Block Diagram/Schematic File ; D:/projects/quartus/adder/adder.bdf ; +; 7400.bdf ; yes ; Megafunction ; d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf ; +; 7486.bdf ; yes ; Megafunction ; d:/altera/90sp2/quartus/libraries/others/maxplus2/7486.bdf ; ++----------------------------------+-----------------+------------------------------------+------------------------------------------------------------+ + + ++--------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+----------------+ +; Resource ; Usage ; ++---------------------------------------------+----------------+ +; Estimated Total logic elements ; 21 ; +; ; ; +; Total combinational functions ; 21 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 9 ; +; -- 3 input functions ; 9 ; +; -- <=2 input functions ; 3 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 21 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 0 ; +; -- Dedicated logic registers ; 0 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 26 ; +; Maximum fan-out node ; 7400:inst8|4~0 ; +; Maximum fan-out ; 4 ; +; Total fan-out ; 78 ; +; Average fan-out ; 1.66 ; ++---------------------------------------------+----------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ +; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ +; |adder ; 21 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 26 ; 0 ; |adder ; work ; +; |7400:inst13| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7400:inst13 ; work ; +; |7400:inst18| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7400:inst18 ; work ; +; |7400:inst23| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7400:inst23 ; work ; +; |7400:inst28| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7400:inst28 ; work ; +; |7400:inst33| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7400:inst33 ; work ; +; |7400:inst38| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7400:inst38 ; work ; +; |7400:inst3| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7400:inst3 ; work ; +; |7400:inst8| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7400:inst8 ; work ; +; |7486:inst10| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7486:inst10 ; work ; +; |7486:inst15| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7486:inst15 ; work ; +; |7486:inst20| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7486:inst20 ; work ; +; |7486:inst25| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7486:inst25 ; work ; +; |7486:inst30| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7486:inst30 ; work ; +; |7486:inst35| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7486:inst35 ; work ; +; |7486:inst40| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7486:inst40 ; work ; +; |7486:inst5| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7486:inst5 ; work ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 0 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Analysis & Synthesis + Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + Info: Processing started: Mon Mar 07 08:49:21 2022 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adder -c adder +Info: Found 1 design units, including 1 entities, in source file adder.bdf + Info: Found entity 1: adder +Info: Elaborating entity "adder" for the top level hierarchy +Info: Elaborating entity "7400" for hierarchy "7400:inst38" +Info: Elaborated megafunction instantiation "7400:inst38" +Info: Elaborating entity "7486" for hierarchy "7486:inst" +Info: Elaborated megafunction instantiation "7486:inst" +Info: Implemented 47 device resources after synthesis - the final resource count might be different + Info: Implemented 17 input pins + Info: Implemented 9 output pins + Info: Implemented 21 logic cells +Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 248 megabytes + Info: Processing ended: Mon Mar 07 08:49:22 2022 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/adder/adder.map.summary b/adder/adder.map.summary new file mode 100644 index 0000000..a7a1b32 --- /dev/null +++ b/adder/adder.map.summary @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Mon Mar 07 08:49:22 2022 +Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +Revision Name : adder +Top-level Entity Name : adder +Family : Cyclone II +Total logic elements : 21 + Total combinational functions : 21 + Dedicated logic registers : 0 +Total registers : 0 +Total pins : 26 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 diff --git a/adder/adder.pin b/adder/adder.pin new file mode 100644 index 0000000..b5147e1 --- /dev/null +++ b/adder/adder.pin @@ -0,0 +1,278 @@ + -- Copyright (C) 1991-2009 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- Bank 3: 3.3V + -- Bank 4: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17), + -- connect each pin marked GND* either individually through a 10k Ohm resistor + -- to GND or tie all pins together and connect through a single 10k Ohm resistor + -- to GND. + -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +CHIP "adder" ASSIGNED TO AN: EP2C8Q208C8 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVTTL : : 1 : N +~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVTTL : : 1 : N +GND* : 3 : : : : 1 : +GND* : 4 : : : : 1 : +A7 : 5 : input : 3.3-V LVTTL : : 1 : N +S7 : 6 : output : 3.3-V LVTTL : : 1 : N +VCCIO1 : 7 : power : : 3.3V : 1 : +GND* : 8 : : : : 1 : +GND : 9 : gnd : : : : +B6 : 10 : input : 3.3-V LVTTL : : 1 : N +B7 : 11 : input : 3.3-V LVTTL : : 1 : N +S6 : 12 : output : 3.3-V LVTTL : : 1 : N +A6 : 13 : input : 3.3-V LVTTL : : 1 : N +B5 : 14 : input : 3.3-V LVTTL : : 1 : N +GND* : 15 : : : : 1 : +TDO : 16 : output : : : 1 : +TMS : 17 : input : : : 1 : +TCK : 18 : input : : : 1 : +TDI : 19 : input : : : 1 : +DATA0 : 20 : input : : : 1 : +DCLK : 21 : : : : 1 : +nCE : 22 : : : : 1 : +A2 : 23 : input : 3.3-V LVTTL : : 1 : N +A0 : 24 : input : 3.3-V LVTTL : : 1 : N +GND : 25 : gnd : : : : +nCONFIG : 26 : : : : 1 : +CI : 27 : input : 3.3-V LVTTL : : 1 : N +B0 : 28 : input : 3.3-V LVTTL : : 1 : N +VCCIO1 : 29 : power : : 3.3V : 1 : +B2 : 30 : input : 3.3-V LVTTL : : 1 : N +S3 : 31 : output : 3.3-V LVTTL : : 1 : N +VCCINT : 32 : power : : 1.2V : : +GND* : 33 : : : : 1 : +S1 : 34 : output : 3.3-V LVTTL : : 1 : N +S5 : 35 : output : 3.3-V LVTTL : : 1 : N +GND : 36 : gnd : : : : +S4 : 37 : output : 3.3-V LVTTL : : 1 : N +GND : 38 : gnd : : : : +B3 : 39 : input : 3.3-V LVTTL : : 1 : N +A3 : 40 : input : 3.3-V LVTTL : : 1 : N +A4 : 41 : input : 3.3-V LVTTL : : 1 : N +VCCIO1 : 42 : power : : 3.3V : 1 : +GND* : 43 : : : : 1 : +GND* : 44 : : : : 1 : +GND* : 45 : : : : 1 : +GND* : 46 : : : : 1 : +GND* : 47 : : : : 1 : +GND* : 48 : : : : 1 : +GND : 49 : gnd : : : : +GND_PLL1 : 50 : gnd : : : : +VCCD_PLL1 : 51 : power : : 1.2V : : +GND_PLL1 : 52 : gnd : : : : +VCCA_PLL1 : 53 : power : : 1.2V : : +GNDA_PLL1 : 54 : gnd : : : : +GND : 55 : gnd : : : : +GND* : 56 : : : : 4 : +A1 : 57 : input : 3.3-V LVTTL : : 4 : N +CO : 58 : output : 3.3-V LVTTL : : 4 : N +GND* : 59 : : : : 4 : +B1 : 60 : input : 3.3-V LVTTL : : 4 : N +GND* : 61 : : : : 4 : +VCCIO4 : 62 : power : : 3.3V : 4 : +GND* : 63 : : : : 4 : +GND* : 64 : : : : 4 : +GND : 65 : gnd : : : : +VCCINT : 66 : power : : 1.2V : : +GND* : 67 : : : : 4 : +GND* : 68 : : : : 4 : +GND* : 69 : : : : 4 : +GND* : 70 : : : : 4 : +VCCIO4 : 71 : power : : 3.3V : 4 : +GND* : 72 : : : : 4 : +GND : 73 : gnd : : : : +GND* : 74 : : : : 4 : +GND* : 75 : : : : 4 : +GND* : 76 : : : : 4 : +GND* : 77 : : : : 4 : +GND : 78 : gnd : : : : +VCCINT : 79 : power : : 1.2V : : +GND* : 80 : : : : 4 : +GND* : 81 : : : : 4 : +GND* : 82 : : : : 4 : +VCCIO4 : 83 : power : : 3.3V : 4 : +GND* : 84 : : : : 4 : +GND : 85 : gnd : : : : +GND* : 86 : : : : 4 : +GND* : 87 : : : : 4 : +GND* : 88 : : : : 4 : +GND* : 89 : : : : 4 : +GND* : 90 : : : : 4 : +VCCIO4 : 91 : power : : 3.3V : 4 : +GND* : 92 : : : : 4 : +GND : 93 : gnd : : : : +GND* : 94 : : : : 4 : +GND* : 95 : : : : 4 : +GND* : 96 : : : : 4 : +GND* : 97 : : : : 4 : +VCCIO4 : 98 : power : : 3.3V : 4 : +GND* : 99 : : : : 4 : +GND : 100 : gnd : : : : +GND* : 101 : : : : 4 : +S0 : 102 : output : 3.3-V LVTTL : : 4 : N +GND* : 103 : : : : 4 : +GND* : 104 : : : : 4 : +GND* : 105 : : : : 3 : +GND* : 106 : : : : 3 : +GND* : 107 : : : : 3 : +~LVDS54p/nCEO~ : 108 : output : 3.3-V LVTTL : : 3 : N +VCCIO3 : 109 : power : : 3.3V : 3 : +GND* : 110 : : : : 3 : +GND : 111 : gnd : : : : +GND* : 112 : : : : 3 : +GND* : 113 : : : : 3 : +GND* : 114 : : : : 3 : +GND* : 115 : : : : 3 : +GND* : 116 : : : : 3 : +GND* : 117 : : : : 3 : +S2 : 118 : output : 3.3-V LVTTL : : 3 : N +GND : 119 : gnd : : : : +VCCINT : 120 : power : : 1.2V : : +nSTATUS : 121 : : : : 3 : +VCCIO3 : 122 : power : : 3.3V : 3 : +CONF_DONE : 123 : : : : 3 : +GND : 124 : gnd : : : : +MSEL1 : 125 : : : : 3 : +MSEL0 : 126 : : : : 3 : +GND* : 127 : : : : 3 : +GND* : 128 : : : : 3 : +GND+ : 129 : : : : 3 : +GND+ : 130 : : : : 3 : +GND+ : 131 : : : : 3 : +GND+ : 132 : : : : 3 : +GND* : 133 : : : : 3 : +GND* : 134 : : : : 3 : +GND* : 135 : : : : 3 : +VCCIO3 : 136 : power : : 3.3V : 3 : +GND* : 137 : : : : 3 : +GND* : 138 : : : : 3 : +GND* : 139 : : : : 3 : +GND : 140 : gnd : : : : +GND* : 141 : : : : 3 : +GND* : 142 : : : : 3 : +GND* : 143 : : : : 3 : +GND* : 144 : : : : 3 : +GND* : 145 : : : : 3 : +GND* : 146 : : : : 3 : +GND* : 147 : : : : 3 : +VCCIO3 : 148 : power : : 3.3V : 3 : +GND* : 149 : : : : 3 : +A5 : 150 : input : 3.3-V LVTTL : : 3 : N +GND* : 151 : : : : 3 : +GND* : 152 : : : : 3 : +GND : 153 : gnd : : : : +GND_PLL2 : 154 : gnd : : : : +VCCD_PLL2 : 155 : power : : 1.2V : : +GND_PLL2 : 156 : gnd : : : : +VCCA_PLL2 : 157 : power : : 1.2V : : +GNDA_PLL2 : 158 : gnd : : : : +GND : 159 : gnd : : : : +GND* : 160 : : : : 2 : +GND* : 161 : : : : 2 : +GND* : 162 : : : : 2 : +GND* : 163 : : : : 2 : +GND* : 164 : : : : 2 : +GND* : 165 : : : : 2 : +VCCIO2 : 166 : power : : 3.3V : 2 : +GND : 167 : gnd : : : : +GND* : 168 : : : : 2 : +GND* : 169 : : : : 2 : +GND* : 170 : : : : 2 : +GND* : 171 : : : : 2 : +VCCIO2 : 172 : power : : 3.3V : 2 : +GND* : 173 : : : : 2 : +GND : 174 : gnd : : : : +GND* : 175 : : : : 2 : +GND* : 176 : : : : 2 : +GND : 177 : gnd : : : : +VCCINT : 178 : power : : 1.2V : : +GND* : 179 : : : : 2 : +GND* : 180 : : : : 2 : +GND* : 181 : : : : 2 : +GND* : 182 : : : : 2 : +VCCIO2 : 183 : power : : 3.3V : 2 : +GND : 184 : gnd : : : : +GND* : 185 : : : : 2 : +GND : 186 : gnd : : : : +GND* : 187 : : : : 2 : +GND* : 188 : : : : 2 : +GND* : 189 : : : : 2 : +VCCINT : 190 : power : : 1.2V : : +GND* : 191 : : : : 2 : +GND* : 192 : : : : 2 : +GND* : 193 : : : : 2 : +VCCIO2 : 194 : power : : 3.3V : 2 : +GND* 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Legal Notice + 2. Timing Analyzer Summary + 3. Timing Analyzer Settings + 4. Parallel Compilation + 5. tpd + 6. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ +; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; ++------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ +; Worst-case tpd ; N/A ; None ; 19.344 ns ; A1 ; CO ; -- ; -- ; 0 ; +; Total number of failed paths ; ; ; ; ; ; ; ; 0 ; ++------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ + + ++--------------------------------------------------------------------------------------------------------------------+ +; Timing Analyzer Settings ; ++---------------------------------------------------------------------+--------------------+------+----+-------------+ +; Option ; Setting ; From ; To ; Entity Name ; ++---------------------------------------------------------------------+--------------------+------+----+-------------+ +; Device Name ; EP2C8Q208C8 ; ; ; ; +; Timing Models ; Final ; ; ; ; +; Default hold multicycle ; Same as Multicycle ; ; ; ; +; Cut paths between unrelated clock domains ; On ; ; ; ; +; Cut off read during write signal paths ; On ; ; ; ; +; Cut off feedback from I/O pins ; On ; ; ; ; +; Report Combined Fast/Slow Timing ; Off ; ; ; ; +; Ignore Clock Settings ; Off ; ; ; ; +; Analyze latches as synchronous elements ; On ; ; ; ; +; Enable Recovery/Removal analysis ; Off ; ; ; ; +; Enable Clock Latency ; Off ; ; ; ; +; Use TimeQuest Timing Analyzer ; Off ; ; ; ; +; Minimum Core Junction Temperature ; 0 ; ; ; ; +; Maximum Core Junction Temperature ; 85 ; ; ; ; +; Number of source nodes to report per destination node ; 10 ; ; ; ; +; Number of destination nodes to report ; 10 ; ; ; ; +; Number of paths to report ; 200 ; ; ; ; +; Report Minimum Timing Checks ; Off ; ; ; ; +; Use Fast Timing Models ; Off ; ; ; ; +; Report IO Paths Separately ; Off ; ; ; ; +; Perform Multicorner Analysis ; On ; ; ; ; +; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ; +; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ; +; Output I/O Timing Endpoint ; Near End ; ; ; ; ++---------------------------------------------------------------------+--------------------+------+----+-------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; 1 processor ; 100.0% ; +; 2-4 processors ; 0.0% ; ++----------------------------+-------------+ + + ++---------------------------------------------------------+ +; tpd ; ++-------+-------------------+-----------------+------+----+ +; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ; ++-------+-------------------+-----------------+------+----+ +; N/A ; None ; 19.344 ns ; A1 ; CO ; +; N/A ; None ; 19.220 ns ; B1 ; CO ; +; N/A ; None ; 18.199 ns ; B2 ; CO ; +; N/A ; None ; 18.173 ns ; A1 ; S7 ; +; N/A ; None ; 18.049 ns ; B1 ; S7 ; +; N/A ; None ; 17.501 ns ; A3 ; CO ; +; N/A ; None ; 17.423 ns ; B3 ; CO ; +; N/A ; None ; 17.266 ns ; B4 ; CO ; +; N/A ; None ; 17.091 ns ; A5 ; CO ; +; N/A ; None ; 17.075 ns ; A4 ; CO ; +; N/A ; None ; 17.028 ns ; B2 ; S7 ; +; N/A ; None ; 17.000 ns ; A1 ; S6 ; +; N/A ; None ; 16.876 ns ; B1 ; S6 ; +; N/A ; None ; 16.330 ns ; A3 ; S7 ; +; N/A ; None ; 16.252 ns ; B3 ; S7 ; +; N/A ; None ; 16.095 ns ; B4 ; S7 ; +; N/A ; None ; 15.940 ns ; B5 ; CO ; +; N/A ; None ; 15.920 ns ; A5 ; S7 ; +; N/A ; None ; 15.904 ns ; A4 ; S7 ; +; N/A ; None ; 15.855 ns ; B2 ; S6 ; +; N/A ; None ; 15.259 ns ; A0 ; CO ; +; N/A ; None ; 15.157 ns ; A3 ; S6 ; +; N/A ; None ; 15.079 ns ; B3 ; S6 ; +; N/A ; None ; 15.027 ns ; B0 ; CO ; +; N/A ; None ; 14.922 ns ; B4 ; S6 ; +; N/A ; None ; 14.769 ns ; B5 ; S7 ; +; N/A ; None ; 14.762 ns ; CI ; CO ; +; N/A ; None ; 14.759 ns ; A1 ; S5 ; +; N/A ; None ; 14.747 ns ; A5 ; S6 ; +; N/A ; None ; 14.731 ns ; A4 ; S6 ; +; N/A ; None ; 14.635 ns ; B1 ; S5 ; +; N/A ; None ; 14.560 ns ; A1 ; S2 ; +; N/A ; None ; 14.436 ns ; B1 ; S2 ; +; N/A ; None ; 14.088 ns ; A0 ; S7 ; +; N/A ; None ; 14.087 ns ; A1 ; S4 ; +; N/A ; None ; 13.963 ns ; B1 ; S4 ; +; N/A ; None ; 13.856 ns ; B0 ; S7 ; +; N/A ; None ; 13.695 ns ; A6 ; CO ; +; N/A ; None ; 13.614 ns ; B2 ; S5 ; +; N/A ; None ; 13.596 ns ; B5 ; S6 ; +; N/A ; None ; 13.591 ns ; CI ; S7 ; +; N/A ; None ; 13.448 ns ; A2 ; CO ; +; N/A ; None ; 13.408 ns ; B2 ; S2 ; +; N/A ; None ; 13.338 ns ; A1 ; S3 ; +; N/A ; None ; 13.214 ns ; B1 ; S3 ; +; N/A ; None ; 12.955 ns ; B6 ; CO ; +; N/A ; None ; 12.942 ns ; B2 ; S4 ; +; N/A ; None ; 12.916 ns ; A3 ; S5 ; +; N/A ; None ; 12.915 ns ; A0 ; S6 ; +; N/A ; None ; 12.838 ns ; B3 ; S5 ; +; N/A ; None ; 12.683 ns ; B0 ; S6 ; +; N/A ; None ; 12.681 ns ; B4 ; S5 ; +; N/A ; None ; 12.613 ns ; B7 ; CO ; +; N/A ; None ; 12.524 ns ; A6 ; S7 ; +; N/A ; None ; 12.501 ns ; A5 ; S5 ; +; N/A ; None ; 12.488 ns ; A4 ; S5 ; +; N/A ; None ; 12.418 ns ; CI ; S6 ; +; N/A ; None ; 12.408 ns ; A7 ; CO ; +; N/A ; None ; 12.277 ns ; A2 ; S7 ; +; N/A ; None ; 12.244 ns ; A3 ; S4 ; +; N/A ; None ; 12.193 ns ; B2 ; S3 ; +; N/A ; None ; 12.166 ns ; B3 ; S4 ; +; N/A ; None ; 12.007 ns ; B4 ; S4 ; +; N/A ; None ; 11.786 ns ; B6 ; S7 ; +; N/A ; None ; 11.579 ns ; A1 ; S1 ; +; N/A ; None ; 11.527 ns ; A4 ; S4 ; +; N/A ; None ; 11.489 ns ; A3 ; S3 ; +; N/A ; None ; 11.458 ns ; B1 ; S1 ; +; N/A ; None ; 11.443 ns ; B7 ; S7 ; +; N/A ; None ; 11.415 ns ; B3 ; S3 ; +; N/A ; None ; 11.378 ns ; A6 ; S6 ; +; N/A ; None ; 11.337 ns ; B5 ; S5 ; +; N/A ; None ; 11.243 ns ; A7 ; S7 ; +; N/A ; None ; 11.104 ns ; A2 ; S6 ; +; N/A ; None ; 11.091 ns ; B6 ; S6 ; +; N/A ; None ; 10.674 ns ; A0 ; S5 ; +; N/A ; None ; 10.475 ns ; A0 ; S2 ; +; N/A ; None ; 10.442 ns ; B0 ; S5 ; +; N/A ; None ; 10.294 ns ; A0 ; S0 ; +; N/A ; None ; 10.243 ns ; B0 ; S2 ; +; N/A ; None ; 10.177 ns ; CI ; S5 ; +; N/A ; None ; 10.065 ns ; B0 ; S0 ; +; N/A ; None ; 10.002 ns ; A0 ; S4 ; +; N/A ; None ; 9.978 ns ; CI ; S2 ; +; N/A ; None ; 9.800 ns ; CI ; S0 ; +; N/A ; None ; 9.770 ns ; B0 ; S4 ; +; N/A ; None ; 9.505 ns ; CI ; S4 ; +; N/A ; None ; 9.253 ns ; A0 ; S3 ; +; N/A ; None ; 9.021 ns ; B0 ; S3 ; +; N/A ; None ; 8.863 ns ; A2 ; S5 ; +; N/A ; None ; 8.756 ns ; CI ; S3 ; +; N/A ; None ; 8.661 ns ; A2 ; S2 ; +; N/A ; None ; 8.191 ns ; A2 ; S4 ; +; N/A ; None ; 7.490 ns ; A0 ; S1 ; +; N/A ; None ; 7.442 ns ; A2 ; S3 ; +; N/A ; None ; 7.258 ns ; B0 ; S1 ; +; N/A ; None ; 6.993 ns ; CI ; S1 ; ++-------+-------------------+-----------------+------+----+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Classic Timing Analyzer + Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + Info: Processing started: Mon Mar 07 08:49:26 2022 +Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off adder -c adder --timing_analysis_only +Info: Parallel compilation is enabled and will use 4 of the 4 processors detected +Info: Longest tpd from source pin "A1" to destination pin "CO" is 19.344 ns + Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_57; Fanout = 2; PIN Node = 'A1' + Info: 2: + IC(6.202 ns) + CELL(0.651 ns) = 7.847 ns; Loc. = LCCOMB_X1_Y7_N12; Fanout = 4; COMB Node = '7400:inst8|4~0' + Info: 3: + IC(0.391 ns) + CELL(0.206 ns) = 8.444 ns; Loc. = LCCOMB_X1_Y7_N8; Fanout = 2; COMB Node = '7400:inst13|4~1' + Info: 4: + IC(0.387 ns) + CELL(0.370 ns) = 9.201 ns; Loc. = LCCOMB_X1_Y7_N4; Fanout = 2; COMB Node = '7400:inst18|4~0' + Info: 5: + IC(0.387 ns) + CELL(0.370 ns) = 9.958 ns; Loc. = LCCOMB_X1_Y7_N6; Fanout = 2; COMB Node = '7400:inst23|4~9' + Info: 6: + IC(0.412 ns) + CELL(0.650 ns) = 11.020 ns; Loc. = LCCOMB_X1_Y7_N0; Fanout = 3; COMB Node = '7400:inst28|4~0' + Info: 7: + IC(1.736 ns) + CELL(0.206 ns) = 12.962 ns; Loc. = LCCOMB_X1_Y15_N24; Fanout = 2; COMB Node = '7400:inst33|4~0' + Info: 8: + IC(0.396 ns) + CELL(0.651 ns) = 14.009 ns; Loc. = LCCOMB_X1_Y15_N4; Fanout = 1; COMB Node = '7400:inst38|4~0' + Info: 9: + IC(2.039 ns) + CELL(3.296 ns) = 19.344 ns; Loc. = PIN_58; Fanout = 0; PIN Node = 'CO' + Info: Total cell delay = 7.394 ns ( 38.22 % ) + Info: Total interconnect delay = 11.950 ns ( 61.78 % ) +Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 212 megabytes + Info: Processing ended: Mon Mar 07 08:49:27 2022 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:00 + + diff --git a/adder/adder.tan.summary b/adder/adder.tan.summary new file mode 100644 index 0000000..b333f61 --- /dev/null +++ b/adder/adder.tan.summary @@ -0,0 +1,26 @@ +-------------------------------------------------------------------------------------- +Timing Analyzer Summary +-------------------------------------------------------------------------------------- + +Type : Worst-case tpd +Slack : N/A +Required Time : None +Actual Time : 19.344 ns +From : A1 +To : CO +From Clock : -- +To Clock : -- +Failed Paths : 0 + +Type : Total number of failed paths +Slack : +Required Time : +Actual Time : +From : +To : +From Clock : +To Clock : +Failed Paths : 0 + +-------------------------------------------------------------------------------------- + diff --git a/adder/db/adder.(0).cnf.cdb b/adder/db/adder.(0).cnf.cdb new file mode 100644 index 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zS!QyoLO^12wt|sDu$Mx3YLbF$N@fXAn<&r(5U7Pv43 7400:inst39.3 +A7 => 7486:inst36.2 +B7 => 7400:inst39.2 +B7 => 7486:inst36.3 +A6 => 7400:inst34.3 +A6 => 7486:inst31.2 +B6 => 7400:inst34.2 +B6 => 7486:inst31.3 +A5 => 7400:inst29.3 +A5 => 7486:inst26.2 +B5 => 7400:inst29.2 +B5 => 7486:inst26.3 +A4 => 7400:inst24.3 +A4 => 7486:inst21.2 +B4 => 7400:inst24.2 +B4 => 7486:inst21.3 +A3 => 7400:inst19.3 +A3 => 7486:inst16.2 +B3 => 7400:inst19.2 +B3 => 7486:inst16.3 +A2 => 7400:inst14.3 +A2 => 7486:inst11.2 +B2 => 7400:inst14.2 +B2 => 7486:inst11.3 +A1 => 7400:inst9.3 +A1 => 7486:inst6.2 +B1 => 7400:inst9.2 +B1 => 7486:inst6.3 +A0 => 7400:inst4.3 +A0 => 7486:inst.2 +B0 => 7400:inst4.2 +B0 => 7486:inst.3 +CI => 7400:inst2.3 +CI => 7486:inst5.3 +S7 <= 7486:inst40.1 +S0 <= 7486:inst5.1 +S1 <= 7486:inst10.1 +S2 <= 7486:inst15.1 +S3 <= 7486:inst20.1 +S4 <= 7486:inst25.1 +S5 <= 7486:inst30.1 +S6 <= 7486:inst35.1 + + +|adder|7400:inst38 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7400:inst39 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7400:inst37 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7400:inst33 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7400:inst34 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7400:inst32 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7400:inst28 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7400:inst29 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7400:inst27 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7400:inst23 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7400:inst24 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7400:inst22 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7400:inst18 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7400:inst19 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7400:inst17 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7400:inst13 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7400:inst14 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7400:inst12 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7400:inst8 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7400:inst9 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7400:inst7 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7400:inst3 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7400:inst4 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7400:inst2 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7486:inst +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7486:inst6 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7486:inst11 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7486:inst16 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7486:inst21 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7486:inst26 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7486:inst31 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7486:inst36 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7486:inst40 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7486:inst5 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7486:inst10 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7486:inst15 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7486:inst20 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7486:inst25 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7486:inst30 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + +|adder|7486:inst35 +1 <= 4.DB_MAX_OUTPUT_PORT_TYPE +2 => 4.IN0 +3 => 4.IN1 + + diff --git a/adder/db/adder.hif b/adder/db/adder.hif new file mode 100644 index 0000000..288d8b0 --- /dev/null +++ b/adder/db/adder.hif @@ -0,0 +1,120 @@ +Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +11 +936 +OFF +OFF +OFF +ON +ON +ON +FV_OFF +Level2 +0 +0 +VRSM_ON +VHSM_ON +0 +-- Start Library Paths -- +-- End Library Paths -- +-- Start VHDL Libraries -- +-- End VHDL Libraries -- +# entity +adder +# storage +db|adder.(0).cnf +db|adder.(0).cnf +# case_insensitive +# source_file +adder.bdf +24315e582bd755b4b98eeb6d569ea2 +26 +# internal_option { +BLOCK_DESIGN_NAMING +AUTO +} +# hierarchies { +| +} +# macro_sequence + +# end +# entity +7400 +# storage +db|adder.(1).cnf +db|adder.(1).cnf +# case_insensitive +# source_file +..|..|..|altera|90sp2|quartus|libraries|others|maxplus2|7400.bdf +2bbb3be4da5c8a854468ca6be3dac +26 +# internal_option { +BLOCK_DESIGN_NAMING +AUTO +} +# hierarchies { +7400:inst38 +7400:inst39 +7400:inst37 +7400:inst33 +7400:inst34 +7400:inst32 +7400:inst28 +7400:inst29 +7400:inst27 +7400:inst23 +7400:inst24 +7400:inst22 +7400:inst18 +7400:inst19 +7400:inst17 +7400:inst13 +7400:inst14 +7400:inst12 +7400:inst8 +7400:inst9 +7400:inst7 +7400:inst3 +7400:inst4 +7400:inst2 +} +# macro_sequence + +# end +# entity +7486 +# storage +db|adder.(2).cnf +db|adder.(2).cnf +# case_insensitive +# source_file +..|..|..|altera|90sp2|quartus|libraries|others|maxplus2|7486.bdf +66760dceba984b0dca8067dd21fcf +26 +# internal_option { +BLOCK_DESIGN_NAMING +AUTO +} +# hierarchies { +7486:inst +7486:inst6 +7486:inst11 +7486:inst16 +7486:inst21 +7486:inst26 +7486:inst31 +7486:inst36 +7486:inst40 +7486:inst5 +7486:inst10 +7486:inst15 +7486:inst20 +7486:inst25 +7486:inst30 +7486:inst35 +} +# macro_sequence + +# end +# complete + \ No newline at end of file diff --git a/adder/db/adder.lpc.html b/adder/db/adder.lpc.html new file mode 100644 index 0000000..fd4875d --- /dev/null +++ b/adder/db/adder.lpc.html @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
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++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/adder/db/adder.map.bpm b/adder/db/adder.map.bpm new file mode 100644 index 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"IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 08:49:21 2022 " "Info: Processing started: Mon Mar 07 08:49:21 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off adder -c adder " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adder -c adder" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adder.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 adder " "Info: Found entity 1: adder" { } { { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_TOP" "adder " "Info: Elaborating entity \"adder\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7400 7400:inst38 " "Info: Elaborating entity \"7400\" for hierarchy \"7400:inst38\"" { } { { "adder.bdf" "inst38" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 184 432 496 224 "inst38" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_ELABORATION_HEADER" "7400:inst38 " "Info: Elaborated megafunction instantiation \"7400:inst38\"" { } { { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 184 432 496 224 "inst38" "" } } } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7486 7486:inst " "Info: Elaborating entity \"7486\" for hierarchy \"7486:inst\"" { } { { "adder.bdf" "inst" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 2096 304 368 2136 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_ELABORATION_HEADER" "7486:inst " "Info: Elaborated megafunction instantiation \"7486:inst\"" { } { { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 2096 304 368 2136 "inst" "" } } } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ICUT_CUT_TM_SUMMARY" "47 " "Info: Implemented 47 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "17 " "Info: Implemented 17 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Info: Implemented 9 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "21 " "Info: Implemented 21 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "248 " "Info: Peak virtual memory: 248 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 08:49:22 2022 " "Info: Processing ended: Mon Mar 07 08:49:22 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 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compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/adder/incremental_db/compiled_partitions/adder.root_partition.cmp.atm b/adder/incremental_db/compiled_partitions/adder.root_partition.cmp.atm new file mode 100644 index 0000000000000000000000000000000000000000..0a8e135269ebe02b81270b8b907654b2975e80ec GIT binary patch literal 8870 zcmYk9WmuF^w}z3fp-Wn%yFPPhM^hh25E+rE@4RN1`#-TzVABM z*}wLFueI*yeb!okRu%3mgnuU>``FCPXGORn#6J{8l}o5%R0I7i==TYd{IsBht@7K^ zi2w`3_-gvLg?gQ*#kD09zV1hVAc4Aa{*RdAB~}|3#d@U}%n*VW)pcQjb+glg3s(u=N7oj zuq&&Z9gU#uNe`NJm*z_@sLS!??3zGs=+qg3!3Uw`zvqWn=0WLUp???V9(5^={~|tT zi%U2@Ejbp4bhm|d06_C7)BNAFF!BzfWF1 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zt5w!K?iKCyq{(;R5Yh7LB$Z@RPOx#!5K(uh;MSUTSj(-GRFd%tV>MO*Q+*Y(`^2sg4OrY4NN??W&@>1&+4XgQPkh zBx40pF{g&8)U_q58ju7x@kxpAyjjq0pyt7k^Q1&kMW=b21s|)5ZKMDlZ;m;|!yqQ9 znOD^9Dzvr69Mv)AOkC`(HqDxwX{P!PRJG;oCX(fMw&iH^$kKk=M6yqH>DY4eweM1( z(mDf$n(FXqtu04&Y&lju(Nd@6)je;twVoW++8}6_PqVmnjH@E0T5`;NGK8zGPTl4a zE_0tW;qDt9T6+T>R=$a)hH!V@#nf6qj_UYv1Q+{^N!_~>sHIFzO!edNH}UolhFrrY zai(L)vEr$S(m6TuV)!vk`748`Z{E({irS;kAG}q{ch2v;mcKSR3*Z+8W1N3m2H`A? zc{Ixb?Gz!3?DAm5ujE{kCHdicEB;?7N#4d=-Tc9e-}hUk*kYE28Ma6zM;I;SuLD|n z`g&o`7Qq#d6Sz8~?$RPl*JZ9l=X2BG7`sc)@!4|enz$&Gx880=F`~RS#_KOC3Ry!} zfmqB>GA#W0r`<|f^PQ8oe17JSP$3%>EQ7fs%x6vN41 z?qB00p`n-F~gTy>0?on + + + + + + + + + From 272185e4d88efa6c1a14cedd7e1abcdff6ebaed6 Mon Sep 17 00:00:00 2001 From: juzeon <812312770@qq.com> Date: Mon, 7 Mar 2022 09:10:22 +0800 Subject: [PATCH 2/7] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=208=E4=BD=8D=E5=AF=84?= =?UTF-8?q?=E5=AD=98=E5=99=A8?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- README.md | 10 +- adder/adder.qws | 4 + adder/db/adder.tmw_info | 6 + data_selector/data_selector.qsf | 3 +- data_selector/data_selector.qws | 10 + register_8b/db/register_8b.(0).cnf.cdb | Bin 0 -> 1120 bytes register_8b/db/register_8b.(0).cnf.hdb | Bin 0 -> 743 bytes register_8b/db/register_8b.asm.qmsg | 7 + register_8b/db/register_8b.asm_labs.ddb | Bin 0 -> 3779 bytes register_8b/db/register_8b.cbx.xml | 5 + register_8b/db/register_8b.cmp.bpm | Bin 0 -> 576 bytes register_8b/db/register_8b.cmp.cdb | Bin 0 -> 4557 bytes register_8b/db/register_8b.cmp.ecobp | Bin 0 -> 28 bytes register_8b/db/register_8b.cmp.hdb | Bin 0 -> 6922 bytes register_8b/db/register_8b.cmp.kpt | 10 + register_8b/db/register_8b.cmp.logdb | 1 + register_8b/db/register_8b.cmp.rdb | Bin 0 -> 15791 bytes register_8b/db/register_8b.cmp.tdb | Bin 0 -> 3307 bytes register_8b/db/register_8b.cmp0.ddb | Bin 0 -> 53718 bytes register_8b/db/register_8b.cmp2.ddb | Bin 0 -> 41256 bytes register_8b/db/register_8b.cmp_merge.kpt | 10 + register_8b/db/register_8b.db_info | 3 + register_8b/db/register_8b.eco.cdb | Bin 0 -> 175 bytes register_8b/db/register_8b.fit.qmsg | 41 + register_8b/db/register_8b.hier_info | 43 + register_8b/db/register_8b.hif | 42 + register_8b/db/register_8b.lpc.html | 18 + register_8b/db/register_8b.lpc.rdb | Bin 0 -> 399 bytes register_8b/db/register_8b.lpc.txt | 5 + register_8b/db/register_8b.map.bpm | Bin 0 -> 561 bytes register_8b/db/register_8b.map.cdb | Bin 0 -> 1205 bytes register_8b/db/register_8b.map.ecobp | Bin 0 -> 28 bytes register_8b/db/register_8b.map.hdb | Bin 0 -> 6564 bytes register_8b/db/register_8b.map.kpt | 154 +++ register_8b/db/register_8b.map.logdb | 1 + register_8b/db/register_8b.map.qmsg | 7 + register_8b/db/register_8b.map_bb.cdb | Bin 0 -> 688 bytes register_8b/db/register_8b.map_bb.hdb | Bin 0 -> 6061 bytes register_8b/db/register_8b.map_bb.logdb | 1 + register_8b/db/register_8b.pre_map.cdb | Bin 0 -> 1063 bytes register_8b/db/register_8b.pre_map.hdb | Bin 0 -> 6683 bytes register_8b/db/register_8b.rtlv.hdb | Bin 0 -> 6680 bytes register_8b/db/register_8b.rtlv_sg.cdb | Bin 0 -> 974 bytes register_8b/db/register_8b.rtlv_sg_swap.cdb | Bin 0 -> 192 bytes register_8b/db/register_8b.sgdiff.cdb | Bin 0 -> 958 bytes register_8b/db/register_8b.sgdiff.hdb | Bin 0 -> 6711 bytes .../db/register_8b.sld_design_entry.sci | Bin 0 -> 168 bytes .../db/register_8b.sld_design_entry_dsc.sci | Bin 0 -> 168 bytes register_8b/db/register_8b.syn_hier_info | 0 register_8b/db/register_8b.tan.qmsg | 10 + register_8b/db/register_8b.tis_db_list.ddb | Bin 0 -> 188 bytes register_8b/incremental_db/README | 11 + .../register_8b.root_partition.cmp.atm | Bin 0 -> 6467 bytes .../register_8b.root_partition.cmp.dfp | Bin 0 -> 33 bytes .../register_8b.root_partition.cmp.hdbx | Bin 0 -> 1872 bytes .../register_8b.root_partition.cmp.kpt | 10 + .../register_8b.root_partition.cmp.logdb | 1 + .../register_8b.root_partition.cmp.rcf | Bin 0 -> 1164 bytes .../register_8b.root_partition.map.atm | Bin 0 -> 3540 bytes .../register_8b.root_partition.map.dpi | Bin 0 -> 716 bytes .../register_8b.root_partition.map.hdbx | Bin 0 -> 1659 bytes .../register_8b.root_partition.map.kpt | 154 +++ register_8b/register_8b.asm.rpt | 129 +++ register_8b/register_8b.bdf | 1004 +++++++++++++++++ register_8b/register_8b.done | 1 + register_8b/register_8b.fit.rpt | 952 ++++++++++++++++ register_8b/register_8b.fit.smsg | 6 + register_8b/register_8b.fit.summary | 16 + register_8b/register_8b.flow.rpt | 120 ++ register_8b/register_8b.map.rpt | 218 ++++ register_8b/register_8b.map.summary | 14 + register_8b/register_8b.pin | 278 +++++ register_8b/register_8b.pof | Bin 0 -> 524488 bytes register_8b/register_8b.qpf | 30 + register_8b/register_8b.qsf | 53 + register_8b/register_8b.sof | Bin 0 -> 240789 bytes register_8b/register_8b.tan.rpt | 216 ++++ register_8b/register_8b.tan.summary | 46 + 78 files changed, 3648 insertions(+), 2 deletions(-) create mode 100644 adder/adder.qws create mode 100644 adder/db/adder.tmw_info create mode 100644 register_8b/db/register_8b.(0).cnf.cdb create mode 100644 register_8b/db/register_8b.(0).cnf.hdb create mode 100644 register_8b/db/register_8b.asm.qmsg create mode 100644 register_8b/db/register_8b.asm_labs.ddb create mode 100644 register_8b/db/register_8b.cbx.xml create mode 100644 register_8b/db/register_8b.cmp.bpm create mode 100644 register_8b/db/register_8b.cmp.cdb create mode 100644 register_8b/db/register_8b.cmp.ecobp create mode 100644 register_8b/db/register_8b.cmp.hdb create mode 100644 register_8b/db/register_8b.cmp.kpt create mode 100644 register_8b/db/register_8b.cmp.logdb create mode 100644 register_8b/db/register_8b.cmp.rdb create mode 100644 register_8b/db/register_8b.cmp.tdb create mode 100644 register_8b/db/register_8b.cmp0.ddb create mode 100644 register_8b/db/register_8b.cmp2.ddb create mode 100644 register_8b/db/register_8b.cmp_merge.kpt create mode 100644 register_8b/db/register_8b.db_info create mode 100644 register_8b/db/register_8b.eco.cdb create mode 100644 register_8b/db/register_8b.fit.qmsg create mode 100644 register_8b/db/register_8b.hier_info create mode 100644 register_8b/db/register_8b.hif create mode 100644 register_8b/db/register_8b.lpc.html create mode 100644 register_8b/db/register_8b.lpc.rdb create mode 100644 register_8b/db/register_8b.lpc.txt create mode 100644 register_8b/db/register_8b.map.bpm create mode 100644 register_8b/db/register_8b.map.cdb create mode 100644 register_8b/db/register_8b.map.ecobp create mode 100644 register_8b/db/register_8b.map.hdb create mode 100644 register_8b/db/register_8b.map.kpt create mode 100644 register_8b/db/register_8b.map.logdb create mode 100644 register_8b/db/register_8b.map.qmsg create mode 100644 register_8b/db/register_8b.map_bb.cdb create mode 100644 register_8b/db/register_8b.map_bb.hdb create mode 100644 register_8b/db/register_8b.map_bb.logdb create mode 100644 register_8b/db/register_8b.pre_map.cdb create mode 100644 register_8b/db/register_8b.pre_map.hdb create mode 100644 register_8b/db/register_8b.rtlv.hdb create mode 100644 register_8b/db/register_8b.rtlv_sg.cdb create mode 100644 register_8b/db/register_8b.rtlv_sg_swap.cdb create mode 100644 register_8b/db/register_8b.sgdiff.cdb create mode 100644 register_8b/db/register_8b.sgdiff.hdb create mode 100644 register_8b/db/register_8b.sld_design_entry.sci create mode 100644 register_8b/db/register_8b.sld_design_entry_dsc.sci create mode 100644 register_8b/db/register_8b.syn_hier_info create mode 100644 register_8b/db/register_8b.tan.qmsg create mode 100644 register_8b/db/register_8b.tis_db_list.ddb create mode 100644 register_8b/incremental_db/README create mode 100644 register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.atm create mode 100644 register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.dfp create mode 100644 register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.hdbx create mode 100644 register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.kpt create mode 100644 register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.logdb create mode 100644 register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.rcf create mode 100644 register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.atm create mode 100644 register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.dpi create mode 100644 register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.hdbx create mode 100644 register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.kpt create mode 100644 register_8b/register_8b.asm.rpt create mode 100644 register_8b/register_8b.bdf create mode 100644 register_8b/register_8b.done create mode 100644 register_8b/register_8b.fit.rpt create mode 100644 register_8b/register_8b.fit.smsg create mode 100644 register_8b/register_8b.fit.summary create mode 100644 register_8b/register_8b.flow.rpt create mode 100644 register_8b/register_8b.map.rpt create mode 100644 register_8b/register_8b.map.summary create mode 100644 register_8b/register_8b.pin create mode 100644 register_8b/register_8b.pof create mode 100644 register_8b/register_8b.qpf create mode 100644 register_8b/register_8b.qsf create mode 100644 register_8b/register_8b.sof create mode 100644 register_8b/register_8b.tan.rpt create mode 100644 register_8b/register_8b.tan.summary diff --git a/README.md b/README.md index b33db2d..72d5852 100644 --- a/README.md +++ b/README.md @@ -1,3 +1,11 @@ # quartus -计组课设。 \ No newline at end of file +计组课设。 + +### adder + +8ä½åŠ æ³•è®¡ç®—器。 + +### data_selector + +8ä½æ•°æ®é€‰æ‹©å™¨ï¼ˆäºŒé€‰ä¸€ï¼‰ã€‚ \ No newline at end of file diff --git a/adder/adder.qws b/adder/adder.qws new file mode 100644 index 0000000..fc216dc --- /dev/null +++ b/adder/adder.qws @@ -0,0 +1,4 @@ +[ProjectWorkspace] +ptn_Child1=Frames +[ProjectWorkspace.Frames] +ptn_Child1=ChildFrames diff --git a/adder/db/adder.tmw_info b/adder/db/adder.tmw_info new file mode 100644 index 0000000..f9d7d70 --- /dev/null +++ b/adder/db/adder.tmw_info @@ -0,0 +1,6 @@ +start_full_compilation:s:00:00:06 +start_analysis_synthesis:s:00:00:02-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:02-start_full_compilation +start_assembler:s:00:00:01-start_full_compilation +start_timing_analyzer:s:00:00:01-start_full_compilation diff --git a/data_selector/data_selector.qsf b/data_selector/data_selector.qsf index acc75cb..a1faa02 100644 --- a/data_selector/data_selector.qsf +++ b/data_selector/data_selector.qsf @@ -53,4 +53,5 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" -set_global_assignment -name MISC_FILE "D:/projects/quartus/data_selector/data_selector.dpf" \ No newline at end of file +set_global_assignment -name MISC_FILE "D:/projects/quartus/data_selector/data_selector.dpf" +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" \ No newline at end of file diff --git a/data_selector/data_selector.qws b/data_selector/data_selector.qws index fc216dc..42962c6 100644 --- a/data_selector/data_selector.qws +++ b/data_selector/data_selector.qws @@ -2,3 +2,13 @@ ptn_Child1=Frames [ProjectWorkspace.Frames] ptn_Child1=ChildFrames +[ProjectWorkspace.Frames.ChildFrames] +ptn_Child1=Document-0 +[ProjectWorkspace.Frames.ChildFrames.Document-0] +ptn_Child1=ViewFrame-0 +[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0] +DocPathName=data_selector.bdf +DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde} 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mode 100644 index 0000000..901c895 --- /dev/null +++ b/register_8b/db/register_8b.cmp_merge.kpt @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/register_8b/db/register_8b.db_info b/register_8b/db/register_8b.db_info new file mode 100644 index 0000000..12b4a80 --- /dev/null +++ b/register_8b/db/register_8b.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +Version_Index = 167832322 +Creation_Time = Mon Mar 07 09:08:50 2022 diff --git a/register_8b/db/register_8b.eco.cdb b/register_8b/db/register_8b.eco.cdb new file mode 100644 index 0000000000000000000000000000000000000000..6612017e10ee479d46d8c5c373ee2759c1d1f0db GIT binary patch literal 175 zcmd;QU|?9w&B%}kg!VvoSZYymW`3T6rJjL;Q)y;Sih_}`se*x-zM;9kk%57wLU3wP zS!QyoLO^12wt|sDu$Mx3YLbF$N@fXAn<&r(5U7Pv43 inst.ACLR +CLR => inst.PRESET +CLR => inst2.ACLR +CLR => inst2.PRESET +CLR => inst3.ACLR +CLR => inst3.PRESET +CLR => inst4.ACLR +CLR => inst4.PRESET +CLR => inst5.ACLR +CLR => inst5.PRESET +CLR => inst6.ACLR +CLR => inst6.PRESET +CLR => inst7.ACLR +CLR => inst7.PRESET +CLR => inst8.ACLR +CLR => inst8.PRESET +CP => inst.CLK +CP => inst2.CLK +CP => inst3.CLK +CP => inst4.CLK +CP => inst5.CLK +CP => inst6.CLK +CP => inst7.CLK +CP => inst8.CLK +D7 => inst.DATAIN +Q6 <= inst2.DB_MAX_OUTPUT_PORT_TYPE +D6 => inst2.DATAIN +Q5 <= inst3.DB_MAX_OUTPUT_PORT_TYPE +D5 => inst3.DATAIN +Q4 <= inst4.DB_MAX_OUTPUT_PORT_TYPE +D4 => inst4.DATAIN +Q3 <= inst5.DB_MAX_OUTPUT_PORT_TYPE +D3 => inst5.DATAIN +Q2 <= inst6.DB_MAX_OUTPUT_PORT_TYPE +D2 => inst6.DATAIN +Q1 <= inst7.DB_MAX_OUTPUT_PORT_TYPE +D1 => inst7.DATAIN +Q0 <= inst8.DB_MAX_OUTPUT_PORT_TYPE +D0 => inst8.DATAIN + + diff --git a/register_8b/db/register_8b.hif b/register_8b/db/register_8b.hif new file mode 100644 index 0000000..fedb6d4 --- /dev/null +++ b/register_8b/db/register_8b.hif @@ -0,0 +1,42 @@ +Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +11 +936 +OFF +OFF +OFF +ON +ON +ON +FV_OFF +Level2 +0 +0 +VRSM_ON +VHSM_ON +0 +-- Start Library Paths -- +-- End Library Paths -- +-- Start VHDL Libraries -- +-- End VHDL Libraries -- +# entity +register_8b +# storage +db|register_8b.(0).cnf +db|register_8b.(0).cnf +# case_insensitive +# source_file +register_8b.bdf +15bb6d6fc64f9448fba2946de88c4c4d +26 +# internal_option { +BLOCK_DESIGN_NAMING +AUTO +} +# hierarchies { +| +} +# macro_sequence + +# end +# complete + \ No newline at end of file diff --git a/register_8b/db/register_8b.lpc.html b/register_8b/db/register_8b.lpc.html new file mode 100644 index 0000000..fd4875d --- /dev/null +++ b/register_8b/db/register_8b.lpc.html @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
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/dev/null +++ b/register_8b/db/register_8b.map.qmsg @@ -0,0 +1,7 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 09:09:53 2022 " "Info: Processing started: Mon Mar 07 09:09:53 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off register_8b -c register_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off register_8b -c register_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "register_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file register_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 register_8b " "Info: Found entity 1: register_8b" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_TOP" "register_8b " "Info: Elaborating entity \"register_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} +{ "Info" "ICUT_CUT_TM_SUMMARY" "26 " "Info: Implemented 26 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Info: Implemented 10 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "248 " "Info: Peak virtual memory: 248 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 09:09:53 2022 " "Info: Processing ended: Mon Mar 07 09:09:53 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 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To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.atm b/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.atm new file mode 100644 index 0000000000000000000000000000000000000000..63f53b75781f0f0f8d680862bb8f3ef239c20ef4 GIT binary patch literal 6467 zcmYkAWmFVi)b8mX7`mmAW!FlLqAs)6)NCzNpS3-eYWh*`*=$9|QV`%+IS>C=a+l!gZSlt@=Yn9qumNKByxWX|Mik*PAs}5 zzuoc`ORM~A$u4g`Oh?U^t{>(mQqiYju8n#=UedibuGGxD6u&vP=zN_}{9An_!c!_c z7Nzwwse1j;XYJSE-MBF72kV^zicvlO+s^dtStqVmrc!(lh4uw3xe|5JZ>KiBb+R*f z=`Yrt;#wl5O;PxZQ;@77?(xVJ)cb=i(;Y^dd2s7usrYIOu8wUva5uIRMx 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+ + + + + + inst5 + + + inst6 + + + inst3 + + + inst4 + + + inst2 + + + inst7 + + + inst8 + + + inst + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/register_8b/register_8b.asm.rpt b/register_8b/register_8b.asm.rpt new file mode 100644 index 0000000..f1a493e --- /dev/null +++ b/register_8b/register_8b.asm.rpt @@ -0,0 +1,129 @@ +Assembler report for register_8b +Mon Mar 07 09:09:56 2022 +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: D:/projects/quartus/register_8b/register_8b.sof + 6. Assembler Device Options: D:/projects/quartus/register_8b/register_8b.pof + 7. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Mon Mar 07 09:09:56 2022 ; +; Revision Name ; register_8b ; +; Top-level Entity Name ; register_8b ; +; Family ; Cyclone II ; +; Device ; EP2C8Q208C8 ; ++-----------------------+---------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Option ; Setting ; Default Value ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Use smart compilation ; Off ; Off ; +; Generate compressed bitstreams ; On ; On ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; Auto user code ; Off ; Off ; +; Use configuration device ; On ; On ; +; Configuration device ; Auto ; Auto ; +; Configuration device auto user code ; Off ; Off ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File start address ; 0 ; 0 ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Release clears before tri-states ; Off ; Off ; +; Auto-restart configuration after error ; On ; On ; +; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; ++-----------------------------------------------------------------------------+----------+---------------+ + + ++-------------------------------------------------+ +; Assembler Generated Files ; ++-------------------------------------------------+ +; File Name ; ++-------------------------------------------------+ +; D:/projects/quartus/register_8b/register_8b.sof ; +; D:/projects/quartus/register_8b/register_8b.pof ; ++-------------------------------------------------+ + + ++---------------------------------------------------------------------------+ +; Assembler Device Options: D:/projects/quartus/register_8b/register_8b.sof ; ++----------------+----------------------------------------------------------+ +; Option ; Setting ; ++----------------+----------------------------------------------------------+ +; Device ; EP2C8Q208C8 ; +; JTAG usercode ; 0xFFFFFFFF ; +; Checksum ; 0x000C5E44 ; ++----------------+----------------------------------------------------------+ + + ++---------------------------------------------------------------------------+ +; Assembler Device Options: D:/projects/quartus/register_8b/register_8b.pof ; ++--------------------+------------------------------------------------------+ +; Option ; Setting ; ++--------------------+------------------------------------------------------+ +; Device ; EPCS4 ; +; JTAG usercode ; 0x00000000 ; +; Checksum ; 0x06F0F18E ; +; Compression Ratio ; 3 ; ++--------------------+------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II Assembler + Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + Info: Processing started: Mon Mar 07 09:09:56 2022 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off register_8b -c register_8b +Info: Writing out detailed assembly data for power analysis +Info: Assembler is generating device programming files +Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled +Info: Quartus II Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 241 megabytes + Info: Processing ended: Mon Mar 07 09:09:56 2022 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:00 + + diff --git a/register_8b/register_8b.bdf b/register_8b/register_8b.bdf new file mode 100644 index 0000000..58d2990 --- /dev/null +++ b/register_8b/register_8b.bdf @@ -0,0 +1,1004 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. 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344) + (pt 376 352) +) +(connector + (pt 280 440) + (pt 280 536) +) +(connector + (pt 280 536) + (pt 280 632) +) +(connector + (pt 280 40) + (pt 280 152) +) +(connector + (pt 280 152) + (pt 280 248) +) +(connector + (pt 280 248) + (pt 280 344) +) +(connector + (pt 280 344) + (pt 280 440) +) +(connector + (pt 376 16) + (pt 376 40) +) +(connector + (pt 376 40) + (pt 376 64) +) +(junction (pt 248 680)) +(junction (pt 248 584)) +(junction (pt 248 488)) +(junction (pt 248 392)) +(junction (pt 248 296)) +(junction (pt 248 104)) +(junction (pt 248 200)) +(junction (pt 376 728)) +(junction (pt 376 152)) +(junction (pt 376 632)) +(junction (pt 376 536)) +(junction (pt 376 440)) +(junction (pt 376 248)) +(junction (pt 280 632)) +(junction (pt 280 536)) +(junction (pt 280 728)) +(junction (pt 376 344)) +(junction (pt 280 440)) +(junction (pt 280 344)) +(junction (pt 280 152)) +(junction (pt 280 248)) +(junction (pt 376 40)) diff --git a/register_8b/register_8b.done b/register_8b/register_8b.done new file mode 100644 index 0000000..3113f2a --- /dev/null +++ b/register_8b/register_8b.done @@ -0,0 +1 @@ +Mon Mar 07 09:09:58 2022 diff --git a/register_8b/register_8b.fit.rpt b/register_8b/register_8b.fit.rpt new file mode 100644 index 0000000..3f251e1 --- /dev/null +++ b/register_8b/register_8b.fit.rpt @@ -0,0 +1,952 @@ +Fitter report for register_8b +Mon Mar 07 09:09:55 2022 +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Input Pins + 11. Output Pins + 12. I/O Bank Usage + 13. All Package Pins + 14. Output Pin Default Load For Reported TCO + 15. Fitter Resource Utilization by Entity + 16. Delay Chain Summary + 17. Pad To Core Delay Chain Fanout + 18. Control Signals + 19. Global & Other Fast Signals + 20. Non-Global High Fan-Out Signals + 21. Interconnect Usage Summary + 22. LAB Logic Elements + 23. LAB-wide Signals + 24. LAB Signals Sourced + 25. LAB Signals Sourced Out + 26. LAB Distinct Inputs + 27. Fitter Device Options + 28. Operating Settings and Conditions + 29. Estimated Delay Added for Hold Timing + 30. Advanced Data - General + 31. Advanced Data - Placement Preparation + 32. Advanced Data - Placement + 33. Advanced Data - Routing + 34. Fitter Messages + 35. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+----------------------------------------------+ +; Fitter Status ; Successful - Mon Mar 07 09:09:55 2022 ; +; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; +; Revision Name ; register_8b ; +; Top-level Entity Name ; register_8b ; +; Family ; Cyclone II ; +; Device ; EP2C8Q208C8 ; +; Timing Models ; Final ; +; Total logic elements ; 8 / 8,256 ( < 1 % ) ; +; Total combinational functions ; 0 / 8,256 ( 0 % ) ; +; Dedicated logic registers ; 8 / 8,256 ( < 1 % ) ; +; Total registers ; 8 ; +; Total pins ; 18 / 138 ( 13 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 165,888 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; +; Total PLLs ; 0 / 2 ( 0 % ) ; ++------------------------------------+----------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Device ; EP2C8Q208C8 ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Use TimeQuest Timing Analyzer ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Always Enable Input Buffers ; Off ; Off ; +; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; +; Optimize Multi-Corner Timing ; Off ; Off ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; On ; On ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Global Memory Control Signals ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Merge PLLs ; On ; On ; +; Ignore PLL Mode When Merging PLLs ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Stop After Congestion Map Generation ; Off ; Off ; +; Save Intermediate Fitting Results ; Off ; Off ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; 1 processor ; 100.0% ; +; 2-4 processors ; < 0.1% ; ++----------------------------+-------------+ + + ++----------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++-------------------------+--------------------+ +; Type ; Value ; ++-------------------------+--------------------+ +; Placement ; ; +; -- Requested ; 0 / 26 ( 0.00 % ) ; +; -- Achieved ; 0 / 26 ( 0.00 % ) ; +; ; ; +; Routing (by Connection) ; ; +; -- Requested ; 0 / 0 ( 0.00 % ) ; +; -- Achieved ; 0 / 0 ( 0.00 % ) ; ++-------------------------+--------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ + + ++--------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++----------------+---------+-------------------+-------------------------+-------------------+ +; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; ++----------------+---------+-------------------+-------------------------+-------------------+ +; Top ; 26 ; 0 ; N/A ; Source File ; ++----------------+---------+-------------------+-------------------------+-------------------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in D:/projects/quartus/register_8b/register_8b.pin. + + ++-------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+---------------------+ +; Resource ; Usage ; ++---------------------------------------------+---------------------+ +; Total logic elements ; 8 / 8,256 ( < 1 % ) ; +; -- Combinational with no register ; 0 ; +; -- Register only ; 8 ; +; -- Combinational with a register ; 0 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 0 ; +; -- 3 input functions ; 0 ; +; -- <=2 input functions ; 0 ; +; -- Register only ; 8 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 0 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 8 / 8,646 ( < 1 % ) ; +; -- Dedicated logic registers ; 8 / 8,256 ( < 1 % ) ; +; -- I/O registers ; 0 / 390 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 8 / 516 ( 2 % ) ; +; User inserted logic elements ; 0 ; +; Virtual pins ; 0 ; +; I/O pins ; 18 / 138 ( 13 % ) ; +; -- Clock pins ; 2 / 4 ( 50 % ) ; +; Global signals ; 2 ; +; M4Ks ; 0 / 36 ( 0 % ) ; +; Total block memory bits ; 0 / 165,888 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 165,888 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; +; PLLs ; 0 / 2 ( 0 % ) ; +; Global clocks ; 2 / 8 ( 25 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Maximum fan-out node ; CLR~clkctrl ; +; Maximum fan-out ; 8 ; +; Highest non-global fan-out signal ; inst ; +; Highest non-global fan-out ; 1 ; +; Total fan-out ; 39 ; +; Average fan-out ; 1.08 ; ++---------------------------------------------+---------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ; ++------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; CLR ; 24 ; 1 ; 0 ; 9 ; 1 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; CP ; 23 ; 1 ; 0 ; 9 ; 0 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; D0 ; 205 ; 2 ; 1 ; 19 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; D1 ; 28 ; 1 ; 0 ; 9 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; D2 ; 27 ; 1 ; 0 ; 9 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; D3 ; 96 ; 4 ; 30 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; D4 ; 15 ; 1 ; 0 ; 14 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; D5 ; 68 ; 4 ; 12 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; D6 ; 34 ; 1 ; 0 ; 7 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; D7 ; 48 ; 1 ; 0 ; 2 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; ++------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; ++------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ +; Q0 ; 45 ; 1 ; 0 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Q1 ; 14 ; 1 ; 0 ; 14 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Q2 ; 188 ; 2 ; 12 ; 19 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Q3 ; 147 ; 3 ; 34 ; 15 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Q4 ; 145 ; 3 ; 34 ; 14 ; 4 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Q5 ; 47 ; 1 ; 0 ; 2 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Q6 ; 74 ; 4 ; 16 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Q7 ; 56 ; 4 ; 1 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; ++------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1 ; 12 / 32 ( 38 % ) ; 3.3V ; -- ; +; 2 ; 2 / 35 ( 6 % ) ; 3.3V ; -- ; +; 3 ; 3 / 35 ( 9 % ) ; 3.3V ; -- ; +; 4 ; 4 / 36 ( 11 % ) ; 3.3V ; -- ; ++----------+------------------+---------------+--------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; 1 ; 0 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; 2 ; 1 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; 3 ; 2 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 4 ; 3 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 5 ; 4 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 6 ; 5 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 8 ; 6 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 10 ; 7 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 11 ; 8 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 12 ; 9 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 13 ; 10 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 14 ; 18 ; 1 ; Q1 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 15 ; 19 ; 1 ; D4 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; 18 ; 22 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; 19 ; 23 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; 20 ; 24 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ; +; 21 ; 25 ; 1 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ; +; 22 ; 26 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; 23 ; 27 ; 1 ; CP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 24 ; 28 ; 1 ; CLR ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 26 ; 29 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; 27 ; 30 ; 1 ; D2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 28 ; 31 ; 1 ; D1 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 30 ; 32 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 31 ; 33 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 33 ; 35 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 34 ; 36 ; 1 ; D6 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 35 ; 37 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 37 ; 39 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 39 ; 43 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 40 ; 44 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 41 ; 45 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 42 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 43 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 44 ; 49 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 45 ; 50 ; 1 ; Q0 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 46 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 47 ; 52 ; 1 ; Q5 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 48 ; 53 ; 1 ; D7 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 49 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 50 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; 51 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 52 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; 53 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 54 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; 55 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 56 ; 54 ; 4 ; Q7 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 57 ; 55 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 58 ; 56 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 59 ; 57 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 60 ; 58 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 61 ; 59 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 63 ; 60 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 64 ; 61 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 67 ; 69 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 68 ; 70 ; 4 ; D5 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 69 ; 71 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 70 ; 74 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 71 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 72 ; 75 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 74 ; 76 ; 4 ; Q6 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 75 ; 77 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 76 ; 78 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 77 ; 79 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 80 ; 82 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 81 ; 83 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 82 ; 84 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 83 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 84 ; 85 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 85 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 86 ; 86 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 87 ; 87 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 88 ; 88 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 89 ; 89 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 90 ; 90 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 91 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 92 ; 91 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 94 ; 92 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 95 ; 93 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 96 ; 94 ; 4 ; D3 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 97 ; 95 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 98 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 99 ; 96 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 100 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 101 ; 97 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 102 ; 98 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 103 ; 99 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 104 ; 100 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 105 ; 101 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 106 ; 102 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 107 ; 105 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 108 ; 106 ; 3 ; ~LVDS54p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 109 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 110 ; 107 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 111 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 112 ; 108 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 113 ; 109 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 114 ; 110 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 115 ; 112 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 116 ; 113 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 117 ; 114 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 118 ; 117 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 119 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 120 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 121 ; 121 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; 122 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 123 ; 122 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; 124 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 125 ; 123 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; 126 ; 124 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; 127 ; 125 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 128 ; 126 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 129 ; 127 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 130 ; 128 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 131 ; 129 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 132 ; 130 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 133 ; 131 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 134 ; 132 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 135 ; 133 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 136 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 137 ; 134 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 138 ; 135 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 139 ; 136 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 141 ; 137 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 142 ; 138 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 143 ; 141 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 144 ; 142 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 145 ; 143 ; 3 ; Q4 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 146 ; 149 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 147 ; 150 ; 3 ; Q3 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 148 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 149 ; 151 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 150 ; 152 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 151 ; 153 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 152 ; 154 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 153 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 154 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; 155 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 156 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; 157 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 158 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; 159 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 160 ; 155 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 161 ; 156 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 162 ; 157 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 163 ; 158 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 164 ; 159 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 165 ; 160 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 166 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 167 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 168 ; 161 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 169 ; 162 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 170 ; 163 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 171 ; 164 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 172 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 173 ; 165 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 174 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 175 ; 168 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 176 ; 169 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 177 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 178 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 179 ; 173 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 180 ; 174 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 181 ; 175 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 182 ; 176 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 183 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 184 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 185 ; 180 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 186 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 187 ; 181 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 188 ; 182 ; 2 ; Q2 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 189 ; 183 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 190 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 191 ; 184 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 192 ; 185 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 193 ; 186 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 194 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 195 ; 187 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 196 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 197 ; 191 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 198 ; 192 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 199 ; 195 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 200 ; 196 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 201 ; 197 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 202 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 203 ; 198 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 204 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 205 ; 199 ; 2 ; D0 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 206 ; 200 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 207 ; 201 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 208 ; 202 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-------------------------------------------------------------------------------+ +; Output Pin Default Load For Reported TCO ; ++----------------------------------+-------+------------------------------------+ +; I/O Standard ; Load ; Termination Resistance ; ++----------------------------------+-------+------------------------------------+ +; 3.3-V LVTTL ; 0 pF ; Not Available ; +; 3.3-V LVCMOS ; 0 pF ; Not Available ; +; 2.5 V ; 0 pF ; Not Available ; +; 1.8 V ; 0 pF ; Not Available ; +; 1.5 V ; 0 pF ; Not Available ; +; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ; +; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ; +; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ; +; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ; +; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ; +; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ; +; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ; +; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ; +; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ; +; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ; +; LVDS ; 0 pF ; 100 Ohm (Differential) ; +; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ; +; RSDS ; 0 pF ; 100 Ohm (Differential) ; +; Simple RSDS ; 0 pF ; Not Available ; +; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ; ++----------------------------------+-------+------------------------------------+ +Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ +; |register_8b ; 8 (8) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 18 ; 0 ; 0 (0) ; 8 (8) ; 0 (0) ; |register_8b ; work ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++------+----------+---------------+---------------+-----------------------+-----+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; ++------+----------+---------------+---------------+-----------------------+-----+ +; Q7 ; Output ; -- ; -- ; -- ; -- ; +; Q6 ; Output ; -- ; -- ; -- ; -- ; +; Q5 ; Output ; -- ; -- ; -- ; -- ; +; Q4 ; Output ; -- ; -- ; -- ; -- ; +; Q3 ; Output ; -- ; -- ; -- ; -- ; +; Q2 ; Output ; -- ; -- ; -- ; -- ; +; Q1 ; Output ; -- ; -- ; -- ; -- ; +; Q0 ; Output ; -- ; -- ; -- ; -- ; +; D7 ; Input ; 6 ; 6 ; -- ; -- ; +; CP ; Input ; 0 ; 0 ; -- ; -- ; +; CLR ; Input ; 0 ; 0 ; -- ; -- ; +; D6 ; Input ; 6 ; 6 ; -- ; -- ; +; D5 ; Input ; 6 ; 6 ; -- ; -- ; +; D4 ; Input ; 6 ; 6 ; -- ; -- ; +; D3 ; Input ; 6 ; 6 ; -- ; -- ; +; D2 ; Input ; 0 ; 0 ; -- ; -- ; +; D1 ; Input ; 0 ; 0 ; -- ; -- ; +; D0 ; Input ; 6 ; 6 ; -- ; -- ; ++------+----------+---------------+---------------+-----------------------+-----+ + + ++---------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++---------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++---------------------+-------------------+---------+ +; D7 ; ; ; +; - inst~feeder ; 1 ; 6 ; +; CP ; ; ; +; CLR ; ; ; +; D6 ; ; ; +; - inst2~feeder ; 0 ; 6 ; +; D5 ; ; ; +; - inst3 ; 0 ; 6 ; +; D4 ; ; ; +; - inst4~feeder ; 1 ; 6 ; +; D3 ; ; ; +; - inst5 ; 0 ; 6 ; +; D2 ; ; ; +; D1 ; ; ; +; D0 ; ; ; +; - inst8~feeder ; 0 ; 6 ; ++---------------------+-------------------+---------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; CLR ; PIN_24 ; 8 ; Async. clear ; yes ; Global Clock ; GCLK1 ; -- ; +; CP ; PIN_23 ; 8 ; Clock ; yes ; Global Clock ; GCLK2 ; -- ; ++------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++------+----------+---------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++------+----------+---------+----------------------+------------------+---------------------------+ +; CLR ; PIN_24 ; 8 ; Global Clock ; GCLK1 ; -- ; +; CP ; PIN_23 ; 8 ; Global Clock ; GCLK2 ; -- ; ++------+----------+---------+----------------------+------------------+---------------------------+ + + ++---------------------------------+ +; Non-Global High Fan-Out Signals ; ++-------+-------------------------+ +; Name ; Fan-Out ; ++-------+-------------------------+ +; D0 ; 1 ; +; D1 ; 1 ; +; D2 ; 1 ; +; D3 ; 1 ; +; D4 ; 1 ; +; D5 ; 1 ; +; D6 ; 1 ; +; D7 ; 1 ; +; inst8 ; 1 ; +; inst7 ; 1 ; +; inst6 ; 1 ; +; inst5 ; 1 ; +; inst4 ; 1 ; +; inst3 ; 1 ; +; inst2 ; 1 ; +; inst ; 1 ; ++-------+-------------------------+ + + ++----------------------------------------------------+ +; Interconnect Usage Summary ; ++----------------------------+-----------------------+ +; Interconnect Resource Type ; Usage ; ++----------------------------+-----------------------+ +; Block interconnects ; 16 / 26,052 ( < 1 % ) ; +; C16 interconnects ; 3 / 1,156 ( < 1 % ) ; +; C4 interconnects ; 11 / 17,952 ( < 1 % ) ; +; Direct links ; 2 / 26,052 ( < 1 % ) ; +; Global clocks ; 2 / 8 ( 25 % ) ; +; Local interconnects ; 0 / 8,256 ( 0 % ) ; +; R24 interconnects ; 3 / 1,020 ( < 1 % ) ; +; R4 interconnects ; 11 / 22,440 ( < 1 % ) ; ++----------------------------+-----------------------+ + + ++--------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 1.00) ; Number of LABs (Total = 8) ; ++--------------------------------------------+-----------------------------+ +; 1 ; 8 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; ++--------------------------------------------+-----------------------------+ + + ++------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+-----------------------------+ +; LAB-wide Signals (Average = 2.00) ; Number of LABs (Total = 8) ; ++------------------------------------+-----------------------------+ +; 1 Async. clear ; 8 ; +; 1 Clock ; 8 ; ++------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++---------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 1.63) ; Number of LABs (Total = 8) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 3 ; +; 2 ; 5 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 1.00) ; Number of LABs (Total = 8) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 8 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 3.00) ; Number of LABs (Total = 8) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 8 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------+ +; Fitter Device Options ; ++----------------------------------------------+--------------------------+ +; Option ; Setting ; ++----------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; nCEO ; As output driving ground ; +; ASDO,nCSO ; As input tri-stated ; +; Reserve all unused pins ; As output driving ground ; +; Base pin-out file on sameframe device ; Off ; ++----------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing ; ++-----------------+----------------------+-------------------+ +; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; ++-----------------+----------------------+-------------------+ + + ++----------------------------+ +; Advanced Data - General ; ++--------------------+-------+ +; Name ; Value ; ++--------------------+-------+ +; Status Code ; 0 ; +; Desired User Slack ; 0 ; +; Fit Attempts ; 1 ; ++--------------------+-------+ + + ++-------------------------------------------------------------------------------+ +; Advanced Data - Placement Preparation ; ++------------------------------------------------------------------+------------+ +; Name ; Value ; ++------------------------------------------------------------------+------------+ +; Auto Fit Point 1 - Fit Attempt 1 ; ff ; +; Mid Wire Use - Fit Attempt 1 ; 0 ; +; Mid Slack - Fit Attempt 1 ; 2147483639 ; +; Internal Atom Count - Fit Attempt 1 ; 9 ; +; LE/ALM Count - Fit Attempt 1 ; 9 ; +; LAB Count - Fit Attempt 1 ; 9 ; +; Outputs per Lab - Fit Attempt 1 ; 0.889 ; +; Inputs per LAB - Fit Attempt 1 ; 0.889 ; +; Global Inputs per LAB - Fit Attempt 1 ; 1.778 ; +; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:9 ; +; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:9 ; +; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:1;1:8 ; +; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:9 ; +; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:1;2:8 ; +; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:9 ; +; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:9 ; +; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:1;1:8 ; +; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:1;1:8 ; +; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:9 ; +; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:9 ; +; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:9 ; +; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:8 ; +; LEs in Chains - Fit Attempt 1 ; 0 ; +; LEs in Long Chains - Fit Attempt 1 ; 0 ; +; LABs with Chains - Fit Attempt 1 ; 0 ; +; LABs with Multiple Chains - Fit Attempt 1 ; 0 ; +; Time - Fit Attempt 1 ; 0 ; ++------------------------------------------------------------------+------------+ + + ++-------------------------------------------------+ +; Advanced Data - Placement ; ++------------------------------------+------------+ +; Name ; Value ; ++------------------------------------+------------+ +; Auto Fit Point 2 - Fit Attempt 1 ; ff ; +; Auto Fit Point 5 - Fit Attempt 1 ; ff ; +; Mid Wire Use - Fit Attempt 1 ; 0 ; +; Mid Slack - Fit Attempt 1 ; 2147483639 ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Auto Fit Point 5 - Fit Attempt 1 ; ff ; +; Mid Wire Use - Fit Attempt 1 ; 0 ; +; Mid Slack - Fit Attempt 1 ; 2147483639 ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Late Wire Use - Fit Attempt 1 ; 0 ; +; Late Slack - Fit Attempt 1 ; 2147483639 ; +; Peak Regional Wire - Fit Attempt 1 ; 0.000 ; +; Auto Fit Point 7 - Fit Attempt 1 ; ff ; +; Time - Fit Attempt 1 ; 0 ; ++------------------------------------+------------+ + + ++--------------------------------------------------+ +; Advanced Data - Routing ; ++------------------------------------+-------------+ +; Name ; Value ; ++------------------------------------+-------------+ +; Early Wire Use - Fit Attempt 1 ; 0 ; +; Peak Regional Wire - Fit Attempt 1 ; 0 ; +; Early Slack - Fit Attempt 1 ; 2147483639 ; +; Mid Slack - Fit Attempt 1 ; 2147483639 ; +; Late Slack - Fit Attempt 1 ; -2147483648 ; +; Late Wire Use - Fit Attempt 1 ; 0 ; +; Time - Fit Attempt 1 ; 0 ; ++------------------------------------+-------------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Info: ******************************************************************* +Info: Running Quartus II Fitter + Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + Info: Processing started: Mon Mar 07 09:09:54 2022 +Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off register_8b -c register_8b +Info: Parallel compilation is enabled and will use 4 of the 4 processors detected +Info: Selected device EP2C8Q208C8 for design "register_8b" +Info: Low junction temperature is 0 degrees C +Info: High junction temperature is 85 degrees C +Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info: Device EP2C5Q208C8 is compatible + Info: Device EP2C5Q208I8 is compatible + Info: Device EP2C8Q208I8 is compatible +Info: Fitter converted 3 user pins into dedicated programming pins + Info: Pin ~ASDO~ is reserved at location 1 + Info: Pin ~nCSO~ is reserved at location 2 + Info: Pin ~LVDS54p/nCEO~ is reserved at location 108 +Warning: No exact pin location assignment(s) for 18 pins of 18 total pins + Info: Pin Q7 not assigned to an exact location on the device + Info: Pin Q6 not assigned to an exact location on the device + Info: Pin Q5 not assigned to an exact location on the device + Info: Pin Q4 not assigned to an exact location on the device + Info: Pin Q3 not assigned to an exact location on the device + Info: Pin Q2 not assigned to an exact location on the device + Info: Pin Q1 not assigned to an exact location on the device + Info: Pin Q0 not assigned to an exact location on the device + Info: Pin D7 not assigned to an exact location on the device + Info: Pin CP not assigned to an exact location on the device + Info: Pin CLR not assigned to an exact location on the device + Info: Pin D6 not assigned to an exact location on the device + Info: Pin D5 not assigned to an exact location on the device + Info: Pin D4 not assigned to an exact location on the device + Info: Pin D3 not assigned to an exact location on the device + Info: Pin D2 not assigned to an exact location on the device + Info: Pin D1 not assigned to an exact location on the device + Info: Pin D0 not assigned to an exact location on the device +Info: Fitter is using the Classic Timing Analyzer +Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time. +Info: Automatically promoted node CP (placed in PIN 23 (CLK0, LVDSCLK0p, Input)) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2 +Info: Automatically promoted node CLR (placed in PIN 24 (CLK1, LVDSCLK0n, Input)) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1 +Info: Starting register packing +Info: Finished register packing + Extra Info: No registers were packed into other blocks +Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info: Number of I/O pins in group: 16 (unused VREF, 3.3V VCCIO, 8 input, 8 output, 0 bidirectional) + Info: I/O standards used: 3.3-V LVTTL. +Info: I/O bank details before I/O pin placement + Info: Statistics of I/O banks + Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 28 pins available + Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available + Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available + Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available +Info: Fitter preparation operations ending: elapsed time is 00:00:00 +Info: Fitter placement preparation operations beginning +Info: Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info: Fitter placement operations beginning +Info: Fitter placement was successful +Info: Fitter placement operations ending: elapsed time is 00:00:00 +Info: Fitter routing operations beginning +Info: Average interconnect usage is 0% of the available device resources + Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X10_Y19 +Info: Fitter routing operations ending: elapsed time is 00:00:00 +Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info: Optimizations that may affect the design's routability were skipped + Info: Optimizations that may affect the design's timing were skipped +Info: Started post-fitting delay annotation +Warning: Found 8 output pins without output pin load capacitance assignment + Info: Pin "Q7" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "Q6" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "Q5" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "Q4" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "Q3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "Q2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "Q1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "Q0" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis +Info: Delay annotation completed successfully +Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. +Info: Generated suppressed messages file D:/projects/quartus/register_8b/register_8b.fit.smsg +Info: Quartus II Fitter was successful. 0 errors, 3 warnings + Info: Peak virtual memory: 306 megabytes + Info: Processing ended: Mon Mar 07 09:09:55 2022 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in D:/projects/quartus/register_8b/register_8b.fit.smsg. + + diff --git a/register_8b/register_8b.fit.smsg b/register_8b/register_8b.fit.smsg new file mode 100644 index 0000000..14764e7 --- /dev/null +++ b/register_8b/register_8b.fit.smsg @@ -0,0 +1,6 @@ +Extra Info: Performing register packing on registers with non-logic cell location assignments +Extra Info: Completed register packing on registers with non-logic cell location assignments +Extra Info: Started Fast Input/Output/OE register processing +Extra Info: Finished Fast Input/Output/OE register processing +Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/register_8b/register_8b.fit.summary b/register_8b/register_8b.fit.summary new file mode 100644 index 0000000..0cb89f1 --- /dev/null +++ b/register_8b/register_8b.fit.summary @@ -0,0 +1,16 @@ +Fitter Status : Successful - Mon Mar 07 09:09:55 2022 +Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +Revision Name : register_8b +Top-level Entity Name : register_8b +Family : Cyclone II +Device : EP2C8Q208C8 +Timing Models : Final +Total logic elements : 8 / 8,256 ( < 1 % ) + Total combinational functions : 0 / 8,256 ( 0 % ) + Dedicated logic registers : 8 / 8,256 ( < 1 % ) +Total registers : 8 +Total pins : 18 / 138 ( 13 % ) +Total virtual pins : 0 +Total memory bits : 0 / 165,888 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % ) +Total PLLs : 0 / 2 ( 0 % ) diff --git a/register_8b/register_8b.flow.rpt b/register_8b/register_8b.flow.rpt new file mode 100644 index 0000000..6fac536 --- /dev/null +++ b/register_8b/register_8b.flow.rpt @@ -0,0 +1,120 @@ +Flow report for register_8b +Mon Mar 07 09:09:57 2022 +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+----------------------------------------------+ +; Flow Status ; Successful - Mon Mar 07 09:09:57 2022 ; +; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; +; Revision Name ; register_8b ; +; Top-level Entity Name ; register_8b ; +; Family ; Cyclone II ; +; Device ; EP2C8Q208C8 ; +; Timing Models ; Final ; +; Met timing requirements ; Yes ; +; Total logic elements ; 8 / 8,256 ( < 1 % ) ; +; Total combinational functions ; 0 / 8,256 ( 0 % ) ; +; Dedicated logic registers ; 8 / 8,256 ( < 1 % ) ; +; Total registers ; 8 ; +; Total pins ; 18 / 138 ( 13 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 165,888 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; +; Total PLLs ; 0 / 2 ( 0 % ) ; ++------------------------------------+----------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 03/07/2022 09:09:53 ; +; Main task ; Compilation ; +; Revision Name ; register_8b ; ++-------------------+---------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++------------------------------------+---------------------------------+---------------+-------------+----------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++------------------------------------+---------------------------------+---------------+-------------+----------------+ +; COMPILER_SIGNATURE_ID ; 220283517943889.164661539321576 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; +; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ; ++------------------------------------+---------------------------------+---------------+-------------+----------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 245 MB ; 00:00:00 ; +; Fitter ; 00:00:01 ; 1.0 ; 306 MB ; 00:00:01 ; +; Assembler ; 00:00:00 ; 1.0 ; 241 MB ; 00:00:00 ; +; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 198 MB ; 00:00:00 ; +; Total ; 00:00:01 ; -- ; -- ; 00:00:01 ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++------------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++-------------------------+------------------+---------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++-------------------------+------------------+---------------+------------+----------------+ +; Analysis & Synthesis ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; +; Fitter ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; +; Assembler ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; +; Classic Timing Analyzer ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; ++-------------------------+------------------+---------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off register_8b -c register_8b +quartus_fit --read_settings_files=off --write_settings_files=off register_8b -c register_8b +quartus_asm --read_settings_files=off --write_settings_files=off register_8b -c register_8b +quartus_tan --read_settings_files=off --write_settings_files=off register_8b -c register_8b --timing_analysis_only + + + diff --git a/register_8b/register_8b.map.rpt b/register_8b/register_8b.map.rpt new file mode 100644 index 0000000..f38816b --- /dev/null +++ b/register_8b/register_8b.map.rpt @@ -0,0 +1,218 @@ +Analysis & Synthesis report for register_8b +Mon Mar 07 09:09:53 2022 +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Analysis & Synthesis Source Files Read + 5. Analysis & Synthesis Resource Usage Summary + 6. Analysis & Synthesis Resource Utilization by Entity + 7. General Register Statistics + 8. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+----------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Mon Mar 07 09:09:53 2022 ; +; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; +; Revision Name ; register_8b ; +; Top-level Entity Name ; register_8b ; +; Family ; Cyclone II ; +; Total logic elements ; 8 ; +; Total combinational functions ; 0 ; +; Dedicated logic registers ; 8 ; +; Total registers ; 8 ; +; Total pins ; 18 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; ++------------------------------------+----------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++--------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP2C8Q208C8 ; ; +; Top-level entity name ; register_8b ; register_8b ; +; Family name ; Cyclone II ; Stratix II ; +; Use Generated Physical Constraints File ; Off ; ; +; Use smart compilation ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL93 ; VHDL93 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Parallel Synthesis ; Off ; Off ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; Off ; Off ; +; Show Parameter Settings Tables in Synthesis Report ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; ++--------------------------------------------------------------+--------------------+--------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------+-------------------------------------------------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; ++----------------------------------+-----------------+------------------------------------+-------------------------------------------------+ +; register_8b.bdf ; yes ; User Block Diagram/Schematic File ; D:/projects/quartus/register_8b/register_8b.bdf ; ++----------------------------------+-----------------+------------------------------------+-------------------------------------------------+ + + ++-----------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-------+ +; Resource ; Usage ; ++---------------------------------------------+-------+ +; Estimated Total logic elements ; 8 ; +; ; ; +; Total combinational functions ; 0 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 0 ; +; -- 3 input functions ; 0 ; +; -- <=2 input functions ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 0 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 8 ; +; -- Dedicated logic registers ; 8 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 18 ; +; Maximum fan-out node ; CP ; +; Maximum fan-out ; 8 ; +; Total fan-out ; 32 ; +; Average fan-out ; 1.23 ; ++---------------------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ +; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ +; |register_8b ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 18 ; 0 ; |register_8b ; work ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 8 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 8 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Analysis & Synthesis + Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + Info: Processing started: Mon Mar 07 09:09:53 2022 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off register_8b -c register_8b +Info: Found 1 design units, including 1 entities, in source file register_8b.bdf + Info: Found entity 1: register_8b +Info: Elaborating entity "register_8b" for the top level hierarchy +Info: Implemented 26 device resources after synthesis - the final resource count might be different + Info: Implemented 10 input pins + Info: Implemented 8 output pins + Info: Implemented 8 logic cells +Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 248 megabytes + Info: Processing ended: Mon Mar 07 09:09:53 2022 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:00 + + diff --git a/register_8b/register_8b.map.summary b/register_8b/register_8b.map.summary new file mode 100644 index 0000000..c976250 --- /dev/null +++ b/register_8b/register_8b.map.summary @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Mon Mar 07 09:09:53 2022 +Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +Revision Name : register_8b +Top-level Entity Name : register_8b +Family : Cyclone II +Total logic elements : 8 + Total combinational functions : 0 + Dedicated logic registers : 8 +Total registers : 8 +Total pins : 18 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 diff --git a/register_8b/register_8b.pin b/register_8b/register_8b.pin new file mode 100644 index 0000000..1931bb2 --- /dev/null +++ b/register_8b/register_8b.pin @@ -0,0 +1,278 @@ + -- Copyright (C) 1991-2009 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- Bank 3: 3.3V + -- Bank 4: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17), + -- connect each pin marked GND* either individually through a 10k Ohm resistor + -- to GND or tie all pins together and connect through a single 10k Ohm resistor + -- to GND. + -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +CHIP "register_8b" ASSIGNED TO AN: EP2C8Q208C8 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVTTL : : 1 : N +~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVTTL : : 1 : N +GND* : 3 : : : : 1 : +GND* : 4 : : : : 1 : +GND* : 5 : : : : 1 : +GND* : 6 : : : : 1 : +VCCIO1 : 7 : power : : 3.3V : 1 : +GND* : 8 : : : : 1 : +GND : 9 : gnd : : : : +GND* : 10 : : : : 1 : +GND* : 11 : : : : 1 : +GND* : 12 : : : : 1 : +GND* : 13 : : : : 1 : +Q1 : 14 : output : 3.3-V LVTTL : : 1 : N +D4 : 15 : input : 3.3-V LVTTL : : 1 : N +TDO : 16 : output : : : 1 : +TMS : 17 : input : : : 1 : +TCK : 18 : input : : : 1 : +TDI : 19 : input : : : 1 : +DATA0 : 20 : input : : : 1 : +DCLK : 21 : : : : 1 : +nCE : 22 : : : : 1 : +CP : 23 : input : 3.3-V LVTTL : : 1 : N +CLR : 24 : input : 3.3-V LVTTL : : 1 : N +GND : 25 : gnd : : : : +nCONFIG : 26 : : : : 1 : +D2 : 27 : input : 3.3-V LVTTL : : 1 : N +D1 : 28 : input : 3.3-V LVTTL : : 1 : N +VCCIO1 : 29 : power : : 3.3V : 1 : +GND* : 30 : : : : 1 : +GND* : 31 : : : : 1 : +VCCINT : 32 : power : : 1.2V : : +GND* : 33 : : : : 1 : +D6 : 34 : input : 3.3-V LVTTL : : 1 : N +GND* : 35 : : : : 1 : +GND : 36 : gnd : : : : +GND* : 37 : : : : 1 : +GND : 38 : gnd : : : : +GND* : 39 : : : : 1 : +GND* : 40 : : : : 1 : +GND* : 41 : : : : 1 : +VCCIO1 : 42 : power : : 3.3V : 1 : +GND* : 43 : : : : 1 : +GND* : 44 : : : : 1 : +Q0 : 45 : output : 3.3-V LVTTL : : 1 : N +GND* : 46 : : : : 1 : +Q5 : 47 : output : 3.3-V LVTTL : : 1 : N +D7 : 48 : input : 3.3-V LVTTL : : 1 : N +GND : 49 : gnd : : : : +GND_PLL1 : 50 : gnd : : : : +VCCD_PLL1 : 51 : power : : 1.2V : : +GND_PLL1 : 52 : gnd : : : : +VCCA_PLL1 : 53 : power : : 1.2V : : +GNDA_PLL1 : 54 : gnd : : : : +GND : 55 : gnd : : : : +Q7 : 56 : output : 3.3-V LVTTL : : 4 : N +GND* : 57 : : : : 4 : +GND* : 58 : : : : 4 : +GND* : 59 : : : : 4 : +GND* : 60 : : : : 4 : +GND* : 61 : : : : 4 : +VCCIO4 : 62 : power : : 3.3V : 4 : +GND* : 63 : : : : 4 : +GND* : 64 : : : : 4 : +GND : 65 : gnd : : : : +VCCINT : 66 : power : : 1.2V : : +GND* : 67 : : : : 4 : +D5 : 68 : input : 3.3-V LVTTL : : 4 : N +GND* : 69 : : : : 4 : +GND* : 70 : : : : 4 : +VCCIO4 : 71 : power : : 3.3V : 4 : +GND* : 72 : : : : 4 : +GND : 73 : gnd : : : : +Q6 : 74 : output : 3.3-V LVTTL : : 4 : N +GND* : 75 : : : : 4 : +GND* : 76 : : : : 4 : +GND* : 77 : : : : 4 : +GND : 78 : gnd : : : : +VCCINT : 79 : power : : 1.2V : : +GND* : 80 : : : : 4 : +GND* : 81 : : : : 4 : +GND* : 82 : : : : 4 : +VCCIO4 : 83 : power : : 3.3V : 4 : +GND* : 84 : : : : 4 : +GND : 85 : gnd : : : : +GND* : 86 : : : : 4 : +GND* : 87 : : : : 4 : +GND* : 88 : : : : 4 : +GND* : 89 : : : : 4 : +GND* : 90 : : : : 4 : +VCCIO4 : 91 : power : : 3.3V : 4 : +GND* : 92 : : : : 4 : +GND : 93 : gnd : : : : +GND* : 94 : : : : 4 : +GND* : 95 : : : : 4 : +D3 : 96 : input : 3.3-V LVTTL : : 4 : N +GND* : 97 : : : : 4 : +VCCIO4 : 98 : power : : 3.3V : 4 : +GND* : 99 : : : : 4 : +GND : 100 : gnd : : : : +GND* : 101 : : : : 4 : +GND* : 102 : : : : 4 : +GND* : 103 : : : : 4 : +GND* : 104 : : : : 4 : +GND* : 105 : : : : 3 : +GND* : 106 : : : : 3 : +GND* : 107 : : : : 3 : +~LVDS54p/nCEO~ : 108 : output : 3.3-V LVTTL : : 3 : N +VCCIO3 : 109 : power : : 3.3V : 3 : +GND* : 110 : : : : 3 : +GND : 111 : gnd : : : : +GND* : 112 : : : : 3 : +GND* : 113 : : : : 3 : +GND* : 114 : : : : 3 : +GND* : 115 : : : : 3 : +GND* : 116 : : : : 3 : +GND* : 117 : : : : 3 : +GND* : 118 : : : : 3 : +GND : 119 : gnd : : : : +VCCINT : 120 : power : : 1.2V : : +nSTATUS : 121 : : : : 3 : +VCCIO3 : 122 : power : : 3.3V : 3 : +CONF_DONE : 123 : : : : 3 : +GND : 124 : gnd : : : : +MSEL1 : 125 : : : : 3 : +MSEL0 : 126 : : : : 3 : +GND* : 127 : : : : 3 : +GND* : 128 : : : : 3 : +GND+ : 129 : : : : 3 : +GND+ : 130 : : : : 3 : +GND+ : 131 : : : : 3 : +GND+ : 132 : : : : 3 : +GND* : 133 : : : : 3 : +GND* : 134 : : : : 3 : +GND* : 135 : : : : 3 : +VCCIO3 : 136 : power : : 3.3V : 3 : +GND* : 137 : : : : 3 : +GND* : 138 : : : : 3 : +GND* : 139 : : : : 3 : +GND : 140 : gnd : : : : +GND* : 141 : : : : 3 : +GND* : 142 : : : : 3 : +GND* : 143 : : : : 3 : +GND* : 144 : : : : 3 : +Q4 : 145 : output : 3.3-V LVTTL : : 3 : N +GND* : 146 : : : : 3 : +Q3 : 147 : output : 3.3-V LVTTL : : 3 : N +VCCIO3 : 148 : power : : 3.3V : 3 : +GND* : 149 : : : : 3 : +GND* : 150 : : : : 3 : +GND* : 151 : : : : 3 : +GND* : 152 : : : : 3 : +GND : 153 : gnd : : : : +GND_PLL2 : 154 : gnd : : : : +VCCD_PLL2 : 155 : power : : 1.2V : : +GND_PLL2 : 156 : gnd : : : : +VCCA_PLL2 : 157 : power : : 1.2V : : +GNDA_PLL2 : 158 : gnd : : : : +GND : 159 : gnd : : : : +GND* : 160 : : : : 2 : +GND* : 161 : : : : 2 : +GND* : 162 : : : : 2 : +GND* : 163 : : : : 2 : +GND* : 164 : : : : 2 : +GND* : 165 : : : : 2 : +VCCIO2 : 166 : power : : 3.3V : 2 : +GND : 167 : gnd : : : : +GND* : 168 : : : : 2 : +GND* : 169 : : : : 2 : +GND* : 170 : : : : 2 : +GND* : 171 : : : : 2 : +VCCIO2 : 172 : power : : 3.3V : 2 : +GND* : 173 : : : : 2 : +GND : 174 : gnd : : : : +GND* : 175 : : : : 2 : +GND* : 176 : : : : 2 : +GND : 177 : gnd : : : : +VCCINT : 178 : power : : 1.2V : : +GND* : 179 : : : : 2 : +GND* : 180 : : : : 2 : +GND* : 181 : : : : 2 : +GND* : 182 : : : : 2 : +VCCIO2 : 183 : power : : 3.3V : 2 : +GND : 184 : gnd : : : : +GND* : 185 : : : : 2 : +GND : 186 : gnd : : : : +GND* : 187 : : : : 2 : +Q2 : 188 : output : 3.3-V LVTTL : : 2 : N +GND* : 189 : : : : 2 : +VCCINT : 190 : power : : 1.2V : : +GND* : 191 : : : : 2 : +GND* : 192 : : : : 2 : +GND* : 193 : : : : 2 : +VCCIO2 : 194 : power : : 3.3V : 2 : +GND* : 195 : : : : 2 : +GND : 196 : gnd : : : : +GND* : 197 : : : : 2 : +GND* : 198 : : : : 2 : +GND* : 199 : : : : 2 : +GND* : 200 : : : : 2 : +GND* : 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zk^y}M4ppy;4NnzW7&XNj)d!hg^=ep6*)mYhK+dwMNMp&sh9@HTgZ=axHQ-r9#X(XE z_j>dTr*YSjAe)&*4s3X;$crU%{bomGp(!pZ12!{@uGsKIYVy`N>Eu0WK4pnKPe&+VCYr9;ppH z3cR0&4MPB(D|M!;SY^5b`K`OZ-WThFo|HqeFSAVeV)4Lb>Uqb;ZYI1A_ z+@;pyu^n&rEd$4Az#s48X*@XDtfG>jtJEyLy*y>Ih{)?qg1@Za3s=91*1~hiz(p3z zKcVc0=kgA$-4FVckI#89nfOI@;47UN0rk6;OjRh&C6v?d4 t^#czD>1h#kh+K(Z_GmI1F{$b$|W8|35AJi^Bi_ literal 0 HcmV?d00001 diff --git a/register_8b/register_8b.tan.rpt b/register_8b/register_8b.tan.rpt new file mode 100644 index 0000000..2dd1b82 --- /dev/null +++ b/register_8b/register_8b.tan.rpt @@ -0,0 +1,216 @@ +Classic Timing Analyzer report for register_8b +Mon Mar 07 09:09:57 2022 +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Timing Analyzer Settings + 4. Clock Settings Summary + 5. Parallel Compilation + 6. tsu + 7. tco + 8. th + 9. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++------------------------------+-------+---------------+-------------+-------+-------+------------+----------+--------------+ +; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; ++------------------------------+-------+---------------+-------------+-------+-------+------------+----------+--------------+ +; Worst-case tsu ; N/A ; None ; 4.872 ns ; D3 ; inst5 ; -- ; CP ; 0 ; +; Worst-case tco ; N/A ; None ; 8.228 ns ; inst3 ; Q5 ; CP ; -- ; 0 ; +; Worst-case th ; N/A ; None ; 0.406 ns ; D1 ; inst7 ; -- ; CP ; 0 ; +; Total number of failed paths ; ; ; ; ; ; ; ; 0 ; ++------------------------------+-------+---------------+-------------+-------+-------+------------+----------+--------------+ + + ++--------------------------------------------------------------------------------------------------------------------+ +; Timing Analyzer Settings ; ++---------------------------------------------------------------------+--------------------+------+----+-------------+ +; Option ; Setting ; From ; To ; Entity Name ; ++---------------------------------------------------------------------+--------------------+------+----+-------------+ +; Device Name ; EP2C8Q208C8 ; ; ; ; +; Timing Models ; Final ; ; ; ; +; Default hold multicycle ; Same as Multicycle ; ; ; ; +; Cut paths between unrelated clock domains ; On ; ; ; ; +; Cut off read during write signal paths ; On ; ; ; ; +; Cut off feedback from I/O pins ; On ; ; ; ; +; Report Combined Fast/Slow Timing ; Off ; ; ; ; +; Ignore Clock Settings ; Off ; ; ; ; +; Analyze latches as synchronous elements ; On ; ; ; ; +; Enable Recovery/Removal analysis ; Off ; ; ; ; +; Enable Clock Latency ; Off ; ; ; ; +; Use TimeQuest Timing Analyzer ; Off ; ; ; ; +; Minimum Core Junction Temperature ; 0 ; ; ; ; +; Maximum Core Junction Temperature ; 85 ; ; ; ; +; Number of source nodes to report per destination node ; 10 ; ; ; ; +; Number of destination nodes to report ; 10 ; ; ; ; +; Number of paths to report ; 200 ; ; ; ; +; Report Minimum Timing Checks ; Off ; ; ; ; +; Use Fast Timing Models ; Off ; ; ; ; +; Report IO Paths Separately ; Off ; ; ; ; +; Perform Multicorner Analysis ; On ; ; ; ; +; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ; +; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ; +; Output I/O Timing Endpoint ; Near End ; ; ; ; ++---------------------------------------------------------------------+--------------------+------+----+-------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Settings Summary ; ++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ +; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ; ++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ +; CP ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ; ++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; 1 processor ; 100.0% ; +; 2-4 processors ; 0.0% ; ++----------------------------+-------------+ + + ++-------------------------------------------------------------+ +; tsu ; ++-------+--------------+------------+------+-------+----------+ +; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ; ++-------+--------------+------------+------+-------+----------+ +; N/A ; None ; 4.872 ns ; D3 ; inst5 ; CP ; +; N/A ; None ; 4.693 ns ; D0 ; inst8 ; CP ; +; N/A ; None ; 4.628 ns ; D4 ; inst4 ; CP ; +; N/A ; None ; 4.577 ns ; D6 ; inst2 ; CP ; +; N/A ; None ; 4.264 ns ; D5 ; inst3 ; CP ; +; N/A ; None ; 4.007 ns ; D7 ; inst ; CP ; +; N/A ; None ; 1.029 ns ; D2 ; inst6 ; CP ; +; N/A ; None ; -0.140 ns ; D1 ; inst7 ; CP ; ++-------+--------------+------------+------+-------+----------+ + + ++-------------------------------------------------------------+ +; tco ; ++-------+--------------+------------+-------+----+------------+ +; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ; ++-------+--------------+------------+-------+----+------------+ +; N/A ; None ; 8.228 ns ; inst3 ; Q5 ; CP ; +; N/A ; None ; 8.096 ns ; inst2 ; Q6 ; CP ; +; N/A ; None ; 7.981 ns ; inst4 ; Q4 ; CP ; +; N/A ; None ; 7.359 ns ; inst6 ; Q2 ; CP ; +; N/A ; None ; 7.354 ns ; inst ; Q7 ; CP ; +; N/A ; None ; 7.258 ns ; inst5 ; Q3 ; CP ; +; N/A ; None ; 6.982 ns ; inst8 ; Q0 ; CP ; +; N/A ; None ; 6.969 ns ; inst7 ; Q1 ; CP ; ++-------+--------------+------------+-------+----+------------+ + + ++-------------------------------------------------------------------+ +; th ; ++---------------+-------------+-----------+------+-------+----------+ +; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ; ++---------------+-------------+-----------+------+-------+----------+ +; N/A ; None ; 0.406 ns ; D1 ; inst7 ; CP ; +; N/A ; None ; -0.763 ns ; D2 ; inst6 ; CP ; +; N/A ; None ; -3.741 ns ; D7 ; inst ; CP ; +; N/A ; None ; -3.998 ns ; D5 ; inst3 ; CP ; +; N/A ; None ; -4.311 ns ; D6 ; inst2 ; CP ; +; N/A ; None ; -4.362 ns ; D4 ; inst4 ; CP ; +; N/A ; None ; -4.427 ns ; D0 ; inst8 ; CP ; +; N/A ; None ; -4.606 ns ; D3 ; inst5 ; CP ; ++---------------+-------------+-----------+------+-------+----------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Classic Timing Analyzer + Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + Info: Processing started: Mon Mar 07 09:09:57 2022 +Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off register_8b -c register_8b --timing_analysis_only +Info: Parallel compilation is enabled and will use 4 of the 4 processors detected +Warning: Found pins functioning as undefined clocks and/or memory enables + Info: Assuming node "CP" is an undefined clock +Info: No valid register-to-register data paths exist for clock "CP" +Info: tsu for register "inst5" (data pin = "D3", clock pin = "CP") is 4.872 ns + Info: + Longest pin to register delay is 7.782 ns + Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_96; Fanout = 1; PIN Node = 'D3' + Info: 2: + IC(6.338 ns) + CELL(0.460 ns) = 7.782 ns; Loc. = LCFF_X32_Y15_N17; Fanout = 1; REG Node = 'inst5' + Info: Total cell delay = 1.444 ns ( 18.56 % ) + Info: Total interconnect delay = 6.338 ns ( 81.44 % ) + Info: + Micro setup delay of destination is -0.040 ns + Info: - Shortest clock path from clock "CP" to destination register is 2.870 ns + Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CP' + Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CP~clkctrl' + Info: 3: + IC(0.925 ns) + CELL(0.666 ns) = 2.870 ns; Loc. = LCFF_X32_Y15_N17; Fanout = 1; REG Node = 'inst5' + Info: Total cell delay = 1.806 ns ( 62.93 % ) + Info: Total interconnect delay = 1.064 ns ( 37.07 % ) +Info: tco from clock "CP" to destination pin "Q5" through register "inst3" is 8.228 ns + Info: + Longest clock path from clock "CP" to source register is 2.879 ns + Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CP' + Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CP~clkctrl' + Info: 3: + IC(0.934 ns) + CELL(0.666 ns) = 2.879 ns; Loc. = LCFF_X12_Y2_N9; Fanout = 1; REG Node = 'inst3' + Info: Total cell delay = 1.806 ns ( 62.73 % ) + Info: Total interconnect delay = 1.073 ns ( 37.27 % ) + Info: + Micro clock to output delay of source is 0.304 ns + Info: + Longest register to pin delay is 5.045 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y2_N9; Fanout = 1; REG Node = 'inst3' + Info: 2: + IC(1.765 ns) + CELL(3.280 ns) = 5.045 ns; Loc. = PIN_47; Fanout = 0; PIN Node = 'Q5' + Info: Total cell delay = 3.280 ns ( 65.01 % ) + Info: Total interconnect delay = 1.765 ns ( 34.99 % ) +Info: th for register "inst7" (data pin = "D1", clock pin = "CP") is 0.406 ns + Info: + Longest clock path from clock "CP" to destination register is 2.855 ns + Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CP' + Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CP~clkctrl' + Info: 3: + IC(0.910 ns) + CELL(0.666 ns) = 2.855 ns; Loc. = LCFF_X1_Y14_N17; Fanout = 1; REG Node = 'inst7' + Info: Total cell delay = 1.806 ns ( 63.26 % ) + Info: Total interconnect delay = 1.049 ns ( 36.74 % ) + Info: + Micro hold delay of destination is 0.306 ns + Info: - Shortest pin to register delay is 2.755 ns + Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_28; Fanout = 1; PIN Node = 'D1' + Info: 2: + IC(1.301 ns) + CELL(0.206 ns) = 2.647 ns; Loc. = LCCOMB_X1_Y14_N16; Fanout = 1; COMB Node = 'inst7~feeder' + Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 2.755 ns; Loc. = LCFF_X1_Y14_N17; Fanout = 1; REG Node = 'inst7' + Info: Total cell delay = 1.454 ns ( 52.78 % ) + Info: Total interconnect delay = 1.301 ns ( 47.22 % ) +Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning + Info: Peak virtual memory: 212 megabytes + Info: Processing ended: Mon Mar 07 09:09:57 2022 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:00 + + diff --git a/register_8b/register_8b.tan.summary b/register_8b/register_8b.tan.summary new file mode 100644 index 0000000..02ebc11 --- /dev/null +++ b/register_8b/register_8b.tan.summary @@ -0,0 +1,46 @@ +-------------------------------------------------------------------------------------- +Timing Analyzer Summary +-------------------------------------------------------------------------------------- + +Type : Worst-case tsu +Slack : N/A +Required Time : None +Actual Time : 4.872 ns +From : D3 +To : inst5 +From Clock : -- +To Clock : CP +Failed Paths : 0 + +Type : Worst-case tco +Slack : N/A +Required Time : None +Actual Time : 8.228 ns +From : inst3 +To : Q5 +From Clock : CP +To Clock : -- +Failed Paths : 0 + +Type : Worst-case th +Slack : N/A +Required Time : None +Actual Time : 0.406 ns +From : D1 +To : inst7 +From Clock : -- +To Clock : CP +Failed Paths : 0 + +Type : Total number of failed paths +Slack : +Required Time : +Actual Time : +From : +To : +From Clock : +To Clock : +Failed Paths : 0 + +-------------------------------------------------------------------------------------- + From a54ad606525377b235c5a017b5e92999cf9726f8 Mon Sep 17 00:00:00 2001 From: juzeon <812312770@qq.com> Date: Mon, 7 Mar 2022 09:13:35 +0800 Subject: [PATCH 3/7] =?UTF-8?q?add=2038=E8=AF=91=E7=A0=81=E5=99=A8?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- 38_decoder/38_decoder.asm.rpt | 129 +++ 38_decoder/38_decoder.bdf | 886 +++++++++++++++++ 38_decoder/38_decoder.done | 1 + 38_decoder/38_decoder.dpf | 12 + 38_decoder/38_decoder.fit.rpt | 914 ++++++++++++++++++ 38_decoder/38_decoder.fit.smsg | 6 + 38_decoder/38_decoder.fit.summary | 16 + 38_decoder/38_decoder.flow.rpt | 121 +++ 38_decoder/38_decoder.map.rpt | 218 +++++ 38_decoder/38_decoder.map.summary | 14 + 38_decoder/38_decoder.pin | 278 ++++++ 38_decoder/38_decoder.pof | Bin 0 -> 524488 bytes 38_decoder/38_decoder.qpf | 30 + 38_decoder/38_decoder.qsf | 54 ++ 38_decoder/38_decoder.sof | Bin 0 -> 240789 bytes 38_decoder/38_decoder.tan.rpt | 149 +++ 38_decoder/38_decoder.tan.summary | 26 + 38_decoder/db/38_decoder.(0).cnf.cdb | Bin 0 -> 1040 bytes 38_decoder/db/38_decoder.(0).cnf.hdb | Bin 0 -> 725 bytes 38_decoder/db/38_decoder.asm.qmsg | 7 + 38_decoder/db/38_decoder.asm_labs.ddb | Bin 0 -> 3427 bytes 38_decoder/db/38_decoder.cbx.xml | 5 + 38_decoder/db/38_decoder.cmp.bpm | Bin 0 -> 526 bytes 38_decoder/db/38_decoder.cmp.cdb | Bin 0 -> 3008 bytes 38_decoder/db/38_decoder.cmp.ecobp | Bin 0 -> 28 bytes 38_decoder/db/38_decoder.cmp.hdb | Bin 0 -> 6744 bytes 38_decoder/db/38_decoder.cmp.kpt | 10 + 38_decoder/db/38_decoder.cmp.logdb | 1 + 38_decoder/db/38_decoder.cmp.rdb | Bin 0 -> 14924 bytes 38_decoder/db/38_decoder.cmp.tdb | Bin 0 -> 2210 bytes 38_decoder/db/38_decoder.cmp0.ddb | Bin 0 -> 49953 bytes 38_decoder/db/38_decoder.cmp2.ddb | Bin 0 -> 40688 bytes 38_decoder/db/38_decoder.cmp_merge.kpt | 10 + 38_decoder/db/38_decoder.db_info | 3 + 38_decoder/db/38_decoder.eco.cdb | Bin 0 -> 175 bytes 38_decoder/db/38_decoder.fit.qmsg | 39 + 38_decoder/db/38_decoder.hier_info | 26 + 38_decoder/db/38_decoder.hif | 42 + 38_decoder/db/38_decoder.lpc.html | 18 + 38_decoder/db/38_decoder.lpc.rdb | Bin 0 -> 399 bytes 38_decoder/db/38_decoder.lpc.txt | 5 + 38_decoder/db/38_decoder.map.bpm | Bin 0 -> 517 bytes 38_decoder/db/38_decoder.map.cdb | Bin 0 -> 1325 bytes 38_decoder/db/38_decoder.map.ecobp | Bin 0 -> 28 bytes 38_decoder/db/38_decoder.map.hdb | Bin 0 -> 6580 bytes 38_decoder/db/38_decoder.map.kpt | 10 + 38_decoder/db/38_decoder.map.logdb | 1 + 38_decoder/db/38_decoder.map.qmsg | 7 + 38_decoder/db/38_decoder.map_bb.cdb | Bin 0 -> 660 bytes 38_decoder/db/38_decoder.map_bb.hdb | Bin 0 -> 6047 bytes 38_decoder/db/38_decoder.map_bb.logdb | 1 + 38_decoder/db/38_decoder.pre_map.cdb | Bin 0 -> 1051 bytes 38_decoder/db/38_decoder.pre_map.hdb | Bin 0 -> 6736 bytes 38_decoder/db/38_decoder.rtlv.hdb | Bin 0 -> 6734 bytes 38_decoder/db/38_decoder.rtlv_sg.cdb | Bin 0 -> 968 bytes 38_decoder/db/38_decoder.rtlv_sg_swap.cdb | Bin 0 -> 192 bytes 38_decoder/db/38_decoder.sgdiff.cdb | Bin 0 -> 839 bytes 38_decoder/db/38_decoder.sgdiff.hdb | Bin 0 -> 6758 bytes 38_decoder/db/38_decoder.sld_design_entry.sci | Bin 0 -> 168 bytes .../db/38_decoder.sld_design_entry_dsc.sci | Bin 0 -> 168 bytes 38_decoder/db/38_decoder.syn_hier_info | 0 38_decoder/db/38_decoder.tan.qmsg | 6 + 38_decoder/db/38_decoder.tis_db_list.ddb | Bin 0 -> 188 bytes 38_decoder/incremental_db/README | 11 + .../38_decoder.root_partition.cmp.atm | Bin 0 -> 5073 bytes .../38_decoder.root_partition.cmp.dfp | Bin 0 -> 33 bytes .../38_decoder.root_partition.cmp.hdbx | Bin 0 -> 1602 bytes .../38_decoder.root_partition.cmp.kpt | 10 + .../38_decoder.root_partition.cmp.logdb | 1 + .../38_decoder.root_partition.cmp.rcf | Bin 0 -> 754 bytes .../38_decoder.root_partition.map.atm | Bin 0 -> 3511 bytes .../38_decoder.root_partition.map.dpi | Bin 0 -> 688 bytes .../38_decoder.root_partition.map.hdbx | Bin 0 -> 1527 bytes .../38_decoder.root_partition.map.kpt | 10 + register_8b/db/register_8b.tmw_info | 6 + register_8b/register_8b.qws | 4 + 76 files changed, 3087 insertions(+) create mode 100644 38_decoder/38_decoder.asm.rpt create mode 100644 38_decoder/38_decoder.bdf create mode 100644 38_decoder/38_decoder.done create mode 100644 38_decoder/38_decoder.dpf create mode 100644 38_decoder/38_decoder.fit.rpt create mode 100644 38_decoder/38_decoder.fit.smsg create mode 100644 38_decoder/38_decoder.fit.summary create mode 100644 38_decoder/38_decoder.flow.rpt create mode 100644 38_decoder/38_decoder.map.rpt create mode 100644 38_decoder/38_decoder.map.summary create mode 100644 38_decoder/38_decoder.pin create mode 100644 38_decoder/38_decoder.pof create mode 100644 38_decoder/38_decoder.qpf create mode 100644 38_decoder/38_decoder.qsf create mode 100644 38_decoder/38_decoder.sof create mode 100644 38_decoder/38_decoder.tan.rpt create mode 100644 38_decoder/38_decoder.tan.summary create mode 100644 38_decoder/db/38_decoder.(0).cnf.cdb create mode 100644 38_decoder/db/38_decoder.(0).cnf.hdb create mode 100644 38_decoder/db/38_decoder.asm.qmsg create mode 100644 38_decoder/db/38_decoder.asm_labs.ddb create mode 100644 38_decoder/db/38_decoder.cbx.xml create mode 100644 38_decoder/db/38_decoder.cmp.bpm create mode 100644 38_decoder/db/38_decoder.cmp.cdb create mode 100644 38_decoder/db/38_decoder.cmp.ecobp create mode 100644 38_decoder/db/38_decoder.cmp.hdb create mode 100644 38_decoder/db/38_decoder.cmp.kpt create mode 100644 38_decoder/db/38_decoder.cmp.logdb create mode 100644 38_decoder/db/38_decoder.cmp.rdb create mode 100644 38_decoder/db/38_decoder.cmp.tdb create mode 100644 38_decoder/db/38_decoder.cmp0.ddb create mode 100644 38_decoder/db/38_decoder.cmp2.ddb create mode 100644 38_decoder/db/38_decoder.cmp_merge.kpt create mode 100644 38_decoder/db/38_decoder.db_info create mode 100644 38_decoder/db/38_decoder.eco.cdb create mode 100644 38_decoder/db/38_decoder.fit.qmsg create mode 100644 38_decoder/db/38_decoder.hier_info create mode 100644 38_decoder/db/38_decoder.hif create mode 100644 38_decoder/db/38_decoder.lpc.html create mode 100644 38_decoder/db/38_decoder.lpc.rdb create mode 100644 38_decoder/db/38_decoder.lpc.txt create mode 100644 38_decoder/db/38_decoder.map.bpm create mode 100644 38_decoder/db/38_decoder.map.cdb create mode 100644 38_decoder/db/38_decoder.map.ecobp create mode 100644 38_decoder/db/38_decoder.map.hdb create mode 100644 38_decoder/db/38_decoder.map.kpt create mode 100644 38_decoder/db/38_decoder.map.logdb create mode 100644 38_decoder/db/38_decoder.map.qmsg create mode 100644 38_decoder/db/38_decoder.map_bb.cdb create mode 100644 38_decoder/db/38_decoder.map_bb.hdb create mode 100644 38_decoder/db/38_decoder.map_bb.logdb create mode 100644 38_decoder/db/38_decoder.pre_map.cdb create mode 100644 38_decoder/db/38_decoder.pre_map.hdb create mode 100644 38_decoder/db/38_decoder.rtlv.hdb create mode 100644 38_decoder/db/38_decoder.rtlv_sg.cdb create mode 100644 38_decoder/db/38_decoder.rtlv_sg_swap.cdb create mode 100644 38_decoder/db/38_decoder.sgdiff.cdb create mode 100644 38_decoder/db/38_decoder.sgdiff.hdb create mode 100644 38_decoder/db/38_decoder.sld_design_entry.sci create mode 100644 38_decoder/db/38_decoder.sld_design_entry_dsc.sci create mode 100644 38_decoder/db/38_decoder.syn_hier_info create mode 100644 38_decoder/db/38_decoder.tan.qmsg create mode 100644 38_decoder/db/38_decoder.tis_db_list.ddb create mode 100644 38_decoder/incremental_db/README create mode 100644 38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.atm create mode 100644 38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.dfp create mode 100644 38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.hdbx create mode 100644 38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.kpt create mode 100644 38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.logdb create mode 100644 38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.rcf create mode 100644 38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.atm create mode 100644 38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.dpi create mode 100644 38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.hdbx create mode 100644 38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.kpt create mode 100644 register_8b/db/register_8b.tmw_info create mode 100644 register_8b/register_8b.qws diff --git a/38_decoder/38_decoder.asm.rpt b/38_decoder/38_decoder.asm.rpt new file mode 100644 index 0000000..4daad42 --- /dev/null +++ b/38_decoder/38_decoder.asm.rpt @@ -0,0 +1,129 @@ +Assembler report for 38_decoder +Mon Mar 07 09:13:07 2022 +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: D:/projects/quartus/38_decoder/38_decoder.sof + 6. Assembler Device Options: D:/projects/quartus/38_decoder/38_decoder.pof + 7. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Mon Mar 07 09:13:07 2022 ; +; Revision Name ; 38_decoder ; +; Top-level Entity Name ; 38_decoder ; +; Family ; Cyclone II ; +; Device ; EP2C8Q208C8 ; ++-----------------------+---------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Option ; Setting ; Default Value ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Use smart compilation ; Off ; Off ; +; Generate compressed bitstreams ; On ; On ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; Auto user code ; Off ; Off ; +; Use configuration device ; On ; On ; +; Configuration device ; Auto ; Auto ; +; Configuration device auto user code ; Off ; Off ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File start address ; 0 ; 0 ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Release clears before tri-states ; Off ; Off ; +; Auto-restart configuration after error ; On ; On ; +; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; ++-----------------------------------------------------------------------------+----------+---------------+ + + ++-----------------------------------------------+ +; Assembler Generated Files ; ++-----------------------------------------------+ +; File Name ; ++-----------------------------------------------+ +; D:/projects/quartus/38_decoder/38_decoder.sof ; +; D:/projects/quartus/38_decoder/38_decoder.pof ; ++-----------------------------------------------+ + + ++-------------------------------------------------------------------------+ +; Assembler Device Options: D:/projects/quartus/38_decoder/38_decoder.sof ; ++----------------+--------------------------------------------------------+ +; Option ; Setting ; ++----------------+--------------------------------------------------------+ +; Device ; EP2C8Q208C8 ; +; JTAG usercode ; 0xFFFFFFFF ; +; Checksum ; 0x000C6513 ; ++----------------+--------------------------------------------------------+ + + ++-------------------------------------------------------------------------+ +; Assembler Device Options: D:/projects/quartus/38_decoder/38_decoder.pof ; ++--------------------+----------------------------------------------------+ +; Option ; Setting ; ++--------------------+----------------------------------------------------+ +; Device ; EPCS4 ; +; JTAG usercode ; 0x00000000 ; +; Checksum ; 0x06F0CA55 ; +; Compression Ratio ; 3 ; ++--------------------+----------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II Assembler + Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + Info: Processing started: Mon Mar 07 09:13:07 2022 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder +Info: Writing out detailed assembly data for power analysis +Info: Assembler is generating device programming files +Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled +Info: Quartus II Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 241 megabytes + Info: Processing ended: Mon Mar 07 09:13:07 2022 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:00 + + diff --git a/38_decoder/38_decoder.bdf b/38_decoder/38_decoder.bdf new file mode 100644 index 0000000..4f89c23 --- /dev/null +++ b/38_decoder/38_decoder.bdf @@ -0,0 +1,886 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. 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+Fitter report for 38_decoder +Mon Mar 07 09:13:06 2022 +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Input Pins + 11. Output Pins + 12. I/O Bank Usage + 13. All Package Pins + 14. Output Pin Default Load For Reported TCO + 15. Fitter Resource Utilization by Entity + 16. Delay Chain Summary + 17. Pad To Core Delay Chain Fanout + 18. Non-Global High Fan-Out Signals + 19. Interconnect Usage Summary + 20. LAB Logic Elements + 21. LAB Signals Sourced + 22. LAB Signals Sourced Out + 23. LAB Distinct Inputs + 24. Fitter Device Options + 25. Operating Settings and Conditions + 26. Estimated Delay Added for Hold Timing + 27. Advanced Data - General + 28. Advanced Data - Placement Preparation + 29. Advanced Data - Placement + 30. Advanced Data - Routing + 31. Fitter Messages + 32. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+----------------------------------------------+ +; Fitter Status ; Successful - Mon Mar 07 09:13:06 2022 ; +; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; +; Revision Name ; 38_decoder ; +; Top-level Entity Name ; 38_decoder ; +; Family ; Cyclone II ; +; Device ; EP2C8Q208C8 ; +; Timing Models ; Final ; +; Total logic elements ; 8 / 8,256 ( < 1 % ) ; +; Total combinational functions ; 8 / 8,256 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 11 / 138 ( 8 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 165,888 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; +; Total PLLs ; 0 / 2 ( 0 % ) ; ++------------------------------------+----------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Device ; EP2C8Q208C8 ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Use TimeQuest Timing Analyzer ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Always Enable Input Buffers ; Off ; Off ; +; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; +; Optimize Multi-Corner Timing ; Off ; Off ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; On ; On ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Global Memory Control Signals ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Merge PLLs ; On ; On ; +; Ignore PLL Mode When Merging PLLs ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Stop After Congestion Map Generation ; Off ; Off ; +; Save Intermediate Fitting Results ; Off ; Off ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; 1 processor ; 100.0% ; +; 2-4 processors ; < 0.1% ; ++----------------------------+-------------+ + + ++----------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++-------------------------+--------------------+ +; Type ; Value ; ++-------------------------+--------------------+ +; Placement ; ; +; -- Requested ; 0 / 19 ( 0.00 % ) ; +; -- Achieved ; 0 / 19 ( 0.00 % ) ; +; ; ; +; Routing (by Connection) ; ; +; -- Requested ; 0 / 0 ( 0.00 % ) ; +; -- Achieved ; 0 / 0 ( 0.00 % ) ; ++-------------------------+--------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ + + ++--------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++----------------+---------+-------------------+-------------------------+-------------------+ +; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; ++----------------+---------+-------------------+-------------------------+-------------------+ +; Top ; 19 ; 0 ; N/A ; Source File ; ++----------------+---------+-------------------+-------------------------+-------------------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in D:/projects/quartus/38_decoder/38_decoder.pin. + + ++-------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+---------------------+ +; Resource ; Usage ; ++---------------------------------------------+---------------------+ +; Total logic elements ; 8 / 8,256 ( < 1 % ) ; +; -- Combinational with no register ; 8 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 0 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 0 ; +; -- 3 input functions ; 8 ; +; -- <=2 input functions ; 0 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 8 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 0 / 8,646 ( 0 % ) ; +; -- Dedicated logic registers ; 0 / 8,256 ( 0 % ) ; +; -- I/O registers ; 0 / 390 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 1 / 516 ( < 1 % ) ; +; User inserted logic elements ; 0 ; +; Virtual pins ; 0 ; +; I/O pins ; 11 / 138 ( 8 % ) ; +; -- Clock pins ; 0 / 4 ( 0 % ) ; +; Global signals ; 0 ; +; M4Ks ; 0 / 36 ( 0 % ) ; +; Total block memory bits ; 0 / 165,888 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 165,888 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; +; PLLs ; 0 / 2 ( 0 % ) ; +; Global clocks ; 0 / 8 ( 0 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Maximum fan-out node ; I2 ; +; Maximum fan-out ; 8 ; +; Highest non-global fan-out signal ; I2 ; +; Highest non-global fan-out ; 8 ; +; Total fan-out ; 32 ; +; Average fan-out ; 1.45 ; ++---------------------------------------------+---------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ; ++------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; I0 ; 35 ; 1 ; 0 ; 7 ; 1 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; I1 ; 14 ; 1 ; 0 ; 14 ; 2 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; I2 ; 41 ; 1 ; 0 ; 4 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; ++------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; ++------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ +; Y0 ; 45 ; 1 ; 0 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Y1 ; 37 ; 1 ; 0 ; 6 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Y2 ; 195 ; 2 ; 9 ; 19 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Y3 ; 33 ; 1 ; 0 ; 8 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Y4 ; 30 ; 1 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Y5 ; 208 ; 2 ; 1 ; 19 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Y6 ; 34 ; 1 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Y7 ; 39 ; 1 ; 0 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; ++------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1 ; 11 / 32 ( 34 % ) ; 3.3V ; -- ; +; 2 ; 2 / 35 ( 6 % ) ; 3.3V ; -- ; +; 3 ; 1 / 35 ( 3 % ) ; 3.3V ; -- ; +; 4 ; 0 / 36 ( 0 % ) ; 3.3V ; -- ; ++----------+------------------+---------------+--------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; 1 ; 0 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; 2 ; 1 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; 3 ; 2 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 4 ; 3 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 5 ; 4 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 6 ; 5 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 8 ; 6 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 10 ; 7 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 11 ; 8 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 12 ; 9 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 13 ; 10 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 14 ; 18 ; 1 ; I1 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 15 ; 19 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; 18 ; 22 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; 19 ; 23 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; 20 ; 24 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ; +; 21 ; 25 ; 1 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ; +; 22 ; 26 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; 23 ; 27 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 24 ; 28 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 26 ; 29 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; 27 ; 30 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 28 ; 31 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 30 ; 32 ; 1 ; Y4 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 31 ; 33 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 33 ; 35 ; 1 ; Y3 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 34 ; 36 ; 1 ; Y6 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 35 ; 37 ; 1 ; I0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 37 ; 39 ; 1 ; Y1 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 39 ; 43 ; 1 ; Y7 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 40 ; 44 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 41 ; 45 ; 1 ; I2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 42 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 43 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 44 ; 49 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 45 ; 50 ; 1 ; Y0 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 46 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 47 ; 52 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 48 ; 53 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 49 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 50 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; 51 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 52 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; 53 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 54 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; 55 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 56 ; 54 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 57 ; 55 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 58 ; 56 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 59 ; 57 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 60 ; 58 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 61 ; 59 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 63 ; 60 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 64 ; 61 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 67 ; 69 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 68 ; 70 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 69 ; 71 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 70 ; 74 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 71 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 72 ; 75 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 74 ; 76 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 75 ; 77 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 76 ; 78 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 77 ; 79 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 80 ; 82 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 81 ; 83 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 82 ; 84 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 83 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 84 ; 85 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 85 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 86 ; 86 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 87 ; 87 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 88 ; 88 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 89 ; 89 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 90 ; 90 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 91 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 92 ; 91 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 94 ; 92 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 95 ; 93 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 96 ; 94 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 97 ; 95 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 98 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 99 ; 96 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 100 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 101 ; 97 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 102 ; 98 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 103 ; 99 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 104 ; 100 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 105 ; 101 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 106 ; 102 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 107 ; 105 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 108 ; 106 ; 3 ; ~LVDS54p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 109 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 110 ; 107 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 111 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 112 ; 108 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 113 ; 109 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 114 ; 110 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 115 ; 112 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 116 ; 113 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 117 ; 114 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 118 ; 117 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 119 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 120 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 121 ; 121 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; 122 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 123 ; 122 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; 124 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 125 ; 123 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; 126 ; 124 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; 127 ; 125 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 128 ; 126 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 129 ; 127 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 130 ; 128 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 131 ; 129 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 132 ; 130 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 133 ; 131 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 134 ; 132 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 135 ; 133 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 136 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 137 ; 134 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 138 ; 135 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 139 ; 136 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 141 ; 137 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 142 ; 138 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 143 ; 141 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 144 ; 142 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 145 ; 143 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 146 ; 149 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 147 ; 150 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 148 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 149 ; 151 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 150 ; 152 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 151 ; 153 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 152 ; 154 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 153 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 154 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; 155 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 156 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; 157 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 158 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; 159 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 160 ; 155 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 161 ; 156 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 162 ; 157 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 163 ; 158 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 164 ; 159 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 165 ; 160 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 166 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 167 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 168 ; 161 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 169 ; 162 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 170 ; 163 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 171 ; 164 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 172 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 173 ; 165 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 174 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 175 ; 168 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 176 ; 169 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 177 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 178 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 179 ; 173 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 180 ; 174 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 181 ; 175 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 182 ; 176 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 183 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 184 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 185 ; 180 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 186 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 187 ; 181 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 188 ; 182 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 189 ; 183 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 190 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 191 ; 184 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 192 ; 185 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 193 ; 186 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 194 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 195 ; 187 ; 2 ; Y2 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 196 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 197 ; 191 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 198 ; 192 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 199 ; 195 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 200 ; 196 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 201 ; 197 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 202 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 203 ; 198 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 204 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 205 ; 199 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 206 ; 200 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 207 ; 201 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 208 ; 202 ; 2 ; Y5 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-------------------------------------------------------------------------------+ +; Output Pin Default Load For Reported TCO ; ++----------------------------------+-------+------------------------------------+ +; I/O Standard ; Load ; Termination Resistance ; ++----------------------------------+-------+------------------------------------+ +; 3.3-V LVTTL ; 0 pF ; Not Available ; +; 3.3-V LVCMOS ; 0 pF ; Not Available ; +; 2.5 V ; 0 pF ; Not Available ; +; 1.8 V ; 0 pF ; Not Available ; +; 1.5 V ; 0 pF ; Not Available ; +; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ; +; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ; +; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ; +; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ; +; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ; +; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ; +; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ; +; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ; +; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ; +; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ; +; LVDS ; 0 pF ; 100 Ohm (Differential) ; +; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ; +; RSDS ; 0 pF ; 100 Ohm (Differential) ; +; Simple RSDS ; 0 pF ; Not Available ; +; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ; ++----------------------------------+-------+------------------------------------+ +Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ +; |38_decoder ; 8 (8) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 11 ; 0 ; 8 (8) ; 0 (0) ; 0 (0) ; |38_decoder ; work ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++------+----------+---------------+---------------+-----------------------+-----+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; ++------+----------+---------------+---------------+-----------------------+-----+ +; Y7 ; Output ; -- ; -- ; -- ; -- ; +; Y0 ; Output ; -- ; -- ; -- ; -- ; +; Y1 ; Output ; -- ; -- ; -- ; -- ; +; Y2 ; Output ; -- ; -- ; -- ; -- ; +; Y3 ; Output ; -- ; -- ; -- ; -- ; +; Y4 ; Output ; -- ; -- ; -- ; -- ; +; Y5 ; Output ; -- ; -- ; -- ; -- ; +; Y6 ; Output ; -- ; -- ; -- ; -- ; +; I2 ; Input ; 6 ; 6 ; -- ; -- ; +; I0 ; Input ; 6 ; 6 ; -- ; -- ; +; I1 ; Input ; 6 ; 6 ; -- ; -- ; ++------+----------+---------------+---------------+-----------------------+-----+ + + ++---------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++---------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++---------------------+-------------------+---------+ +; I2 ; ; ; +; - inst10~0 ; 1 ; 6 ; +; - inst10~1 ; 1 ; 6 ; +; - inst10~2 ; 1 ; 6 ; +; - inst10~3 ; 1 ; 6 ; +; - inst10~4 ; 1 ; 6 ; +; - inst10~5 ; 1 ; 6 ; +; - inst10~6 ; 1 ; 6 ; +; - inst10~7 ; 1 ; 6 ; +; I0 ; ; ; +; - inst10~0 ; 0 ; 6 ; +; - inst10~1 ; 0 ; 6 ; +; - inst10~2 ; 0 ; 6 ; +; - inst10~3 ; 0 ; 6 ; +; - inst10~4 ; 0 ; 6 ; +; - inst10~5 ; 0 ; 6 ; +; - inst10~6 ; 0 ; 6 ; +; - inst10~7 ; 0 ; 6 ; +; I1 ; ; ; +; - inst10~0 ; 1 ; 6 ; +; - inst10~1 ; 1 ; 6 ; +; - inst10~2 ; 1 ; 6 ; +; - inst10~3 ; 1 ; 6 ; +; - inst10~4 ; 1 ; 6 ; +; - inst10~5 ; 1 ; 6 ; +; - inst10~6 ; 1 ; 6 ; +; - inst10~7 ; 1 ; 6 ; ++---------------------+-------------------+---------+ + + ++---------------------------------+ +; Non-Global High Fan-Out Signals ; ++----------+----------------------+ +; Name ; Fan-Out ; ++----------+----------------------+ +; I1 ; 8 ; +; I0 ; 8 ; +; I2 ; 8 ; +; inst10~7 ; 1 ; +; inst10~6 ; 1 ; +; inst10~5 ; 1 ; +; inst10~4 ; 1 ; +; inst10~3 ; 1 ; +; inst10~2 ; 1 ; +; inst10~1 ; 1 ; +; inst10~0 ; 1 ; ++----------+----------------------+ + + ++----------------------------------------------------+ +; Interconnect Usage Summary ; ++----------------------------+-----------------------+ +; Interconnect Resource Type ; Usage ; ++----------------------------+-----------------------+ +; Block interconnects ; 11 / 26,052 ( < 1 % ) ; +; C16 interconnects ; 0 / 1,156 ( 0 % ) ; +; C4 interconnects ; 13 / 17,952 ( < 1 % ) ; +; Direct links ; 1 / 26,052 ( < 1 % ) ; +; Global clocks ; 0 / 8 ( 0 % ) ; +; Local interconnects ; 0 / 8,256 ( 0 % ) ; +; R24 interconnects ; 0 / 1,020 ( 0 % ) ; +; R4 interconnects ; 4 / 22,440 ( < 1 % ) ; ++----------------------------+-----------------------+ + + ++--------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 8.00) ; Number of LABs (Total = 1) ; ++--------------------------------------------+-----------------------------+ +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 1 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; ++--------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++---------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 8.00) ; Number of LABs (Total = 1) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 8.00) ; Number of LABs (Total = 1) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 3.00) ; Number of LABs (Total = 1) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------+ +; Fitter Device Options ; ++----------------------------------------------+--------------------------+ +; Option ; Setting ; ++----------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; nCEO ; As output driving ground ; +; ASDO,nCSO ; As input tri-stated ; +; Reserve all unused pins ; As output driving ground ; +; Base pin-out file on sameframe device ; Off ; ++----------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing ; ++-----------------+----------------------+-------------------+ +; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; ++-----------------+----------------------+-------------------+ + + ++----------------------------+ +; Advanced Data - General ; ++--------------------+-------+ +; Name ; Value ; ++--------------------+-------+ +; Status Code ; 0 ; +; Desired User Slack ; 0 ; +; Fit Attempts ; 1 ; ++--------------------+-------+ + + ++-------------------------------------------------------------------------------+ +; Advanced Data - Placement Preparation ; ++------------------------------------------------------------------+------------+ +; Name ; Value ; ++------------------------------------------------------------------+------------+ +; Auto Fit Point 1 - Fit Attempt 1 ; ff ; +; Mid Wire Use - Fit Attempt 1 ; 0 ; +; Mid Slack - Fit Attempt 1 ; 2147483639 ; +; Internal Atom Count - Fit Attempt 1 ; 9 ; +; LE/ALM Count - Fit Attempt 1 ; 9 ; +; LAB Count - Fit Attempt 1 ; 2 ; +; Outputs per Lab - Fit Attempt 1 ; 4.000 ; +; Inputs per LAB - Fit Attempt 1 ; 1.500 ; +; Global Inputs per LAB - Fit Attempt 1 ; 0.000 ; +; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:2 ; +; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:2 ; +; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:2 ; +; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:2 ; +; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:2 ; +; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:2 ; +; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:2 ; +; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:2 ; +; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:2 ; +; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:2 ; +; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:2 ; +; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:2 ; +; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:1 ; +; LEs in Chains - Fit Attempt 1 ; 0 ; +; LEs in Long Chains - Fit Attempt 1 ; 0 ; +; LABs with Chains - Fit Attempt 1 ; 0 ; +; LABs with Multiple Chains - Fit Attempt 1 ; 0 ; +; Time - Fit Attempt 1 ; 0 ; ++------------------------------------------------------------------+------------+ + + ++-------------------------------------------------+ +; Advanced Data - Placement ; ++------------------------------------+------------+ +; Name ; Value ; ++------------------------------------+------------+ +; Auto Fit Point 2 - Fit Attempt 1 ; ff ; +; Auto Fit Point 5 - Fit Attempt 1 ; ff ; +; Mid Wire Use - Fit Attempt 1 ; 0 ; +; Mid Slack - Fit Attempt 1 ; 2147483639 ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Auto Fit Point 5 - Fit Attempt 1 ; ff ; +; Mid Wire Use - Fit Attempt 1 ; 0 ; +; Mid Slack - Fit Attempt 1 ; 2147483639 ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Late Wire Use - Fit Attempt 1 ; 0 ; +; Late Slack - Fit Attempt 1 ; 2147483639 ; +; Peak Regional Wire - Fit Attempt 1 ; 0.000 ; +; Auto Fit Point 7 - Fit Attempt 1 ; ff ; +; Time - Fit Attempt 1 ; 0 ; ++------------------------------------+------------+ + + ++---------------------------------------------------+ +; Advanced Data - Routing ; ++-------------------------------------+-------------+ +; Name ; Value ; ++-------------------------------------+-------------+ +; Early Slack - Fit Attempt 1 ; 2147483639 ; +; Mid Slack - Fit Attempt 1 ; 2147483639 ; +; Late Slack - Fit Attempt 1 ; -2147483648 ; +; Early Wire Use - Fit Attempt 1 ; 0 ; +; Peak Regional Wire - Fit Attempt 1 ; 0 ; +; Late Wire Use - Fit Attempt 1 ; 0 ; +; Time - Fit Attempt 1 ; 0 ; +; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016 ; ++-------------------------------------+-------------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Info: ******************************************************************* +Info: Running Quartus II Fitter + Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + Info: Processing started: Mon Mar 07 09:13:05 2022 +Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder +Info: Parallel compilation is enabled and will use 4 of the 4 processors detected +Info: Selected device EP2C8Q208C8 for design "38_decoder" +Info: Low junction temperature is 0 degrees C +Info: High junction temperature is 85 degrees C +Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info: Device EP2C5Q208C8 is compatible + Info: Device EP2C5Q208I8 is compatible + Info: Device EP2C8Q208I8 is compatible +Info: Fitter converted 3 user pins into dedicated programming pins + Info: Pin ~ASDO~ is reserved at location 1 + Info: Pin ~nCSO~ is reserved at location 2 + Info: Pin ~LVDS54p/nCEO~ is reserved at location 108 +Warning: No exact pin location assignment(s) for 11 pins of 11 total pins + Info: Pin Y7 not assigned to an exact location on the device + Info: Pin Y0 not assigned to an exact location on the device + Info: Pin Y1 not assigned to an exact location on the device + Info: Pin Y2 not assigned to an exact location on the device + Info: Pin Y3 not assigned to an exact location on the device + Info: Pin Y4 not assigned to an exact location on the device + Info: Pin Y5 not assigned to an exact location on the device + Info: Pin Y6 not assigned to an exact location on the device + Info: Pin I2 not assigned to an exact location on the device + Info: Pin I0 not assigned to an exact location on the device + Info: Pin I1 not assigned to an exact location on the device +Info: Fitter is using the Classic Timing Analyzer +Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time. +Info: Starting register packing +Info: Finished register packing + Extra Info: No registers were packed into other blocks +Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info: Number of I/O pins in group: 11 (unused VREF, 3.3V VCCIO, 3 input, 8 output, 0 bidirectional) + Info: I/O standards used: 3.3-V LVTTL. +Info: I/O bank details before I/O pin placement + Info: Statistics of I/O banks + Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available + Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available + Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available + Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available +Info: Fitter preparation operations ending: elapsed time is 00:00:00 +Info: Fitter placement preparation operations beginning +Info: Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info: Fitter placement operations beginning +Info: Fitter placement was successful +Info: Fitter placement operations ending: elapsed time is 00:00:00 +Info: Fitter routing operations beginning +Info: Average interconnect usage is 0% of the available device resources + Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9 +Info: Fitter routing operations ending: elapsed time is 00:00:00 +Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info: Optimizations that may affect the design's routability were skipped + Info: Optimizations that may affect the design's timing were skipped +Info: Started post-fitting delay annotation +Warning: Found 8 output pins without output pin load capacitance assignment + Info: Pin "Y7" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "Y0" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "Y1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "Y2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "Y3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "Y4" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "Y5" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "Y6" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis +Info: Delay annotation completed successfully +Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. +Info: Generated suppressed messages file D:/projects/quartus/38_decoder/38_decoder.fit.smsg +Info: Quartus II Fitter was successful. 0 errors, 3 warnings + Info: Peak virtual memory: 306 megabytes + Info: Processing ended: Mon Mar 07 09:13:06 2022 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in D:/projects/quartus/38_decoder/38_decoder.fit.smsg. + + diff --git a/38_decoder/38_decoder.fit.smsg b/38_decoder/38_decoder.fit.smsg new file mode 100644 index 0000000..14764e7 --- /dev/null +++ b/38_decoder/38_decoder.fit.smsg @@ -0,0 +1,6 @@ +Extra Info: Performing register packing on registers with non-logic cell location assignments +Extra Info: Completed register packing on registers with non-logic cell location assignments +Extra Info: Started Fast Input/Output/OE register processing +Extra Info: Finished Fast Input/Output/OE register processing +Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/38_decoder/38_decoder.fit.summary b/38_decoder/38_decoder.fit.summary new file mode 100644 index 0000000..23abfbc --- /dev/null +++ b/38_decoder/38_decoder.fit.summary @@ -0,0 +1,16 @@ +Fitter Status : Successful - Mon Mar 07 09:13:06 2022 +Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +Revision Name : 38_decoder +Top-level Entity Name : 38_decoder +Family : Cyclone II +Device : EP2C8Q208C8 +Timing Models : Final +Total logic elements : 8 / 8,256 ( < 1 % ) + Total combinational functions : 8 / 8,256 ( < 1 % ) + Dedicated logic registers : 0 / 8,256 ( 0 % ) +Total registers : 0 +Total pins : 11 / 138 ( 8 % ) +Total virtual pins : 0 +Total memory bits : 0 / 165,888 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % ) +Total PLLs : 0 / 2 ( 0 % ) diff --git a/38_decoder/38_decoder.flow.rpt b/38_decoder/38_decoder.flow.rpt new file mode 100644 index 0000000..3452d9e --- /dev/null +++ b/38_decoder/38_decoder.flow.rpt @@ -0,0 +1,121 @@ +Flow report for 38_decoder +Mon Mar 07 09:13:08 2022 +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+----------------------------------------------+ +; Flow Status ; Successful - Mon Mar 07 09:13:08 2022 ; +; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; +; Revision Name ; 38_decoder ; +; Top-level Entity Name ; 38_decoder ; +; Family ; Cyclone II ; +; Device ; EP2C8Q208C8 ; +; Timing Models ; Final ; +; Met timing requirements ; Yes ; +; Total logic elements ; 8 / 8,256 ( < 1 % ) ; +; Total combinational functions ; 8 / 8,256 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 11 / 138 ( 8 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 165,888 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; +; Total PLLs ; 0 / 2 ( 0 % ) ; ++------------------------------------+----------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 03/07/2022 09:13:04 ; +; Main task ; Compilation ; +; Revision Name ; 38_decoder ; ++-------------------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++------------------------------------+-----------------------------------------------+---------------+-------------+----------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++------------------------------------+-----------------------------------------------+---------------+-------------+----------------+ +; COMPILER_SIGNATURE_ID ; 220283517943889.164661558410840 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; MISC_FILE ; D:/projects/quartus/38_decoder/38_decoder.dpf ; -- ; -- ; -- ; +; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; +; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ; ++------------------------------------+-----------------------------------------------+---------------+-------------+----------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 245 MB ; 00:00:00 ; +; Fitter ; 00:00:01 ; 1.0 ; 306 MB ; 00:00:01 ; +; Assembler ; 00:00:00 ; 1.0 ; 241 MB ; 00:00:00 ; +; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 198 MB ; 00:00:00 ; +; Total ; 00:00:01 ; -- ; -- ; 00:00:01 ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++------------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++-------------------------+------------------+---------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++-------------------------+------------------+---------------+------------+----------------+ +; Analysis & Synthesis ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; +; Fitter ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; +; Assembler ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; +; Classic Timing Analyzer ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; ++-------------------------+------------------+---------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off 38_decoder -c 38_decoder +quartus_fit --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder +quartus_asm --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder +quartus_tan --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder --timing_analysis_only + + + diff --git a/38_decoder/38_decoder.map.rpt b/38_decoder/38_decoder.map.rpt new file mode 100644 index 0000000..ee4c415 --- /dev/null +++ b/38_decoder/38_decoder.map.rpt @@ -0,0 +1,218 @@ +Analysis & Synthesis report for 38_decoder +Mon Mar 07 09:13:04 2022 +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Analysis & Synthesis Source Files Read + 5. Analysis & Synthesis Resource Usage Summary + 6. Analysis & Synthesis Resource Utilization by Entity + 7. General Register Statistics + 8. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+----------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Mon Mar 07 09:13:04 2022 ; +; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; +; Revision Name ; 38_decoder ; +; Top-level Entity Name ; 38_decoder ; +; Family ; Cyclone II ; +; Total logic elements ; 8 ; +; Total combinational functions ; 8 ; +; Dedicated logic registers ; 0 ; +; Total registers ; 0 ; +; Total pins ; 11 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; ++------------------------------------+----------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++--------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP2C8Q208C8 ; ; +; Top-level entity name ; 38_decoder ; 38_decoder ; +; Family name ; Cyclone II ; Stratix II ; +; Use Generated Physical Constraints File ; Off ; ; +; Use smart compilation ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL93 ; VHDL93 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Parallel Synthesis ; Off ; Off ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; Off ; Off ; +; Show Parameter Settings Tables in Synthesis Report ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; ++--------------------------------------------------------------+--------------------+--------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------+-----------------------------------------------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; ++----------------------------------+-----------------+------------------------------------+-----------------------------------------------+ +; 38_decoder.bdf ; yes ; User Block Diagram/Schematic File ; D:/projects/quartus/38_decoder/38_decoder.bdf ; ++----------------------------------+-----------------+------------------------------------+-----------------------------------------------+ + + ++-----------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-------+ +; Resource ; Usage ; ++---------------------------------------------+-------+ +; Estimated Total logic elements ; 8 ; +; ; ; +; Total combinational functions ; 8 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 0 ; +; -- 3 input functions ; 8 ; +; -- <=2 input functions ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 8 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 0 ; +; -- Dedicated logic registers ; 0 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 11 ; +; Maximum fan-out node ; I2 ; +; Maximum fan-out ; 8 ; +; Total fan-out ; 32 ; +; Average fan-out ; 1.68 ; ++---------------------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ +; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ +; |38_decoder ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 11 ; 0 ; |38_decoder ; work ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 0 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Analysis & Synthesis + Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + Info: Processing started: Mon Mar 07 09:13:04 2022 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off 38_decoder -c 38_decoder +Info: Found 1 design units, including 1 entities, in source file 38_decoder.bdf + Info: Found entity 1: 38_decoder +Info: Elaborating entity "38_decoder" for the top level hierarchy +Info: Implemented 19 device resources after synthesis - the final resource count might be different + Info: Implemented 3 input pins + Info: Implemented 8 output pins + Info: Implemented 8 logic cells +Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 248 megabytes + Info: Processing ended: Mon Mar 07 09:13:04 2022 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:00 + + diff --git a/38_decoder/38_decoder.map.summary b/38_decoder/38_decoder.map.summary new file mode 100644 index 0000000..20c6ab9 --- /dev/null +++ b/38_decoder/38_decoder.map.summary @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Mon Mar 07 09:13:04 2022 +Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +Revision Name : 38_decoder +Top-level Entity Name : 38_decoder +Family : Cyclone II +Total logic elements : 8 + Total combinational functions : 8 + Dedicated logic registers : 0 +Total registers : 0 +Total pins : 11 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 diff --git a/38_decoder/38_decoder.pin b/38_decoder/38_decoder.pin new file mode 100644 index 0000000..32bdd6e --- /dev/null +++ b/38_decoder/38_decoder.pin @@ -0,0 +1,278 @@ + -- Copyright (C) 1991-2009 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- Bank 3: 3.3V + -- Bank 4: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17), + -- connect each pin marked GND* either individually through a 10k Ohm resistor + -- to GND or tie all pins together and connect through a single 10k Ohm resistor + -- to GND. + -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +CHIP "38_decoder" ASSIGNED TO AN: EP2C8Q208C8 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVTTL : : 1 : N +~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVTTL : : 1 : N +GND* : 3 : : : : 1 : +GND* : 4 : : : : 1 : +GND* : 5 : : : : 1 : +GND* : 6 : : : : 1 : +VCCIO1 : 7 : power : : 3.3V : 1 : +GND* : 8 : : : : 1 : +GND : 9 : gnd : : : : +GND* : 10 : : : : 1 : +GND* : 11 : : : : 1 : +GND* : 12 : : : : 1 : +GND* : 13 : : : : 1 : +I1 : 14 : input : 3.3-V LVTTL : : 1 : N +GND* : 15 : : : : 1 : +TDO : 16 : output : : : 1 : +TMS : 17 : input : : : 1 : +TCK : 18 : input : : : 1 : +TDI : 19 : input : : : 1 : +DATA0 : 20 : input : : : 1 : +DCLK : 21 : : : : 1 : +nCE : 22 : : : : 1 : +GND+ : 23 : : : : 1 : +GND+ : 24 : : : : 1 : +GND : 25 : gnd : : : : +nCONFIG : 26 : : : : 1 : +GND+ : 27 : : : : 1 : +GND+ : 28 : : : : 1 : +VCCIO1 : 29 : power : : 3.3V : 1 : +Y4 : 30 : output : 3.3-V LVTTL : : 1 : N +GND* : 31 : : : : 1 : +VCCINT : 32 : power : : 1.2V : : +Y3 : 33 : output : 3.3-V LVTTL : : 1 : N +Y6 : 34 : output : 3.3-V LVTTL : : 1 : N +I0 : 35 : input : 3.3-V LVTTL : : 1 : N +GND : 36 : gnd : : : : +Y1 : 37 : output : 3.3-V LVTTL : : 1 : N +GND : 38 : gnd : : : : +Y7 : 39 : output : 3.3-V LVTTL : : 1 : N +GND* : 40 : : : : 1 : +I2 : 41 : input : 3.3-V LVTTL : : 1 : N +VCCIO1 : 42 : power : : 3.3V : 1 : +GND* : 43 : : : : 1 : +GND* : 44 : : : : 1 : +Y0 : 45 : output : 3.3-V LVTTL : : 1 : N +GND* : 46 : : : : 1 : +GND* : 47 : : : : 1 : +GND* : 48 : : : : 1 : +GND : 49 : gnd : : : : +GND_PLL1 : 50 : gnd : : : : +VCCD_PLL1 : 51 : power : : 1.2V : : +GND_PLL1 : 52 : gnd : : : : +VCCA_PLL1 : 53 : power : : 1.2V : : +GNDA_PLL1 : 54 : gnd : : : : +GND : 55 : gnd : : : : +GND* : 56 : : : : 4 : +GND* : 57 : : : : 4 : +GND* : 58 : : : : 4 : +GND* : 59 : : : : 4 : +GND* : 60 : : : : 4 : +GND* : 61 : : : : 4 : +VCCIO4 : 62 : power : : 3.3V : 4 : +GND* : 63 : : : : 4 : +GND* : 64 : : : : 4 : +GND : 65 : gnd : : : : +VCCINT : 66 : power : : 1.2V : : +GND* : 67 : : : : 4 : +GND* : 68 : : : : 4 : +GND* : 69 : : : : 4 : +GND* : 70 : : : : 4 : +VCCIO4 : 71 : power : : 3.3V : 4 : +GND* : 72 : : : : 4 : +GND : 73 : gnd : : : : +GND* : 74 : : : : 4 : +GND* : 75 : : : : 4 : +GND* : 76 : : : : 4 : +GND* : 77 : : : : 4 : +GND : 78 : gnd : : : : +VCCINT : 79 : power : : 1.2V : : +GND* : 80 : : : : 4 : +GND* : 81 : : : : 4 : +GND* : 82 : : : : 4 : +VCCIO4 : 83 : power : : 3.3V : 4 : +GND* : 84 : : : : 4 : +GND : 85 : gnd : : : : +GND* : 86 : : : : 4 : +GND* : 87 : : : : 4 : +GND* : 88 : : : : 4 : +GND* : 89 : : : : 4 : +GND* : 90 : : : : 4 : +VCCIO4 : 91 : power : : 3.3V : 4 : +GND* : 92 : : : : 4 : +GND : 93 : gnd : : : : +GND* : 94 : : : : 4 : +GND* : 95 : : : : 4 : +GND* : 96 : : : : 4 : +GND* : 97 : : : : 4 : +VCCIO4 : 98 : power : : 3.3V : 4 : +GND* : 99 : : : : 4 : +GND : 100 : gnd : : : : +GND* : 101 : : : : 4 : +GND* : 102 : : : : 4 : +GND* : 103 : : : : 4 : +GND* : 104 : : : : 4 : +GND* : 105 : : : : 3 : +GND* : 106 : : : : 3 : +GND* : 107 : : : : 3 : +~LVDS54p/nCEO~ : 108 : output : 3.3-V LVTTL : : 3 : N +VCCIO3 : 109 : power : : 3.3V : 3 : +GND* : 110 : : : : 3 : +GND : 111 : gnd : : : : +GND* : 112 : : : : 3 : +GND* : 113 : : : : 3 : +GND* : 114 : : : : 3 : +GND* : 115 : : : : 3 : +GND* : 116 : : : : 3 : +GND* : 117 : : : : 3 : +GND* : 118 : : : : 3 : +GND : 119 : gnd : : : : +VCCINT : 120 : power : : 1.2V : : +nSTATUS : 121 : : : : 3 : +VCCIO3 : 122 : power : : 3.3V : 3 : +CONF_DONE : 123 : : : : 3 : +GND : 124 : gnd : : : : +MSEL1 : 125 : : : : 3 : +MSEL0 : 126 : : : : 3 : +GND* : 127 : : : : 3 : +GND* : 128 : : : : 3 : +GND+ : 129 : : : : 3 : +GND+ : 130 : : : : 3 : +GND+ : 131 : : : : 3 : +GND+ : 132 : : : : 3 : +GND* : 133 : : : : 3 : +GND* : 134 : : : : 3 : +GND* : 135 : : : : 3 : +VCCIO3 : 136 : power : : 3.3V : 3 : +GND* : 137 : : : : 3 : +GND* : 138 : : : : 3 : +GND* : 139 : : : : 3 : +GND : 140 : gnd : : : : +GND* : 141 : : : : 3 : +GND* : 142 : : : : 3 : +GND* : 143 : : : : 3 : +GND* : 144 : : : : 3 : +GND* : 145 : : : : 3 : +GND* : 146 : : : : 3 : +GND* : 147 : : : : 3 : +VCCIO3 : 148 : power : : 3.3V : 3 : +GND* : 149 : : : : 3 : +GND* : 150 : : : : 3 : +GND* : 151 : : : : 3 : +GND* : 152 : : : : 3 : +GND : 153 : gnd : : : : +GND_PLL2 : 154 : gnd : : : : +VCCD_PLL2 : 155 : power : : 1.2V : : +GND_PLL2 : 156 : gnd : : : : +VCCA_PLL2 : 157 : power : : 1.2V : : +GNDA_PLL2 : 158 : gnd : : : : +GND : 159 : gnd : : : : +GND* : 160 : : : : 2 : +GND* : 161 : : : : 2 : +GND* : 162 : : : : 2 : +GND* : 163 : : : : 2 : +GND* : 164 : : : : 2 : +GND* : 165 : : : : 2 : +VCCIO2 : 166 : power : : 3.3V : 2 : +GND : 167 : gnd : : : : +GND* : 168 : : : : 2 : +GND* : 169 : : : : 2 : +GND* : 170 : : : : 2 : +GND* : 171 : : : : 2 : +VCCIO2 : 172 : power : : 3.3V : 2 : +GND* : 173 : : : : 2 : +GND : 174 : gnd : : : : +GND* : 175 : : : : 2 : +GND* : 176 : : : : 2 : +GND : 177 : gnd : : : : +VCCINT : 178 : power : : 1.2V : : +GND* : 179 : : : : 2 : +GND* : 180 : : : : 2 : +GND* : 181 : : : : 2 : +GND* : 182 : : : : 2 : +VCCIO2 : 183 : power : : 3.3V : 2 : +GND : 184 : gnd : : : : +GND* : 185 : : : : 2 : +GND : 186 : gnd : : : : +GND* : 187 : : : : 2 : +GND* : 188 : : : : 2 : +GND* : 189 : : : : 2 : +VCCINT : 190 : power : : 1.2V : : +GND* : 191 : : : : 2 : +GND* : 192 : : : : 2 : +GND* : 193 : : : : 2 : +VCCIO2 : 194 : power : : 3.3V : 2 : +Y2 : 195 : output : 3.3-V LVTTL : : 2 : N +GND : 196 : gnd : : : : +GND* : 197 : : : : 2 : +GND* : 198 : : : : 2 : +GND* : 199 : : : : 2 : +GND* : 200 : : : : 2 : +GND* : 201 : : : : 2 : +VCCIO2 : 202 : power : : 3.3V : 2 : +GND* : 203 : : : : 2 : +GND : 204 : gnd : : : : +GND* : 205 : : : : 2 : +GND* : 206 : : : : 2 : +GND* : 207 : : : : 2 : +Y5 : 208 : output : 3.3-V LVTTL : : 2 : N diff --git a/38_decoder/38_decoder.pof b/38_decoder/38_decoder.pof new file mode 100644 index 0000000000000000000000000000000000000000..bbba2ec5797d3a862b5b1ba995cf962bf4c039f7 GIT binary patch literal 524488 zcmeI*3zQr6edzI#Si(AKQfn-y+QrUFDWzdrMy`9Ej0a(IcRX+G^8_Um=>dhKV{+wyt z!|QMV?1mfHhgYt-@sr_!@Q0U%Ke~Qx_?mSa?v&LuzrBNNRxbYV0__5AlI-TXPv5!W z&Rf>6(*oM>X`M15KMYA&&ejY!|M2XP_VGoNwEB^{WouR~eYCDyZC!WWouB#WUFz>6 zpI!gayVif?6YD=R>#|h?mmR(F3yZD|Ol{F$z*qco@*e8m6X=epDaA4Sy*RP3WO3fx zyHrIm3Zv6b1p++*d6`lf#`1E_=9j~%-SX?d{o7kV@W!!YgYPb{Ul=PdRvfe6tG{&S z?&tTP>h69ha!S`{NN{RCe_hSnQ+#pSkIif%CPtGy))nY-m^bH^UO26*{XEoE)&JKJ&}{=9j-b zIq$S#%#hI5P5HT+`^)0XOYbR#*Ix3Biqy}ly zFP#A||GwHxP{nc;Bl9~w`g6SSeLE=SU=;S0-&(VM zSJVCA>>F>q*z@xI`BRGfuAE|zzo-^bFUQ{IeOHFmUD)5s_txw$^X=Dn?mVcjeDyo5 zpEBN|dn-YxrvI&e{p{wSMqf*(FNv1Vn#u#6|L&Dj#yj+HHT-XW{j)E=cJI9}?*G-F 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-------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +# Date created = 09:11:53 March 07, 2022 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "9.0" +DATE = "09:11:53 March 07, 2022" + +# Revisions + +PROJECT_REVISION = "38_decoder" diff --git a/38_decoder/38_decoder.qsf b/38_decoder/38_decoder.qsf new file mode 100644 index 0000000..c51ed34 --- /dev/null +++ b/38_decoder/38_decoder.qsf @@ -0,0 +1,54 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +# Date created = 09:11:53 March 07, 2022 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# 38_decoder_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone II" +set_global_assignment -name DEVICE EP2C8Q208C8 +set_global_assignment -name TOP_LEVEL_ENTITY 38_decoder +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:11:53 MARCH 07, 2022" +set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2" +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name MISC_FILE "D:/projects/quartus/38_decoder/38_decoder.dpf" +set_global_assignment -name BDF_FILE 38_decoder.bdf +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top 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+Quartus_Version = Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +Version_Index = 167832322 +Creation_Time = Mon Mar 07 09:11:53 2022 diff --git a/38_decoder/db/38_decoder.eco.cdb b/38_decoder/db/38_decoder.eco.cdb new file mode 100644 index 0000000000000000000000000000000000000000..6612017e10ee479d46d8c5c373ee2759c1d1f0db GIT binary patch literal 175 zcmd;QU|?9w&B%}kg!VvoSZYymW`3T6rJjL;Q)y;Sih_}`se*x-zM;9kk%57wLU3wP zS!QyoLO^12wt|sDu$Mx3YLbF$N@fXAn<&r(5U7Pv43 inst3.IN0 +I2 => inst.IN0 +I2 => inst6.IN0 +I2 => inst5.IN0 +I2 => inst4.IN0 +I1 => inst3.IN1 +I1 => inst1.IN0 +I1 => inst8.IN1 +I1 => inst7.IN1 +I1 => inst4.IN1 +I0 => inst3.IN2 +I0 => inst2.IN0 +I0 => inst9.IN2 +I0 => inst7.IN2 +I0 => inst5.IN2 +Y0 <= inst10.DB_MAX_OUTPUT_PORT_TYPE +Y1 <= inst9.DB_MAX_OUTPUT_PORT_TYPE +Y2 <= inst8.DB_MAX_OUTPUT_PORT_TYPE +Y3 <= inst7.DB_MAX_OUTPUT_PORT_TYPE +Y4 <= inst6.DB_MAX_OUTPUT_PORT_TYPE +Y5 <= inst5.DB_MAX_OUTPUT_PORT_TYPE +Y6 <= inst4.DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/38_decoder/db/38_decoder.hif b/38_decoder/db/38_decoder.hif new file mode 100644 index 0000000..2a7a787 --- /dev/null +++ b/38_decoder/db/38_decoder.hif @@ -0,0 +1,42 @@ +Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +11 +936 +OFF +OFF +OFF +ON +ON +ON +FV_OFF +Level2 +0 +0 +VRSM_ON +VHSM_ON +0 +-- Start Library Paths -- +-- End Library Paths -- +-- Start VHDL Libraries -- +-- End VHDL Libraries -- +# entity +38_decoder +# storage +db|38_decoder.(0).cnf +db|38_decoder.(0).cnf +# case_insensitive +# source_file +38_decoder.bdf +ce95eaa7a0801a2b705ca5ea74e4b7a +26 +# internal_option { +BLOCK_DESIGN_NAMING +AUTO +} +# hierarchies { +| +} +# macro_sequence + +# end +# complete + \ No newline at end of file diff --git a/38_decoder/db/38_decoder.lpc.html b/38_decoder/db/38_decoder.lpc.html new file mode 100644 index 0000000..fd4875d --- /dev/null +++ b/38_decoder/db/38_decoder.lpc.html @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
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"IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 09:13:04 2022 " "Info: Processing started: Mon Mar 07 09:13:04 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off 38_decoder -c 38_decoder " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off 38_decoder -c 38_decoder" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "38_decoder.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file 38_decoder.bdf" { { "Info" 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+start_timing_analyzer:s:00:00:01-start_full_compilation diff --git a/register_8b/register_8b.qws b/register_8b/register_8b.qws new file mode 100644 index 0000000..fc216dc --- /dev/null +++ b/register_8b/register_8b.qws @@ -0,0 +1,4 @@ +[ProjectWorkspace] +ptn_Child1=Frames +[ProjectWorkspace.Frames] +ptn_Child1=ChildFrames From 9ff3e8947f5d6f1c9fd07d7d3abab79269cd6f41 Mon Sep 17 00:00:00 2001 From: juzeon <812312770@qq.com> Date: Mon, 7 Mar 2022 09:53:45 +0800 Subject: [PATCH 4/7] README --- 38_decoder/38_decoder.qws | 14 ++++++++++++++ 38_decoder/db/38_decoder.tmw_info | 6 ++++++ README.md | 10 +++++++++- data_selector/data_selector.qws | 10 ---------- 4 files changed, 29 insertions(+), 11 deletions(-) create mode 100644 38_decoder/38_decoder.qws create mode 100644 38_decoder/db/38_decoder.tmw_info diff --git a/38_decoder/38_decoder.qws b/38_decoder/38_decoder.qws new file mode 100644 index 0000000..4e30f11 --- /dev/null +++ b/38_decoder/38_decoder.qws @@ -0,0 +1,14 @@ +[ProjectWorkspace] +ptn_Child1=Frames +[ProjectWorkspace.Frames] +ptn_Child1=ChildFrames +[ProjectWorkspace.Frames.ChildFrames] +ptn_Child1=Document-0 +[ProjectWorkspace.Frames.ChildFrames.Document-0] +ptn_Child1=ViewFrame-0 +[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0] +DocPathName=38_decoder.bdf +DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde} +IsChildFrameDetached=False +IsActiveChildFrame=True +ptn_Child1=StateMap diff --git a/38_decoder/db/38_decoder.tmw_info b/38_decoder/db/38_decoder.tmw_info new file mode 100644 index 0000000..15a6255 --- /dev/null +++ b/38_decoder/db/38_decoder.tmw_info @@ -0,0 +1,6 @@ +start_full_compilation:s:00:00:05 +start_analysis_synthesis:s:00:00:01-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:02-start_full_compilation +start_assembler:s:00:00:01-start_full_compilation +start_timing_analyzer:s:00:00:01-start_full_compilation diff --git a/README.md b/README.md index 72d5852..81fe87d 100644 --- a/README.md +++ b/README.md @@ -8,4 +8,12 @@ ### data_selector -8ä½æ•°æ®é€‰æ‹©å™¨ï¼ˆäºŒé€‰ä¸€ï¼‰ã€‚ \ No newline at end of file +8ä½æ•°æ®é€‰æ‹©å™¨ï¼ˆäºŒé€‰ä¸€ï¼‰ã€‚ + +### register_8b + +8ä½å¯„存器。 + +### 38_decoder + +3-8译ç å™¨ã€‚ \ No newline at end of file diff --git a/data_selector/data_selector.qws b/data_selector/data_selector.qws index 42962c6..fc216dc 100644 --- a/data_selector/data_selector.qws +++ b/data_selector/data_selector.qws @@ -2,13 +2,3 @@ ptn_Child1=Frames [ProjectWorkspace.Frames] ptn_Child1=ChildFrames -[ProjectWorkspace.Frames.ChildFrames] -ptn_Child1=Document-0 -[ProjectWorkspace.Frames.ChildFrames.Document-0] -ptn_Child1=ViewFrame-0 -[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0] -DocPathName=data_selector.bdf -DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde} -IsChildFrameDetached=False -IsActiveChildFrame=True -ptn_Child1=StateMap From d39a6bc50a97e92e6715e91e1c5fdf94dd986135 Mon Sep 17 00:00:00 2001 From: juzeon <812312770@qq.com> Date: Mon, 7 Mar 2022 10:22:43 +0800 Subject: [PATCH 5/7] modify adder_8b --- README.md | 2 +- adder/adder.bsf | 211 --- adder/adder.done | 1 - adder/adder.qws | 4 - adder/db/adder.(0).cnf.hdb | Bin 1270 -> 0 bytes adder/db/adder.cmp.bpm | Bin 673 -> 0 bytes adder/db/adder.cmp.cdb | Bin 6286 -> 0 bytes adder/db/adder.cmp.hdb | Bin 8241 -> 0 bytes adder/db/adder.cmp.rdb | Bin 17244 -> 0 bytes adder/db/adder.cmp.tdb | Bin 5803 -> 0 bytes adder/db/adder.cmp0.ddb | Bin 59317 -> 0 bytes adder/db/adder.map.bpm | Bin 656 -> 0 bytes adder/db/adder.map.cdb | Bin 2132 -> 0 bytes adder/db/adder.map.hdb | Bin 7920 -> 0 bytes adder/db/adder.map_bb.cdb | Bin 743 -> 0 bytes adder/db/adder.map_bb.hdb | Bin 7177 -> 0 bytes adder/db/adder.pre_map.cdb | Bin 2341 -> 0 bytes adder/db/adder.pre_map.hdb | Bin 7950 -> 0 bytes adder/db/adder.rtlv.hdb | Bin 7966 -> 0 bytes adder/db/adder.sgdiff.cdb | Bin 1696 -> 0 bytes adder/db/adder.sgdiff.hdb | Bin 7979 -> 0 bytes adder/db/adder.tan.qmsg | 6 - adder/db/adder.tmw_info | 6 - .../adder.root_partition.cmp.atm | Bin 8870 -> 0 bytes .../adder.root_partition.cmp.hdbx | Bin 3314 -> 0 bytes .../adder.root_partition.cmp.rcf | Bin 1605 -> 0 bytes .../adder.root_partition.map.atm | Bin 6004 -> 0 bytes .../adder.root_partition.map.dpi | Bin 1311 -> 0 bytes .../adder.root_partition.map.hdbx | Bin 3202 -> 0 bytes .../adder_8b.asm.rpt | 76 +- adder/adder.bdf => adder_8b/adder_8b.bdf | 1204 ++++++++--------- adder_8b/adder_8b.done | 1 + .../adder_8b.fit.rpt | 70 +- .../adder_8b.fit.smsg | 0 .../adder_8b.fit.summary | 6 +- .../adder_8b.flow.rpt | 30 +- .../adder_8b.map.rpt | 72 +- .../adder_8b.map.summary | 6 +- adder/adder.pin => adder_8b/adder_8b.pin | 2 +- adder/adder.pof => adder_8b/adder_8b.pof | Bin adder/adder.qpf => adder_8b/adder_8b.qpf | 6 +- adder/adder.qsf => adder_8b/adder_8b.qsf | 10 +- adder/adder.sof => adder_8b/adder_8b.sof | Bin .../adder_8b.tan.rpt | 12 +- .../adder_8b.tan.summary | 0 .../db/adder_8b.(0).cnf.cdb | Bin adder_8b/db/adder_8b.(0).cnf.hdb | Bin 0 -> 1276 bytes .../db/adder_8b.(1).cnf.cdb | Bin .../db/adder_8b.(1).cnf.hdb | Bin .../db/adder_8b.(2).cnf.cdb | Bin .../db/adder_8b.(2).cnf.hdb | Bin .../db/adder_8b.asm.qmsg | 6 +- .../db/adder_8b.asm_labs.ddb | Bin .../db/adder_8b.cbx.xml | 2 +- adder_8b/db/adder_8b.cmp.bpm | Bin 0 -> 674 bytes adder_8b/db/adder_8b.cmp.cdb | Bin 0 -> 6287 bytes .../db/adder_8b.cmp.ecobp | Bin adder_8b/db/adder_8b.cmp.hdb | Bin 0 -> 8222 bytes .../db/adder_8b.cmp.kpt | 2 +- .../db/adder_8b.cmp.logdb | 0 adder_8b/db/adder_8b.cmp.rdb | Bin 0 -> 17257 bytes adder_8b/db/adder_8b.cmp.tdb | Bin 0 -> 5808 bytes adder_8b/db/adder_8b.cmp0.ddb | Bin 0 -> 59350 bytes .../db/adder_8b.cmp2.ddb | Bin .../db/adder_8b.cmp_merge.kpt | 2 +- .../db/adder_8b.db_info | 2 +- .../db/adder_8b.eco.cdb | Bin .../db/adder_8b.fit.qmsg | 12 +- .../db/adder_8b.hier_info | 82 +- .../db/adder.hif => adder_8b/db/adder_8b.hif | 18 +- .../db/adder_8b.lpc.html | 0 .../db/adder_8b.lpc.rdb | Bin .../db/adder_8b.lpc.txt | 0 adder_8b/db/adder_8b.map.bpm | Bin 0 -> 663 bytes adder_8b/db/adder_8b.map.cdb | Bin 0 -> 2132 bytes .../db/adder_8b.map.ecobp | Bin adder_8b/db/adder_8b.map.hdb | Bin 0 -> 7934 bytes .../db/adder_8b.map.kpt | 2 +- .../db/adder_8b.map.logdb | 0 .../db/adder_8b.map.qmsg | 18 +- adder_8b/db/adder_8b.map_bb.cdb | Bin 0 -> 743 bytes adder_8b/db/adder_8b.map_bb.hdb | Bin 0 -> 7170 bytes .../db/adder_8b.map_bb.logdb | 0 adder_8b/db/adder_8b.pre_map.cdb | Bin 0 -> 2341 bytes adder_8b/db/adder_8b.pre_map.hdb | Bin 0 -> 7951 bytes adder_8b/db/adder_8b.rtlv.hdb | Bin 0 -> 7975 bytes .../db/adder_8b.rtlv_sg.cdb | Bin .../db/adder_8b.rtlv_sg_swap.cdb | Bin adder_8b/db/adder_8b.sgdiff.cdb | Bin 0 -> 1698 bytes adder_8b/db/adder_8b.sgdiff.hdb | Bin 0 -> 7997 bytes .../db/adder_8b.sld_design_entry.sci | Bin .../db/adder_8b.sld_design_entry_dsc.sci | Bin .../db/adder_8b.syn_hier_info | 0 adder_8b/db/adder_8b.tan.qmsg | 6 + .../db/adder_8b.tis_db_list.ddb | Bin {adder => adder_8b}/incremental_db/README | 0 .../adder_8b.root_partition.cmp.atm | Bin 0 -> 8873 bytes .../adder_8b.root_partition.cmp.dfp | Bin .../adder_8b.root_partition.cmp.hdbx | Bin 0 -> 3327 bytes .../adder_8b.root_partition.cmp.kpt | 0 .../adder_8b.root_partition.cmp.logdb | 0 .../adder_8b.root_partition.cmp.rcf | Bin 0 -> 1606 bytes .../adder_8b.root_partition.map.atm | Bin 0 -> 6006 bytes .../adder_8b.root_partition.map.dpi | Bin 0 -> 1315 bytes .../adder_8b.root_partition.map.hdbx | Bin 0 -> 3235 bytes .../adder_8b.root_partition.map.kpt | 2 +- 106 files changed, 829 insertions(+), 1050 deletions(-) delete mode 100644 adder/adder.bsf delete mode 100644 adder/adder.done delete mode 100644 adder/adder.qws delete mode 100644 adder/db/adder.(0).cnf.hdb delete mode 100644 adder/db/adder.cmp.bpm delete mode 100644 adder/db/adder.cmp.cdb delete mode 100644 adder/db/adder.cmp.hdb delete mode 100644 adder/db/adder.cmp.rdb delete mode 100644 adder/db/adder.cmp.tdb delete mode 100644 adder/db/adder.cmp0.ddb delete mode 100644 adder/db/adder.map.bpm delete mode 100644 adder/db/adder.map.cdb delete mode 100644 adder/db/adder.map.hdb delete mode 100644 adder/db/adder.map_bb.cdb delete mode 100644 adder/db/adder.map_bb.hdb delete mode 100644 adder/db/adder.pre_map.cdb delete mode 100644 adder/db/adder.pre_map.hdb delete mode 100644 adder/db/adder.rtlv.hdb delete mode 100644 adder/db/adder.sgdiff.cdb delete mode 100644 adder/db/adder.sgdiff.hdb delete mode 100644 adder/db/adder.tan.qmsg delete mode 100644 adder/db/adder.tmw_info delete mode 100644 adder/incremental_db/compiled_partitions/adder.root_partition.cmp.atm delete mode 100644 adder/incremental_db/compiled_partitions/adder.root_partition.cmp.hdbx delete mode 100644 adder/incremental_db/compiled_partitions/adder.root_partition.cmp.rcf delete mode 100644 adder/incremental_db/compiled_partitions/adder.root_partition.map.atm delete mode 100644 adder/incremental_db/compiled_partitions/adder.root_partition.map.dpi delete mode 100644 adder/incremental_db/compiled_partitions/adder.root_partition.map.hdbx rename adder/adder.asm.rpt => adder_8b/adder_8b.asm.rpt (83%) rename adder/adder.bdf => adder_8b/adder_8b.bdf (87%) create mode 100644 adder_8b/adder_8b.done rename adder/adder.fit.rpt => adder_8b/adder_8b.fit.rpt (97%) rename adder/adder.fit.smsg => adder_8b/adder_8b.fit.smsg (100%) rename adder/adder.fit.summary => adder_8b/adder_8b.fit.summary (80%) rename adder/adder.flow.rpt => adder_8b/adder_8b.flow.rpt (89%) rename adder/adder.map.rpt => adder_8b/adder_8b.map.rpt (90%) rename adder/adder.map.summary => adder_8b/adder_8b.map.summary (72%) rename adder/adder.pin => adder_8b/adder_8b.pin (99%) rename adder/adder.pof => adder_8b/adder_8b.pof (100%) rename adder/adder.qpf => adder_8b/adder_8b.qpf (91%) rename adder/adder.qsf => adder_8b/adder_8b.qsf (90%) rename adder/adder.sof => adder_8b/adder_8b.sof (100%) rename adder/adder.tan.rpt => adder_8b/adder_8b.tan.rpt (98%) rename adder/adder.tan.summary => adder_8b/adder_8b.tan.summary (100%) rename adder/db/adder.(0).cnf.cdb => adder_8b/db/adder_8b.(0).cnf.cdb (100%) create mode 100644 adder_8b/db/adder_8b.(0).cnf.hdb rename adder/db/adder.(1).cnf.cdb => adder_8b/db/adder_8b.(1).cnf.cdb (100%) rename adder/db/adder.(1).cnf.hdb => adder_8b/db/adder_8b.(1).cnf.hdb (100%) rename adder/db/adder.(2).cnf.cdb => adder_8b/db/adder_8b.(2).cnf.cdb (100%) rename adder/db/adder.(2).cnf.hdb => adder_8b/db/adder_8b.(2).cnf.hdb (100%) rename adder/db/adder.asm.qmsg => adder_8b/db/adder_8b.asm.qmsg (75%) rename adder/db/adder.asm_labs.ddb => adder_8b/db/adder_8b.asm_labs.ddb (100%) rename adder/db/adder.cbx.xml => adder_8b/db/adder_8b.cbx.xml (68%) create mode 100644 adder_8b/db/adder_8b.cmp.bpm create mode 100644 adder_8b/db/adder_8b.cmp.cdb rename adder/db/adder.cmp.ecobp => adder_8b/db/adder_8b.cmp.ecobp (100%) create mode 100644 adder_8b/db/adder_8b.cmp.hdb rename adder/db/adder.cmp.kpt => adder_8b/db/adder_8b.cmp.kpt (85%) rename adder/db/adder.cmp.logdb => adder_8b/db/adder_8b.cmp.logdb (100%) create mode 100644 adder_8b/db/adder_8b.cmp.rdb create mode 100644 adder_8b/db/adder_8b.cmp.tdb create mode 100644 adder_8b/db/adder_8b.cmp0.ddb rename adder/db/adder.cmp2.ddb => adder_8b/db/adder_8b.cmp2.ddb (100%) rename adder/db/adder.cmp_merge.kpt => adder_8b/db/adder_8b.cmp_merge.kpt (84%) rename adder/db/adder.db_info => adder_8b/db/adder_8b.db_info (72%) rename adder/db/adder.eco.cdb => adder_8b/db/adder_8b.eco.cdb (100%) rename adder/db/adder.fit.qmsg => adder_8b/db/adder_8b.fit.qmsg (56%) rename adder/db/adder.hier_info => adder_8b/db/adder_8b.hier_info (77%) rename adder/db/adder.hif => adder_8b/db/adder_8b.hif (82%) rename adder/db/adder.lpc.html => adder_8b/db/adder_8b.lpc.html (100%) rename adder/db/adder.lpc.rdb => adder_8b/db/adder_8b.lpc.rdb (100%) rename adder/db/adder.lpc.txt => adder_8b/db/adder_8b.lpc.txt (100%) create mode 100644 adder_8b/db/adder_8b.map.bpm create mode 100644 adder_8b/db/adder_8b.map.cdb rename adder/db/adder.map.ecobp => adder_8b/db/adder_8b.map.ecobp (100%) create mode 100644 adder_8b/db/adder_8b.map.hdb rename adder/db/adder.map.kpt => adder_8b/db/adder_8b.map.kpt (85%) rename adder/db/adder.map.logdb => adder_8b/db/adder_8b.map.logdb (100%) rename adder/db/adder.map.qmsg => adder_8b/db/adder_8b.map.qmsg (54%) create mode 100644 adder_8b/db/adder_8b.map_bb.cdb create mode 100644 adder_8b/db/adder_8b.map_bb.hdb rename adder/db/adder.map_bb.logdb => adder_8b/db/adder_8b.map_bb.logdb (100%) create mode 100644 adder_8b/db/adder_8b.pre_map.cdb create mode 100644 adder_8b/db/adder_8b.pre_map.hdb create mode 100644 adder_8b/db/adder_8b.rtlv.hdb rename adder/db/adder.rtlv_sg.cdb => adder_8b/db/adder_8b.rtlv_sg.cdb (100%) rename adder/db/adder.rtlv_sg_swap.cdb => adder_8b/db/adder_8b.rtlv_sg_swap.cdb (100%) create mode 100644 adder_8b/db/adder_8b.sgdiff.cdb create mode 100644 adder_8b/db/adder_8b.sgdiff.hdb rename adder/db/adder.sld_design_entry.sci => adder_8b/db/adder_8b.sld_design_entry.sci (100%) rename adder/db/adder.sld_design_entry_dsc.sci => adder_8b/db/adder_8b.sld_design_entry_dsc.sci (100%) rename adder/db/adder.syn_hier_info => adder_8b/db/adder_8b.syn_hier_info (100%) create mode 100644 adder_8b/db/adder_8b.tan.qmsg rename adder/db/adder.tis_db_list.ddb => adder_8b/db/adder_8b.tis_db_list.ddb (100%) rename {adder => adder_8b}/incremental_db/README (100%) create mode 100644 adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.atm rename adder/incremental_db/compiled_partitions/adder.root_partition.cmp.dfp => adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.dfp (100%) create mode 100644 adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.hdbx rename adder/incremental_db/compiled_partitions/adder.root_partition.cmp.kpt => adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.kpt (100%) rename adder/incremental_db/compiled_partitions/adder.root_partition.cmp.logdb => adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.logdb (100%) create mode 100644 adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.rcf create mode 100644 adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.map.atm create mode 100644 adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.map.dpi create mode 100644 adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.map.hdbx rename adder/incremental_db/compiled_partitions/adder.root_partition.map.kpt => adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.map.kpt (84%) diff --git a/README.md b/README.md index 81fe87d..b89dc79 100644 --- a/README.md +++ b/README.md @@ -2,7 +2,7 @@ 计组课设。 -### adder +### adder_8b 8ä½åŠ æ³•è®¡ç®—器。 diff --git a/adder/adder.bsf b/adder/adder.bsf deleted file mode 100644 index 0eb6e3f..0000000 --- a/adder/adder.bsf +++ /dev/null @@ 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File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. 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z1)}k%Usd*?=q9tZ0#3&R1L`&6!6H{79j052!aC!ohby_)9T+RRuv?n;(ekYh{Vupx z*Dq>SrKjX**SY8~UEK$Kw`0gh{RMbPPcp+fOJyUE6cV|wnEwEgM@`*LHZANAPYXB_ zWX@O8Zhrd#wq8OA#?zgHdhO@f1bCNH9Zwi|;v97g11aXF>{K^AOEOB2kqLDB%?(&5 zkcrhq?55fd+&!@E%{No9=jp;q&ciRj_dG14wxitq(Dxd{_4#|PXT}jB=A=Dg8uPPczE5- z%{bJG5z5@rOR3(fe&?!DePL_6*bkG8PYM5Vg%ummawSq!&a=;gjpJpF=*Xfi$2ow|%=!HT6C zN6X!i>ZAZWuV{=X2(Yy|fWmX(oJw?HRkO&O6*qks6hW&hLc^W?vX7izUod8AoAKhD zB$C?J(>Ns{npqaD|5J+yWqKUa8DeV9hXECp!7qx$$CyA{?mtx|T%Zg}BC>fvO|mQi z%qOK|Bea7EW26Uw#S3N_#@Q4Vg!|3%$rU^<(>er=C&n(DL0~}~|K3Q~W*XTMhDmW; zI5>N`KM3WcN+@lVMjuxKmwB8EFrZ`c5XDlS64xZ2o0=CtvmB7;KTG8>AD{HuulN_1 z?t}>*ir!)!tyi91B^FL2hVdc}JEphYt0k27pNabA`6$YEzjh^5|EY0--#}WzBDDXv U^niDQt($3>E(aI?^q>6sA4Y?nVE_OC diff --git a/adder/db/adder.tan.qmsg b/adder/db/adder.tan.qmsg deleted file mode 100644 index 3fcee9e..0000000 --- a/adder/db/adder.tan.qmsg +++ /dev/null @@ -1,6 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 08:49:26 2022 " "Info: Processing started: Mon Mar 07 08:49:26 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off adder -c adder --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off adder -c adder --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "ITDB_FULL_TPD_RESULT" "A1 CO 19.344 ns Longest " "Info: Longest tpd from source pin \"A1\" to destination pin \"CO\" is 19.344 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns A1 1 PIN PIN_57 2 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_57; Fanout = 2; PIN Node = 'A1'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A1 } "NODE_NAME" } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 1824 80 248 1840 "A1" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.202 ns) + CELL(0.651 ns) 7.847 ns 7400:inst8\|4~0 2 COMB LCCOMB_X1_Y7_N12 4 " "Info: 2: + IC(6.202 ns) + CELL(0.651 ns) = 7.847 ns; Loc. = LCCOMB_X1_Y7_N12; Fanout = 4; COMB Node = '7400:inst8\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.853 ns" { A1 7400:inst8|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.391 ns) + CELL(0.206 ns) 8.444 ns 7400:inst13\|4~1 3 COMB LCCOMB_X1_Y7_N8 2 " "Info: 3: + IC(0.391 ns) + CELL(0.206 ns) = 8.444 ns; Loc. = LCCOMB_X1_Y7_N8; Fanout = 2; COMB Node = '7400:inst13\|4~1'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.597 ns" { 7400:inst8|4~0 7400:inst13|4~1 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.387 ns) + CELL(0.370 ns) 9.201 ns 7400:inst18\|4~0 4 COMB LCCOMB_X1_Y7_N4 2 " "Info: 4: + IC(0.387 ns) + CELL(0.370 ns) = 9.201 ns; Loc. = LCCOMB_X1_Y7_N4; Fanout = 2; COMB Node = '7400:inst18\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.757 ns" { 7400:inst13|4~1 7400:inst18|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.387 ns) + CELL(0.370 ns) 9.958 ns 7400:inst23\|4~9 5 COMB LCCOMB_X1_Y7_N6 2 " "Info: 5: + IC(0.387 ns) + CELL(0.370 ns) = 9.958 ns; Loc. = LCCOMB_X1_Y7_N6; Fanout = 2; COMB Node = '7400:inst23\|4~9'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.757 ns" { 7400:inst18|4~0 7400:inst23|4~9 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.412 ns) + CELL(0.650 ns) 11.020 ns 7400:inst28\|4~0 6 COMB LCCOMB_X1_Y7_N0 3 " "Info: 6: + IC(0.412 ns) + CELL(0.650 ns) = 11.020 ns; Loc. = LCCOMB_X1_Y7_N0; Fanout = 3; COMB Node = '7400:inst28\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.062 ns" { 7400:inst23|4~9 7400:inst28|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.736 ns) + CELL(0.206 ns) 12.962 ns 7400:inst33\|4~0 7 COMB LCCOMB_X1_Y15_N24 2 " "Info: 7: + IC(1.736 ns) + CELL(0.206 ns) = 12.962 ns; Loc. = LCCOMB_X1_Y15_N24; Fanout = 2; COMB Node = '7400:inst33\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.942 ns" { 7400:inst28|4~0 7400:inst33|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.396 ns) + CELL(0.651 ns) 14.009 ns 7400:inst38\|4~0 8 COMB LCCOMB_X1_Y15_N4 1 " "Info: 8: + IC(0.396 ns) + CELL(0.651 ns) = 14.009 ns; Loc. = LCCOMB_X1_Y15_N4; Fanout = 1; COMB Node = '7400:inst38\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.047 ns" { 7400:inst33|4~0 7400:inst38|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.039 ns) + CELL(3.296 ns) 19.344 ns CO 9 PIN PIN_58 0 " "Info: 9: + IC(2.039 ns) + CELL(3.296 ns) = 19.344 ns; Loc. = PIN_58; Fanout = 0; PIN Node = 'CO'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.335 ns" { 7400:inst38|4~0 CO } "NODE_NAME" } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 32 536 712 48 "CO" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.394 ns ( 38.22 % ) " "Info: Total cell delay = 7.394 ns ( 38.22 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "11.950 ns ( 61.78 % ) " "Info: Total interconnect delay = 11.950 ns ( 61.78 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "19.344 ns" { A1 7400:inst8|4~0 7400:inst13|4~1 7400:inst18|4~0 7400:inst23|4~9 7400:inst28|4~0 7400:inst33|4~0 7400:inst38|4~0 CO } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "19.344 ns" { A1 {} A1~combout {} 7400:inst8|4~0 {} 7400:inst13|4~1 {} 7400:inst18|4~0 {} 7400:inst23|4~9 {} 7400:inst28|4~0 {} 7400:inst33|4~0 {} 7400:inst38|4~0 {} CO {} } { 0.000ns 0.000ns 6.202ns 0.391ns 0.387ns 0.387ns 0.412ns 1.736ns 0.396ns 2.039ns } { 0.000ns 0.994ns 0.651ns 0.206ns 0.370ns 0.370ns 0.650ns 0.206ns 0.651ns 3.296ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 08:49:27 2022 " "Info: Processing ended: Mon Mar 07 08:49:27 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/adder/db/adder.tmw_info b/adder/db/adder.tmw_info deleted file mode 100644 index f9d7d70..0000000 --- a/adder/db/adder.tmw_info +++ /dev/null @@ -1,6 +0,0 @@ -start_full_compilation:s:00:00:06 -start_analysis_synthesis:s:00:00:02-start_full_compilation -start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:02-start_full_compilation -start_assembler:s:00:00:01-start_full_compilation -start_timing_analyzer:s:00:00:01-start_full_compilation diff --git a/adder/incremental_db/compiled_partitions/adder.root_partition.cmp.atm b/adder/incremental_db/compiled_partitions/adder.root_partition.cmp.atm deleted file mode 100644 index 0a8e135269ebe02b81270b8b907654b2975e80ec..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8870 zcmYk9WmuF^w}z3fp-Wn%yFPPhM^hh25E+rE@4RN1`#-TzVABM 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zYhSZ7Vp3js=~96+e~Wb=zj3-DGcW*xkCA4I(+wEer|eDQO{yLqUJT!F?St=HgVpP1 zx*Bm=V93=pwCYl$1MuouSFStcx+KaHny3E(z1lv&kSiB}UKP-b@M!kb2=6hU8;4T+gb1Z<;}sDm;&*>0mFkTP?~~9QKi&~#eW~`!N$Teg_R^$CM0Snf{lR)miB_J zjVOYU!t>v`GwwqN?#wXvJO4T7KbQHEC%%SwP4SAQry`*o;aUqSj)YKt;D~!4t6RH) z(Q$nzn(rf;;rD;=B6j74_)7EVhg}+8HX%8F&Y6&=VD&(S!6gwX={Ex9S)n?ilPUXb z%Wpp3{%seM$oHI!FT@|=g_I^fDYHBD_RRB@K|~PUPeRcmIyBXCK$+Ineh^gDcOo!& z2jf}3bw)(%*M6KlptlDMgc?v4pjIs1#oWs5LA^I^h$=tRRF1ePZ2^@-dbeF=gughk zmw4=0vGw%so$ZRo#`T?OnWM(KF|@uqcr!n%A=9QtQ5O_3u+pb*wH$rtavdX9;Di(W zKFX`DMJ2t^jdQOy`v_J&VG-B@;y*Kbd;MiCuVH}cndu$KvHZ^G0X;NuFbSgeg6#&r zkW#s}a9w2wUR^u6R9Jm8q}!cmbg~DRfyTDJ?mXC|n|Q literal 0 HcmV?d00001 diff --git a/adder/db/adder.cmp2.ddb b/adder_8b/db/adder_8b.cmp2.ddb similarity index 100% rename from adder/db/adder.cmp2.ddb rename to adder_8b/db/adder_8b.cmp2.ddb diff --git a/adder/db/adder.cmp_merge.kpt b/adder_8b/db/adder_8b.cmp_merge.kpt similarity index 84% rename from adder/db/adder.cmp_merge.kpt rename to adder_8b/db/adder_8b.cmp_merge.kpt index ad1741f..e6e63e0 100644 --- a/adder/db/adder.cmp_merge.kpt +++ b/adder_8b/db/adder_8b.cmp_merge.kpt @@ -1,4 +1,4 @@ - + diff --git a/adder/db/adder.db_info b/adder_8b/db/adder_8b.db_info similarity index 72% rename from adder/db/adder.db_info rename to adder_8b/db/adder_8b.db_info index 90ca49d..89f88e0 100644 --- a/adder/db/adder.db_info +++ b/adder_8b/db/adder_8b.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition Version_Index = 167832322 -Creation_Time = Mon Mar 07 08:48:37 2022 +Creation_Time = Mon Mar 07 10:21:41 2022 diff --git a/adder/db/adder.eco.cdb b/adder_8b/db/adder_8b.eco.cdb similarity index 100% rename from adder/db/adder.eco.cdb rename to adder_8b/db/adder_8b.eco.cdb diff --git a/adder/db/adder.fit.qmsg b/adder_8b/db/adder_8b.fit.qmsg similarity index 56% rename from adder/db/adder.fit.qmsg rename to adder_8b/db/adder_8b.fit.qmsg index 36253d3..5e266ed 100644 --- a/adder/db/adder.fit.qmsg +++ b/adder_8b/db/adder_8b.fit.qmsg @@ -1,14 +1,14 @@ { "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 08:49:23 2022 " "Info: Processing started: Mon Mar 07 08:49:23 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off adder -c adder " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off adder -c adder" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:22:22 2022 " "Info: Processing started: Mon Mar 07 10:22:22 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "IMPP_MPP_USER_DEVICE" "adder EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"adder\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "IMPP_MPP_USER_DEVICE" "adder_8b EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"adder_8b\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} { "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1} -{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "26 26 " "Warning: No exact pin location assignment(s) for 26 pins of 26 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CO " "Info: Pin CO not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { CO } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 32 536 712 48 "CO" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CO } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S7 " "Info: Pin S7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S7 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 64 536 712 80 "S7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S0 " "Info: Pin S0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S0 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 2120 536 712 2136 "S0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S1 " "Info: Pin S1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S1 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 1840 536 712 1856 "S1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S2 " "Info: Pin S2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S2 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 1544 536 712 1560 "S2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S3 " "Info: Pin S3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S3 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 1248 536 712 1264 "S3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S4 " "Info: Pin S4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S4 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 952 536 712 968 "S4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S5 " "Info: Pin S5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S5 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 656 536 712 672 "S5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S6 " "Info: Pin S6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S6 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 360 536 712 376 "S6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A6 " "Info: Pin A6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A6 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 344 80 248 360 "A6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A3 " "Info: Pin A3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A3 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 1232 80 248 1248 "A3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B3 " "Info: Pin B3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B3 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 1248 80 248 1264 "B3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A4 " "Info: Pin A4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A4 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 936 80 248 952 "A4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A2 " "Info: Pin A2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A2 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 1528 80 248 1544 "A2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A0 " "Info: Pin A0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A0 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 2104 80 248 2120 "A0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CI " "Info: Pin CI not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { CI } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 2136 80 248 2152 "CI" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CI } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B0 " "Info: Pin B0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B0 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 2120 80 248 2136 "B0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A1 " "Info: Pin A1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A1 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 1824 80 248 1840 "A1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B1 " "Info: Pin B1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B1 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 1840 80 248 1856 "B1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B2 " "Info: Pin B2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B2 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 1544 80 248 1560 "B2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B4 " "Info: Pin B4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B4 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 952 80 248 968 "B4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A5 " "Info: Pin A5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A5 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 640 80 248 656 "A5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B5 " "Info: Pin B5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B5 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 656 80 248 672 "B5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B6 " "Info: Pin B6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B6 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 360 80 248 376 "B6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A7 " "Info: Pin A7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A7 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 48 80 248 64 "A7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B7 " "Info: Pin B7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B7 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 64 80 248 80 "B7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1} +{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "26 26 " "Warning: No exact pin location assignment(s) for 26 pins of 26 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CO " "Info: Pin CO not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { CO } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 32 504 680 48 "CO" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CO } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S7 " "Info: Pin S7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S7 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 64 504 680 80 "S7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S0 " "Info: Pin S0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S0 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2120 504 680 2136 "S0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S1 " "Info: Pin S1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S1 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1840 504 680 1856 "S1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S2 " "Info: Pin S2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S2 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1544 504 680 1560 "S2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S3 " "Info: Pin S3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S3 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1248 504 680 1264 "S3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S4 " "Info: Pin S4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S4 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 952 504 680 968 "S4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S5 " "Info: Pin S5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S5 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 656 504 680 672 "S5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S6 " "Info: Pin S6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S6 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 360 504 680 376 "S6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A6 " "Info: Pin A6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A6 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 344 48 216 360 "A6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A3 " "Info: Pin A3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A3 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1232 48 216 1248 "A3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B3 " "Info: Pin B3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B3 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1248 48 216 1264 "B3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A4 " "Info: Pin A4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A4 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 936 48 216 952 "A4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A2 " "Info: Pin A2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A2 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1528 48 216 1544 "A2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A0 " "Info: Pin A0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A0 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2104 48 216 2120 "A0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CI " "Info: Pin CI not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { CI } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2136 48 216 2152 "CI" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CI } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B0 " "Info: Pin B0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B0 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2120 48 216 2136 "B0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A1 " "Info: Pin A1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A1 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1824 48 216 1840 "A1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B1 " "Info: Pin B1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B1 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1840 48 216 1856 "B1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B2 " "Info: Pin B2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B2 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1544 48 216 1560 "B2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B4 " "Info: Pin B4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B4 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 952 48 216 968 "B4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A5 " "Info: Pin A5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A5 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 640 48 216 656 "A5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B5 " "Info: Pin B5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B5 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 656 48 216 672 "B5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B6 " "Info: Pin B6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B6 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 360 48 216 376 "B6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A7 " "Info: Pin A7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A7 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 48 48 216 64 "A7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B7 " "Info: Pin B7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B7 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 64 48 216 80 "B7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1} { "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1} { "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1} @@ -35,5 +35,5 @@ { "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "9 " "Warning: Found 9 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "CO 0 " "Info: Pin \"CO\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S7 0 " "Info: Pin \"S7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S0 0 " "Info: Pin \"S0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S1 0 " "Info: Pin \"S1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S2 0 " "Info: Pin \"S2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S3 0 " "Info: Pin \"S3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S4 0 " "Info: Pin \"S4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S5 0 " "Info: Pin \"S5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S6 0 " "Info: Pin \"S6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1} { "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} { "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/adder/adder.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/adder/adder.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "305 " "Info: Peak virtual memory: 305 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 08:49:24 2022 " "Info: Processing ended: Mon Mar 07 08:49:24 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/adder_8b/adder_8b.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/adder_8b/adder_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "305 " "Info: Peak virtual memory: 305 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 10:22:23 2022 " "Info: Processing ended: Mon Mar 07 10:22:23 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/adder/db/adder.hier_info b/adder_8b/db/adder_8b.hier_info similarity index 77% rename from adder/db/adder.hier_info rename to adder_8b/db/adder_8b.hier_info index 4f08f30..7be6838 100644 --- a/adder/db/adder.hier_info +++ b/adder_8b/db/adder_8b.hier_info @@ -1,4 +1,4 @@ -|adder +|adder_8b CO <= 7400:inst38.1 A7 => 7400:inst39.3 A7 => 7486:inst36.2 @@ -44,241 +44,241 @@ S5 <= 7486:inst30.1 S6 <= 7486:inst35.1 -|adder|7400:inst38 +|adder_8b|7400:inst38 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7400:inst39 +|adder_8b|7400:inst39 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7400:inst37 +|adder_8b|7400:inst37 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7400:inst33 +|adder_8b|7400:inst33 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7400:inst34 +|adder_8b|7400:inst34 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7400:inst32 +|adder_8b|7400:inst32 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7400:inst28 +|adder_8b|7400:inst28 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7400:inst29 +|adder_8b|7400:inst29 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7400:inst27 +|adder_8b|7400:inst27 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7400:inst23 +|adder_8b|7400:inst23 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7400:inst24 +|adder_8b|7400:inst24 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7400:inst22 +|adder_8b|7400:inst22 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7400:inst18 +|adder_8b|7400:inst18 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7400:inst19 +|adder_8b|7400:inst19 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7400:inst17 +|adder_8b|7400:inst17 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7400:inst13 +|adder_8b|7400:inst13 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7400:inst14 +|adder_8b|7400:inst14 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7400:inst12 +|adder_8b|7400:inst12 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7400:inst8 +|adder_8b|7400:inst8 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7400:inst9 +|adder_8b|7400:inst9 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7400:inst7 +|adder_8b|7400:inst7 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7400:inst3 +|adder_8b|7400:inst3 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7400:inst4 +|adder_8b|7400:inst4 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7400:inst2 +|adder_8b|7400:inst2 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7486:inst +|adder_8b|7486:inst 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7486:inst6 +|adder_8b|7486:inst6 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7486:inst11 +|adder_8b|7486:inst11 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7486:inst16 +|adder_8b|7486:inst16 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7486:inst21 +|adder_8b|7486:inst21 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7486:inst26 +|adder_8b|7486:inst26 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7486:inst31 +|adder_8b|7486:inst31 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7486:inst36 +|adder_8b|7486:inst36 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7486:inst40 +|adder_8b|7486:inst40 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7486:inst5 +|adder_8b|7486:inst5 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7486:inst10 +|adder_8b|7486:inst10 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7486:inst15 +|adder_8b|7486:inst15 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7486:inst20 +|adder_8b|7486:inst20 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7486:inst25 +|adder_8b|7486:inst25 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7486:inst30 +|adder_8b|7486:inst30 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 -|adder|7486:inst35 +|adder_8b|7486:inst35 1 <= 4.DB_MAX_OUTPUT_PORT_TYPE 2 => 4.IN0 3 => 4.IN1 diff --git a/adder/db/adder.hif b/adder_8b/db/adder_8b.hif similarity index 82% rename from adder/db/adder.hif rename to adder_8b/db/adder_8b.hif index 288d8b0..e5ca282 100644 --- a/adder/db/adder.hif +++ b/adder_8b/db/adder_8b.hif @@ -19,14 +19,14 @@ VHSM_ON -- Start VHDL Libraries -- -- End VHDL Libraries -- # entity -adder +adder_8b # storage -db|adder.(0).cnf -db|adder.(0).cnf +db|adder_8b.(0).cnf +db|adder_8b.(0).cnf # case_insensitive # source_file -adder.bdf -24315e582bd755b4b98eeb6d569ea2 +adder_8b.bdf +a2e51ddcd21f2ca4364ec3cc2afc185 26 # internal_option { BLOCK_DESIGN_NAMING @@ -41,8 +41,8 @@ AUTO # entity 7400 # storage -db|adder.(1).cnf -db|adder.(1).cnf +db|adder_8b.(1).cnf +db|adder_8b.(1).cnf # case_insensitive # source_file ..|..|..|altera|90sp2|quartus|libraries|others|maxplus2|7400.bdf @@ -84,8 +84,8 @@ AUTO # entity 7486 # storage -db|adder.(2).cnf -db|adder.(2).cnf +db|adder_8b.(2).cnf +db|adder_8b.(2).cnf # case_insensitive # source_file ..|..|..|altera|90sp2|quartus|libraries|others|maxplus2|7486.bdf diff --git a/adder/db/adder.lpc.html b/adder_8b/db/adder_8b.lpc.html similarity index 100% rename from adder/db/adder.lpc.html rename to adder_8b/db/adder_8b.lpc.html diff --git a/adder/db/adder.lpc.rdb b/adder_8b/db/adder_8b.lpc.rdb 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a/adder/db/adder.map.qmsg b/adder_8b/db/adder_8b.map.qmsg similarity index 54% rename from adder/db/adder.map.qmsg rename to adder_8b/db/adder_8b.map.qmsg index fb8e01f..ca9ca77 100644 --- a/adder/db/adder.map.qmsg +++ b/adder_8b/db/adder_8b.map.qmsg @@ -1,11 +1,11 @@ { "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 08:49:21 2022 " "Info: Processing started: Mon Mar 07 08:49:21 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off adder -c adder " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adder -c adder" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adder.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 adder " "Info: Found entity 1: adder" { } { { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_START_ELABORATION_TOP" "adder " "Info: Elaborating entity \"adder\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7400 7400:inst38 " "Info: Elaborating entity \"7400\" for hierarchy \"7400:inst38\"" { } { { "adder.bdf" "inst38" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 184 432 496 224 "inst38" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} -{ "Info" "ISGN_ELABORATION_HEADER" "7400:inst38 " "Info: Elaborated megafunction instantiation \"7400:inst38\"" { } { { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 184 432 496 224 "inst38" "" } } } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7486 7486:inst " "Info: Elaborating entity \"7486\" for hierarchy \"7486:inst\"" { } { { "adder.bdf" "inst" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 2096 304 368 2136 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} -{ "Info" "ISGN_ELABORATION_HEADER" "7486:inst " "Info: Elaborated megafunction instantiation \"7486:inst\"" { } { { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 2096 304 368 2136 "inst" "" } } } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:22:20 2022 " "Info: Processing started: Mon Mar 07 10:22:20 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off adder_8b -c adder_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adder_8b -c adder_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adder_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file adder_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 adder_8b " "Info: Found entity 1: adder_8b" { } { { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_TOP" "adder_8b " "Info: Elaborating entity \"adder_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7400 7400:inst38 " "Info: Elaborating entity \"7400\" for hierarchy \"7400:inst38\"" { } { { "adder_8b.bdf" "inst38" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 184 400 464 224 "inst38" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_ELABORATION_HEADER" "7400:inst38 " "Info: Elaborated megafunction instantiation \"7400:inst38\"" { } { { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 184 400 464 224 "inst38" "" } } } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7486 7486:inst " "Info: Elaborating entity \"7486\" for hierarchy \"7486:inst\"" { } { { "adder_8b.bdf" "inst" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2096 272 336 2136 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_ELABORATION_HEADER" "7486:inst " "Info: Elaborated megafunction instantiation \"7486:inst\"" { } { { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2096 272 336 2136 "inst" "" } } } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_SUMMARY" "47 " "Info: Implemented 47 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "17 " "Info: Implemented 17 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Info: Implemented 9 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "21 " "Info: Implemented 21 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "248 " "Info: Peak virtual memory: 248 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 08:49:22 2022 " "Info: Processing ended: Mon Mar 07 08:49:22 2022" { } { } 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a/adder/db/adder.sld_design_entry_dsc.sci b/adder_8b/db/adder_8b.sld_design_entry_dsc.sci similarity index 100% rename from adder/db/adder.sld_design_entry_dsc.sci rename to adder_8b/db/adder_8b.sld_design_entry_dsc.sci diff --git a/adder/db/adder.syn_hier_info b/adder_8b/db/adder_8b.syn_hier_info similarity index 100% rename from adder/db/adder.syn_hier_info rename to adder_8b/db/adder_8b.syn_hier_info diff --git a/adder_8b/db/adder_8b.tan.qmsg b/adder_8b/db/adder_8b.tan.qmsg new file mode 100644 index 0000000..14356c5 --- /dev/null +++ b/adder_8b/db/adder_8b.tan.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:22:25 2022 " "Info: Processing started: Mon Mar 07 10:22:25 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_TPD_RESULT" "A1 CO 19.344 ns Longest " "Info: Longest tpd from source pin \"A1\" to destination pin \"CO\" is 19.344 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns A1 1 PIN PIN_57 2 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_57; Fanout = 2; PIN Node = 'A1'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A1 } "NODE_NAME" } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1824 48 216 1840 "A1" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.202 ns) + CELL(0.651 ns) 7.847 ns 7400:inst8\|4~0 2 COMB LCCOMB_X1_Y7_N12 4 " "Info: 2: + IC(6.202 ns) + CELL(0.651 ns) = 7.847 ns; Loc. = LCCOMB_X1_Y7_N12; Fanout = 4; COMB Node = '7400:inst8\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.853 ns" { A1 7400:inst8|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.391 ns) + CELL(0.206 ns) 8.444 ns 7400:inst13\|4~1 3 COMB LCCOMB_X1_Y7_N8 2 " "Info: 3: + IC(0.391 ns) + CELL(0.206 ns) = 8.444 ns; Loc. = LCCOMB_X1_Y7_N8; Fanout = 2; COMB Node = '7400:inst13\|4~1'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.597 ns" { 7400:inst8|4~0 7400:inst13|4~1 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.387 ns) + CELL(0.370 ns) 9.201 ns 7400:inst18\|4~0 4 COMB LCCOMB_X1_Y7_N4 2 " "Info: 4: + IC(0.387 ns) + CELL(0.370 ns) = 9.201 ns; Loc. = LCCOMB_X1_Y7_N4; Fanout = 2; COMB Node = '7400:inst18\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.757 ns" { 7400:inst13|4~1 7400:inst18|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.387 ns) + CELL(0.370 ns) 9.958 ns 7400:inst23\|4~9 5 COMB LCCOMB_X1_Y7_N6 2 " "Info: 5: + IC(0.387 ns) + CELL(0.370 ns) = 9.958 ns; Loc. = LCCOMB_X1_Y7_N6; Fanout = 2; COMB Node = '7400:inst23\|4~9'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.757 ns" { 7400:inst18|4~0 7400:inst23|4~9 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.412 ns) + CELL(0.650 ns) 11.020 ns 7400:inst28\|4~0 6 COMB LCCOMB_X1_Y7_N0 3 " "Info: 6: + IC(0.412 ns) + CELL(0.650 ns) = 11.020 ns; Loc. = LCCOMB_X1_Y7_N0; Fanout = 3; COMB Node = '7400:inst28\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.062 ns" { 7400:inst23|4~9 7400:inst28|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.736 ns) + CELL(0.206 ns) 12.962 ns 7400:inst33\|4~0 7 COMB LCCOMB_X1_Y15_N24 2 " "Info: 7: + IC(1.736 ns) + CELL(0.206 ns) = 12.962 ns; Loc. = LCCOMB_X1_Y15_N24; Fanout = 2; COMB Node = '7400:inst33\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.942 ns" { 7400:inst28|4~0 7400:inst33|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.396 ns) + CELL(0.651 ns) 14.009 ns 7400:inst38\|4~0 8 COMB LCCOMB_X1_Y15_N4 1 " "Info: 8: + IC(0.396 ns) + CELL(0.651 ns) = 14.009 ns; Loc. = LCCOMB_X1_Y15_N4; Fanout = 1; COMB Node = '7400:inst38\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.047 ns" { 7400:inst33|4~0 7400:inst38|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.039 ns) + CELL(3.296 ns) 19.344 ns CO 9 PIN PIN_58 0 " "Info: 9: + IC(2.039 ns) + CELL(3.296 ns) = 19.344 ns; Loc. = PIN_58; Fanout = 0; PIN Node = 'CO'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.335 ns" { 7400:inst38|4~0 CO } "NODE_NAME" } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 32 504 680 48 "CO" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.394 ns ( 38.22 % ) " "Info: Total cell delay = 7.394 ns ( 38.22 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "11.950 ns ( 61.78 % ) " "Info: Total interconnect delay = 11.950 ns ( 61.78 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "19.344 ns" { A1 7400:inst8|4~0 7400:inst13|4~1 7400:inst18|4~0 7400:inst23|4~9 7400:inst28|4~0 7400:inst33|4~0 7400:inst38|4~0 CO } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "19.344 ns" { A1 {} A1~combout {} 7400:inst8|4~0 {} 7400:inst13|4~1 {} 7400:inst18|4~0 {} 7400:inst23|4~9 {} 7400:inst28|4~0 {} 7400:inst33|4~0 {} 7400:inst38|4~0 {} CO {} } { 0.000ns 0.000ns 6.202ns 0.391ns 0.387ns 0.387ns 0.412ns 1.736ns 0.396ns 2.039ns } { 0.000ns 0.994ns 0.651ns 0.206ns 0.370ns 0.370ns 0.650ns 0.206ns 0.651ns 3.296ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 10:22:25 2022 " "Info: Processing ended: Mon Mar 07 10:22:25 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/adder/db/adder.tis_db_list.ddb b/adder_8b/db/adder_8b.tis_db_list.ddb similarity index 100% rename from adder/db/adder.tis_db_list.ddb rename to adder_8b/db/adder_8b.tis_db_list.ddb diff --git a/adder/incremental_db/README b/adder_8b/incremental_db/README similarity index 100% rename from adder/incremental_db/README rename to adder_8b/incremental_db/README diff --git a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.atm b/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.atm new file mode 100644 index 0000000000000000000000000000000000000000..ddb4508d97c9bc2c91e18123b594c1f70cb669f9 GIT binary patch literal 8873 zcmYj!by$>N)UC7%L&y-qfPjK@$I#s&AOk~6OLs{((k0#9-5@R93^kNUibxMJ(3FI^bGH3 zQ~9@}lOCU-F;(x{7wgm?me%09T;2C>L9dkMbANm-gfp60%ht(#MNj_?Dc$2WxMakl;2 z_J)K{P*$je8udo#88@xfQr$D{RL(#zupAqqQ?bqpD5 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zjfQpuB@lj^hc1dLI?dZ?_*7MFBMWFccg!iCD=|sU1f%Y7p{=#;sHSaa;$nBUY1Z6i zGu4uys%d98kutxsX-At!nfCLhlS2wj)3g)srWbmZ))_0*R7Xf_O*^V-+Ogu{m^y8* zZkD61b?m6_=0dZ4FvhK;UKK3Wuw(ACVP0*q>Nbygnft7n_s{^*-B;+a@|7<&%)9sA zr`Ec4RMV}?e?0}B53YMX1GSWCim7fL{v!VW(XMOQgw8bWI#xVjQ93FoUIM@BDSj^T z{O!BhI}QN){iCvt=-!<6y}< zfQKEAF~*`#fbCT7;iqSK*;85MVl&V?<|Is(J7OmD38O({Zs*H^Dk%iRyF# zQq!4EPUH{1&$3O(r^Ab3?|b`LgC4x|dNBQfe&4_SL3|$LH!F9L z@@o|T%u|BpGVs&zW3Us72SesFkQz6idsT_s;S + From db64b867f654d2e6c6ff5633bec9bcface7ac2d3 Mon Sep 17 00:00:00 2001 From: juzeon <812312770@qq.com> Date: Mon, 7 Mar 2022 10:41:24 +0800 Subject: [PATCH 6/7] add triple_selector_8b, shifter_8b --- README.md | 10 +- adder_8b/adder_8b.qws | 14 + adder_8b/db/adder_8b.tmw_info | 6 + shifter_8b/db/prev_cmp_shifter_8b.map.qmsg | 7 + shifter_8b/db/prev_cmp_shifter_8b.qmsg | 8 + shifter_8b/db/shifter_8b.(0).cnf.cdb | Bin 0 -> 1254 bytes shifter_8b/db/shifter_8b.(0).cnf.hdb | Bin 0 -> 795 bytes shifter_8b/db/shifter_8b.(1).cnf.cdb | Bin 0 -> 1503 bytes shifter_8b/db/shifter_8b.(1).cnf.hdb | Bin 0 -> 1200 bytes shifter_8b/db/shifter_8b.asm.qmsg | 7 + shifter_8b/db/shifter_8b.asm_labs.ddb | Bin 0 -> 3681 bytes shifter_8b/db/shifter_8b.cbx.xml | 5 + shifter_8b/db/shifter_8b.cmp.bpm | Bin 0 -> 627 bytes shifter_8b/db/shifter_8b.cmp.cdb | Bin 0 -> 5336 bytes shifter_8b/db/shifter_8b.cmp.ecobp | Bin 0 -> 28 bytes shifter_8b/db/shifter_8b.cmp.hdb | Bin 0 -> 7319 bytes shifter_8b/db/shifter_8b.cmp.kpt | 10 + shifter_8b/db/shifter_8b.cmp.logdb | 1 + shifter_8b/db/shifter_8b.cmp.rdb | Bin 0 -> 16033 bytes shifter_8b/db/shifter_8b.cmp.tdb | Bin 0 -> 4352 bytes shifter_8b/db/shifter_8b.cmp0.ddb | Bin 0 -> 56278 bytes shifter_8b/db/shifter_8b.cmp2.ddb | Bin 0 -> 41510 bytes shifter_8b/db/shifter_8b.cmp_merge.kpt | 10 + shifter_8b/db/shifter_8b.db_info | 3 + shifter_8b/db/shifter_8b.eco.cdb | Bin 0 -> 175 bytes shifter_8b/db/shifter_8b.fit.qmsg | 39 + shifter_8b/db/shifter_8b.hier_info | 102 + shifter_8b/db/shifter_8b.hif | 62 + shifter_8b/db/shifter_8b.lpc.html | 34 + shifter_8b/db/shifter_8b.lpc.rdb | Bin 0 -> 435 bytes shifter_8b/db/shifter_8b.lpc.txt | 7 + shifter_8b/db/shifter_8b.map.bpm | Bin 0 -> 609 bytes shifter_8b/db/shifter_8b.map.cdb | Bin 0 -> 1762 bytes shifter_8b/db/shifter_8b.map.ecobp | Bin 0 -> 28 bytes shifter_8b/db/shifter_8b.map.hdb | Bin 0 -> 7043 bytes shifter_8b/db/shifter_8b.map.kpt | 10 + shifter_8b/db/shifter_8b.map.logdb | 1 + shifter_8b/db/shifter_8b.map.qmsg | 9 + shifter_8b/db/shifter_8b.map_bb.cdb | Bin 0 -> 722 bytes shifter_8b/db/shifter_8b.map_bb.hdb | Bin 0 -> 6398 bytes shifter_8b/db/shifter_8b.map_bb.logdb | 1 + shifter_8b/db/shifter_8b.pre_map.cdb | Bin 0 -> 1894 bytes shifter_8b/db/shifter_8b.pre_map.hdb | Bin 0 -> 7660 bytes shifter_8b/db/shifter_8b.rtlv.hdb | Bin 0 -> 7655 bytes shifter_8b/db/shifter_8b.rtlv_sg.cdb | Bin 0 -> 2437 bytes shifter_8b/db/shifter_8b.rtlv_sg_swap.cdb | Bin 0 -> 634 bytes shifter_8b/db/shifter_8b.sgdiff.cdb | Bin 0 -> 1561 bytes shifter_8b/db/shifter_8b.sgdiff.hdb | Bin 0 -> 7751 bytes shifter_8b/db/shifter_8b.sld_design_entry.sci | Bin 0 -> 168 bytes .../db/shifter_8b.sld_design_entry_dsc.sci | Bin 0 -> 168 bytes shifter_8b/db/shifter_8b.syn_hier_info | 0 shifter_8b/db/shifter_8b.tan.qmsg | 6 + shifter_8b/db/shifter_8b.tis_db_list.ddb | Bin 0 -> 188 bytes shifter_8b/incremental_db/README | 11 + .../shifter_8b.root_partition.cmp.atm | Bin 0 -> 7523 bytes .../shifter_8b.root_partition.cmp.dfp | Bin 0 -> 33 bytes .../shifter_8b.root_partition.cmp.hdbx | Bin 0 -> 2104 bytes .../shifter_8b.root_partition.cmp.kpt | 10 + .../shifter_8b.root_partition.cmp.logdb | 1 + .../shifter_8b.root_partition.cmp.rcf | Bin 0 -> 1336 bytes .../shifter_8b.root_partition.map.atm | Bin 0 -> 4955 bytes .../shifter_8b.root_partition.map.dpi | Bin 0 -> 837 bytes .../shifter_8b.root_partition.map.hdbx | Bin 0 -> 2020 bytes .../shifter_8b.root_partition.map.kpt | 10 + shifter_8b/shifter_8b.asm.rpt | 129 + shifter_8b/shifter_8b.bdf | 1081 ++++++++ shifter_8b/shifter_8b.done | 1 + shifter_8b/shifter_8b.fit.rpt | 1006 ++++++++ shifter_8b/shifter_8b.fit.smsg | 6 + shifter_8b/shifter_8b.fit.summary | 16 + shifter_8b/shifter_8b.flow.rpt | 120 + shifter_8b/shifter_8b.map.rpt | 223 ++ shifter_8b/shifter_8b.map.summary | 14 + shifter_8b/shifter_8b.pin | 278 ++ shifter_8b/shifter_8b.pof | Bin 0 -> 524488 bytes shifter_8b/shifter_8b.qpf | 30 + shifter_8b/shifter_8b.qsf | 53 + shifter_8b/shifter_8b.sof | Bin 0 -> 240789 bytes shifter_8b/shifter_8b.tan.rpt | 178 ++ shifter_8b/shifter_8b.tan.summary | 26 + shifter_8b/triple_selector_8b.bdf | 2247 +++++++++++++++++ shifter_8b/triple_selector_8b.bsf | 274 ++ .../db/triple_selector_8b.(0).cnf.cdb | Bin 0 -> 1502 bytes .../db/triple_selector_8b.(0).cnf.hdb | Bin 0 -> 1208 bytes .../db/triple_selector_8b.asm.qmsg | 7 + .../db/triple_selector_8b.asm_labs.ddb | Bin 0 -> 3853 bytes .../db/triple_selector_8b.cbx.xml | 5 + .../db/triple_selector_8b.cmp.bpm | Bin 0 -> 714 bytes .../db/triple_selector_8b.cmp.cdb | Bin 0 -> 5854 bytes .../db/triple_selector_8b.cmp.ecobp | Bin 0 -> 28 bytes .../db/triple_selector_8b.cmp.hdb | Bin 0 -> 7396 bytes .../db/triple_selector_8b.cmp.kpt | 10 + .../db/triple_selector_8b.cmp.logdb | 1 + .../db/triple_selector_8b.cmp.rdb | Bin 0 -> 16485 bytes .../db/triple_selector_8b.cmp.tdb | Bin 0 -> 4600 bytes .../db/triple_selector_8b.cmp0.ddb | Bin 0 -> 59672 bytes .../db/triple_selector_8b.cmp2.ddb | Bin 0 -> 41904 bytes .../db/triple_selector_8b.cmp_merge.kpt | 10 + .../db/triple_selector_8b.db_info | 3 + .../db/triple_selector_8b.eco.cdb | Bin 0 -> 175 bytes .../db/triple_selector_8b.fit.qmsg | 39 + .../db/triple_selector_8b.hier_info | 59 + triple_selector_8b/db/triple_selector_8b.hif | 42 + .../db/triple_selector_8b.lpc.html | 18 + .../db/triple_selector_8b.lpc.rdb | Bin 0 -> 399 bytes .../db/triple_selector_8b.lpc.txt | 5 + .../db/triple_selector_8b.map.bpm | Bin 0 -> 702 bytes .../db/triple_selector_8b.map.cdb | Bin 0 -> 1821 bytes .../db/triple_selector_8b.map.ecobp | Bin 0 -> 28 bytes .../db/triple_selector_8b.map.hdb | Bin 0 -> 7018 bytes .../db/triple_selector_8b.map.kpt | 10 + .../db/triple_selector_8b.map.logdb | 1 + .../db/triple_selector_8b.map.qmsg | 7 + .../db/triple_selector_8b.map_bb.cdb | Bin 0 -> 756 bytes .../db/triple_selector_8b.map_bb.hdb | Bin 0 -> 6323 bytes .../db/triple_selector_8b.map_bb.logdb | 1 + .../db/triple_selector_8b.pre_map.cdb | Bin 0 -> 1603 bytes .../db/triple_selector_8b.pre_map.hdb | Bin 0 -> 7160 bytes .../db/triple_selector_8b.rtlv.hdb | Bin 0 -> 7158 bytes .../db/triple_selector_8b.rtlv_sg.cdb | Bin 0 -> 1518 bytes .../db/triple_selector_8b.rtlv_sg_swap.cdb | Bin 0 -> 192 bytes .../db/triple_selector_8b.sgdiff.cdb | Bin 0 -> 1401 bytes .../db/triple_selector_8b.sgdiff.hdb | Bin 0 -> 7182 bytes .../triple_selector_8b.sld_design_entry.sci | Bin 0 -> 168 bytes ...riple_selector_8b.sld_design_entry_dsc.sci | Bin 0 -> 168 bytes .../db/triple_selector_8b.syn_hier_info | 0 .../db/triple_selector_8b.tan.qmsg | 6 + .../db/triple_selector_8b.tis_db_list.ddb | Bin 0 -> 188 bytes .../db/triple_selector_8b.tmw_info | 6 + triple_selector_8b/incremental_db/README | 11 + .../triple_selector_8b.root_partition.cmp.atm | Bin 0 -> 8675 bytes .../triple_selector_8b.root_partition.cmp.dfp | Bin 0 -> 33 bytes ...triple_selector_8b.root_partition.cmp.hdbx | Bin 0 -> 2157 bytes .../triple_selector_8b.root_partition.cmp.kpt | 10 + ...riple_selector_8b.root_partition.cmp.logdb | 1 + .../triple_selector_8b.root_partition.cmp.rcf | Bin 0 -> 1469 bytes .../triple_selector_8b.root_partition.map.atm | Bin 0 -> 5329 bytes .../triple_selector_8b.root_partition.map.dpi | Bin 0 -> 781 bytes ...triple_selector_8b.root_partition.map.hdbx | Bin 0 -> 2079 bytes .../triple_selector_8b.root_partition.map.kpt | 10 + triple_selector_8b/shifter_8b.bsf | 183 ++ triple_selector_8b/triple_selector_8b.asm.rpt | 129 + triple_selector_8b/triple_selector_8b.bdf | 2247 +++++++++++++++++ triple_selector_8b/triple_selector_8b.bsf | 274 ++ triple_selector_8b/triple_selector_8b.done | 1 + triple_selector_8b/triple_selector_8b.fit.rpt | 1094 ++++++++ .../triple_selector_8b.fit.smsg | 6 + .../triple_selector_8b.fit.summary | 16 + .../triple_selector_8b.flow.rpt | 120 + triple_selector_8b/triple_selector_8b.map.rpt | 218 ++ .../triple_selector_8b.map.summary | 14 + triple_selector_8b/triple_selector_8b.pin | 278 ++ triple_selector_8b/triple_selector_8b.pof | Bin 0 -> 524488 bytes triple_selector_8b/triple_selector_8b.qpf | 30 + triple_selector_8b/triple_selector_8b.qsf | 53 + triple_selector_8b/triple_selector_8b.qws | 14 + triple_selector_8b/triple_selector_8b.sof | Bin 0 -> 240789 bytes triple_selector_8b/triple_selector_8b.tan.rpt | 174 ++ .../triple_selector_8b.tan.summary | 26 + 159 files changed, 11204 insertions(+), 1 deletion(-) create mode 100644 adder_8b/adder_8b.qws create mode 100644 adder_8b/db/adder_8b.tmw_info create mode 100644 shifter_8b/db/prev_cmp_shifter_8b.map.qmsg create mode 100644 shifter_8b/db/prev_cmp_shifter_8b.qmsg create mode 100644 shifter_8b/db/shifter_8b.(0).cnf.cdb create mode 100644 shifter_8b/db/shifter_8b.(0).cnf.hdb create mode 100644 shifter_8b/db/shifter_8b.(1).cnf.cdb create mode 100644 shifter_8b/db/shifter_8b.(1).cnf.hdb create mode 100644 shifter_8b/db/shifter_8b.asm.qmsg create mode 100644 shifter_8b/db/shifter_8b.asm_labs.ddb create mode 100644 shifter_8b/db/shifter_8b.cbx.xml create mode 100644 shifter_8b/db/shifter_8b.cmp.bpm create mode 100644 shifter_8b/db/shifter_8b.cmp.cdb create mode 100644 shifter_8b/db/shifter_8b.cmp.ecobp create mode 100644 shifter_8b/db/shifter_8b.cmp.hdb create mode 100644 shifter_8b/db/shifter_8b.cmp.kpt create mode 100644 shifter_8b/db/shifter_8b.cmp.logdb create mode 100644 shifter_8b/db/shifter_8b.cmp.rdb create mode 100644 shifter_8b/db/shifter_8b.cmp.tdb create mode 100644 shifter_8b/db/shifter_8b.cmp0.ddb create mode 100644 shifter_8b/db/shifter_8b.cmp2.ddb create mode 100644 shifter_8b/db/shifter_8b.cmp_merge.kpt create mode 100644 shifter_8b/db/shifter_8b.db_info create mode 100644 shifter_8b/db/shifter_8b.eco.cdb create mode 100644 shifter_8b/db/shifter_8b.fit.qmsg create mode 100644 shifter_8b/db/shifter_8b.hier_info create mode 100644 shifter_8b/db/shifter_8b.hif create mode 100644 shifter_8b/db/shifter_8b.lpc.html create mode 100644 shifter_8b/db/shifter_8b.lpc.rdb create mode 100644 shifter_8b/db/shifter_8b.lpc.txt create mode 100644 shifter_8b/db/shifter_8b.map.bpm create mode 100644 shifter_8b/db/shifter_8b.map.cdb create mode 100644 shifter_8b/db/shifter_8b.map.ecobp create mode 100644 shifter_8b/db/shifter_8b.map.hdb create mode 100644 shifter_8b/db/shifter_8b.map.kpt create mode 100644 shifter_8b/db/shifter_8b.map.logdb create mode 100644 shifter_8b/db/shifter_8b.map.qmsg create mode 100644 shifter_8b/db/shifter_8b.map_bb.cdb create mode 100644 shifter_8b/db/shifter_8b.map_bb.hdb create mode 100644 shifter_8b/db/shifter_8b.map_bb.logdb create mode 100644 shifter_8b/db/shifter_8b.pre_map.cdb create mode 100644 shifter_8b/db/shifter_8b.pre_map.hdb create mode 100644 shifter_8b/db/shifter_8b.rtlv.hdb create mode 100644 shifter_8b/db/shifter_8b.rtlv_sg.cdb create mode 100644 shifter_8b/db/shifter_8b.rtlv_sg_swap.cdb create mode 100644 shifter_8b/db/shifter_8b.sgdiff.cdb create mode 100644 shifter_8b/db/shifter_8b.sgdiff.hdb create mode 100644 shifter_8b/db/shifter_8b.sld_design_entry.sci create mode 100644 shifter_8b/db/shifter_8b.sld_design_entry_dsc.sci create mode 100644 shifter_8b/db/shifter_8b.syn_hier_info create mode 100644 shifter_8b/db/shifter_8b.tan.qmsg create mode 100644 shifter_8b/db/shifter_8b.tis_db_list.ddb create mode 100644 shifter_8b/incremental_db/README create mode 100644 shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.atm create mode 100644 shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.dfp create mode 100644 shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.hdbx create mode 100644 shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.kpt create mode 100644 shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.logdb create mode 100644 shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.rcf create mode 100644 shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.atm create mode 100644 shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.dpi create mode 100644 shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.hdbx create mode 100644 shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.kpt create mode 100644 shifter_8b/shifter_8b.asm.rpt create mode 100644 shifter_8b/shifter_8b.bdf create mode 100644 shifter_8b/shifter_8b.done create mode 100644 shifter_8b/shifter_8b.fit.rpt create mode 100644 shifter_8b/shifter_8b.fit.smsg create mode 100644 shifter_8b/shifter_8b.fit.summary create mode 100644 shifter_8b/shifter_8b.flow.rpt create mode 100644 shifter_8b/shifter_8b.map.rpt create mode 100644 shifter_8b/shifter_8b.map.summary create mode 100644 shifter_8b/shifter_8b.pin create mode 100644 shifter_8b/shifter_8b.pof create mode 100644 shifter_8b/shifter_8b.qpf create mode 100644 shifter_8b/shifter_8b.qsf create mode 100644 shifter_8b/shifter_8b.sof create mode 100644 shifter_8b/shifter_8b.tan.rpt create mode 100644 shifter_8b/shifter_8b.tan.summary create mode 100644 shifter_8b/triple_selector_8b.bdf create mode 100644 shifter_8b/triple_selector_8b.bsf create mode 100644 triple_selector_8b/db/triple_selector_8b.(0).cnf.cdb create mode 100644 triple_selector_8b/db/triple_selector_8b.(0).cnf.hdb create mode 100644 triple_selector_8b/db/triple_selector_8b.asm.qmsg create mode 100644 triple_selector_8b/db/triple_selector_8b.asm_labs.ddb create mode 100644 triple_selector_8b/db/triple_selector_8b.cbx.xml create mode 100644 triple_selector_8b/db/triple_selector_8b.cmp.bpm create mode 100644 triple_selector_8b/db/triple_selector_8b.cmp.cdb create mode 100644 triple_selector_8b/db/triple_selector_8b.cmp.ecobp create mode 100644 triple_selector_8b/db/triple_selector_8b.cmp.hdb create mode 100644 triple_selector_8b/db/triple_selector_8b.cmp.kpt create mode 100644 triple_selector_8b/db/triple_selector_8b.cmp.logdb create mode 100644 triple_selector_8b/db/triple_selector_8b.cmp.rdb create mode 100644 triple_selector_8b/db/triple_selector_8b.cmp.tdb create mode 100644 triple_selector_8b/db/triple_selector_8b.cmp0.ddb create mode 100644 triple_selector_8b/db/triple_selector_8b.cmp2.ddb create mode 100644 triple_selector_8b/db/triple_selector_8b.cmp_merge.kpt create mode 100644 triple_selector_8b/db/triple_selector_8b.db_info create mode 100644 triple_selector_8b/db/triple_selector_8b.eco.cdb create mode 100644 triple_selector_8b/db/triple_selector_8b.fit.qmsg create mode 100644 triple_selector_8b/db/triple_selector_8b.hier_info create mode 100644 triple_selector_8b/db/triple_selector_8b.hif create mode 100644 triple_selector_8b/db/triple_selector_8b.lpc.html create mode 100644 triple_selector_8b/db/triple_selector_8b.lpc.rdb create mode 100644 triple_selector_8b/db/triple_selector_8b.lpc.txt create mode 100644 triple_selector_8b/db/triple_selector_8b.map.bpm create mode 100644 triple_selector_8b/db/triple_selector_8b.map.cdb create mode 100644 triple_selector_8b/db/triple_selector_8b.map.ecobp create mode 100644 triple_selector_8b/db/triple_selector_8b.map.hdb create mode 100644 triple_selector_8b/db/triple_selector_8b.map.kpt create mode 100644 triple_selector_8b/db/triple_selector_8b.map.logdb create mode 100644 triple_selector_8b/db/triple_selector_8b.map.qmsg create mode 100644 triple_selector_8b/db/triple_selector_8b.map_bb.cdb create mode 100644 triple_selector_8b/db/triple_selector_8b.map_bb.hdb create mode 100644 triple_selector_8b/db/triple_selector_8b.map_bb.logdb create mode 100644 triple_selector_8b/db/triple_selector_8b.pre_map.cdb create mode 100644 triple_selector_8b/db/triple_selector_8b.pre_map.hdb create mode 100644 triple_selector_8b/db/triple_selector_8b.rtlv.hdb create mode 100644 triple_selector_8b/db/triple_selector_8b.rtlv_sg.cdb create mode 100644 triple_selector_8b/db/triple_selector_8b.rtlv_sg_swap.cdb create mode 100644 triple_selector_8b/db/triple_selector_8b.sgdiff.cdb create mode 100644 triple_selector_8b/db/triple_selector_8b.sgdiff.hdb create mode 100644 triple_selector_8b/db/triple_selector_8b.sld_design_entry.sci create mode 100644 triple_selector_8b/db/triple_selector_8b.sld_design_entry_dsc.sci create mode 100644 triple_selector_8b/db/triple_selector_8b.syn_hier_info create mode 100644 triple_selector_8b/db/triple_selector_8b.tan.qmsg create mode 100644 triple_selector_8b/db/triple_selector_8b.tis_db_list.ddb create mode 100644 triple_selector_8b/db/triple_selector_8b.tmw_info create mode 100644 triple_selector_8b/incremental_db/README create mode 100644 triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.cmp.atm create mode 100644 triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.cmp.dfp create mode 100644 triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.cmp.hdbx create mode 100644 triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.cmp.kpt create mode 100644 triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.cmp.logdb create mode 100644 triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.cmp.rcf create mode 100644 triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.map.atm create mode 100644 triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.map.dpi create mode 100644 triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.map.hdbx create mode 100644 triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.map.kpt create mode 100644 triple_selector_8b/shifter_8b.bsf create mode 100644 triple_selector_8b/triple_selector_8b.asm.rpt create mode 100644 triple_selector_8b/triple_selector_8b.bdf create mode 100644 triple_selector_8b/triple_selector_8b.bsf create mode 100644 triple_selector_8b/triple_selector_8b.done create mode 100644 triple_selector_8b/triple_selector_8b.fit.rpt create mode 100644 triple_selector_8b/triple_selector_8b.fit.smsg create mode 100644 triple_selector_8b/triple_selector_8b.fit.summary create mode 100644 triple_selector_8b/triple_selector_8b.flow.rpt create mode 100644 triple_selector_8b/triple_selector_8b.map.rpt create mode 100644 triple_selector_8b/triple_selector_8b.map.summary create mode 100644 triple_selector_8b/triple_selector_8b.pin create mode 100644 triple_selector_8b/triple_selector_8b.pof create mode 100644 triple_selector_8b/triple_selector_8b.qpf create mode 100644 triple_selector_8b/triple_selector_8b.qsf create mode 100644 triple_selector_8b/triple_selector_8b.qws create mode 100644 triple_selector_8b/triple_selector_8b.sof create mode 100644 triple_selector_8b/triple_selector_8b.tan.rpt create mode 100644 triple_selector_8b/triple_selector_8b.tan.summary diff --git a/README.md b/README.md index b89dc79..57d4cc8 100644 --- a/README.md +++ b/README.md @@ -16,4 +16,12 @@ ### 38_decoder -3-8译ç å™¨ã€‚ \ No newline at end of file +3-8译ç å™¨ã€‚ + +### triple_selector_8b + +8ä½æ•°æ®é€‰æ‹©å™¨ï¼ˆä¸‰é€‰ä¸€ï¼‰ã€‚ + +### shifter_8b + +8ä½æ•°æ®ç§»ä½å™¨ã€‚ \ No newline at end of file diff --git a/adder_8b/adder_8b.qws b/adder_8b/adder_8b.qws new file mode 100644 index 0000000..9b540c2 --- /dev/null +++ b/adder_8b/adder_8b.qws @@ -0,0 +1,14 @@ +[ProjectWorkspace] +ptn_Child1=Frames +[ProjectWorkspace.Frames] +ptn_Child1=ChildFrames +[ProjectWorkspace.Frames.ChildFrames] +ptn_Child1=Document-0 +[ProjectWorkspace.Frames.ChildFrames.Document-0] +ptn_Child1=ViewFrame-0 +[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0] +DocPathName=adder_8b.bdf +DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde} +IsChildFrameDetached=False +IsActiveChildFrame=True +ptn_Child1=StateMap diff --git a/adder_8b/db/adder_8b.tmw_info b/adder_8b/db/adder_8b.tmw_info new file mode 100644 index 0000000..f9d7d70 --- /dev/null +++ b/adder_8b/db/adder_8b.tmw_info @@ -0,0 +1,6 @@ +start_full_compilation:s:00:00:06 +start_analysis_synthesis:s:00:00:02-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:02-start_full_compilation +start_assembler:s:00:00:01-start_full_compilation +start_timing_analyzer:s:00:00:01-start_full_compilation diff --git a/shifter_8b/db/prev_cmp_shifter_8b.map.qmsg b/shifter_8b/db/prev_cmp_shifter_8b.map.qmsg new file mode 100644 index 0000000..701b624 --- /dev/null +++ b/shifter_8b/db/prev_cmp_shifter_8b.map.qmsg @@ -0,0 +1,7 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:36:47 2022 " "Info: Processing started: Mon Mar 07 10:36:47 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 shifter_8b " "Info: Found entity 1: shifter_8b" { } { { "shifter_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_TOP" "shifter_8b " "Info: Elaborating entity \"shifter_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} +{ "Error" "ESGN_ENTITY_IS_MISSING" "inst triple_selector_8b " "Error: Node instance \"inst\" instantiates undefined entity \"triple_selector_8b\"" { } { { "shifter_8b.bdf" "inst" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { { 32 488 584 512 "inst" "" } } } } } 0 0 "Node instance \"%1!s!\" instantiates undefined entity \"%2!s!\"" 0 0 "" 0 -1} +{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "246 " "Error: Peak virtual memory: 246 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Error" "EQEXE_END_BANNER_TIME" "Mon Mar 07 10:36:47 2022 " "Error: Processing ended: Mon Mar 07 10:36:47 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Error: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Error: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/shifter_8b/db/prev_cmp_shifter_8b.qmsg b/shifter_8b/db/prev_cmp_shifter_8b.qmsg new file mode 100644 index 0000000..d72ebb1 --- /dev/null +++ b/shifter_8b/db/prev_cmp_shifter_8b.qmsg @@ -0,0 +1,8 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:36:47 2022 " "Info: Processing started: Mon Mar 07 10:36:47 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 shifter_8b " "Info: Found entity 1: shifter_8b" { } { { "shifter_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_TOP" "shifter_8b " "Info: Elaborating entity \"shifter_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} +{ "Error" "ESGN_ENTITY_IS_MISSING" "inst triple_selector_8b " "Error: Node instance \"inst\" instantiates undefined entity \"triple_selector_8b\"" { } { { "shifter_8b.bdf" "inst" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { { 32 488 584 512 "inst" "" } } } } } 0 0 "Node instance \"%1!s!\" instantiates undefined entity \"%2!s!\"" 0 0 "" 0 -1} +{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "246 " "Error: Peak virtual memory: 246 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Error" "EQEXE_END_BANNER_TIME" "Mon Mar 07 10:36:47 2022 " "Error: Processing ended: Mon Mar 07 10:36:47 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Error: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Error: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} +{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 0 s " "Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings" { } { } 0 0 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/shifter_8b/db/shifter_8b.(0).cnf.cdb b/shifter_8b/db/shifter_8b.(0).cnf.cdb new file mode 100644 index 0000000000000000000000000000000000000000..441729cff03f365333ac9f8b78f82d9f251aabfc GIT binary patch literal 1254 zcmV@6CZfX_)000000N?`v000000KEYK z000000OkY$000000C)lHSj%n`F%)%Do(rBr1;LUf8{QyRGYMiY9 zvCNmjU+@LpAl?!n-W|@l<9nI$Oq>h}Dij=fY#-la`#$U$C(rYI8+p+=_Z{W$$QasE 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triple_selector_8b:inst.B1 +A1 => triple_selector_8b:inst.C0 +A0 => triple_selector_8b:inst.A1 +A0 => triple_selector_8b:inst.B0 +A0 => inst2.IN0 +L => triple_selector_8b:inst.A0 +LM => triple_selector_8b:inst.AY +LM => inst1.IN0 +DM => triple_selector_8b:inst.BY +RM => triple_selector_8b:inst.CY +RM => inst2.IN1 +Y1 <= triple_selector_8b:inst.Y1 +Y2 <= triple_selector_8b:inst.Y2 +Y3 <= triple_selector_8b:inst.Y3 +Y4 <= triple_selector_8b:inst.Y4 +Y5 <= triple_selector_8b:inst.Y5 +Y6 <= triple_selector_8b:inst.Y6 +Y7 <= triple_selector_8b:inst.Y7 +OF <= inst3.DB_MAX_OUTPUT_PORT_TYPE + + +|shifter_8b|triple_selector_8b:inst +Y0 <= inst3.DB_MAX_OUTPUT_PORT_TYPE +B0 => inst1.IN0 +BY => inst1.IN1 +BY => inst5.IN1 +BY => inst9.IN1 +BY => inst13.IN1 +BY => inst16.IN1 +BY => inst21.IN1 +BY => inst24.IN1 +BY => inst29.IN1 +C0 => inst2.IN0 +CY => inst2.IN1 +CY => inst6.IN1 +CY => inst10.IN1 +CY => inst14.IN1 +CY => inst18.IN1 +CY => inst22.IN1 +CY => inst26.IN1 +CY => inst30.IN1 +A0 => inst.IN0 +AY => inst.IN1 +AY => inst4.IN1 +AY => inst8.IN1 +AY => inst12.IN1 +AY => inst17.IN1 +AY => inst20.IN1 +AY => inst25.IN1 +AY => inst28.IN1 +Y1 <= inst7.DB_MAX_OUTPUT_PORT_TYPE +B1 => inst5.IN0 +C1 => inst6.IN0 +A1 => inst4.IN0 +Y2 <= inst11.DB_MAX_OUTPUT_PORT_TYPE +B2 => inst9.IN0 +C2 => inst10.IN0 +A2 => inst8.IN0 +Y3 <= inst15.DB_MAX_OUTPUT_PORT_TYPE +B3 => inst13.IN0 +C3 => inst14.IN0 +A3 => inst12.IN0 +Y4 <= inst19.DB_MAX_OUTPUT_PORT_TYPE +B4 => inst16.IN0 +C4 => inst18.IN0 +A4 => inst17.IN0 +Y5 <= inst23.DB_MAX_OUTPUT_PORT_TYPE +B5 => inst21.IN0 +C5 => inst22.IN0 +A5 => inst20.IN0 +Y6 <= inst27.DB_MAX_OUTPUT_PORT_TYPE +B6 => inst24.IN0 +C6 => inst26.IN0 +A6 => inst25.IN0 +Y7 <= inst31.DB_MAX_OUTPUT_PORT_TYPE +B7 => inst29.IN0 +C7 => inst30.IN0 +A7 => inst28.IN0 + + diff --git a/shifter_8b/db/shifter_8b.hif b/shifter_8b/db/shifter_8b.hif new file mode 100644 index 0000000..82d156d --- /dev/null +++ b/shifter_8b/db/shifter_8b.hif @@ -0,0 +1,62 @@ +Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +11 +936 +OFF +OFF +OFF +ON +ON +ON +FV_OFF +Level2 +0 +0 +VRSM_ON +VHSM_ON +0 +-- Start Library Paths -- +-- End Library Paths -- +-- Start VHDL Libraries -- +-- End VHDL Libraries -- +# entity +shifter_8b +# storage +db|shifter_8b.(0).cnf +db|shifter_8b.(0).cnf +# case_insensitive +# source_file +shifter_8b.bdf +323ebfa5afd7389abf1fcd4efaf6de +26 +# internal_option { +BLOCK_DESIGN_NAMING +AUTO +} +# hierarchies { +| +} +# macro_sequence + +# end +# entity +triple_selector_8b +# storage +db|shifter_8b.(1).cnf +db|shifter_8b.(1).cnf +# case_insensitive +# source_file +triple_selector_8b.bdf +91b7a41e9ebd47591ce44c4793a9f2e +26 +# internal_option { +BLOCK_DESIGN_NAMING +AUTO +} +# hierarchies { +triple_selector_8b:inst +} +# macro_sequence + +# end +# complete + \ No newline at end of file diff --git a/shifter_8b/db/shifter_8b.lpc.html b/shifter_8b/db/shifter_8b.lpc.html new file mode 100644 index 0000000..10ca6de --- /dev/null +++ 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    HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
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+1,7 @@ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; inst ; 27 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 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b/shifter_8b/db/shifter_8b.map.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/shifter_8b/db/shifter_8b.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/shifter_8b/db/shifter_8b.map.qmsg b/shifter_8b/db/shifter_8b.map.qmsg new file mode 100644 index 0000000..f38999f --- /dev/null +++ b/shifter_8b/db/shifter_8b.map.qmsg @@ -0,0 +1,9 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:37:40 2022 " "Info: Processing started: Mon Mar 07 10:37:40 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 shifter_8b " "Info: Found entity 1: shifter_8b" { } { { "shifter_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_TOP" "shifter_8b " "Info: Elaborating entity \"shifter_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} +{ "Warning" "WSGN_SEARCH_FILE" "triple_selector_8b.bdf 1 1 " "Warning: Using design file triple_selector_8b.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 triple_selector_8b " "Info: Found entity 1: triple_selector_8b" { } { { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/triple_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "triple_selector_8b triple_selector_8b:inst " "Info: Elaborating entity \"triple_selector_8b\" for hierarchy \"triple_selector_8b:inst\"" { } { { "shifter_8b.bdf" "inst" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { { 32 488 584 512 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "ICUT_CUT_TM_SUMMARY" "39 " "Info: Implemented 39 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "13 " "Info: Implemented 13 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Info: Implemented 9 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "17 " "Info: Implemented 17 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" 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compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.atm b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.atm new file mode 100644 index 0000000000000000000000000000000000000000..c2b74b6423cd3ab4770963fae8a0728fdef19f00 GIT binary patch literal 7523 zcmYk91x%bxw1$BKr8pGpVnr4!?nR4jafdF&y|}v-mg4SOe1V1HP~6>FWGNIVP>Q=Q z*319jKR5SFCYi~Z_c`x5llhXVBtS*^=kv}vG}L!n7Oo5Q48&04VlE$5_3l#64ajF* z`V&elz_=B2{bg&>wa|@f1US-`E#7#(tS0151eD@c(PU~LTu>z@dX36I^ANCNkCG?x zV)A}{+wAu6PSN|=pOA4Z>5)FV5V&|xU?0?>$tm6XwH)43?15%%~;d0 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Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: D:/projects/quartus/shifter_8b/shifter_8b.sof + 6. Assembler Device Options: D:/projects/quartus/shifter_8b/shifter_8b.pof + 7. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Mon Mar 07 10:37:44 2022 ; +; Revision Name ; shifter_8b ; +; Top-level Entity Name ; shifter_8b ; +; Family ; Cyclone II ; +; Device ; EP2C8Q208C8 ; ++-----------------------+---------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Option ; Setting ; Default Value ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Use smart compilation ; Off ; Off ; +; Generate compressed bitstreams ; On ; On ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; Auto user code ; Off ; Off ; +; Use configuration device ; On ; On ; +; Configuration device ; Auto ; Auto ; +; Configuration device auto user code ; Off ; Off ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File start address ; 0 ; 0 ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Release clears before tri-states ; Off ; Off ; +; Auto-restart configuration after error ; On ; On ; +; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; ++-----------------------------------------------------------------------------+----------+---------------+ + + ++-----------------------------------------------+ +; Assembler Generated Files ; ++-----------------------------------------------+ +; File Name ; ++-----------------------------------------------+ +; D:/projects/quartus/shifter_8b/shifter_8b.sof ; +; D:/projects/quartus/shifter_8b/shifter_8b.pof ; ++-----------------------------------------------+ + + ++-------------------------------------------------------------------------+ +; Assembler Device Options: D:/projects/quartus/shifter_8b/shifter_8b.sof ; ++----------------+--------------------------------------------------------+ +; Option ; Setting ; ++----------------+--------------------------------------------------------+ +; Device ; EP2C8Q208C8 ; +; JTAG usercode ; 0xFFFFFFFF ; +; Checksum ; 0x000C7CD6 ; ++----------------+--------------------------------------------------------+ + + ++-------------------------------------------------------------------------+ +; Assembler Device Options: D:/projects/quartus/shifter_8b/shifter_8b.pof ; ++--------------------+----------------------------------------------------+ +; Option ; Setting ; ++--------------------+----------------------------------------------------+ +; Device ; EPCS4 ; +; JTAG usercode ; 0x00000000 ; +; Checksum ; 0x06F093B0 ; +; Compression Ratio ; 3 ; ++--------------------+----------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II Assembler + Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + Info: Processing started: Mon Mar 07 10:37:43 2022 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b +Info: Writing out detailed assembly data for power analysis +Info: Assembler is generating device programming files +Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled +Info: Quartus II Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 241 megabytes + Info: Processing ended: Mon Mar 07 10:37:44 2022 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/shifter_8b/shifter_8b.bdf b/shifter_8b/shifter_8b.bdf new file mode 100644 index 0000000..836a242 --- /dev/null +++ b/shifter_8b/shifter_8b.bdf @@ -0,0 +1,1081 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. 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b/shifter_8b/shifter_8b.fit.rpt new file mode 100644 index 0000000..eff54a9 --- /dev/null +++ b/shifter_8b/shifter_8b.fit.rpt @@ -0,0 +1,1006 @@ +Fitter report for shifter_8b +Mon Mar 07 10:37:42 2022 +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Input Pins + 11. Output Pins + 12. I/O Bank Usage + 13. All Package Pins + 14. Output Pin Default Load For Reported TCO + 15. Fitter Resource Utilization by Entity + 16. Delay Chain Summary + 17. Pad To Core Delay Chain Fanout + 18. Non-Global High Fan-Out Signals + 19. Interconnect Usage Summary + 20. LAB Logic Elements + 21. LAB Signals Sourced + 22. LAB Signals Sourced Out + 23. LAB Distinct Inputs + 24. Fitter Device Options + 25. Operating Settings and Conditions + 26. Estimated Delay Added for Hold Timing + 27. Advanced Data - General + 28. Advanced Data - Placement Preparation + 29. Advanced Data - Placement + 30. Advanced Data - Routing + 31. Fitter Messages + 32. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+----------------------------------------------+ +; Fitter Status ; Successful - Mon Mar 07 10:37:42 2022 ; +; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; +; Revision Name ; shifter_8b ; +; Top-level Entity Name ; shifter_8b ; +; Family ; Cyclone II ; +; Device ; EP2C8Q208C8 ; +; Timing Models ; Final ; +; Total logic elements ; 17 / 8,256 ( < 1 % ) ; +; Total combinational functions ; 17 / 8,256 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 22 / 138 ( 16 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 165,888 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; +; Total PLLs ; 0 / 2 ( 0 % ) ; ++------------------------------------+----------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Device ; EP2C8Q208C8 ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Use TimeQuest Timing Analyzer ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Always Enable Input Buffers ; Off ; Off ; +; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; +; Optimize Multi-Corner Timing ; Off ; Off ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; On ; On ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Global Memory Control Signals ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Merge PLLs ; On ; On ; +; Ignore PLL Mode When Merging PLLs ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Stop After Congestion Map Generation ; Off ; Off ; +; Save Intermediate Fitting Results ; Off ; Off ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; 1 processor ; 100.0% ; +; 2-4 processors ; < 0.1% ; ++----------------------------+-------------+ + + ++----------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++-------------------------+--------------------+ +; Type ; Value ; ++-------------------------+--------------------+ +; Placement ; ; +; -- Requested ; 0 / 39 ( 0.00 % ) ; +; -- Achieved ; 0 / 39 ( 0.00 % ) ; +; ; ; +; Routing (by Connection) ; ; +; -- Requested ; 0 / 0 ( 0.00 % ) ; +; -- Achieved ; 0 / 0 ( 0.00 % ) ; ++-------------------------+--------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ + + ++--------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++----------------+---------+-------------------+-------------------------+-------------------+ +; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; ++----------------+---------+-------------------+-------------------------+-------------------+ +; Top ; 39 ; 0 ; N/A ; Source File ; ++----------------+---------+-------------------+-------------------------+-------------------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin. + + ++--------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+----------------------+ +; Resource ; Usage ; ++---------------------------------------------+----------------------+ +; Total logic elements ; 17 / 8,256 ( < 1 % ) ; +; -- Combinational with no register ; 17 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 0 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 9 ; +; -- 3 input functions ; 8 ; +; -- <=2 input functions ; 0 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 17 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 0 / 8,646 ( 0 % ) ; +; -- Dedicated logic registers ; 0 / 8,256 ( 0 % ) ; +; -- I/O registers ; 0 / 390 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 2 / 516 ( < 1 % ) ; +; User inserted logic elements ; 0 ; +; Virtual pins ; 0 ; +; I/O pins ; 22 / 138 ( 16 % ) ; +; -- Clock pins ; 2 / 4 ( 50 % ) ; +; Global signals ; 0 ; +; M4Ks ; 0 / 36 ( 0 % ) ; +; Total block memory bits ; 0 / 165,888 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 165,888 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; +; PLLs ; 0 / 2 ( 0 % ) ; +; Global clocks ; 0 / 8 ( 0 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Maximum fan-out node ; LM ; +; Maximum fan-out ; 9 ; +; Highest non-global fan-out signal ; LM ; +; Highest non-global fan-out ; 9 ; +; Total fan-out ; 69 ; +; Average fan-out ; 1.64 ; ++---------------------------------------------+----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ; ++------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; A0 ; 60 ; 4 ; 3 ; 0 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; A1 ; 23 ; 1 ; 0 ; 9 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; A2 ; 27 ; 1 ; 0 ; 9 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; A3 ; 28 ; 1 ; 0 ; 9 ; 3 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; A4 ; 4 ; 1 ; 0 ; 18 ; 3 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; A5 ; 8 ; 1 ; 0 ; 17 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; A6 ; 14 ; 1 ; 0 ; 14 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; A7 ; 15 ; 1 ; 0 ; 14 ; 3 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; DM ; 35 ; 1 ; 0 ; 7 ; 1 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; L ; 199 ; 2 ; 3 ; 19 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; LM ; 57 ; 4 ; 1 ; 0 ; 2 ; 9 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; R ; 30 ; 1 ; 0 ; 8 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; RM ; 24 ; 1 ; 0 ; 9 ; 1 ; 9 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; ++------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; ++------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ +; OF ; 40 ; 1 ; 0 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Y0 ; 31 ; 1 ; 0 ; 8 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Y1 ; 34 ; 1 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Y2 ; 12 ; 1 ; 0 ; 16 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Y3 ; 11 ; 1 ; 0 ; 16 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Y4 ; 208 ; 2 ; 1 ; 19 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Y5 ; 13 ; 1 ; 0 ; 16 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Y6 ; 5 ; 1 ; 0 ; 17 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Y7 ; 33 ; 1 ; 0 ; 8 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; ++------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1 ; 20 / 32 ( 63 % ) ; 3.3V ; -- ; +; 2 ; 2 / 35 ( 6 % ) ; 3.3V ; -- ; +; 3 ; 1 / 35 ( 3 % ) ; 3.3V ; -- ; +; 4 ; 2 / 36 ( 6 % ) ; 3.3V ; -- ; ++----------+------------------+---------------+--------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; 1 ; 0 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; 2 ; 1 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; 3 ; 2 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 4 ; 3 ; 1 ; A4 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 5 ; 4 ; 1 ; Y6 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 6 ; 5 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 8 ; 6 ; 1 ; A5 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 10 ; 7 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 11 ; 8 ; 1 ; Y3 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 12 ; 9 ; 1 ; Y2 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 13 ; 10 ; 1 ; Y5 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 14 ; 18 ; 1 ; A6 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 15 ; 19 ; 1 ; A7 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; 18 ; 22 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; 19 ; 23 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; 20 ; 24 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ; +; 21 ; 25 ; 1 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ; +; 22 ; 26 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; 23 ; 27 ; 1 ; A1 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 24 ; 28 ; 1 ; RM ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 26 ; 29 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; 27 ; 30 ; 1 ; A2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 28 ; 31 ; 1 ; A3 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 30 ; 32 ; 1 ; R ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 31 ; 33 ; 1 ; Y0 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 33 ; 35 ; 1 ; Y7 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 34 ; 36 ; 1 ; Y1 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 35 ; 37 ; 1 ; DM ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 37 ; 39 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 39 ; 43 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 40 ; 44 ; 1 ; OF ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 41 ; 45 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 42 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 43 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 44 ; 49 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 45 ; 50 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 46 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 47 ; 52 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 48 ; 53 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 49 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 50 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; 51 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 52 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; 53 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 54 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; 55 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 56 ; 54 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 57 ; 55 ; 4 ; LM ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 58 ; 56 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 59 ; 57 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 60 ; 58 ; 4 ; A0 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 61 ; 59 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 63 ; 60 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 64 ; 61 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 67 ; 69 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 68 ; 70 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 69 ; 71 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 70 ; 74 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 71 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 72 ; 75 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 74 ; 76 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 75 ; 77 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 76 ; 78 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 77 ; 79 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 80 ; 82 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 81 ; 83 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 82 ; 84 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 83 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 84 ; 85 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 85 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 86 ; 86 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 87 ; 87 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 88 ; 88 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 89 ; 89 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 90 ; 90 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 91 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 92 ; 91 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 94 ; 92 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 95 ; 93 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 96 ; 94 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 97 ; 95 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 98 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 99 ; 96 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 100 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 101 ; 97 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 102 ; 98 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 103 ; 99 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 104 ; 100 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 105 ; 101 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 106 ; 102 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 107 ; 105 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 108 ; 106 ; 3 ; ~LVDS54p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 109 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 110 ; 107 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 111 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 112 ; 108 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 113 ; 109 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 114 ; 110 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 115 ; 112 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 116 ; 113 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 117 ; 114 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 118 ; 117 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 119 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 120 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 121 ; 121 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; 122 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 123 ; 122 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; 124 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 125 ; 123 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; 126 ; 124 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; 127 ; 125 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 128 ; 126 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 129 ; 127 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 130 ; 128 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 131 ; 129 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 132 ; 130 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 133 ; 131 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 134 ; 132 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 135 ; 133 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 136 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 137 ; 134 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 138 ; 135 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 139 ; 136 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 141 ; 137 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 142 ; 138 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 143 ; 141 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 144 ; 142 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 145 ; 143 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 146 ; 149 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 147 ; 150 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 148 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 149 ; 151 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 150 ; 152 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 151 ; 153 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 152 ; 154 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 153 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 154 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; 155 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 156 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; 157 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 158 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; 159 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 160 ; 155 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 161 ; 156 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 162 ; 157 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 163 ; 158 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 164 ; 159 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 165 ; 160 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 166 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 167 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 168 ; 161 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 169 ; 162 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 170 ; 163 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 171 ; 164 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 172 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 173 ; 165 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 174 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 175 ; 168 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 176 ; 169 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 177 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 178 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 179 ; 173 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 180 ; 174 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 181 ; 175 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 182 ; 176 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 183 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 184 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 185 ; 180 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 186 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 187 ; 181 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 188 ; 182 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 189 ; 183 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 190 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 191 ; 184 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 192 ; 185 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 193 ; 186 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 194 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 195 ; 187 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 196 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 197 ; 191 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 198 ; 192 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 199 ; 195 ; 2 ; L ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 200 ; 196 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 201 ; 197 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 202 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 203 ; 198 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 204 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 205 ; 199 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 206 ; 200 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 207 ; 201 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 208 ; 202 ; 2 ; Y4 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-------------------------------------------------------------------------------+ +; Output Pin Default Load For Reported TCO ; ++----------------------------------+-------+------------------------------------+ +; I/O Standard ; Load ; Termination Resistance ; ++----------------------------------+-------+------------------------------------+ +; 3.3-V LVTTL ; 0 pF ; Not Available ; +; 3.3-V LVCMOS ; 0 pF ; Not Available ; +; 2.5 V ; 0 pF ; Not Available ; +; 1.8 V ; 0 pF ; Not Available ; +; 1.5 V ; 0 pF ; Not Available ; +; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ; +; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ; +; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ; +; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ; +; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ; +; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ; +; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ; +; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ; +; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ; +; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ; +; LVDS ; 0 pF ; 100 Ohm (Differential) ; +; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ; +; RSDS ; 0 pF ; 100 Ohm (Differential) ; +; Simple RSDS ; 0 pF ; Not Available ; +; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ; ++----------------------------------+-------+------------------------------------+ +Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; ++------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------+--------------+ +; |shifter_8b ; 17 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 22 ; 0 ; 17 (1) ; 0 (0) ; 0 (0) ; |shifter_8b ; work ; +; |triple_selector_8b:inst| ; 16 (16) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (16) ; 0 (0) ; 0 (0) ; |shifter_8b|triple_selector_8b:inst ; work ; ++------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++------+----------+---------------+---------------+-----------------------+-----+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; ++------+----------+---------------+---------------+-----------------------+-----+ +; Y0 ; Output ; -- ; -- ; -- ; -- ; +; Y1 ; Output ; -- ; -- ; -- ; -- ; +; Y2 ; Output ; -- ; -- ; -- ; -- ; +; Y3 ; Output ; -- ; -- ; -- ; -- ; +; Y4 ; Output ; -- ; -- ; -- ; -- ; +; Y5 ; Output ; -- ; -- ; -- ; -- ; +; Y6 ; Output ; -- ; -- ; -- ; -- ; +; Y7 ; Output ; -- ; -- ; -- ; -- ; +; OF ; Output ; -- ; -- ; -- ; -- ; +; A0 ; Input ; 6 ; 6 ; -- ; -- ; +; L ; Input ; 6 ; 6 ; -- ; -- ; +; LM ; Input ; 6 ; 6 ; -- ; -- ; +; DM ; Input ; 6 ; 6 ; -- ; -- ; +; A1 ; Input ; 0 ; 0 ; -- ; -- ; +; RM ; Input ; 0 ; 0 ; -- ; -- ; +; A2 ; Input ; 0 ; 0 ; -- ; -- ; +; A3 ; Input ; 0 ; 0 ; -- ; -- ; +; A4 ; Input ; 6 ; 6 ; -- ; -- ; +; A5 ; Input ; 6 ; 6 ; -- ; -- ; +; A6 ; Input ; 6 ; 6 ; -- ; -- ; +; A7 ; Input ; 6 ; 6 ; -- ; -- ; +; R ; Input ; 6 ; 6 ; -- ; -- ; ++------+----------+---------------+---------------+-----------------------+-----+ + + ++-----------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++-----------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++-----------------------------------------+-------------------+---------+ +; A0 ; ; ; +; - triple_selector_8b:inst|inst3~0 ; 1 ; 6 ; +; - triple_selector_8b:inst|inst7~0 ; 1 ; 6 ; +; - inst3 ; 1 ; 6 ; +; L ; ; ; +; - triple_selector_8b:inst|inst3~0 ; 0 ; 6 ; +; LM ; ; ; +; - triple_selector_8b:inst|inst3~0 ; 1 ; 6 ; +; - triple_selector_8b:inst|inst7~0 ; 1 ; 6 ; +; - triple_selector_8b:inst|inst11~0 ; 1 ; 6 ; +; - triple_selector_8b:inst|inst15~0 ; 1 ; 6 ; +; - triple_selector_8b:inst|inst19~0 ; 1 ; 6 ; +; - triple_selector_8b:inst|inst23~0 ; 1 ; 6 ; +; - triple_selector_8b:inst|inst27~0 ; 1 ; 6 ; +; - triple_selector_8b:inst|inst31~0 ; 1 ; 6 ; +; - inst3 ; 1 ; 6 ; +; DM ; ; ; +; - triple_selector_8b:inst|inst3~0 ; 1 ; 6 ; +; - triple_selector_8b:inst|inst7~0 ; 1 ; 6 ; +; - triple_selector_8b:inst|inst11~0 ; 1 ; 6 ; +; - triple_selector_8b:inst|inst15~0 ; 1 ; 6 ; +; - triple_selector_8b:inst|inst19~0 ; 1 ; 6 ; +; - triple_selector_8b:inst|inst23~0 ; 1 ; 6 ; +; - triple_selector_8b:inst|inst27~0 ; 1 ; 6 ; +; - triple_selector_8b:inst|inst31~0 ; 1 ; 6 ; +; A1 ; ; ; +; RM ; ; ; +; A2 ; ; ; +; A3 ; ; ; +; A4 ; ; ; +; - triple_selector_8b:inst|inst15 ; 1 ; 6 ; +; - triple_selector_8b:inst|inst19~0 ; 1 ; 6 ; +; - triple_selector_8b:inst|inst23~0 ; 1 ; 6 ; +; A5 ; ; ; +; - triple_selector_8b:inst|inst19 ; 0 ; 6 ; +; - triple_selector_8b:inst|inst23~0 ; 0 ; 6 ; +; - triple_selector_8b:inst|inst27~0 ; 0 ; 6 ; +; A6 ; ; ; +; - triple_selector_8b:inst|inst23 ; 1 ; 6 ; +; - triple_selector_8b:inst|inst27~0 ; 0 ; 6 ; +; - triple_selector_8b:inst|inst31~0 ; 0 ; 6 ; +; A7 ; ; ; +; - triple_selector_8b:inst|inst27 ; 1 ; 6 ; +; - triple_selector_8b:inst|inst31~0 ; 1 ; 6 ; +; - inst3 ; 1 ; 6 ; +; R ; ; ; +; - triple_selector_8b:inst|inst31 ; 0 ; 6 ; ++-----------------------------------------+-------------------+---------+ + + ++--------------------------------------------+ +; Non-Global High Fan-Out Signals ; ++----------------------------------+---------+ +; Name ; Fan-Out ; ++----------------------------------+---------+ +; RM ; 9 ; +; LM ; 9 ; +; DM ; 8 ; +; A7 ; 3 ; +; A6 ; 3 ; +; A5 ; 3 ; +; A4 ; 3 ; +; A3 ; 3 ; +; A2 ; 3 ; +; A1 ; 3 ; +; A0 ; 3 ; +; R ; 1 ; +; L ; 1 ; +; inst3 ; 1 ; +; triple_selector_8b:inst|inst31 ; 1 ; +; triple_selector_8b:inst|inst31~0 ; 1 ; +; triple_selector_8b:inst|inst27 ; 1 ; +; triple_selector_8b:inst|inst27~0 ; 1 ; +; triple_selector_8b:inst|inst23 ; 1 ; +; triple_selector_8b:inst|inst23~0 ; 1 ; +; triple_selector_8b:inst|inst19 ; 1 ; +; triple_selector_8b:inst|inst19~0 ; 1 ; +; triple_selector_8b:inst|inst15 ; 1 ; +; triple_selector_8b:inst|inst15~0 ; 1 ; +; triple_selector_8b:inst|inst11 ; 1 ; +; triple_selector_8b:inst|inst11~0 ; 1 ; +; triple_selector_8b:inst|inst7 ; 1 ; +; triple_selector_8b:inst|inst7~0 ; 1 ; +; triple_selector_8b:inst|inst3 ; 1 ; +; triple_selector_8b:inst|inst3~0 ; 1 ; ++----------------------------------+---------+ + + ++----------------------------------------------------+ +; Interconnect Usage Summary ; ++----------------------------+-----------------------+ +; Interconnect Resource Type ; Usage ; ++----------------------------+-----------------------+ +; Block interconnects ; 26 / 26,052 ( < 1 % ) ; +; C16 interconnects ; 2 / 1,156 ( < 1 % ) ; +; C4 interconnects ; 30 / 17,952 ( < 1 % ) ; +; Direct links ; 0 / 26,052 ( 0 % ) ; +; Global clocks ; 0 / 8 ( 0 % ) ; +; Local interconnects ; 7 / 8,256 ( < 1 % ) ; +; R24 interconnects ; 0 / 1,020 ( 0 % ) ; +; R4 interconnects ; 6 / 22,440 ( < 1 % ) ; ++----------------------------+-----------------------+ + + ++--------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 8.50) ; Number of LABs (Total = 2) ; ++--------------------------------------------+-----------------------------+ +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 1 ; ++--------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++---------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 8.50) ; Number of LABs (Total = 2) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 5.00) ; Number of LABs (Total = 2) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 7.50) ; Number of LABs (Total = 2) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 1 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------+ +; Fitter Device Options ; ++----------------------------------------------+--------------------------+ +; Option ; Setting ; ++----------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; nCEO ; As output driving ground ; +; ASDO,nCSO ; As input tri-stated ; +; Reserve all unused pins ; As output driving ground ; +; Base pin-out file on sameframe device ; Off ; ++----------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing ; ++-----------------+----------------------+-------------------+ +; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; ++-----------------+----------------------+-------------------+ + + ++----------------------------+ +; Advanced Data - General ; ++--------------------+-------+ +; Name ; Value ; ++--------------------+-------+ +; Status Code ; 0 ; +; Desired User Slack ; 0 ; +; Fit Attempts ; 1 ; ++--------------------+-------+ + + ++-------------------------------------------------------------------------------+ +; Advanced Data - Placement Preparation ; ++------------------------------------------------------------------+------------+ +; Name ; Value ; ++------------------------------------------------------------------+------------+ +; Auto Fit Point 1 - Fit Attempt 1 ; ff ; +; Mid Wire Use - Fit Attempt 1 ; 0 ; +; Mid Slack - Fit Attempt 1 ; 2147483639 ; +; Internal Atom Count - Fit Attempt 1 ; 18 ; +; LE/ALM Count - Fit Attempt 1 ; 18 ; +; LAB Count - Fit Attempt 1 ; 3 ; +; Outputs per Lab - Fit Attempt 1 ; 3.333 ; +; Inputs per LAB - Fit Attempt 1 ; 5.000 ; +; Global Inputs per LAB - Fit Attempt 1 ; 0.000 ; +; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:3 ; +; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:3 ; +; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:3 ; +; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:3 ; +; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:3 ; +; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:3 ; +; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:3 ; +; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:3 ; +; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:3 ; +; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:3 ; +; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:3 ; +; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:3 ; +; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:2 ; +; LEs in Chains - Fit Attempt 1 ; 0 ; +; LEs in Long Chains - Fit Attempt 1 ; 0 ; +; LABs with Chains - Fit Attempt 1 ; 0 ; +; LABs with Multiple Chains - Fit Attempt 1 ; 0 ; +; Time - Fit Attempt 1 ; 0 ; +; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016 ; ++------------------------------------------------------------------+------------+ + + ++-------------------------------------------------+ +; Advanced Data - Placement ; ++------------------------------------+------------+ +; Name ; Value ; ++------------------------------------+------------+ +; Auto Fit Point 2 - Fit Attempt 1 ; ff ; +; Auto Fit Point 5 - Fit Attempt 1 ; ff ; +; Mid Wire Use - Fit Attempt 1 ; 0 ; +; Mid Slack - Fit Attempt 1 ; 2147483639 ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Auto Fit Point 5 - Fit Attempt 1 ; ff ; +; Mid Wire Use - Fit Attempt 1 ; 0 ; +; Mid Slack - Fit Attempt 1 ; 2147483639 ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Late Wire Use - Fit Attempt 1 ; 0 ; +; Late Slack - Fit Attempt 1 ; 2147483639 ; +; Peak Regional Wire - Fit Attempt 1 ; 0.000 ; +; Auto Fit Point 7 - Fit Attempt 1 ; ff ; +; Time - Fit Attempt 1 ; 0 ; ++------------------------------------+------------+ + + ++--------------------------------------------------+ +; Advanced Data - Routing ; ++------------------------------------+-------------+ +; Name ; Value ; ++------------------------------------+-------------+ +; Early Slack - Fit Attempt 1 ; 2147483639 ; +; Early Wire Use - Fit Attempt 1 ; 0 ; +; Peak Regional Wire - Fit Attempt 1 ; 1 ; +; Mid Slack - Fit Attempt 1 ; 2147483639 ; +; Late Slack - Fit Attempt 1 ; -2147483648 ; +; Late Wire Use - Fit Attempt 1 ; 0 ; +; Time - Fit Attempt 1 ; 0 ; ++------------------------------------+-------------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Info: ******************************************************************* +Info: Running Quartus II Fitter + Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + Info: Processing started: Mon Mar 07 10:37:41 2022 +Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b +Info: Parallel compilation is enabled and will use 4 of the 4 processors detected +Info: Selected device EP2C8Q208C8 for design "shifter_8b" +Info: Low junction temperature is 0 degrees C +Info: High junction temperature is 85 degrees C +Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info: Device EP2C5Q208C8 is compatible + Info: Device EP2C5Q208I8 is compatible + Info: Device EP2C8Q208I8 is compatible +Info: Fitter converted 3 user pins into dedicated programming pins + Info: Pin ~ASDO~ is reserved at location 1 + Info: Pin ~nCSO~ is reserved at location 2 + Info: Pin ~LVDS54p/nCEO~ is reserved at location 108 +Warning: No exact pin location assignment(s) for 22 pins of 22 total pins + Info: Pin Y0 not assigned to an exact location on the device + Info: Pin Y1 not assigned to an exact location on the device + Info: Pin Y2 not assigned to an exact location on the device + Info: Pin Y3 not assigned to an exact location on the device + Info: Pin Y4 not assigned to an exact location on the device + Info: Pin Y5 not assigned to an exact location on the device + Info: Pin Y6 not assigned to an exact location on the device + Info: Pin Y7 not assigned to an exact location on the device + Info: Pin OF not assigned to an exact location on the device + Info: Pin A0 not assigned to an exact location on the device + Info: Pin L not assigned to an exact location on the device + Info: Pin LM not assigned to an exact location on the device + Info: Pin DM not assigned to an exact location on the device + Info: Pin A1 not assigned to an exact location on the device + Info: Pin RM not assigned to an exact location on the device + Info: Pin A2 not assigned to an exact location on the device + Info: Pin A3 not assigned to an exact location on the device + Info: Pin A4 not assigned to an exact location on the device + Info: Pin A5 not assigned to an exact location on the device + Info: Pin A6 not assigned to an exact location on the device + Info: Pin A7 not assigned to an exact location on the device + Info: Pin R not assigned to an exact location on the device +Info: Fitter is using the Classic Timing Analyzer +Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time. +Info: Starting register packing +Info: Finished register packing + Extra Info: No registers were packed into other blocks +Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info: Number of I/O pins in group: 22 (unused VREF, 3.3V VCCIO, 13 input, 9 output, 0 bidirectional) + Info: I/O standards used: 3.3-V LVTTL. +Info: I/O bank details before I/O pin placement + Info: Statistics of I/O banks + Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available + Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available + Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available + Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available +Info: Fitter preparation operations ending: elapsed time is 00:00:01 +Info: Fitter placement preparation operations beginning +Info: Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info: Fitter placement operations beginning +Info: Fitter placement was successful +Info: Fitter placement operations ending: elapsed time is 00:00:00 +Info: Fitter routing operations beginning +Info: Average interconnect usage is 0% of the available device resources + Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X10_Y19 +Info: Fitter routing operations ending: elapsed time is 00:00:00 +Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info: Optimizations that may affect the design's routability were skipped + Info: Optimizations that may affect the design's timing were skipped +Info: Started post-fitting delay annotation +Warning: Found 9 output pins without output pin load capacitance assignment + Info: Pin "Y0" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "Y1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "Y2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "Y3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "Y4" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "Y5" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "Y6" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "Y7" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "OF" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis +Info: Delay annotation completed successfully +Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. +Info: Generated suppressed messages file D:/projects/quartus/shifter_8b/shifter_8b.fit.smsg +Info: Quartus II Fitter was successful. 0 errors, 3 warnings + Info: Peak virtual memory: 306 megabytes + Info: Processing ended: Mon Mar 07 10:37:42 2022 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in D:/projects/quartus/shifter_8b/shifter_8b.fit.smsg. + + diff --git a/shifter_8b/shifter_8b.fit.smsg b/shifter_8b/shifter_8b.fit.smsg new file mode 100644 index 0000000..14764e7 --- /dev/null +++ b/shifter_8b/shifter_8b.fit.smsg @@ -0,0 +1,6 @@ +Extra Info: Performing register packing on registers with non-logic cell location assignments +Extra Info: Completed register packing on registers with non-logic cell location assignments +Extra Info: Started Fast Input/Output/OE register processing +Extra Info: Finished Fast Input/Output/OE register processing +Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/shifter_8b/shifter_8b.fit.summary b/shifter_8b/shifter_8b.fit.summary new file mode 100644 index 0000000..1faa531 --- /dev/null +++ b/shifter_8b/shifter_8b.fit.summary @@ -0,0 +1,16 @@ +Fitter Status : Successful - Mon Mar 07 10:37:42 2022 +Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +Revision Name : shifter_8b +Top-level Entity Name : shifter_8b +Family : Cyclone II +Device : EP2C8Q208C8 +Timing Models : Final +Total logic elements : 17 / 8,256 ( < 1 % ) + Total combinational functions : 17 / 8,256 ( < 1 % ) + Dedicated logic registers : 0 / 8,256 ( 0 % ) +Total registers : 0 +Total pins : 22 / 138 ( 16 % ) +Total virtual pins : 0 +Total memory bits : 0 / 165,888 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % ) +Total PLLs : 0 / 2 ( 0 % ) diff --git a/shifter_8b/shifter_8b.flow.rpt b/shifter_8b/shifter_8b.flow.rpt new file mode 100644 index 0000000..a6e5837 --- /dev/null +++ b/shifter_8b/shifter_8b.flow.rpt @@ -0,0 +1,120 @@ +Flow report for shifter_8b +Mon Mar 07 10:37:44 2022 +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+----------------------------------------------+ +; Flow Status ; Successful - Mon Mar 07 10:37:44 2022 ; +; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; +; Revision Name ; shifter_8b ; +; Top-level Entity Name ; shifter_8b ; +; Family ; Cyclone II ; +; Device ; EP2C8Q208C8 ; +; Timing Models ; Final ; +; Met timing requirements ; Yes ; +; Total logic elements ; 17 / 8,256 ( < 1 % ) ; +; Total combinational functions ; 17 / 8,256 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 22 / 138 ( 16 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 165,888 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; +; Total PLLs ; 0 / 2 ( 0 % ) ; ++------------------------------------+----------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 03/07/2022 10:37:40 ; +; Main task ; Compilation ; +; Revision Name ; shifter_8b ; ++-------------------+---------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++------------------------------------+---------------------------------+---------------+-------------+----------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++------------------------------------+---------------------------------+---------------+-------------+----------------+ +; COMPILER_SIGNATURE_ID ; 220283517943889.164662066022984 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; +; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ; ++------------------------------------+---------------------------------+---------------+-------------+----------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 245 MB ; 00:00:00 ; +; Fitter ; 00:00:01 ; 1.0 ; 306 MB ; 00:00:01 ; +; Assembler ; 00:00:01 ; 1.0 ; 241 MB ; 00:00:00 ; +; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 198 MB ; 00:00:00 ; +; Total ; 00:00:02 ; -- ; -- ; 00:00:01 ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++------------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++-------------------------+------------------+---------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++-------------------------+------------------+---------------+------------+----------------+ +; Analysis & Synthesis ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; +; Fitter ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; +; Assembler ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; +; Classic Timing Analyzer ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; ++-------------------------+------------------+---------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b +quartus_fit --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b +quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b +quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only + + + diff --git a/shifter_8b/shifter_8b.map.rpt b/shifter_8b/shifter_8b.map.rpt new file mode 100644 index 0000000..98de55c --- /dev/null +++ b/shifter_8b/shifter_8b.map.rpt @@ -0,0 +1,223 @@ +Analysis & Synthesis report for shifter_8b +Mon Mar 07 10:37:40 2022 +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Analysis & Synthesis Source Files Read + 5. Analysis & Synthesis Resource Usage Summary + 6. Analysis & Synthesis Resource Utilization by Entity + 7. General Register Statistics + 8. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+----------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Mon Mar 07 10:37:40 2022 ; +; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; +; Revision Name ; shifter_8b ; +; Top-level Entity Name ; shifter_8b ; +; Family ; Cyclone II ; +; Total logic elements ; 17 ; +; Total combinational functions ; 17 ; +; Dedicated logic registers ; 0 ; +; Total registers ; 0 ; +; Total pins ; 22 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; ++------------------------------------+----------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++--------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP2C8Q208C8 ; ; +; Top-level entity name ; shifter_8b ; shifter_8b ; +; Family name ; Cyclone II ; Stratix II ; +; Use Generated Physical Constraints File ; Off ; ; +; Use smart compilation ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL93 ; VHDL93 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Parallel Synthesis ; Off ; Off ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; Off ; Off ; +; Show Parameter Settings Tables in Synthesis Report ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; ++--------------------------------------------------------------+--------------------+--------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------------+-------------------------------------------------------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; ++----------------------------------+-----------------+------------------------------------------+-------------------------------------------------------+ +; shifter_8b.bdf ; yes ; User Block Diagram/Schematic File ; D:/projects/quartus/shifter_8b/shifter_8b.bdf ; +; triple_selector_8b.bdf ; yes ; Auto-Found Block Diagram/Schematic File ; D:/projects/quartus/shifter_8b/triple_selector_8b.bdf ; ++----------------------------------+-----------------+------------------------------------------+-------------------------------------------------------+ + + ++-----------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-------+ +; Resource ; Usage ; ++---------------------------------------------+-------+ +; Estimated Total logic elements ; 17 ; +; ; ; +; Total combinational functions ; 17 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 9 ; +; -- 3 input functions ; 8 ; +; -- <=2 input functions ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 17 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 0 ; +; -- Dedicated logic registers ; 0 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 22 ; +; Maximum fan-out node ; LM ; +; Maximum fan-out ; 9 ; +; Total fan-out ; 69 ; +; Average fan-out ; 1.77 ; ++---------------------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------+--------------+ +; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------+--------------+ +; |shifter_8b ; 17 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 22 ; 0 ; |shifter_8b ; work ; +; |triple_selector_8b:inst| ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |shifter_8b|triple_selector_8b:inst ; work ; ++------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 0 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Analysis & Synthesis + Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + Info: Processing started: Mon Mar 07 10:37:40 2022 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b +Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf + Info: Found entity 1: shifter_8b +Info: Elaborating entity "shifter_8b" for the top level hierarchy +Warning: Using design file triple_selector_8b.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project + Info: Found entity 1: triple_selector_8b +Info: Elaborating entity "triple_selector_8b" for hierarchy "triple_selector_8b:inst" +Info: Implemented 39 device resources after synthesis - the final resource count might be different + Info: Implemented 13 input pins + Info: Implemented 9 output pins + Info: Implemented 17 logic cells +Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning + Info: Peak virtual memory: 249 megabytes + Info: Processing ended: Mon Mar 07 10:37:40 2022 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:00 + + diff --git a/shifter_8b/shifter_8b.map.summary b/shifter_8b/shifter_8b.map.summary new file mode 100644 index 0000000..757ffe6 --- /dev/null +++ b/shifter_8b/shifter_8b.map.summary @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Mon Mar 07 10:37:40 2022 +Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +Revision Name : shifter_8b +Top-level Entity Name : shifter_8b +Family : Cyclone II +Total logic elements : 17 + Total combinational functions : 17 + Dedicated logic registers : 0 +Total registers : 0 +Total pins : 22 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 diff --git a/shifter_8b/shifter_8b.pin b/shifter_8b/shifter_8b.pin new file mode 100644 index 0000000..66321e7 --- /dev/null +++ b/shifter_8b/shifter_8b.pin @@ -0,0 +1,278 @@ + -- Copyright (C) 1991-2009 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- Bank 3: 3.3V + -- Bank 4: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17), + -- connect each pin marked GND* either individually through a 10k Ohm resistor + -- to GND or tie all pins together and connect through a single 10k Ohm resistor + -- to GND. + -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +CHIP "shifter_8b" ASSIGNED TO AN: EP2C8Q208C8 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVTTL : : 1 : N +~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVTTL : : 1 : N +GND* : 3 : : : : 1 : +A4 : 4 : input : 3.3-V LVTTL : : 1 : N +Y6 : 5 : output : 3.3-V LVTTL : : 1 : N +GND* : 6 : : : : 1 : +VCCIO1 : 7 : power : : 3.3V : 1 : +A5 : 8 : input : 3.3-V LVTTL : : 1 : N +GND : 9 : gnd : : : : +GND* : 10 : : : : 1 : +Y3 : 11 : output : 3.3-V LVTTL : : 1 : N +Y2 : 12 : output : 3.3-V LVTTL : : 1 : N +Y5 : 13 : output : 3.3-V LVTTL : : 1 : N +A6 : 14 : input : 3.3-V LVTTL : : 1 : N +A7 : 15 : input : 3.3-V LVTTL : : 1 : N +TDO : 16 : output : : : 1 : +TMS : 17 : input : : : 1 : +TCK : 18 : input : : : 1 : +TDI : 19 : input : : : 1 : +DATA0 : 20 : input : : : 1 : +DCLK : 21 : : : : 1 : +nCE : 22 : : : : 1 : +A1 : 23 : input : 3.3-V LVTTL : : 1 : N +RM : 24 : input : 3.3-V LVTTL : : 1 : N +GND : 25 : gnd : : : : +nCONFIG : 26 : : : : 1 : +A2 : 27 : input : 3.3-V LVTTL : : 1 : N +A3 : 28 : input : 3.3-V LVTTL : : 1 : N +VCCIO1 : 29 : power : : 3.3V : 1 : +R : 30 : input : 3.3-V LVTTL : : 1 : N +Y0 : 31 : output : 3.3-V LVTTL : : 1 : N +VCCINT : 32 : power : : 1.2V : : +Y7 : 33 : output : 3.3-V LVTTL : : 1 : N +Y1 : 34 : output : 3.3-V LVTTL : : 1 : N +DM : 35 : input : 3.3-V LVTTL : : 1 : N +GND : 36 : gnd : : : : +GND* : 37 : : : : 1 : +GND : 38 : gnd : : : : +GND* : 39 : : : : 1 : +OF : 40 : output : 3.3-V LVTTL : : 1 : N +GND* : 41 : : : : 1 : +VCCIO1 : 42 : power : : 3.3V : 1 : +GND* : 43 : : : : 1 : +GND* : 44 : : : : 1 : +GND* : 45 : : : : 1 : +GND* : 46 : : : : 1 : +GND* : 47 : : : : 1 : +GND* : 48 : : : : 1 : +GND : 49 : gnd : : : : +GND_PLL1 : 50 : gnd : : : : +VCCD_PLL1 : 51 : power : : 1.2V : : +GND_PLL1 : 52 : gnd : : : : +VCCA_PLL1 : 53 : power : : 1.2V : : +GNDA_PLL1 : 54 : gnd : : : : +GND : 55 : gnd : : : : +GND* : 56 : : : : 4 : +LM : 57 : input : 3.3-V LVTTL : : 4 : N +GND* : 58 : : : : 4 : +GND* : 59 : : : : 4 : +A0 : 60 : input : 3.3-V LVTTL : : 4 : N +GND* : 61 : : : : 4 : +VCCIO4 : 62 : power : : 3.3V : 4 : +GND* : 63 : : : : 4 : +GND* : 64 : : : : 4 : +GND : 65 : gnd : : : : +VCCINT : 66 : power : : 1.2V : : +GND* : 67 : : : : 4 : +GND* : 68 : : : : 4 : +GND* : 69 : : : : 4 : +GND* : 70 : : : : 4 : +VCCIO4 : 71 : power : : 3.3V : 4 : +GND* : 72 : : : : 4 : +GND : 73 : gnd : : : : +GND* : 74 : : : : 4 : +GND* : 75 : : : : 4 : +GND* : 76 : : : : 4 : +GND* : 77 : : : : 4 : +GND : 78 : gnd : : : : +VCCINT : 79 : power : : 1.2V : : +GND* : 80 : : : : 4 : +GND* : 81 : : : : 4 : +GND* : 82 : : : : 4 : +VCCIO4 : 83 : power : : 3.3V : 4 : +GND* : 84 : : : : 4 : +GND : 85 : gnd : : : : +GND* : 86 : : : : 4 : +GND* : 87 : : : : 4 : +GND* : 88 : : : : 4 : +GND* : 89 : : : : 4 : +GND* : 90 : : : : 4 : +VCCIO4 : 91 : power : : 3.3V : 4 : +GND* : 92 : : : : 4 : +GND : 93 : gnd : : : : +GND* : 94 : : : : 4 : +GND* : 95 : : : : 4 : +GND* : 96 : : : : 4 : +GND* : 97 : : : : 4 : +VCCIO4 : 98 : power : : 3.3V : 4 : +GND* : 99 : : : : 4 : +GND : 100 : gnd : : : : +GND* : 101 : : : : 4 : +GND* : 102 : : : : 4 : +GND* : 103 : : : : 4 : +GND* : 104 : : : : 4 : +GND* : 105 : : : : 3 : +GND* : 106 : : : : 3 : +GND* : 107 : : : : 3 : +~LVDS54p/nCEO~ : 108 : output : 3.3-V LVTTL : : 3 : N +VCCIO3 : 109 : power : : 3.3V : 3 : +GND* : 110 : : : : 3 : +GND : 111 : gnd : : : : +GND* : 112 : : : : 3 : +GND* : 113 : : : : 3 : +GND* : 114 : : : : 3 : +GND* : 115 : : : : 3 : +GND* : 116 : : : : 3 : +GND* : 117 : : : : 3 : +GND* : 118 : : : : 3 : +GND : 119 : gnd : : : : +VCCINT : 120 : power : : 1.2V : : +nSTATUS : 121 : : : : 3 : +VCCIO3 : 122 : power : : 3.3V : 3 : +CONF_DONE : 123 : : : : 3 : +GND : 124 : gnd : : : : +MSEL1 : 125 : : : : 3 : +MSEL0 : 126 : : : : 3 : +GND* : 127 : : : : 3 : +GND* : 128 : : : : 3 : +GND+ : 129 : : : : 3 : +GND+ : 130 : : : : 3 : +GND+ : 131 : : : : 3 : +GND+ : 132 : : : : 3 : +GND* : 133 : : : : 3 : +GND* : 134 : : : : 3 : +GND* : 135 : : : : 3 : +VCCIO3 : 136 : power : : 3.3V : 3 : +GND* : 137 : : : : 3 : +GND* : 138 : : : : 3 : +GND* : 139 : : : : 3 : +GND : 140 : gnd : : : : +GND* : 141 : : : : 3 : +GND* : 142 : : : : 3 : +GND* : 143 : : : : 3 : +GND* : 144 : : : : 3 : +GND* : 145 : : : : 3 : +GND* : 146 : : : : 3 : +GND* : 147 : : : : 3 : +VCCIO3 : 148 : power : : 3.3V : 3 : +GND* : 149 : : : : 3 : +GND* : 150 : : : : 3 : +GND* : 151 : : : : 3 : +GND* : 152 : : : : 3 : +GND : 153 : gnd : : : : +GND_PLL2 : 154 : gnd : : : : +VCCD_PLL2 : 155 : power : : 1.2V : : +GND_PLL2 : 156 : gnd : : : : +VCCA_PLL2 : 157 : power : : 1.2V : : +GNDA_PLL2 : 158 : gnd : : : : +GND : 159 : gnd : : : : +GND* : 160 : : : : 2 : +GND* : 161 : : : : 2 : +GND* : 162 : : : : 2 : +GND* : 163 : : : : 2 : +GND* : 164 : : : : 2 : +GND* : 165 : : : : 2 : +VCCIO2 : 166 : power : : 3.3V : 2 : +GND : 167 : gnd : : : : +GND* : 168 : : : : 2 : +GND* : 169 : : : : 2 : +GND* : 170 : : : : 2 : +GND* : 171 : : : : 2 : +VCCIO2 : 172 : power : : 3.3V : 2 : +GND* : 173 : : : : 2 : +GND : 174 : gnd : : : : +GND* : 175 : : : : 2 : +GND* : 176 : : : : 2 : +GND : 177 : gnd : : : : +VCCINT : 178 : power : : 1.2V : : +GND* : 179 : : : : 2 : +GND* : 180 : : : : 2 : +GND* : 181 : : : : 2 : +GND* : 182 : : : : 2 : +VCCIO2 : 183 : power : : 3.3V : 2 : +GND : 184 : gnd : : : : +GND* : 185 : : : : 2 : +GND : 186 : gnd : : : : +GND* : 187 : : : : 2 : +GND* : 188 : : : : 2 : +GND* : 189 : : : : 2 : +VCCINT : 190 : power : : 1.2V : : +GND* : 191 : : : : 2 : +GND* : 192 : : : : 2 : +GND* : 193 : : : : 2 : +VCCIO2 : 194 : power : : 3.3V : 2 : +GND* : 195 : : : : 2 : +GND : 196 : gnd : : : : +GND* : 197 : : : : 2 : +GND* : 198 : : : : 2 : +L : 199 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a/shifter_8b/shifter_8b.qpf b/shifter_8b/shifter_8b.qpf new file mode 100644 index 0000000..2f3b44e --- /dev/null +++ b/shifter_8b/shifter_8b.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +# Date created = 10:34:26 March 07, 2022 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "9.0" +DATE = "10:34:26 March 07, 2022" + +# Revisions + +PROJECT_REVISION = "shifter_8b" diff --git a/shifter_8b/shifter_8b.qsf b/shifter_8b/shifter_8b.qsf new file mode 100644 index 0000000..fd6e762 --- /dev/null +++ b/shifter_8b/shifter_8b.qsf @@ -0,0 +1,53 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +# Date created = 10:34:26 March 07, 2022 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# shifter_8b_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone II" +set_global_assignment -name DEVICE EP2C8Q208C8 +set_global_assignment -name TOP_LEVEL_ENTITY shifter_8b +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:34:26 MARCH 07, 2022" +set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2" +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name BDF_FILE shifter_8b.bdf +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 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inst19.DB_MAX_OUTPUT_PORT_TYPE +B4 => inst16.IN0 +C4 => inst18.IN0 +A4 => inst17.IN0 +Y5 <= inst23.DB_MAX_OUTPUT_PORT_TYPE +B5 => inst21.IN0 +C5 => inst22.IN0 +A5 => inst20.IN0 +Y6 <= inst27.DB_MAX_OUTPUT_PORT_TYPE +B6 => inst24.IN0 +C6 => inst26.IN0 +A6 => inst25.IN0 +Y7 <= inst31.DB_MAX_OUTPUT_PORT_TYPE +B7 => inst29.IN0 +C7 => inst30.IN0 +A7 => inst28.IN0 + + diff --git a/triple_selector_8b/db/triple_selector_8b.hif b/triple_selector_8b/db/triple_selector_8b.hif new file mode 100644 index 0000000..096c9ff --- /dev/null +++ b/triple_selector_8b/db/triple_selector_8b.hif @@ -0,0 +1,42 @@ +Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +11 +936 +OFF +OFF +OFF +ON +ON +ON +FV_OFF +Level2 +0 +0 +VRSM_ON +VHSM_ON +0 +-- Start Library Paths -- +-- End Library Paths -- +-- Start VHDL Libraries -- +-- End VHDL Libraries -- +# entity +triple_selector_8b +# storage +db|triple_selector_8b.(0).cnf +db|triple_selector_8b.(0).cnf +# case_insensitive +# source_file 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    HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
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++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/triple_selector_8b/db/triple_selector_8b.map.bpm b/triple_selector_8b/db/triple_selector_8b.map.bpm new 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b/triple_selector_8b/db/triple_selector_8b.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/triple_selector_8b/db/triple_selector_8b.map.qmsg b/triple_selector_8b/db/triple_selector_8b.map.qmsg new file mode 100644 index 0000000..67830c6 --- /dev/null +++ b/triple_selector_8b/db/triple_selector_8b.map.qmsg @@ -0,0 +1,7 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:24:25 2022 " "Info: Processing started: Mon Mar 07 10:24:25 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off triple_selector_8b -c triple_selector_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off triple_selector_8b -c triple_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "triple_selector_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file triple_selector_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 triple_selector_8b " "Info: Found entity 1: triple_selector_8b" { } { { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_TOP" "triple_selector_8b " "Info: Elaborating entity \"triple_selector_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} +{ "Info" "ICUT_CUT_TM_SUMMARY" "51 " "Info: Implemented 51 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Info: Implemented 27 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "16 " "Info: Implemented 16 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "249 " "Info: Peak virtual memory: 249 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 10:24:26 2022 " "Info: Processing ended: Mon Mar 07 10:24:26 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/triple_selector_8b/db/triple_selector_8b.map_bb.cdb b/triple_selector_8b/db/triple_selector_8b.map_bb.cdb new file mode 100644 index 0000000000000000000000000000000000000000..ff17d9a70b21d5104ed0301673c43ce19888ff81 GIT binary patch literal 756 zcmd;QU|?9w&B%}kg!VvoSZYymW`3T6rJjL;Q)y;Sih_}`se*x-zM;9kk%57wLU3wP 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b/triple_selector_8b/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.cmp.atm b/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.cmp.atm new file mode 100644 index 0000000000000000000000000000000000000000..1f85076dd8b4f9a63843b85bf5539349dbd46803 GIT binary patch literal 8675 zcmY*;2Q*y$7p)i>5k?77M(-rb=*);@h)$ySHcHg!y#&J`1i?h_qW2bE)aWf*2+@0V z5u&~Eefi$|zq{AEYwo?jbI#uToZp(cYf6ajVBH>`sk>>fU2^1NdyGB&?@KzA!LmJ) zmy;r!DDELrtaYt|f70z!ckF6;>IkZNX*EmGSJ#M%#iVLkz^_{e*d-HCu z<|4&`=%%rmdMzdI^ZOgIH}%uV@i)dzEzLfO&pMYOM?Gs<;qeJ^Pis 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for triple_selector_8b +Mon Mar 07 10:24:29 2022 +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: D:/projects/quartus/triple_selector_8b/triple_selector_8b.sof + 6. Assembler Device Options: D:/projects/quartus/triple_selector_8b/triple_selector_8b.pof + 7. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Mon Mar 07 10:24:29 2022 ; +; Revision Name ; triple_selector_8b ; +; Top-level Entity Name ; triple_selector_8b ; +; Family ; Cyclone II ; +; Device ; EP2C8Q208C8 ; ++-----------------------+---------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Option ; Setting ; Default Value ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Use smart compilation ; Off ; Off ; +; Generate compressed bitstreams ; On ; On ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; Auto user code ; Off ; Off ; +; Use configuration device ; On ; On ; +; Configuration device ; Auto ; Auto ; +; Configuration device auto user code ; Off ; Off ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File start address ; 0 ; 0 ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Release clears before tri-states ; Off ; Off ; +; Auto-restart configuration after error ; On ; On ; +; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; ++-----------------------------------------------------------------------------+----------+---------------+ + + ++---------------------------------------------------------------+ +; Assembler Generated Files ; ++---------------------------------------------------------------+ +; File Name ; ++---------------------------------------------------------------+ +; D:/projects/quartus/triple_selector_8b/triple_selector_8b.sof ; +; D:/projects/quartus/triple_selector_8b/triple_selector_8b.pof ; ++---------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------+ +; Assembler Device Options: D:/projects/quartus/triple_selector_8b/triple_selector_8b.sof ; ++----------------+------------------------------------------------------------------------+ +; Option ; Setting ; ++----------------+------------------------------------------------------------------------+ +; Device ; EP2C8Q208C8 ; +; JTAG usercode ; 0xFFFFFFFF ; +; Checksum ; 0x000C82A8 ; ++----------------+------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------+ +; Assembler Device Options: D:/projects/quartus/triple_selector_8b/triple_selector_8b.pof ; ++--------------------+--------------------------------------------------------------------+ +; Option ; Setting ; ++--------------------+--------------------------------------------------------------------+ +; Device ; EPCS4 ; +; JTAG usercode ; 0x00000000 ; +; Checksum ; 0x06F0BC42 ; +; Compression Ratio ; 3 ; ++--------------------+--------------------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II Assembler + Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + Info: Processing started: Mon Mar 07 10:24:28 2022 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off triple_selector_8b -c triple_selector_8b +Info: Writing out detailed assembly data for power analysis +Info: Assembler is generating device programming files +Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled +Info: Quartus II Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 242 megabytes + Info: Processing ended: Mon Mar 07 10:24:29 2022 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/triple_selector_8b/triple_selector_8b.bdf b/triple_selector_8b/triple_selector_8b.bdf new file mode 100644 index 0000000..8eca736 --- /dev/null +++ b/triple_selector_8b/triple_selector_8b.bdf @@ -0,0 +1,2247 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. 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Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Input Pins + 11. Output Pins + 12. I/O Bank Usage + 13. All Package Pins + 14. Output Pin Default Load For Reported TCO + 15. Fitter Resource Utilization by Entity + 16. Delay Chain Summary + 17. Pad To Core Delay Chain Fanout + 18. Non-Global High Fan-Out Signals + 19. Interconnect Usage Summary + 20. LAB Logic Elements + 21. LAB Signals Sourced + 22. LAB Signals Sourced Out + 23. LAB Distinct Inputs + 24. Fitter Device Options + 25. Operating Settings and Conditions + 26. Estimated Delay Added for Hold Timing + 27. Advanced Data - General + 28. Advanced Data - Placement Preparation + 29. Advanced Data - Placement + 30. Advanced Data - Routing + 31. Fitter Messages + 32. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+----------------------------------------------+ +; Fitter Status ; Successful - Mon Mar 07 10:24:27 2022 ; +; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; +; Revision Name ; triple_selector_8b ; +; Top-level Entity Name ; triple_selector_8b ; +; Family ; Cyclone II ; +; Device ; EP2C8Q208C8 ; +; Timing Models ; Final ; +; Total logic elements ; 16 / 8,256 ( < 1 % ) ; +; Total combinational functions ; 16 / 8,256 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 35 / 138 ( 25 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 165,888 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; +; Total PLLs ; 0 / 2 ( 0 % ) ; ++------------------------------------+----------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Device ; EP2C8Q208C8 ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Use TimeQuest Timing Analyzer ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Always Enable Input Buffers ; Off ; Off ; +; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; +; Optimize Multi-Corner Timing ; Off ; Off ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; On ; On ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Global Memory Control Signals ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Merge PLLs ; On ; On ; +; Ignore PLL Mode When Merging PLLs ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Stop After Congestion Map Generation ; Off ; Off ; +; Save Intermediate Fitting Results ; Off ; Off ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; 1 processor ; 100.0% ; +; 2-4 processors ; < 0.1% ; ++----------------------------+-------------+ + + ++----------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++-------------------------+--------------------+ +; Type ; Value ; ++-------------------------+--------------------+ +; Placement ; ; +; -- Requested ; 0 / 51 ( 0.00 % ) ; +; -- Achieved ; 0 / 51 ( 0.00 % ) ; +; ; ; +; Routing (by Connection) ; ; +; -- Requested ; 0 / 0 ( 0.00 % ) ; +; -- Achieved ; 0 / 0 ( 0.00 % ) ; ++-------------------------+--------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ + + ++--------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++----------------+---------+-------------------+-------------------------+-------------------+ +; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; ++----------------+---------+-------------------+-------------------------+-------------------+ +; Top ; 51 ; 0 ; N/A ; Source File ; ++----------------+---------+-------------------+-------------------------+-------------------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in D:/projects/quartus/triple_selector_8b/triple_selector_8b.pin. + + ++--------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+----------------------+ +; Resource ; Usage ; ++---------------------------------------------+----------------------+ +; Total logic elements ; 16 / 8,256 ( < 1 % ) ; +; -- Combinational with no register ; 16 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 0 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 8 ; +; -- 3 input functions ; 8 ; +; -- <=2 input functions ; 0 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 16 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 0 / 8,646 ( 0 % ) ; +; -- Dedicated logic registers ; 0 / 8,256 ( 0 % ) ; +; -- I/O registers ; 0 / 390 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 1 / 516 ( < 1 % ) ; +; User inserted logic elements ; 0 ; +; Virtual pins ; 0 ; +; I/O pins ; 35 / 138 ( 25 % ) ; +; -- Clock pins ; 2 / 4 ( 50 % ) ; +; Global signals ; 0 ; +; M4Ks ; 0 / 36 ( 0 % ) ; +; Total block memory bits ; 0 / 165,888 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 165,888 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; +; PLLs ; 0 / 2 ( 0 % ) ; +; Global clocks ; 0 / 8 ( 0 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Maximum fan-out node ; AY ; +; Maximum fan-out ; 8 ; +; Highest non-global fan-out signal ; AY ; +; Highest non-global fan-out ; 8 ; +; Total fan-out ; 64 ; +; Average fan-out ; 1.19 ; ++---------------------------------------------+----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ; ++------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; A0 ; 110 ; 3 ; 34 ; 3 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; A1 ; 103 ; 4 ; 32 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; A2 ; 141 ; 3 ; 34 ; 12 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; A3 ; 129 ; 3 ; 34 ; 10 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; A4 ; 132 ; 3 ; 34 ; 10 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; A5 ; 143 ; 3 ; 34 ; 13 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; A6 ; 137 ; 3 ; 34 ; 11 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; A7 ; 135 ; 3 ; 34 ; 11 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; AY ; 127 ; 3 ; 34 ; 9 ; 1 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; B0 ; 138 ; 3 ; 34 ; 12 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; B1 ; 134 ; 3 ; 34 ; 11 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; B2 ; 105 ; 3 ; 34 ; 1 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; B3 ; 130 ; 3 ; 34 ; 10 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; B4 ; 128 ; 3 ; 34 ; 9 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; B5 ; 144 ; 3 ; 34 ; 13 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; B6 ; 115 ; 3 ; 34 ; 4 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; B7 ; 133 ; 3 ; 34 ; 11 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; BY ; 31 ; 1 ; 0 ; 8 ; 1 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; C0 ; 116 ; 3 ; 34 ; 5 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; C1 ; 139 ; 3 ; 34 ; 12 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; C2 ; 113 ; 3 ; 34 ; 3 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; C3 ; 131 ; 3 ; 34 ; 10 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; C4 ; 114 ; 3 ; 34 ; 4 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; C5 ; 145 ; 3 ; 34 ; 14 ; 4 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; C6 ; 112 ; 3 ; 34 ; 3 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; C7 ; 118 ; 3 ; 34 ; 7 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; CY ; 142 ; 3 ; 34 ; 12 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; ++------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; ++------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ +; Y0 ; 107 ; 3 ; 34 ; 2 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Y1 ; 15 ; 1 ; 0 ; 14 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Y2 ; 87 ; 4 ; 25 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Y3 ; 102 ; 4 ; 32 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Y4 ; 117 ; 3 ; 34 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Y5 ; 34 ; 1 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Y6 ; 30 ; 1 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Y7 ; 171 ; 2 ; 28 ; 19 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; ++------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1 ; 6 / 32 ( 19 % ) ; 3.3V ; -- ; +; 2 ; 1 / 35 ( 3 % ) ; 3.3V ; -- ; +; 3 ; 28 / 35 ( 80 % ) ; 3.3V ; -- ; +; 4 ; 3 / 36 ( 8 % ) ; 3.3V ; -- ; ++----------+------------------+---------------+--------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; 1 ; 0 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; 2 ; 1 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; 3 ; 2 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 4 ; 3 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 5 ; 4 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 6 ; 5 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 8 ; 6 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 10 ; 7 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 11 ; 8 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 12 ; 9 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 13 ; 10 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 14 ; 18 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 15 ; 19 ; 1 ; Y1 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; 18 ; 22 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; 19 ; 23 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; 20 ; 24 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ; +; 21 ; 25 ; 1 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ; +; 22 ; 26 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; 23 ; 27 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 24 ; 28 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 26 ; 29 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; 27 ; 30 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 28 ; 31 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 30 ; 32 ; 1 ; Y6 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 31 ; 33 ; 1 ; BY ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 33 ; 35 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 34 ; 36 ; 1 ; Y5 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 35 ; 37 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 37 ; 39 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 39 ; 43 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 40 ; 44 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 41 ; 45 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 42 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 43 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 44 ; 49 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 45 ; 50 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 46 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 47 ; 52 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 48 ; 53 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 49 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 50 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; 51 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 52 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; 53 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 54 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; 55 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 56 ; 54 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 57 ; 55 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 58 ; 56 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 59 ; 57 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 60 ; 58 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 61 ; 59 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 63 ; 60 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 64 ; 61 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 67 ; 69 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 68 ; 70 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 69 ; 71 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 70 ; 74 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 71 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 72 ; 75 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 74 ; 76 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 75 ; 77 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 76 ; 78 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 77 ; 79 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 80 ; 82 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 81 ; 83 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 82 ; 84 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 83 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 84 ; 85 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 85 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 86 ; 86 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 87 ; 87 ; 4 ; Y2 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 88 ; 88 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 89 ; 89 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 90 ; 90 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 91 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 92 ; 91 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 94 ; 92 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 95 ; 93 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 96 ; 94 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 97 ; 95 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 98 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 99 ; 96 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 100 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 101 ; 97 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 102 ; 98 ; 4 ; Y3 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 103 ; 99 ; 4 ; A1 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 104 ; 100 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 105 ; 101 ; 3 ; B2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 106 ; 102 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 107 ; 105 ; 3 ; Y0 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 108 ; 106 ; 3 ; ~LVDS54p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 109 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 110 ; 107 ; 3 ; A0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 111 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 112 ; 108 ; 3 ; C6 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 113 ; 109 ; 3 ; C2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 114 ; 110 ; 3 ; C4 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 115 ; 112 ; 3 ; B6 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 116 ; 113 ; 3 ; C0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 117 ; 114 ; 3 ; Y4 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 118 ; 117 ; 3 ; C7 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 119 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 120 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 121 ; 121 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; 122 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 123 ; 122 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; 124 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 125 ; 123 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; 126 ; 124 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; 127 ; 125 ; 3 ; AY ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 128 ; 126 ; 3 ; B4 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 129 ; 127 ; 3 ; A3 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 130 ; 128 ; 3 ; B3 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 131 ; 129 ; 3 ; C3 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 132 ; 130 ; 3 ; A4 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 133 ; 131 ; 3 ; B7 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 134 ; 132 ; 3 ; B1 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 135 ; 133 ; 3 ; A7 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 136 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 137 ; 134 ; 3 ; A6 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 138 ; 135 ; 3 ; B0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 139 ; 136 ; 3 ; C1 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 141 ; 137 ; 3 ; A2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 142 ; 138 ; 3 ; CY ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 143 ; 141 ; 3 ; A5 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 144 ; 142 ; 3 ; B5 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 145 ; 143 ; 3 ; C5 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 146 ; 149 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 147 ; 150 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 148 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 149 ; 151 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 150 ; 152 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 151 ; 153 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 152 ; 154 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 153 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 154 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; 155 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 156 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; 157 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 158 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; 159 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 160 ; 155 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 161 ; 156 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 162 ; 157 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 163 ; 158 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 164 ; 159 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 165 ; 160 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 166 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 167 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 168 ; 161 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 169 ; 162 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 170 ; 163 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 171 ; 164 ; 2 ; Y7 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 172 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 173 ; 165 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 174 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 175 ; 168 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 176 ; 169 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 177 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 178 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 179 ; 173 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 180 ; 174 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 181 ; 175 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 182 ; 176 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 183 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 184 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 185 ; 180 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 186 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 187 ; 181 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 188 ; 182 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 189 ; 183 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 190 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 191 ; 184 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 192 ; 185 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 193 ; 186 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 194 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 195 ; 187 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 196 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 197 ; 191 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 198 ; 192 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 199 ; 195 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 200 ; 196 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 201 ; 197 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 202 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 203 ; 198 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 204 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 205 ; 199 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 206 ; 200 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 207 ; 201 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 208 ; 202 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-------------------------------------------------------------------------------+ +; Output Pin Default Load For Reported TCO ; ++----------------------------------+-------+------------------------------------+ +; I/O Standard ; Load ; Termination Resistance ; ++----------------------------------+-------+------------------------------------+ +; 3.3-V LVTTL ; 0 pF ; Not Available ; +; 3.3-V LVCMOS ; 0 pF ; Not Available ; +; 2.5 V ; 0 pF ; Not Available ; +; 1.8 V ; 0 pF ; Not Available ; +; 1.5 V ; 0 pF ; Not Available ; +; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ; +; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ; +; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ; +; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ; +; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ; +; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ; +; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ; +; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ; +; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ; +; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ; +; LVDS ; 0 pF ; 100 Ohm (Differential) ; +; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ; +; RSDS ; 0 pF ; 100 Ohm (Differential) ; +; Simple RSDS ; 0 pF ; Not Available ; +; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ; ++----------------------------------+-------+------------------------------------+ +Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ +; |triple_selector_8b ; 16 (16) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 35 ; 0 ; 16 (16) ; 0 (0) ; 0 (0) ; |triple_selector_8b ; work ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++------+----------+---------------+---------------+-----------------------+-----+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; ++------+----------+---------------+---------------+-----------------------+-----+ +; Y0 ; Output ; -- ; -- ; -- ; -- ; +; Y1 ; Output ; -- ; -- ; -- ; -- ; +; Y2 ; Output ; -- ; -- ; -- ; -- ; +; Y3 ; Output ; -- ; -- ; -- ; -- ; +; Y4 ; Output ; -- ; -- ; -- ; -- ; +; Y5 ; Output ; -- ; -- ; -- ; -- ; +; Y6 ; Output ; -- ; -- ; -- ; -- ; +; Y7 ; Output ; -- ; -- ; -- ; -- ; +; B0 ; Input ; 6 ; 6 ; -- ; -- ; +; A0 ; Input ; 6 ; 6 ; -- ; -- ; +; AY ; Input ; 6 ; 6 ; -- ; -- ; +; BY ; Input ; 6 ; 6 ; -- ; -- ; +; C0 ; Input ; 6 ; 6 ; -- ; -- ; +; CY ; Input ; 6 ; 6 ; -- ; -- ; +; A1 ; Input ; 6 ; 6 ; -- ; -- ; +; B1 ; Input ; 6 ; 6 ; -- ; -- ; +; C1 ; Input ; 6 ; 6 ; -- ; -- ; +; A2 ; Input ; 6 ; 6 ; -- ; -- ; +; B2 ; Input ; 6 ; 6 ; -- ; -- ; +; C2 ; Input ; 6 ; 6 ; -- ; -- ; +; A3 ; Input ; 0 ; 0 ; -- ; -- ; +; B3 ; Input ; 0 ; 0 ; -- ; -- ; +; C3 ; Input ; 0 ; 0 ; -- ; -- ; +; A4 ; Input ; 0 ; 0 ; -- ; -- ; +; B4 ; Input ; 6 ; 6 ; -- ; -- ; +; C4 ; Input ; 6 ; 6 ; -- ; -- ; +; A5 ; Input ; 6 ; 6 ; -- ; -- ; +; B5 ; Input ; 6 ; 6 ; -- ; -- ; +; C5 ; Input ; 6 ; 6 ; -- ; -- ; +; A6 ; Input ; 6 ; 6 ; -- ; -- ; +; B6 ; Input ; 6 ; 6 ; -- ; -- ; +; C6 ; Input ; 6 ; 6 ; -- ; -- ; +; A7 ; Input ; 6 ; 6 ; -- ; -- ; +; B7 ; Input ; 6 ; 6 ; -- ; -- ; +; C7 ; Input ; 6 ; 6 ; -- ; -- ; ++------+----------+---------------+---------------+-----------------------+-----+ + + ++---------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++---------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++---------------------+-------------------+---------+ +; B0 ; ; ; +; - inst3~0 ; 1 ; 6 ; +; A0 ; ; ; +; - inst3~0 ; 0 ; 6 ; +; AY ; ; ; +; - inst3~0 ; 0 ; 6 ; +; - inst7~0 ; 0 ; 6 ; +; - inst11~0 ; 0 ; 6 ; +; - inst15~0 ; 0 ; 6 ; +; - inst19~0 ; 0 ; 6 ; +; - inst23~0 ; 0 ; 6 ; +; - inst27~0 ; 0 ; 6 ; +; - inst31~0 ; 0 ; 6 ; +; BY ; ; ; +; - inst3~0 ; 1 ; 6 ; +; - inst7~0 ; 1 ; 6 ; +; - inst11~0 ; 1 ; 6 ; +; - inst15~0 ; 1 ; 6 ; +; - inst19~0 ; 1 ; 6 ; +; - inst23~0 ; 1 ; 6 ; +; - inst27~0 ; 1 ; 6 ; +; - inst31~0 ; 1 ; 6 ; +; C0 ; ; ; +; - inst3 ; 0 ; 6 ; +; CY ; ; ; +; - inst3 ; 1 ; 6 ; +; - inst7 ; 1 ; 6 ; +; - inst11 ; 1 ; 6 ; +; - inst15 ; 1 ; 6 ; +; - inst19 ; 1 ; 6 ; +; - inst23 ; 1 ; 6 ; +; - inst27 ; 1 ; 6 ; +; - inst31 ; 1 ; 6 ; +; A1 ; ; ; +; - inst7~0 ; 0 ; 6 ; +; B1 ; ; ; +; - inst7~0 ; 1 ; 6 ; +; C1 ; ; ; +; - inst7 ; 0 ; 6 ; +; A2 ; ; ; +; - inst11~0 ; 1 ; 6 ; +; B2 ; ; ; +; - inst11~0 ; 0 ; 6 ; +; C2 ; ; ; +; - inst11 ; 0 ; 6 ; +; A3 ; ; ; +; B3 ; ; ; +; C3 ; ; ; +; A4 ; ; ; +; B4 ; ; ; +; - inst19~0 ; 1 ; 6 ; +; C4 ; ; ; +; - inst19 ; 1 ; 6 ; +; A5 ; ; ; +; - inst23~0 ; 1 ; 6 ; +; B5 ; ; ; +; - inst23~0 ; 0 ; 6 ; +; C5 ; ; ; +; - inst23 ; 0 ; 6 ; +; A6 ; ; ; +; - inst27~0 ; 1 ; 6 ; +; B6 ; ; ; +; - inst27~0 ; 0 ; 6 ; +; C6 ; ; ; +; - inst27 ; 1 ; 6 ; +; A7 ; ; ; +; - inst31~0 ; 1 ; 6 ; +; B7 ; ; ; +; - inst31~0 ; 1 ; 6 ; +; C7 ; ; ; +; - inst31 ; 0 ; 6 ; ++---------------------+-------------------+---------+ + + ++---------------------------------+ +; Non-Global High Fan-Out Signals ; ++----------+----------------------+ +; Name ; Fan-Out ; ++----------+----------------------+ +; CY ; 8 ; +; BY ; 8 ; +; AY ; 8 ; +; C7 ; 1 ; +; B7 ; 1 ; +; A7 ; 1 ; +; C6 ; 1 ; +; B6 ; 1 ; +; A6 ; 1 ; +; C5 ; 1 ; +; B5 ; 1 ; +; A5 ; 1 ; +; C4 ; 1 ; +; B4 ; 1 ; +; A4 ; 1 ; +; C3 ; 1 ; +; B3 ; 1 ; +; A3 ; 1 ; +; C2 ; 1 ; +; B2 ; 1 ; +; A2 ; 1 ; +; C1 ; 1 ; +; B1 ; 1 ; +; A1 ; 1 ; +; C0 ; 1 ; +; A0 ; 1 ; +; B0 ; 1 ; +; inst31 ; 1 ; +; inst31~0 ; 1 ; +; inst27 ; 1 ; +; inst27~0 ; 1 ; +; inst23 ; 1 ; +; inst23~0 ; 1 ; +; inst19 ; 1 ; +; inst19~0 ; 1 ; +; inst15 ; 1 ; +; inst15~0 ; 1 ; +; inst11 ; 1 ; +; inst11~0 ; 1 ; +; inst7 ; 1 ; +; inst7~0 ; 1 ; +; inst3 ; 1 ; +; inst3~0 ; 1 ; ++----------+----------------------+ + + ++----------------------------------------------------+ +; Interconnect Usage Summary ; ++----------------------------+-----------------------+ +; Interconnect Resource Type ; Usage ; ++----------------------------+-----------------------+ +; Block interconnects ; 36 / 26,052 ( < 1 % ) ; +; C16 interconnects ; 1 / 1,156 ( < 1 % ) ; +; C4 interconnects ; 47 / 17,952 ( < 1 % ) ; +; Direct links ; 0 / 26,052 ( 0 % ) ; +; Global clocks ; 0 / 8 ( 0 % ) ; +; Local interconnects ; 8 / 8,256 ( < 1 % ) ; +; R24 interconnects ; 5 / 1,020 ( < 1 % ) ; +; R4 interconnects ; 28 / 22,440 ( < 1 % ) ; ++----------------------------+-----------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Logic Elements ; ++---------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 16.00) ; Number of LABs (Total = 1) ; ++---------------------------------------------+-----------------------------+ +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 16.00) ; Number of LABs (Total = 1) ; ++----------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 1 ; ++----------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 8.00) ; Number of LABs (Total = 1) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++----------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 27.00) ; Number of LABs (Total = 1) ; ++----------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; +; 17 ; 0 ; +; 18 ; 0 ; +; 19 ; 0 ; +; 20 ; 0 ; +; 21 ; 0 ; +; 22 ; 0 ; +; 23 ; 0 ; +; 24 ; 0 ; +; 25 ; 0 ; +; 26 ; 0 ; +; 27 ; 1 ; ++----------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------+ +; Fitter Device Options ; ++----------------------------------------------+--------------------------+ +; Option ; Setting ; ++----------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; nCEO ; As output driving ground ; +; ASDO,nCSO ; As input tri-stated ; +; Reserve all unused pins ; As output driving ground ; +; Base pin-out file on sameframe device ; Off ; ++----------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing ; ++-----------------+----------------------+-------------------+ +; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; ++-----------------+----------------------+-------------------+ + + ++----------------------------+ +; Advanced Data - General ; ++--------------------+-------+ +; Name ; Value ; ++--------------------+-------+ +; Status Code ; 0 ; +; Desired User Slack ; 0 ; +; Fit Attempts ; 1 ; ++--------------------+-------+ + + ++-------------------------------------------------------------------------------+ +; Advanced Data - Placement Preparation ; ++------------------------------------------------------------------+------------+ +; Name ; Value ; ++------------------------------------------------------------------+------------+ +; Auto Fit Point 1 - Fit Attempt 1 ; ff ; +; Mid Wire Use - Fit Attempt 1 ; 0 ; +; Mid Slack - Fit Attempt 1 ; 2147483639 ; +; Internal Atom Count - Fit Attempt 1 ; 17 ; +; LE/ALM Count - Fit Attempt 1 ; 17 ; +; LAB Count - Fit Attempt 1 ; 2 ; +; Outputs per Lab - Fit Attempt 1 ; 4.000 ; +; Inputs per LAB - Fit Attempt 1 ; 13.500 ; +; Global Inputs per LAB - Fit Attempt 1 ; 0.000 ; +; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:2 ; +; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:2 ; +; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:2 ; +; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:2 ; +; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:2 ; +; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:2 ; +; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:2 ; +; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:2 ; +; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:2 ; +; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:2 ; +; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:2 ; +; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:2 ; +; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:1 ; +; LEs in Chains - Fit Attempt 1 ; 0 ; +; LEs in Long Chains - Fit Attempt 1 ; 0 ; +; LABs with Chains - Fit Attempt 1 ; 0 ; +; LABs with Multiple Chains - Fit Attempt 1 ; 0 ; +; Time - Fit Attempt 1 ; 0 ; ++------------------------------------------------------------------+------------+ + + ++--------------------------------------------------+ +; Advanced Data - Placement ; ++-------------------------------------+------------+ +; Name ; Value ; ++-------------------------------------+------------+ +; Auto Fit Point 2 - Fit Attempt 1 ; ff ; +; Auto Fit Point 5 - Fit Attempt 1 ; ff ; +; Mid Wire Use - Fit Attempt 1 ; 0 ; +; Mid Slack - Fit Attempt 1 ; 2147483639 ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Auto Fit Point 5 - Fit Attempt 1 ; ff ; +; Mid Wire Use - Fit Attempt 1 ; 0 ; +; Mid Slack - Fit Attempt 1 ; 2147483639 ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Auto Fit Point 6 - Fit Attempt 1 ; ff ; +; Late Wire Use - Fit Attempt 1 ; 0 ; +; Late Slack - Fit Attempt 1 ; 2147483639 ; +; Peak Regional Wire - Fit Attempt 1 ; 0.000 ; +; Auto Fit Point 7 - Fit Attempt 1 ; ff ; +; Time - Fit Attempt 1 ; 0 ; +; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016 ; ++-------------------------------------+------------+ + + ++--------------------------------------------------+ +; Advanced Data - Routing ; ++------------------------------------+-------------+ +; Name ; Value ; ++------------------------------------+-------------+ +; Early Slack - Fit Attempt 1 ; 2147483639 ; +; Early Wire Use - Fit Attempt 1 ; 0 ; +; Peak Regional Wire - Fit Attempt 1 ; 1 ; +; Mid Slack - Fit Attempt 1 ; 2147483639 ; +; Late Slack - Fit Attempt 1 ; -2147483648 ; +; Late Wire Use - Fit Attempt 1 ; 0 ; +; Time - Fit Attempt 1 ; 0 ; ++------------------------------------+-------------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Info: ******************************************************************* +Info: Running Quartus II Fitter + Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + Info: Processing started: Mon Mar 07 10:24:26 2022 +Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off triple_selector_8b -c triple_selector_8b +Info: Parallel compilation is enabled and will use 4 of the 4 processors detected +Info: Selected device EP2C8Q208C8 for design "triple_selector_8b" +Info: Low junction temperature is 0 degrees C +Info: High junction temperature is 85 degrees C +Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info: Device EP2C5Q208C8 is compatible + Info: Device EP2C5Q208I8 is compatible + Info: Device EP2C8Q208I8 is compatible +Info: Fitter converted 3 user pins into dedicated programming pins + Info: Pin ~ASDO~ is reserved at location 1 + Info: Pin ~nCSO~ is reserved at location 2 + Info: Pin ~LVDS54p/nCEO~ is reserved at location 108 +Warning: No exact pin location assignment(s) for 35 pins of 35 total pins + Info: Pin Y0 not assigned to an exact location on the device + Info: Pin Y1 not assigned to an exact location on the device + Info: Pin Y2 not assigned to an exact location on the device + Info: Pin Y3 not assigned to an exact location on the device + Info: Pin Y4 not assigned to an exact location on the device + Info: Pin Y5 not assigned to an exact location on the device + Info: Pin Y6 not assigned to an exact location on the device + Info: Pin Y7 not assigned to an exact location on the device + Info: Pin B0 not assigned to an exact location on the device + Info: Pin A0 not assigned to an exact location on the device + Info: Pin AY not assigned to an exact location on the device + Info: Pin BY not assigned to an exact location on the device + Info: Pin C0 not assigned to an exact location on the device + Info: Pin CY not assigned to an exact location on the device + Info: Pin A1 not assigned to an exact location on the device + Info: Pin B1 not assigned to an exact location on the device + Info: Pin C1 not assigned to an exact location on the device + Info: Pin A2 not assigned to an exact location on the device + Info: Pin B2 not assigned to an exact location on the device + Info: Pin C2 not assigned to an exact location on the device + Info: Pin A3 not assigned to an exact location on the device + Info: Pin B3 not assigned to an exact location on the device + Info: Pin C3 not assigned to an exact location on the device + Info: Pin A4 not assigned to an exact location on the device + Info: Pin B4 not assigned to an exact location on the device + Info: Pin C4 not assigned to an exact location on the device + Info: Pin A5 not assigned to an exact location on the device + Info: Pin B5 not assigned to an exact location on the device + Info: Pin C5 not assigned to an exact location on the device + Info: Pin A6 not assigned to an exact location on the device + Info: Pin B6 not assigned to an exact location on the device + Info: Pin C6 not assigned to an exact location on the device + Info: Pin A7 not assigned to an exact location on the device + Info: Pin B7 not assigned to an exact location on the device + Info: Pin C7 not assigned to an exact location on the device +Info: Fitter is using the Classic Timing Analyzer +Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time. +Info: Starting register packing +Info: Finished register packing + Extra Info: No registers were packed into other blocks +Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info: Number of I/O pins in group: 35 (unused VREF, 3.3V VCCIO, 27 input, 8 output, 0 bidirectional) + Info: I/O standards used: 3.3-V LVTTL. +Info: I/O bank details before I/O pin placement + Info: Statistics of I/O banks + Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available + Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available + Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available + Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available +Info: Fitter preparation operations ending: elapsed time is 00:00:00 +Info: Fitter placement preparation operations beginning +Info: Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info: Fitter placement operations beginning +Info: Fitter placement was successful +Info: Fitter placement operations ending: elapsed time is 00:00:00 +Info: Fitter routing operations beginning +Info: Average interconnect usage is 0% of the available device resources + Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y10 to location X34_Y19 +Info: Fitter routing operations ending: elapsed time is 00:00:00 +Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info: Optimizations that may affect the design's routability were skipped + Info: Optimizations that may affect the design's timing were skipped +Info: Started post-fitting delay annotation +Warning: Found 8 output pins without output pin load capacitance assignment + Info: Pin "Y0" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "Y1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "Y2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "Y3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "Y4" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "Y5" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "Y6" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "Y7" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis +Info: Delay annotation completed successfully +Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. +Info: Generated suppressed messages file D:/projects/quartus/triple_selector_8b/triple_selector_8b.fit.smsg +Info: Quartus II Fitter was successful. 0 errors, 3 warnings + Info: Peak virtual memory: 306 megabytes + Info: Processing ended: Mon Mar 07 10:24:27 2022 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in D:/projects/quartus/triple_selector_8b/triple_selector_8b.fit.smsg. + + diff --git a/triple_selector_8b/triple_selector_8b.fit.smsg b/triple_selector_8b/triple_selector_8b.fit.smsg new file mode 100644 index 0000000..14764e7 --- /dev/null +++ b/triple_selector_8b/triple_selector_8b.fit.smsg @@ -0,0 +1,6 @@ +Extra Info: Performing register packing on registers with non-logic cell location assignments +Extra Info: Completed register packing on registers with non-logic cell location assignments +Extra Info: Started Fast Input/Output/OE register processing +Extra Info: Finished Fast Input/Output/OE register processing +Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/triple_selector_8b/triple_selector_8b.fit.summary b/triple_selector_8b/triple_selector_8b.fit.summary new file mode 100644 index 0000000..e668314 --- /dev/null +++ b/triple_selector_8b/triple_selector_8b.fit.summary @@ -0,0 +1,16 @@ +Fitter Status : Successful - Mon Mar 07 10:24:27 2022 +Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +Revision Name : triple_selector_8b +Top-level Entity Name : triple_selector_8b +Family : Cyclone II +Device : EP2C8Q208C8 +Timing Models : Final +Total logic elements : 16 / 8,256 ( < 1 % ) + Total combinational functions : 16 / 8,256 ( < 1 % ) + Dedicated logic registers : 0 / 8,256 ( 0 % ) +Total registers : 0 +Total pins : 35 / 138 ( 25 % ) +Total virtual pins : 0 +Total memory bits : 0 / 165,888 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % ) +Total PLLs : 0 / 2 ( 0 % ) diff --git a/triple_selector_8b/triple_selector_8b.flow.rpt b/triple_selector_8b/triple_selector_8b.flow.rpt new file mode 100644 index 0000000..6342bf2 --- /dev/null +++ b/triple_selector_8b/triple_selector_8b.flow.rpt @@ -0,0 +1,120 @@ +Flow report for triple_selector_8b +Mon Mar 07 10:24:29 2022 +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+----------------------------------------------+ +; Flow Status ; Successful - Mon Mar 07 10:24:29 2022 ; +; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; +; Revision Name ; triple_selector_8b ; +; Top-level Entity Name ; triple_selector_8b ; +; Family ; Cyclone II ; +; Device ; EP2C8Q208C8 ; +; Timing Models ; Final ; +; Met timing requirements ; Yes ; +; Total logic elements ; 16 / 8,256 ( < 1 % ) ; +; Total combinational functions ; 16 / 8,256 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 35 / 138 ( 25 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 165,888 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; +; Total PLLs ; 0 / 2 ( 0 % ) ; ++------------------------------------+----------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 03/07/2022 10:24:25 ; +; Main task ; Compilation ; +; Revision Name ; triple_selector_8b ; ++-------------------+---------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++------------------------------------+---------------------------------+---------------+-------------+----------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++------------------------------------+---------------------------------+---------------+-------------+----------------+ +; COMPILER_SIGNATURE_ID ; 220283517943889.164661986528660 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; +; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ; ++------------------------------------+---------------------------------+---------------+-------------+----------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 245 MB ; 00:00:00 ; +; Fitter ; 00:00:01 ; 1.0 ; 306 MB ; 00:00:01 ; +; Assembler ; 00:00:01 ; 1.0 ; 242 MB ; 00:00:00 ; +; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 198 MB ; 00:00:00 ; +; Total ; 00:00:02 ; -- ; -- ; 00:00:01 ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++------------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++-------------------------+------------------+---------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++-------------------------+------------------+---------------+------------+----------------+ +; Analysis & Synthesis ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; +; Fitter ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; +; Assembler ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; +; Classic Timing Analyzer ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; ++-------------------------+------------------+---------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off triple_selector_8b -c triple_selector_8b +quartus_fit --read_settings_files=off --write_settings_files=off triple_selector_8b -c triple_selector_8b +quartus_asm --read_settings_files=off --write_settings_files=off triple_selector_8b -c triple_selector_8b +quartus_tan --read_settings_files=off --write_settings_files=off triple_selector_8b -c triple_selector_8b --timing_analysis_only + + + diff --git a/triple_selector_8b/triple_selector_8b.map.rpt b/triple_selector_8b/triple_selector_8b.map.rpt new file mode 100644 index 0000000..f157c1b --- /dev/null +++ b/triple_selector_8b/triple_selector_8b.map.rpt @@ -0,0 +1,218 @@ +Analysis & Synthesis report for triple_selector_8b +Mon Mar 07 10:24:26 2022 +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Analysis & Synthesis Source Files Read + 5. Analysis & Synthesis Resource Usage Summary + 6. Analysis & Synthesis Resource Utilization by Entity + 7. General Register Statistics + 8. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+----------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Mon Mar 07 10:24:25 2022 ; +; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; +; Revision Name ; triple_selector_8b ; +; Top-level Entity Name ; triple_selector_8b ; +; Family ; Cyclone II ; +; Total logic elements ; 16 ; +; Total combinational functions ; 16 ; +; Dedicated logic registers ; 0 ; +; Total registers ; 0 ; +; Total pins ; 35 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; ++------------------------------------+----------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++--------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP2C8Q208C8 ; ; +; Top-level entity name ; triple_selector_8b ; triple_selector_8b ; +; Family name ; Cyclone II ; Stratix II ; +; Use Generated Physical Constraints File ; Off ; ; +; Use smart compilation ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL93 ; VHDL93 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Parallel Synthesis ; Off ; Off ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; Off ; Off ; +; Show Parameter Settings Tables in Synthesis Report ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; ++--------------------------------------------------------------+--------------------+--------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; ++----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+ +; triple_selector_8b.bdf ; yes ; User Block Diagram/Schematic File ; D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf ; ++----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+ + + ++-----------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-------+ +; Resource ; Usage ; ++---------------------------------------------+-------+ +; Estimated Total logic elements ; 16 ; +; ; ; +; Total combinational functions ; 16 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 8 ; +; -- 3 input functions ; 8 ; +; -- <=2 input functions ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 16 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 0 ; +; -- Dedicated logic registers ; 0 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 35 ; +; Maximum fan-out node ; AY ; +; Maximum fan-out ; 8 ; +; Total fan-out ; 64 ; +; Average fan-out ; 1.25 ; ++---------------------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ +; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ +; |triple_selector_8b ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 35 ; 0 ; |triple_selector_8b ; work ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 0 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Analysis & Synthesis + Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + Info: Processing started: Mon Mar 07 10:24:25 2022 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off triple_selector_8b -c triple_selector_8b +Info: Found 1 design units, including 1 entities, in source file triple_selector_8b.bdf + Info: Found entity 1: triple_selector_8b +Info: Elaborating entity "triple_selector_8b" for the top level hierarchy +Info: Implemented 51 device resources after synthesis - the final resource count might be different + Info: Implemented 27 input pins + Info: Implemented 8 output pins + Info: Implemented 16 logic cells +Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 249 megabytes + Info: Processing ended: Mon Mar 07 10:24:26 2022 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:00 + + diff --git a/triple_selector_8b/triple_selector_8b.map.summary b/triple_selector_8b/triple_selector_8b.map.summary new file mode 100644 index 0000000..1508710 --- /dev/null +++ b/triple_selector_8b/triple_selector_8b.map.summary @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Mon Mar 07 10:24:25 2022 +Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition +Revision Name : triple_selector_8b +Top-level Entity Name : triple_selector_8b +Family : Cyclone II +Total logic elements : 16 + Total combinational functions : 16 + Dedicated logic registers : 0 +Total registers : 0 +Total pins : 35 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 diff --git a/triple_selector_8b/triple_selector_8b.pin b/triple_selector_8b/triple_selector_8b.pin new file mode 100644 index 0000000..232228d --- /dev/null +++ b/triple_selector_8b/triple_selector_8b.pin @@ -0,0 +1,278 @@ + -- Copyright (C) 1991-2009 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- Bank 3: 3.3V + -- Bank 4: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17), + -- connect each pin marked GND* either individually through a 10k Ohm resistor + -- to GND or tie all pins together and connect through a single 10k Ohm resistor + -- to GND. + -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +CHIP "triple_selector_8b" ASSIGNED TO AN: EP2C8Q208C8 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVTTL : : 1 : N +~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVTTL : : 1 : N +GND* : 3 : : : : 1 : +GND* : 4 : : : : 1 : +GND* : 5 : : : : 1 : +GND* : 6 : : : : 1 : +VCCIO1 : 7 : power : : 3.3V : 1 : +GND* : 8 : : : : 1 : +GND : 9 : gnd : : : : +GND* : 10 : : : : 1 : +GND* : 11 : : : : 1 : +GND* : 12 : : : : 1 : +GND* : 13 : : : : 1 : +GND* : 14 : : : : 1 : +Y1 : 15 : output : 3.3-V LVTTL : : 1 : N +TDO : 16 : output : : : 1 : +TMS : 17 : input : : : 1 : +TCK : 18 : input : : : 1 : +TDI : 19 : input : : : 1 : +DATA0 : 20 : input : : : 1 : +DCLK : 21 : : : : 1 : +nCE : 22 : : : : 1 : +GND+ : 23 : : : : 1 : +GND+ : 24 : : : : 1 : +GND : 25 : gnd : : : : +nCONFIG : 26 : : : : 1 : +GND+ : 27 : : : : 1 : +GND+ : 28 : : : : 1 : +VCCIO1 : 29 : power : : 3.3V : 1 : +Y6 : 30 : output : 3.3-V LVTTL : : 1 : N +BY : 31 : input : 3.3-V LVTTL : : 1 : N +VCCINT : 32 : power : : 1.2V : : +GND* : 33 : : : : 1 : +Y5 : 34 : output : 3.3-V LVTTL : : 1 : N +GND* : 35 : : : : 1 : +GND : 36 : gnd : : : : +GND* : 37 : : : : 1 : +GND : 38 : gnd : : : : +GND* : 39 : : : : 1 : +GND* : 40 : : : : 1 : +GND* : 41 : : : : 1 : +VCCIO1 : 42 : power : : 3.3V : 1 : +GND* : 43 : : : : 1 : +GND* : 44 : : : : 1 : +GND* : 45 : : : : 1 : +GND* : 46 : : : : 1 : +GND* : 47 : : : : 1 : +GND* : 48 : : : : 1 : +GND : 49 : gnd : : : : +GND_PLL1 : 50 : gnd : : : : +VCCD_PLL1 : 51 : power : : 1.2V : : +GND_PLL1 : 52 : gnd : : : : +VCCA_PLL1 : 53 : power : : 1.2V : : +GNDA_PLL1 : 54 : gnd : : : : +GND : 55 : gnd : : : : +GND* : 56 : : : : 4 : +GND* : 57 : : : : 4 : +GND* : 58 : : : : 4 : +GND* : 59 : : : : 4 : +GND* : 60 : : : : 4 : +GND* : 61 : : : : 4 : +VCCIO4 : 62 : power : : 3.3V : 4 : +GND* : 63 : : : : 4 : +GND* : 64 : : : : 4 : +GND : 65 : gnd : : : : +VCCINT : 66 : power : : 1.2V : : +GND* : 67 : : : : 4 : +GND* : 68 : : : : 4 : +GND* : 69 : : : : 4 : +GND* : 70 : : : : 4 : +VCCIO4 : 71 : power : : 3.3V : 4 : +GND* : 72 : : : : 4 : +GND : 73 : gnd : : : : +GND* : 74 : : : : 4 : +GND* : 75 : : : : 4 : +GND* : 76 : : : : 4 : +GND* : 77 : : : : 4 : +GND : 78 : gnd : : : : +VCCINT : 79 : power : : 1.2V : : +GND* : 80 : : : : 4 : +GND* : 81 : : : : 4 : +GND* : 82 : : : : 4 : +VCCIO4 : 83 : power : : 3.3V : 4 : +GND* : 84 : : : : 4 : +GND : 85 : gnd : : : : +GND* : 86 : : : : 4 : +Y2 : 87 : output : 3.3-V LVTTL : : 4 : N +GND* : 88 : : : : 4 : +GND* : 89 : : : : 4 : +GND* : 90 : : : : 4 : +VCCIO4 : 91 : power : : 3.3V : 4 : +GND* : 92 : : : : 4 : +GND : 93 : gnd : : : : +GND* : 94 : : : : 4 : +GND* : 95 : : : : 4 : +GND* : 96 : : : : 4 : +GND* : 97 : : : : 4 : +VCCIO4 : 98 : power : : 3.3V : 4 : +GND* : 99 : : : : 4 : +GND : 100 : gnd : : : : +GND* : 101 : : : : 4 : +Y3 : 102 : output : 3.3-V LVTTL : : 4 : N +A1 : 103 : input : 3.3-V LVTTL : : 4 : N +GND* : 104 : : : : 4 : +B2 : 105 : input : 3.3-V LVTTL : : 3 : N +GND* : 106 : : : : 3 : +Y0 : 107 : output : 3.3-V LVTTL : : 3 : N +~LVDS54p/nCEO~ : 108 : output : 3.3-V LVTTL : : 3 : N +VCCIO3 : 109 : power : : 3.3V : 3 : +A0 : 110 : input : 3.3-V LVTTL : : 3 : N +GND : 111 : gnd : : : : +C6 : 112 : input : 3.3-V LVTTL : : 3 : N +C2 : 113 : input : 3.3-V LVTTL : : 3 : N +C4 : 114 : input : 3.3-V LVTTL : : 3 : N +B6 : 115 : input : 3.3-V LVTTL : : 3 : N +C0 : 116 : input : 3.3-V LVTTL : : 3 : N +Y4 : 117 : output : 3.3-V LVTTL : : 3 : N +C7 : 118 : input : 3.3-V LVTTL : : 3 : N +GND : 119 : gnd : : : : +VCCINT : 120 : power : : 1.2V : : +nSTATUS : 121 : : : : 3 : +VCCIO3 : 122 : power : : 3.3V : 3 : +CONF_DONE : 123 : : : : 3 : +GND : 124 : gnd : : : : +MSEL1 : 125 : : : : 3 : +MSEL0 : 126 : : : : 3 : +AY : 127 : input : 3.3-V LVTTL : : 3 : N +B4 : 128 : input : 3.3-V LVTTL : : 3 : N +A3 : 129 : input : 3.3-V LVTTL : : 3 : N +B3 : 130 : input : 3.3-V LVTTL : : 3 : N +C3 : 131 : input : 3.3-V LVTTL : : 3 : N +A4 : 132 : input : 3.3-V LVTTL : : 3 : N +B7 : 133 : input : 3.3-V LVTTL : : 3 : N +B1 : 134 : input : 3.3-V LVTTL : : 3 : N +A7 : 135 : input : 3.3-V LVTTL : : 3 : N +VCCIO3 : 136 : power : : 3.3V : 3 : +A6 : 137 : input : 3.3-V LVTTL : : 3 : N +B0 : 138 : input : 3.3-V LVTTL : : 3 : N +C1 : 139 : input : 3.3-V LVTTL : : 3 : N +GND : 140 : gnd : : : : +A2 : 141 : input : 3.3-V LVTTL : : 3 : N +CY : 142 : input : 3.3-V LVTTL : : 3 : N +A5 : 143 : input : 3.3-V LVTTL : : 3 : N +B5 : 144 : input : 3.3-V LVTTL : : 3 : N +C5 : 145 : input : 3.3-V LVTTL : : 3 : N +GND* : 146 : : : : 3 : +GND* : 147 : : : : 3 : +VCCIO3 : 148 : power : : 3.3V : 3 : +GND* : 149 : : : : 3 : +GND* : 150 : : : : 3 : +GND* : 151 : : : : 3 : +GND* : 152 : : : : 3 : +GND : 153 : gnd : : : : +GND_PLL2 : 154 : gnd : : : : +VCCD_PLL2 : 155 : power : : 1.2V : : +GND_PLL2 : 156 : gnd : : : : +VCCA_PLL2 : 157 : power : : 1.2V : : +GNDA_PLL2 : 158 : gnd : : : : +GND : 159 : gnd : : : : +GND* : 160 : : : : 2 : +GND* : 161 : : : : 2 : +GND* : 162 : : : : 2 : +GND* : 163 : : : : 2 : +GND* : 164 : : : : 2 : +GND* : 165 : : : : 2 : +VCCIO2 : 166 : power : : 3.3V : 2 : +GND : 167 : gnd : : : : +GND* : 168 : : : : 2 : +GND* : 169 : : : : 2 : +GND* : 170 : : : : 2 : +Y7 : 171 : output : 3.3-V LVTTL : : 2 : N +VCCIO2 : 172 : power : : 3.3V : 2 : +GND* : 173 : : : : 2 : +GND : 174 : gnd : : : : +GND* : 175 : : : : 2 : +GND* : 176 : : : : 2 : +GND : 177 : gnd : : : : +VCCINT : 178 : power : : 1.2V : : +GND* : 179 : : : : 2 : +GND* : 180 : : : : 2 : +GND* : 181 : : : : 2 : +GND* : 182 : : : : 2 : +VCCIO2 : 183 : power : : 3.3V : 2 : +GND : 184 : gnd : : : : +GND* : 185 : : : : 2 : +GND : 186 : gnd : : : : +GND* : 187 : : : : 2 : +GND* : 188 : : : : 2 : +GND* : 189 : : : : 2 : +VCCINT : 190 : power : : 1.2V : : +GND* : 191 : : : : 2 : +GND* : 192 : : : : 2 : +GND* : 193 : : : : 2 : +VCCIO2 : 194 : power : : 3.3V : 2 : +GND* : 195 : : : : 2 : +GND : 196 : gnd : : : : +GND* : 197 : : : : 2 : +GND* : 198 : : : : 2 : +GND* : 199 : : : : 2 : +GND* : 200 : : : : 2 : +GND* : 201 : : : : 2 : +VCCIO2 : 202 : power : : 3.3V : 2 : +GND* : 203 : : : : 2 : +GND : 204 : gnd : : : : +GND* : 205 : : : : 2 : +GND* : 206 : : : : 2 : +GND* : 207 : : : : 2 : +GND* : 208 : : : : 2 : diff --git a/triple_selector_8b/triple_selector_8b.pof b/triple_selector_8b/triple_selector_8b.pof new file mode 100644 index 0000000000000000000000000000000000000000..1be17812505b7201e648e9ab7296e1d7c25d25eb GIT binary patch literal 524488 zcmeI*4VY8)o#^p1V{C(K?IaUy7@;KLNF#3pGx&m{Bq7ifa0)6a-QBy&TPv+yTea4E zd!MIC$hZMfOJH}Q)&*RAR`2#cD)8*;*0mA1d)2jy$h{YCZ7pkWZ~Hv91h7_nQSR@5 zPLj#%%sFUu#{HgWCOPlte?I4b{%_|cix{i@}Gc`H}nE{kdH<_6|1o_ozq?F?;{Z06cOzkT)XH?LZ$ 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Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +# Date created = 10:23:46 March 07, 2022 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "9.0" +DATE = "10:23:46 March 07, 2022" + +# Revisions + +PROJECT_REVISION = "triple_selector_8b" diff --git a/triple_selector_8b/triple_selector_8b.qsf b/triple_selector_8b/triple_selector_8b.qsf new file mode 100644 index 0000000..9b3392b --- /dev/null +++ b/triple_selector_8b/triple_selector_8b.qsf @@ -0,0 +1,53 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +# Date created = 10:23:46 March 07, 2022 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# triple_selector_8b_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone II" +set_global_assignment -name DEVICE EP2C8Q208C8 +set_global_assignment -name TOP_LEVEL_ENTITY triple_selector_8b +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:23:46 MARCH 07, 2022" +set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2" +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name BDF_FILE triple_selector_8b.bdf +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" \ No newline at end of file diff --git a/triple_selector_8b/triple_selector_8b.qws b/triple_selector_8b/triple_selector_8b.qws new file mode 100644 index 0000000..7891c27 --- /dev/null +++ b/triple_selector_8b/triple_selector_8b.qws @@ -0,0 +1,14 @@ +[ProjectWorkspace] +ptn_Child1=Frames +[ProjectWorkspace.Frames] +ptn_Child1=ChildFrames +[ProjectWorkspace.Frames.ChildFrames] +ptn_Child1=Document-0 +[ProjectWorkspace.Frames.ChildFrames.Document-0] +ptn_Child1=ViewFrame-0 +[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0] +DocPathName=triple_selector_8b.bdf +DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde} +IsChildFrameDetached=False +IsActiveChildFrame=True +ptn_Child1=StateMap diff --git a/triple_selector_8b/triple_selector_8b.sof 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HcmV?d00001 diff --git a/triple_selector_8b/triple_selector_8b.tan.rpt b/triple_selector_8b/triple_selector_8b.tan.rpt new file mode 100644 index 0000000..855cc3e --- /dev/null +++ b/triple_selector_8b/triple_selector_8b.tan.rpt @@ -0,0 +1,174 @@ +Classic Timing Analyzer report for triple_selector_8b +Mon Mar 07 10:24:29 2022 +Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Timing Analyzer Settings + 4. Parallel Compilation + 5. tpd + 6. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ +; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; ++------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ +; Worst-case tpd ; N/A ; None ; 16.101 ns ; BY ; Y6 ; -- ; -- ; 0 ; +; Total number of failed paths ; ; ; ; ; ; ; ; 0 ; ++------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ + + ++--------------------------------------------------------------------------------------------------------------------+ +; Timing Analyzer Settings ; ++---------------------------------------------------------------------+--------------------+------+----+-------------+ +; Option ; Setting ; From ; To ; Entity Name ; ++---------------------------------------------------------------------+--------------------+------+----+-------------+ +; Device Name ; EP2C8Q208C8 ; ; ; ; +; Timing Models ; Final ; ; ; ; +; Default hold multicycle ; Same as Multicycle ; ; ; ; +; Cut paths between unrelated clock domains ; On ; ; ; ; +; Cut off read during write signal paths ; On ; ; ; ; +; Cut off feedback from I/O pins ; On ; ; ; ; +; Report Combined Fast/Slow Timing ; Off ; ; ; ; +; Ignore Clock Settings ; Off ; ; ; ; +; Analyze latches as synchronous elements ; On ; ; ; ; +; Enable Recovery/Removal analysis ; Off ; ; ; ; +; Enable Clock Latency ; Off ; ; ; ; +; Use TimeQuest Timing Analyzer ; Off ; ; ; ; +; Minimum Core Junction Temperature ; 0 ; ; ; ; +; Maximum Core Junction Temperature ; 85 ; ; ; ; +; Number of source nodes to report per destination node ; 10 ; ; ; ; +; Number of destination nodes to report ; 10 ; ; ; ; +; Number of paths to report ; 200 ; ; ; ; +; Report Minimum Timing Checks ; Off ; ; ; ; +; Use Fast Timing Models ; Off ; ; ; ; +; Report IO Paths Separately ; Off ; ; ; ; +; Perform Multicorner Analysis ; On ; ; ; ; +; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ; +; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ; +; Output I/O Timing Endpoint ; Near End ; ; ; ; ++---------------------------------------------------------------------+--------------------+------+----+-------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; 1 processor ; 100.0% ; +; 2-4 processors ; 0.0% ; ++----------------------------+-------------+ + + ++---------------------------------------------------------+ +; tpd ; ++-------+-------------------+-----------------+------+----+ +; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ; ++-------+-------------------+-----------------+------+----+ +; N/A ; None ; 16.101 ns ; BY ; Y6 ; +; N/A ; None ; 15.802 ns ; AY ; Y6 ; +; N/A ; None ; 15.533 ns ; BY ; Y5 ; +; N/A ; None ; 15.448 ns ; BY ; Y1 ; +; N/A ; None ; 15.059 ns ; BY ; Y2 ; +; N/A ; None ; 15.018 ns ; B6 ; Y6 ; +; N/A ; None ; 14.809 ns ; A1 ; Y1 ; +; N/A ; None ; 14.793 ns ; B2 ; Y2 ; +; N/A ; None ; 14.673 ns ; BY ; Y3 ; +; N/A ; None ; 14.653 ns ; BY ; Y0 ; +; N/A ; None ; 14.271 ns ; BY ; Y7 ; +; N/A ; None ; 14.263 ns ; B5 ; Y5 ; +; N/A ; None ; 14.243 ns ; C6 ; Y6 ; +; N/A ; None ; 14.234 ns ; AY ; Y5 ; +; N/A ; None ; 14.152 ns ; AY ; Y1 ; +; N/A ; None ; 14.062 ns ; A5 ; Y5 ; +; N/A ; None ; 13.973 ns ; A6 ; Y6 ; +; N/A ; None ; 13.949 ns ; CY ; Y6 ; +; N/A ; None ; 13.897 ns ; A0 ; Y0 ; +; N/A ; None ; 13.829 ns ; BY ; Y4 ; +; N/A ; None ; 13.768 ns ; AY ; Y2 ; +; N/A ; None ; 13.685 ns ; CY ; Y5 ; +; N/A ; None ; 13.662 ns ; A2 ; Y2 ; +; N/A ; None ; 13.484 ns ; C2 ; Y2 ; +; N/A ; None ; 13.409 ns ; B1 ; Y1 ; +; N/A ; None ; 13.376 ns ; AY ; Y3 ; +; N/A ; None ; 13.362 ns ; AY ; Y0 ; +; N/A ; None ; 13.348 ns ; B0 ; Y0 ; +; N/A ; None ; 13.191 ns ; CY ; Y2 ; +; N/A ; None ; 13.149 ns ; C5 ; Y5 ; +; N/A ; None ; 12.995 ns ; CY ; Y1 ; +; N/A ; None ; 12.981 ns ; AY ; Y7 ; +; N/A ; None ; 12.730 ns ; C1 ; Y1 ; +; N/A ; None ; 12.665 ns ; C7 ; Y7 ; +; N/A ; None ; 12.656 ns ; A7 ; Y7 ; +; N/A ; None ; 12.630 ns ; B4 ; Y4 ; +; N/A ; None ; 12.565 ns ; B7 ; Y7 ; +; N/A ; None ; 12.532 ns ; AY ; Y4 ; +; N/A ; None ; 12.414 ns ; CY ; Y7 ; +; N/A ; None ; 12.344 ns ; C0 ; Y0 ; +; N/A ; None ; 12.325 ns ; C4 ; Y4 ; +; N/A ; None ; 12.158 ns ; CY ; Y3 ; +; N/A ; None ; 12.140 ns ; CY ; Y0 ; +; N/A ; None ; 11.975 ns ; CY ; Y4 ; +; N/A ; None ; 9.351 ns ; A3 ; Y3 ; +; N/A ; None ; 8.853 ns ; B3 ; Y3 ; +; N/A ; None ; 8.008 ns ; A4 ; Y4 ; +; N/A ; None ; 7.755 ns ; C3 ; Y3 ; ++-------+-------------------+-----------------+------+----+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Classic Timing Analyzer + Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition + Info: Processing started: Mon Mar 07 10:24:29 2022 +Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off triple_selector_8b -c triple_selector_8b --timing_analysis_only +Info: Parallel compilation is enabled and will use 4 of the 4 processors detected +Info: Longest tpd from source pin "BY" to destination pin "Y6" is 16.101 ns + Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_31; Fanout = 8; PIN Node = 'BY' + Info: 2: + IC(6.949 ns) + CELL(0.651 ns) = 8.585 ns; Loc. = LCCOMB_X33_Y11_N0; Fanout = 1; COMB Node = 'inst27~0' + Info: 3: + IC(0.366 ns) + CELL(0.624 ns) = 9.575 ns; Loc. = LCCOMB_X33_Y11_N10; Fanout = 1; COMB Node = 'inst27' + Info: 4: + IC(3.430 ns) + CELL(3.096 ns) = 16.101 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'Y6' + Info: Total cell delay = 5.356 ns ( 33.27 % ) + Info: Total interconnect delay = 10.745 ns ( 66.73 % ) +Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 212 megabytes + Info: Processing ended: Mon Mar 07 10:24:29 2022 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:00 + + diff --git a/triple_selector_8b/triple_selector_8b.tan.summary b/triple_selector_8b/triple_selector_8b.tan.summary new file mode 100644 index 0000000..2cad432 --- /dev/null +++ b/triple_selector_8b/triple_selector_8b.tan.summary @@ -0,0 +1,26 @@ +-------------------------------------------------------------------------------------- +Timing Analyzer Summary +-------------------------------------------------------------------------------------- + +Type : Worst-case tpd +Slack : N/A +Required Time : None +Actual Time : 16.101 ns +From : BY +To : Y6 +From Clock : -- +To Clock : -- +Failed Paths : 0 + +Type : Total number of failed paths +Slack : +Required Time : +Actual Time : +From : +To : +From Clock : +To Clock : +Failed Paths : 0 + +-------------------------------------------------------------------------------------- + From 196a946bf9966facba93c71082f498fe05c79faa Mon Sep 17 00:00:00 2001 From: juzeon <812312770@qq.com> Date: Mon, 7 Mar 2022 10:44:00 +0800 Subject: [PATCH 7/7] move symbol file --- {triple_selector_8b => shifter_8b}/shifter_8b.bsf | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename {triple_selector_8b => shifter_8b}/shifter_8b.bsf (100%) diff --git a/triple_selector_8b/shifter_8b.bsf b/shifter_8b/shifter_8b.bsf similarity index 100% rename from triple_selector_8b/shifter_8b.bsf rename to shifter_8b/shifter_8b.bsf

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