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增加 8位寄存器

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juzeon 2022-03-07 09:10:22 +08:00
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共有 78 個檔案被更改，包括 3648 行新增 和 2 行删除
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8
README.md
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# quartus # quartus
计组课设。 计组课设。
### adder
8位加法计算器。
### data_selector
8位数据选择器（二选一）。

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adder/adder.qws Normal file
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[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames

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adder/db/adder.tmw_info Normal file
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start_full_compilation:s:00:00:06
start_analysis_synthesis:s:00:00:02-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:02-start_full_compilation
start_assembler:s:00:00:01-start_full_compilation
start_timing_analyzer:s:00:00:01-start_full_compilation

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data_selector/data_selector.qsf
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@ -54,3 +54,4 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name MISC_FILE "D:/projects/quartus/data_selector/data_selector.dpf" set_global_assignment -name MISC_FILE "D:/projects/quartus/data_selector/data_selector.dpf"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"

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data_selector/data_selector.qws
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ptn_Child1=Frames ptn_Child1=Frames
[ProjectWorkspace.Frames] [ProjectWorkspace.Frames]
ptn_Child1=ChildFrames ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
[ProjectWorkspace.Frames.ChildFrames.Document-0]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
DocPathName=data_selector.bdf
DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde}
IsChildFrameDetached=False
IsActiveChildFrame=True
ptn_Child1=StateMap

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register_8b/db/register_8b.(0).cnf.cdb Normal file
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register_8b/db/register_8b.(0).cnf.hdb Normal file
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register_8b/db/register_8b.asm.qmsg Normal file
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 09:09:56 2022 " "Info: Processing started: Mon Mar 07 09:09:56 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off register_8b -c register_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off register_8b -c register_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 09:09:56 2022 " "Info: Processing ended: Mon Mar 07 09:09:56 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

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register_8b/db/register_8b.asm_labs.ddb Normal file
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register_8b/db/register_8b.cbx.xml Normal file
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<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="register_8b">
</PROJECT>
</LOG_ROOT>

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register_8b/db/register_8b.cmp.bpm Normal file
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register_8b/db/register_8b.cmp.cdb Normal file
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register_8b/db/register_8b.cmp.ecobp Normal file
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register_8b/db/register_8b.cmp.hdb Normal file
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register_8b/db/register_8b.cmp.kpt Normal file
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<kpt_db name="register_8b.cmp" kpt_version="1.1">
<key_points_set type="reference" hier_sep="|">
</key_points_set>
<key_points_set type="transition" hier_sep="|">
</key_points_set>
<key_points_set type="transformed" hier_sep="|">
</key_points_set>
<transformations_set hier_sep="|">
</transformations_set>
</kpt_db>

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register_8b/db/register_8b.cmp.logdb Normal file
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v1

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register_8b/db/register_8b.cmp.rdb Normal file
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register_8b/db/register_8b.cmp.tdb Normal file
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register_8b/db/register_8b.cmp0.ddb Normal file
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register_8b/db/register_8b.cmp2.ddb Normal file
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register_8b/db/register_8b.cmp_merge.kpt Normal file
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<kpt_db name="register_8b.cmp_merge" kpt_version="1.1">
<key_points_set type="reference" hier_sep="|">
</key_points_set>
<key_points_set type="transition" hier_sep="|">
</key_points_set>
<key_points_set type="transformed" hier_sep="|">
</key_points_set>
<transformations_set hier_sep="|">
</transformations_set>
</kpt_db>

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register_8b/db/register_8b.db_info Normal file
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Quartus_Version = Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Version_Index = 167832322
Creation_Time = Mon Mar 07 09:08:50 2022

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register_8b/db/register_8b.eco.cdb Normal file
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register_8b/db/register_8b.fit.qmsg Normal file
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register_8b/db/register_8b.hier_info Normal file
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|register_8b
Q7 <= inst.DB_MAX_OUTPUT_PORT_TYPE
CLR => inst.ACLR
CLR => inst.PRESET
CLR => inst2.ACLR
CLR => inst2.PRESET
CLR => inst3.ACLR
CLR => inst3.PRESET
CLR => inst4.ACLR
CLR => inst4.PRESET
CLR => inst5.ACLR
CLR => inst5.PRESET
CLR => inst6.ACLR
CLR => inst6.PRESET
CLR => inst7.ACLR
CLR => inst7.PRESET
CLR => inst8.ACLR
CLR => inst8.PRESET
CP => inst.CLK
CP => inst2.CLK
CP => inst3.CLK
CP => inst4.CLK
CP => inst5.CLK
CP => inst6.CLK
CP => inst7.CLK
CP => inst8.CLK
D7 => inst.DATAIN
Q6 <= inst2.DB_MAX_OUTPUT_PORT_TYPE
D6 => inst2.DATAIN
Q5 <= inst3.DB_MAX_OUTPUT_PORT_TYPE
D5 => inst3.DATAIN
Q4 <= inst4.DB_MAX_OUTPUT_PORT_TYPE
D4 => inst4.DATAIN
Q3 <= inst5.DB_MAX_OUTPUT_PORT_TYPE
D3 => inst5.DATAIN
Q2 <= inst6.DB_MAX_OUTPUT_PORT_TYPE
D2 => inst6.DATAIN
Q1 <= inst7.DB_MAX_OUTPUT_PORT_TYPE
D1 => inst7.DATAIN
Q0 <= inst8.DB_MAX_OUTPUT_PORT_TYPE
D0 => inst8.DATAIN

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register_8b/db/register_8b.hif Normal file
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Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
11
936
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
register_8b
# storage
db|register_8b.(0).cnf
db|register_8b.(0).cnf
# case_insensitive
# source_file
register_8b.bdf
15bb6d6fc64f9448fba2946de88c4c4d
26
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
|
}
# macro_sequence
# end
# complete

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register_8b/db/register_8b.lpc.html Normal file
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<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
</TABLE>

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register_8b/db/register_8b.lpc.rdb Normal file
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register_8b/db/register_8b.lpc.txt Normal file
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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

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register_8b/db/register_8b.map.bpm Normal file
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register_8b/db/register_8b.map.cdb Normal file
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register_8b/db/register_8b.map.ecobp Normal file
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register_8b/db/register_8b.map.hdb Normal file
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register_8b/db/register_8b.map.kpt Normal file
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<kpt_db name="register_8b.map" kpt_version="1.1">
<key_points_set type="reference" hier_sep="/">
<key_point id="1" type="register">
<name>inst5</name>
</key_point>
<key_point id="2" type="register">
<name>inst6</name>
</key_point>
<key_point id="3" type="register">
<name>inst3</name>
</key_point>
<key_point id="4" type="register">
<name>inst4</name>
</key_point>
<key_point id="5" type="register">
<name>inst2</name>
</key_point>
<key_point id="6" type="register">
<name>inst7</name>
</key_point>
<key_point id="7" type="register">
<name>inst8</name>
</key_point>
<key_point id="8" type="register">
<name>inst</name>
</key_point>
</key_points_set>
<key_points_set type="transition" hier_sep="|">
</key_points_set>
<key_points_set type="transformed" hier_sep="|">
<key_point id="9" type="register">
<name>inst5</name>
</key_point>
<key_point id="10" type="register">
<name>inst6</name>
</key_point>
<key_point id="11" type="register">
<name>inst3</name>
</key_point>
<key_point id="12" type="register">
<name>inst4</name>
</key_point>
<key_point id="13" type="register">
<name>inst2</name>
</key_point>
<key_point id="14" type="register">
<name>inst7</name>
</key_point>
<key_point id="15" type="register">
<name>inst8</name>
</key_point>
<key_point id="16" type="register">
<name>inst</name>
</key_point>
</key_points_set>
<transformations_set hier_sep="|">
<transformation>
<kp_set type="reference">
<kp_state index="0">
<kp id="4" type="proxy"></kp>
</kp_state>
</kp_set>
<kp_set type="transformed">
<kp_state index="0">
<kp id="12" type="proxy"></kp>
</kp_state>
</kp_set>
</transformation>
<transformation>
<kp_set type="reference">
<kp_state index="0">
<kp id="7" type="proxy"></kp>
</kp_state>
</kp_set>
<kp_set type="transformed">
<kp_state index="0">
<kp id="15" type="proxy"></kp>
</kp_state>
</kp_set>
</transformation>
<transformation>
<kp_set type="reference">
<kp_state index="0">
<kp id="5" type="proxy"></kp>
</kp_state>
</kp_set>
<kp_set type="transformed">
<kp_state index="0">
<kp id="13" type="proxy"></kp>
</kp_state>
</kp_set>
</transformation>
<transformation>
<kp_set type="reference">
<kp_state index="0">
<kp id="8" type="proxy"></kp>
</kp_state>
</kp_set>
<kp_set type="transformed">
<kp_state index="0">
<kp id="16" type="proxy"></kp>
</kp_state>
</kp_set>
</transformation>
<transformation>
<kp_set type="reference">
<kp_state index="0">
<kp id="6" type="proxy"></kp>
</kp_state>
</kp_set>
<kp_set type="transformed">
<kp_state index="0">
<kp id="14" type="proxy"></kp>
</kp_state>
</kp_set>
</transformation>
<transformation>
<kp_set type="reference">
<kp_state index="0">
<kp id="2" type="proxy"></kp>
</kp_state>
</kp_set>
<kp_set type="transformed">
<kp_state index="0">
<kp id="10" type="proxy"></kp>
</kp_state>
</kp_set>
</transformation>
<transformation>
<kp_set type="reference">
<kp_state index="0">
<kp id="3" type="proxy"></kp>
</kp_state>
</kp_set>
<kp_set type="transformed">
<kp_state index="0">
<kp id="11" type="proxy"></kp>
</kp_state>
</kp_set>
</transformation>
<transformation>
<kp_set type="reference">
<kp_state index="0">
<kp id="1" type="proxy"></kp>
</kp_state>
</kp_set>
<kp_set type="transformed">
<kp_state index="0">
<kp id="9" type="proxy"></kp>
</kp_state>
</kp_set>
</transformation>
</transformations_set>
</kpt_db>

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register_8b/db/register_8b.map.logdb Normal file
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v1

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register_8b/db/register_8b.map.qmsg Normal file
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 09:09:53 2022 " "Info: Processing started: Mon Mar 07 09:09:53 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off register_8b -c register_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off register_8b -c register_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "register_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file register_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 register_8b " "Info: Found entity 1: register_8b" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "register_8b " "Info: Elaborating entity \"register_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "26 " "Info: Implemented 26 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Info: Implemented 10 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "248 " "Info: Peak virtual memory: 248 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 09:09:53 2022 " "Info: Processing ended: Mon Mar 07 09:09:53 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

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register_8b/db/register_8b.map_bb.cdb Normal file
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register_8b/db/register_8b.syn_hier_info Normal file
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register_8b/db/register_8b.tan.qmsg Normal file
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register_8b/incremental_db/README Normal file
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This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.

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register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.atm Normal file
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register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.dfp Normal file
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register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.hdbx Normal file
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register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.kpt Normal file
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<kpt_db name="root_partition" kpt_version="1.1">
<key_points_set type="reference" hier_sep="|">
</key_points_set>
<key_points_set type="transition" hier_sep="|">
</key_points_set>
<key_points_set type="transformed" hier_sep="|">
</key_points_set>
<transformations_set hier_sep="|">
</transformations_set>
</kpt_db>

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register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.logdb Normal file
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v1

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register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.rcf Normal file
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register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.atm Normal file
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register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.dpi Normal file
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register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.hdbx Normal file
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register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.kpt Normal file
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<kpt_db name="register_8b.map_bb" kpt_version="1.1">
<key_points_set type="reference" hier_sep="/">
<key_point id="1" type="register">
<name>inst5</name>
</key_point>
<key_point id="2" type="register">
<name>inst6</name>
</key_point>
<key_point id="3" type="register">
<name>inst3</name>
</key_point>
<key_point id="4" type="register">
<name>inst4</name>
</key_point>
<key_point id="5" type="register">
<name>inst2</name>
</key_point>
<key_point id="6" type="register">
<name>inst7</name>
</key_point>
<key_point id="7" type="register">
<name>inst8</name>
</key_point>
<key_point id="8" type="register">
<name>inst</name>
</key_point>
</key_points_set>
<key_points_set type="transition" hier_sep="|">
</key_points_set>
<key_points_set type="transformed" hier_sep="|">
<key_point id="9" type="register">
<name>inst5</name>
</key_point>
<key_point id="10" type="register">
<name>inst6</name>
</key_point>
<key_point id="11" type="register">
<name>inst3</name>
</key_point>
<key_point id="12" type="register">
<name>inst4</name>
</key_point>
<key_point id="13" type="register">
<name>inst2</name>
</key_point>
<key_point id="14" type="register">
<name>inst7</name>
</key_point>
<key_point id="15" type="register">
<name>inst8</name>
</key_point>
<key_point id="16" type="register">
<name>inst</name>
</key_point>
</key_points_set>
<transformations_set hier_sep="|">
<transformation>
<kp_set type="reference">
<kp_state index="0">
<kp id="4" type="proxy"></kp>
</kp_state>
</kp_set>
<kp_set type="transformed">
<kp_state index="0">
<kp id="12" type="proxy"></kp>
</kp_state>
</kp_set>
</transformation>
<transformation>
<kp_set type="reference">
<kp_state index="0">
<kp id="7" type="proxy"></kp>
</kp_state>
</kp_set>
<kp_set type="transformed">
<kp_state index="0">
<kp id="15" type="proxy"></kp>
</kp_state>
</kp_set>
</transformation>
<transformation>
<kp_set type="reference">
<kp_state index="0">
<kp id="5" type="proxy"></kp>
</kp_state>
</kp_set>
<kp_set type="transformed">
<kp_state index="0">
<kp id="13" type="proxy"></kp>
</kp_state>
</kp_set>
</transformation>
<transformation>
<kp_set type="reference">
<kp_state index="0">
<kp id="8" type="proxy"></kp>
</kp_state>
</kp_set>
<kp_set type="transformed">
<kp_state index="0">
<kp id="16" type="proxy"></kp>
</kp_state>
</kp_set>
</transformation>
<transformation>
<kp_set type="reference">
<kp_state index="0">
<kp id="6" type="proxy"></kp>
</kp_state>
</kp_set>
<kp_set type="transformed">
<kp_state index="0">
<kp id="14" type="proxy"></kp>
</kp_state>
</kp_set>
</transformation>
<transformation>
<kp_set type="reference">
<kp_state index="0">
<kp id="2" type="proxy"></kp>
</kp_state>
</kp_set>
<kp_set type="transformed">
<kp_state index="0">
<kp id="10" type="proxy"></kp>
</kp_state>
</kp_set>
</transformation>
<transformation>
<kp_set type="reference">
<kp_state index="0">
<kp id="3" type="proxy"></kp>
</kp_state>
</kp_set>
<kp_set type="transformed">
<kp_state index="0">
<kp id="11" type="proxy"></kp>
</kp_state>
</kp_set>
</transformation>
<transformation>
<kp_set type="reference">
<kp_state index="0">
<kp id="1" type="proxy"></kp>
</kp_state>
</kp_set>
<kp_set type="transformed">
<kp_state index="0">
<kp id="9" type="proxy"></kp>
</kp_state>
</kp_set>
</transformation>
</transformations_set>
</kpt_db>

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register_8b/register_8b.asm.rpt Normal file
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Assembler report for register_8b
Mon Mar 07 09:09:56 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: D:/projects/quartus/register_8b/register_8b.sof
6. Assembler Device Options: D:/projects/quartus/register_8b/register_8b.pof
7. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Mon Mar 07 09:09:56 2022 ;
; Revision Name ; register_8b ;
; Top-level Entity Name ; register_8b ;
; Family ; Cyclone II ;
; Device ; EP2C8Q208C8 ;
+-----------------------+---------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Assembler Settings ;
+-----------------------------------------------------------------------------+----------+---------------+
; Option ; Setting ; Default Value ;
+-----------------------------------------------------------------------------+----------+---------------+
; Use smart compilation ; Off ; Off ;
; Generate compressed bitstreams ; On ; On ;
; Compression mode ; Off ; Off ;
; Clock source for configuration device ; Internal ; Internal ;
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
; Divide clock frequency by ; 1 ; 1 ;
; Auto user code ; Off ; Off ;
; Use configuration device ; On ; On ;
; Configuration device ; Auto ; Auto ;
; Configuration device auto user code ; Off ; Off ;
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
; Hexadecimal Output File start address ; 0 ; 0 ;
; Hexadecimal Output File count direction ; Up ; Up ;
; Release clears before tri-states ; Off ; Off ;
; Auto-restart configuration after error ; On ; On ;
; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ;
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
+-----------------------------------------------------------------------------+----------+---------------+
+-------------------------------------------------+
; Assembler Generated Files ;
+-------------------------------------------------+
; File Name ;
+-------------------------------------------------+
; D:/projects/quartus/register_8b/register_8b.sof ;
; D:/projects/quartus/register_8b/register_8b.pof ;
+-------------------------------------------------+
+---------------------------------------------------------------------------+
; Assembler Device Options: D:/projects/quartus/register_8b/register_8b.sof ;
+----------------+----------------------------------------------------------+
; Option ; Setting ;
+----------------+----------------------------------------------------------+
; Device ; EP2C8Q208C8 ;
; JTAG usercode ; 0xFFFFFFFF ;
; Checksum ; 0x000C5E44 ;
+----------------+----------------------------------------------------------+
+---------------------------------------------------------------------------+
; Assembler Device Options: D:/projects/quartus/register_8b/register_8b.pof ;
+--------------------+------------------------------------------------------+
; Option ; Setting ;
+--------------------+------------------------------------------------------+
; Device ; EPCS4 ;
; JTAG usercode ; 0x00000000 ;
; Checksum ; 0x06F0F18E ;
; Compression Ratio ; 3 ;
+--------------------+------------------------------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Mon Mar 07 09:09:56 2022
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off register_8b -c register_8b
Info: Writing out detailed assembly data for power analysis
Info: Assembler is generating device programming files
Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 241 megabytes
Info: Processing ended: Mon Mar 07 09:09:56 2022
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00

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register_8b/register_8b.bdf Normal file
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1
register_8b/register_8b.done Normal file
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Mon Mar 07 09:09:58 2022

952
register_8b/register_8b.fit.rpt Normal file
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Fitter report for register_8b
Mon Mar 07 09:09:55 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Parallel Compilation
5. Incremental Compilation Preservation Summary
6. Incremental Compilation Partition Settings
7. Incremental Compilation Placement Preservation
8. Pin-Out File
9. Fitter Resource Usage Summary
10. Input Pins
11. Output Pins
12. I/O Bank Usage
13. All Package Pins
14. Output Pin Default Load For Reported TCO
15. Fitter Resource Utilization by Entity
16. Delay Chain Summary
17. Pad To Core Delay Chain Fanout
18. Control Signals
19. Global & Other Fast Signals
20. Non-Global High Fan-Out Signals
21. Interconnect Usage Summary
22. LAB Logic Elements
23. LAB-wide Signals
24. LAB Signals Sourced
25. LAB Signals Sourced Out
26. LAB Distinct Inputs
27. Fitter Device Options
28. Operating Settings and Conditions
29. Estimated Delay Added for Hold Timing
30. Advanced Data - General
31. Advanced Data - Placement Preparation
32. Advanced Data - Placement
33. Advanced Data - Routing
34. Fitter Messages
35. Fitter Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+----------------------------------------------+
; Fitter Status ; Successful - Mon Mar 07 09:09:55 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; register_8b ;
; Top-level Entity Name ; register_8b ;
; Family ; Cyclone II ;
; Device ; EP2C8Q208C8 ;
; Timing Models ; Final ;
; Total logic elements ; 8 / 8,256 ( < 1 % ) ;
; Total combinational functions ; 0 / 8,256 ( 0 % ) ;
; Dedicated logic registers ; 8 / 8,256 ( < 1 % ) ;
; Total registers ; 8 ;
; Total pins ; 18 / 138 ( 13 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 165,888 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
; Total PLLs ; 0 / 2 ( 0 % ) ;
+------------------------------------+----------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device ; EP2C8Q208C8 ; ;
; Minimum Core Junction Temperature ; 0 ; ;
; Maximum Core Junction Temperature ; 85 ; ;
; Fit Attempts to Skip ; 0 ; 0.0 ;
; Use smart compilation ; Off ; Off ;
; Use TimeQuest Timing Analyzer ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
; Placement Effort Multiplier ; 1.0 ; 1.0 ;
; Router Effort Multiplier ; 1.0 ; 1.0 ;
; Always Enable Input Buffers ; Off ; Off ;
; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Multi-Corner Timing ; Off ; Off ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
; Optimize Timing for ECOs ; Off ; Off ;
; Regenerate full fit report during ECO compiles ; Off ; Off ;
; Optimize IOC Register Placement for Timing ; On ; On ;
; Limit to One Fitting Attempt ; Off ; Off ;
; Final Placement Optimizations ; Automatically ; Automatically ;
; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; PCI I/O ; Off ; Off ;
; Weak Pull-Up Resistor ; Off ; Off ;
; Enable Bus-Hold Circuitry ; Off ; Off ;
; Auto Global Memory Control Signals ; Off ; Off ;
; Auto Packed Registers ; Auto ; Auto ;
; Auto Delay Chains ; On ; On ;
; Auto Merge PLLs ; On ; On ;
; Ignore PLL Mode When Merging PLLs ; Off ; Off ;
; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
; Perform Register Duplication for Performance ; Off ; Off ;
; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
; Perform Register Retiming for Performance ; Off ; Off ;
; Perform Asynchronous Signal Pipelining ; Off ; Off ;
; Fitter Effort ; Auto Fit ; Auto Fit ;
; Physical Synthesis Effort Level ; Normal ; Normal ;
; Auto Global Clock ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
; Stop After Congestion Map Generation ; Off ; Off ;
; Save Intermediate Fitting Results ; Off ; Off ;
; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 4 ;
; ; ;
; Usage by Processor ; % Time Used ;
; 1 processor ; 100.0% ;
; 2-4 processors ; < 0.1% ;
+----------------------------+-------------+
+----------------------------------------------+
; Incremental Compilation Preservation Summary ;
+-------------------------+--------------------+
; Type ; Value ;
+-------------------------+--------------------+
; Placement ; ;
; -- Requested ; 0 / 26 ( 0.00 % ) ;
; -- Achieved ; 0 / 26 ( 0.00 % ) ;
; ; ;
; Routing (by Connection) ; ;
; -- Requested ; 0 / 0 ( 0.00 % ) ;
; -- Achieved ; 0 / 0 ( 0.00 % ) ;
+-------------------------+--------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Partition Settings ;
+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
+--------------------------------------------------------------------------------------------+
; Incremental Compilation Placement Preservation ;
+----------------+---------+-------------------+-------------------------+-------------------+
; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
+----------------+---------+-------------------+-------------------------+-------------------+
; Top ; 26 ; 0 ; N/A ; Source File ;
+----------------+---------+-------------------+-------------------------+-------------------+
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/projects/quartus/register_8b/register_8b.pin.
+-------------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+---------------------------------------------+---------------------+
; Resource ; Usage ;
+---------------------------------------------+---------------------+
; Total logic elements ; 8 / 8,256 ( < 1 % ) ;
; -- Combinational with no register ; 0 ;
; -- Register only ; 8 ;
; -- Combinational with a register ; 0 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 0 ;
; -- 3 input functions ; 0 ;
; -- <=2 input functions ; 0 ;
; -- Register only ; 8 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 0 ;
; -- arithmetic mode ; 0 ;
; ; ;
; Total registers* ; 8 / 8,646 ( < 1 % ) ;
; -- Dedicated logic registers ; 8 / 8,256 ( < 1 % ) ;
; -- I/O registers ; 0 / 390 ( 0 % ) ;
; ; ;
; Total LABs: partially or completely used ; 8 / 516 ( 2 % ) ;
; User inserted logic elements ; 0 ;
; Virtual pins ; 0 ;
; I/O pins ; 18 / 138 ( 13 % ) ;
; -- Clock pins ; 2 / 4 ( 50 % ) ;
; Global signals ; 2 ;
; M4Ks ; 0 / 36 ( 0 % ) ;
; Total block memory bits ; 0 / 165,888 ( 0 % ) ;
; Total block memory implementation bits ; 0 / 165,888 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
; PLLs ; 0 / 2 ( 0 % ) ;
; Global clocks ; 2 / 8 ( 25 % ) ;
; JTAGs ; 0 / 1 ( 0 % ) ;
; ASMI blocks ; 0 / 1 ( 0 % ) ;
; CRC blocks ; 0 / 1 ( 0 % ) ;
; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ;
; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ;
; Maximum fan-out node ; CLR~clkctrl ;
; Maximum fan-out ; 8 ;
; Highest non-global fan-out signal ; inst ;
; Highest non-global fan-out ; 1 ;
; Total fan-out ; 39 ;
; Average fan-out ; 1.08 ;
+---------------------------------------------+---------------------+
* Register count does not include registers inside RAM blocks or DSP blocks.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; CLR ; 24 ; 1 ; 0 ; 9 ; 1 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; CP ; 23 ; 1 ; 0 ; 9 ; 0 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; D0 ; 205 ; 2 ; 1 ; 19 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; D1 ; 28 ; 1 ; 0 ; 9 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; D2 ; 27 ; 1 ; 0 ; 9 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; D3 ; 96 ; 4 ; 30 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; D4 ; 15 ; 1 ; 0 ; 14 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; D5 ; 68 ; 4 ; 12 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; D6 ; 34 ; 1 ; 0 ; 7 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; D7 ; 48 ; 1 ; 0 ; 2 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; Q0 ; 45 ; 1 ; 0 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Q1 ; 14 ; 1 ; 0 ; 14 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Q2 ; 188 ; 2 ; 12 ; 19 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Q3 ; 147 ; 3 ; 34 ; 15 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Q4 ; 145 ; 3 ; 34 ; 14 ; 4 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Q5 ; 47 ; 1 ; 0 ; 2 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Q6 ; 74 ; 4 ; 16 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Q7 ; 56 ; 4 ; 1 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
+------------------------------------------------------------+
; I/O Bank Usage ;
+----------+------------------+---------------+--------------+
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
+----------+------------------+---------------+--------------+
; 1 ; 12 / 32 ( 38 % ) ; 3.3V ; -- ;
; 2 ; 2 / 35 ( 6 % ) ; 3.3V ; -- ;
; 3 ; 3 / 35 ( 9 % ) ; 3.3V ; -- ;
; 4 ; 4 / 36 ( 11 % ) ; 3.3V ; -- ;
+----------+------------------+---------------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; All Package Pins ;
+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; 1 ; 0 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
; 2 ; 1 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
; 3 ; 2 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 4 ; 3 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 5 ; 4 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 6 ; 5 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 8 ; 6 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 10 ; 7 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 11 ; 8 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 12 ; 9 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 13 ; 10 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 14 ; 18 ; 1 ; Q1 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 15 ; 19 ; 1 ; D4 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
; 18 ; 22 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
; 19 ; 23 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
; 20 ; 24 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ;
; 21 ; 25 ; 1 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ;
; 22 ; 26 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
; 23 ; 27 ; 1 ; CP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 24 ; 28 ; 1 ; CLR ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 26 ; 29 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
; 27 ; 30 ; 1 ; D2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 28 ; 31 ; 1 ; D1 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 30 ; 32 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 31 ; 33 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 33 ; 35 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 34 ; 36 ; 1 ; D6 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 35 ; 37 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 37 ; 39 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 39 ; 43 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 40 ; 44 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 41 ; 45 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 42 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 43 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 44 ; 49 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 45 ; 50 ; 1 ; Q0 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 46 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 47 ; 52 ; 1 ; Q5 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 48 ; 53 ; 1 ; D7 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 49 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 50 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
; 51 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 52 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
; 53 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 54 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
; 55 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 56 ; 54 ; 4 ; Q7 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 57 ; 55 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 58 ; 56 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 59 ; 57 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 60 ; 58 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 61 ; 59 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 63 ; 60 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 64 ; 61 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 67 ; 69 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 68 ; 70 ; 4 ; D5 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 69 ; 71 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 70 ; 74 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 71 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 72 ; 75 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 74 ; 76 ; 4 ; Q6 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 75 ; 77 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 76 ; 78 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 77 ; 79 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 80 ; 82 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 81 ; 83 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 82 ; 84 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 83 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 84 ; 85 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 85 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 86 ; 86 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 87 ; 87 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 88 ; 88 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 89 ; 89 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 90 ; 90 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 91 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 92 ; 91 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 94 ; 92 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 95 ; 93 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 96 ; 94 ; 4 ; D3 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 97 ; 95 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 98 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 99 ; 96 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 100 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 101 ; 97 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 102 ; 98 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 103 ; 99 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 104 ; 100 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 105 ; 101 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 106 ; 102 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 107 ; 105 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 108 ; 106 ; 3 ; ~LVDS54p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 109 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 110 ; 107 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 111 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 112 ; 108 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 113 ; 109 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 114 ; 110 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 115 ; 112 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 116 ; 113 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 117 ; 114 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 118 ; 117 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 119 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 120 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 121 ; 121 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
; 122 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 123 ; 122 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
; 124 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 125 ; 123 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
; 126 ; 124 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
; 127 ; 125 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 128 ; 126 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 129 ; 127 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 130 ; 128 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 131 ; 129 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 132 ; 130 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 133 ; 131 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 134 ; 132 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 135 ; 133 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 136 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 137 ; 134 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 138 ; 135 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 139 ; 136 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 141 ; 137 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 142 ; 138 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 143 ; 141 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 144 ; 142 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 145 ; 143 ; 3 ; Q4 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 146 ; 149 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 147 ; 150 ; 3 ; Q3 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 148 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 149 ; 151 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 150 ; 152 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 151 ; 153 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 152 ; 154 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 153 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 154 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
; 155 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 156 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
; 157 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 158 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
; 159 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 160 ; 155 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 161 ; 156 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 162 ; 157 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 163 ; 158 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 164 ; 159 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 165 ; 160 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 166 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 167 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 168 ; 161 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 169 ; 162 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 170 ; 163 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 171 ; 164 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 172 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 173 ; 165 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 174 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 175 ; 168 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 176 ; 169 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 177 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 178 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 179 ; 173 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 180 ; 174 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 181 ; 175 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 182 ; 176 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 183 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 184 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 185 ; 180 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 186 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 187 ; 181 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 188 ; 182 ; 2 ; Q2 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 189 ; 183 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 190 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 191 ; 184 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 192 ; 185 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 193 ; 186 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 194 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 195 ; 187 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 196 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 197 ; 191 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 198 ; 192 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 199 ; 195 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 200 ; 196 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 201 ; 197 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 202 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 203 ; 198 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 204 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 205 ; 199 ; 2 ; D0 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 206 ; 200 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 207 ; 201 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 208 ; 202 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+-------------------------------------------------------------------------------+
; Output Pin Default Load For Reported TCO ;
+----------------------------------+-------+------------------------------------+
; I/O Standard ; Load ; Termination Resistance ;
+----------------------------------+-------+------------------------------------+
; 3.3-V LVTTL ; 0 pF ; Not Available ;
; 3.3-V LVCMOS ; 0 pF ; Not Available ;
; 2.5 V ; 0 pF ; Not Available ;
; 1.8 V ; 0 pF ; Not Available ;
; 1.5 V ; 0 pF ; Not Available ;
; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ;
; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ;
; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;
; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;
; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;
; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;
; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ;
; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ;
; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ;
; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ;
; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ;
; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ;
; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ;
; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ;
; LVDS ; 0 pF ; 100 Ohm (Differential) ;
; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ;
; RSDS ; 0 pF ; 100 Ohm (Differential) ;
; Simple RSDS ; 0 pF ; Not Available ;
; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ;
+----------------------------------+-------+------------------------------------+
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity ;
+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
; |register_8b ; 8 (8) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 18 ; 0 ; 0 (0) ; 8 (8) ; 0 (0) ; |register_8b ; work ;
+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-------------------------------------------------------------------------------+
; Delay Chain Summary ;
+------+----------+---------------+---------------+-----------------------+-----+
; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
+------+----------+---------------+---------------+-----------------------+-----+
; Q7 ; Output ; -- ; -- ; -- ; -- ;
; Q6 ; Output ; -- ; -- ; -- ; -- ;
; Q5 ; Output ; -- ; -- ; -- ; -- ;
; Q4 ; Output ; -- ; -- ; -- ; -- ;
; Q3 ; Output ; -- ; -- ; -- ; -- ;
; Q2 ; Output ; -- ; -- ; -- ; -- ;
; Q1 ; Output ; -- ; -- ; -- ; -- ;
; Q0 ; Output ; -- ; -- ; -- ; -- ;
; D7 ; Input ; 6 ; 6 ; -- ; -- ;
; CP ; Input ; 0 ; 0 ; -- ; -- ;
; CLR ; Input ; 0 ; 0 ; -- ; -- ;
; D6 ; Input ; 6 ; 6 ; -- ; -- ;
; D5 ; Input ; 6 ; 6 ; -- ; -- ;
; D4 ; Input ; 6 ; 6 ; -- ; -- ;
; D3 ; Input ; 6 ; 6 ; -- ; -- ;
; D2 ; Input ; 0 ; 0 ; -- ; -- ;
; D1 ; Input ; 0 ; 0 ; -- ; -- ;
; D0 ; Input ; 6 ; 6 ; -- ; -- ;
+------+----------+---------------+---------------+-----------------------+-----+
+---------------------------------------------------+
; Pad To Core Delay Chain Fanout ;
+---------------------+-------------------+---------+
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
+---------------------+-------------------+---------+
; D7 ; ; ;
; - inst~feeder ; 1 ; 6 ;
; CP ; ; ;
; CLR ; ; ;
; D6 ; ; ;
; - inst2~feeder ; 0 ; 6 ;
; D5 ; ; ;
; - inst3 ; 0 ; 6 ;
; D4 ; ; ;
; - inst4~feeder ; 1 ; 6 ;
; D3 ; ; ;
; - inst5 ; 0 ; 6 ;
; D2 ; ; ;
; D1 ; ; ;
; D0 ; ; ;
; - inst8~feeder ; 0 ; 6 ;
+---------------------+-------------------+---------+
+-------------------------------------------------------------------------------------------------------------------------+
; Control Signals ;
+------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+
; CLR ; PIN_24 ; 8 ; Async. clear ; yes ; Global Clock ; GCLK1 ; -- ;
; CP ; PIN_23 ; 8 ; Clock ; yes ; Global Clock ; GCLK2 ; -- ;
+------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+
+-------------------------------------------------------------------------------------------------+
; Global & Other Fast Signals ;
+------+----------+---------+----------------------+------------------+---------------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+------+----------+---------+----------------------+------------------+---------------------------+
; CLR ; PIN_24 ; 8 ; Global Clock ; GCLK1 ; -- ;
; CP ; PIN_23 ; 8 ; Global Clock ; GCLK2 ; -- ;
+------+----------+---------+----------------------+------------------+---------------------------+
+---------------------------------+
; Non-Global High Fan-Out Signals ;
+-------+-------------------------+
; Name ; Fan-Out ;
+-------+-------------------------+
; D0 ; 1 ;
; D1 ; 1 ;
; D2 ; 1 ;
; D3 ; 1 ;
; D4 ; 1 ;
; D5 ; 1 ;
; D6 ; 1 ;
; D7 ; 1 ;
; inst8 ; 1 ;
; inst7 ; 1 ;
; inst6 ; 1 ;
; inst5 ; 1 ;
; inst4 ; 1 ;
; inst3 ; 1 ;
; inst2 ; 1 ;
; inst ; 1 ;
+-------+-------------------------+
+----------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+-----------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+-----------------------+
; Block interconnects ; 16 / 26,052 ( < 1 % ) ;
; C16 interconnects ; 3 / 1,156 ( < 1 % ) ;
; C4 interconnects ; 11 / 17,952 ( < 1 % ) ;
; Direct links ; 2 / 26,052 ( < 1 % ) ;
; Global clocks ; 2 / 8 ( 25 % ) ;
; Local interconnects ; 0 / 8,256 ( 0 % ) ;
; R24 interconnects ; 3 / 1,020 ( < 1 % ) ;
; R4 interconnects ; 11 / 22,440 ( < 1 % ) ;
+----------------------------+-----------------------+
+--------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements (Average = 1.00) ; Number of LABs (Total = 8) ;
+--------------------------------------------+-----------------------------+
; 1 ; 8 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 0 ;
+--------------------------------------------+-----------------------------+
+------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+-----------------------------+
; LAB-wide Signals (Average = 2.00) ; Number of LABs (Total = 8) ;
+------------------------------------+-----------------------------+
; 1 Async. clear ; 8 ;
; 1 Clock ; 8 ;
+------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced (Average = 1.63) ; Number of LABs (Total = 8) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 3 ;
; 2 ; 5 ;
+---------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out (Average = 1.00) ; Number of LABs (Total = 8) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 8 ;
+-------------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs (Average = 3.00) ; Number of LABs (Total = 8) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 8 ;
+---------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+--------------------------+
; Option ; Setting ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Active Serial ;
; Error detection CRC ; Off ;
; nCEO ; As output driving ground ;
; ASDO,nCSO ; As input tri-stated ;
; Reserve all unused pins ; As output driving ground ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+--------------------------+
+------------------------------------+
; Operating Settings and Conditions ;
+---------------------------+--------+
; Setting ; Value ;
+---------------------------+--------+
; Nominal Core Voltage ; 1.20 V ;
; Low Junction Temperature ; 0 °C ;
; High Junction Temperature ; 85 °C ;
+---------------------------+--------+
+------------------------------------------------------------+
; Estimated Delay Added for Hold Timing ;
+-----------------+----------------------+-------------------+
; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
+-----------------+----------------------+-------------------+
+----------------------------+
; Advanced Data - General ;
+--------------------+-------+
; Name ; Value ;
+--------------------+-------+
; Status Code ; 0 ;
; Desired User Slack ; 0 ;
; Fit Attempts ; 1 ;
+--------------------+-------+
+-------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation ;
+------------------------------------------------------------------+------------+
; Name ; Value ;
+------------------------------------------------------------------+------------+
; Auto Fit Point 1 - Fit Attempt 1 ; ff ;
; Mid Wire Use - Fit Attempt 1 ; 0 ;
; Mid Slack - Fit Attempt 1 ; 2147483639 ;
; Internal Atom Count - Fit Attempt 1 ; 9 ;
; LE/ALM Count - Fit Attempt 1 ; 9 ;
; LAB Count - Fit Attempt 1 ; 9 ;
; Outputs per Lab - Fit Attempt 1 ; 0.889 ;
; Inputs per LAB - Fit Attempt 1 ; 0.889 ;
; Global Inputs per LAB - Fit Attempt 1 ; 1.778 ;
; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:9 ;
; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:9 ;
; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:1;1:8 ;
; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:9 ;
; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:1;2:8 ;
; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:9 ;
; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:9 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:1;1:8 ;
; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:1;1:8 ;
; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:9 ;
; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:9 ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:9 ;
; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:8 ;
; LEs in Chains - Fit Attempt 1 ; 0 ;
; LEs in Long Chains - Fit Attempt 1 ; 0 ;
; LABs with Chains - Fit Attempt 1 ; 0 ;
; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;
; Time - Fit Attempt 1 ; 0 ;
+------------------------------------------------------------------+------------+
+-------------------------------------------------+
; Advanced Data - Placement ;
+------------------------------------+------------+
; Name ; Value ;
+------------------------------------+------------+
; Auto Fit Point 2 - Fit Attempt 1 ; ff ;
; Auto Fit Point 5 - Fit Attempt 1 ; ff ;
; Mid Wire Use - Fit Attempt 1 ; 0 ;
; Mid Slack - Fit Attempt 1 ; 2147483639 ;
; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
; Auto Fit Point 5 - Fit Attempt 1 ; ff ;
; Mid Wire Use - Fit Attempt 1 ; 0 ;
; Mid Slack - Fit Attempt 1 ; 2147483639 ;
; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
; Late Wire Use - Fit Attempt 1 ; 0 ;
; Late Slack - Fit Attempt 1 ; 2147483639 ;
; Peak Regional Wire - Fit Attempt 1 ; 0.000 ;
; Auto Fit Point 7 - Fit Attempt 1 ; ff ;
; Time - Fit Attempt 1 ; 0 ;
+------------------------------------+------------+
+--------------------------------------------------+
; Advanced Data - Routing ;
+------------------------------------+-------------+
; Name ; Value ;
+------------------------------------+-------------+
; Early Wire Use - Fit Attempt 1 ; 0 ;
; Peak Regional Wire - Fit Attempt 1 ; 0 ;
; Early Slack - Fit Attempt 1 ; 2147483639 ;
; Mid Slack - Fit Attempt 1 ; 2147483639 ;
; Late Slack - Fit Attempt 1 ; -2147483648 ;
; Late Wire Use - Fit Attempt 1 ; 0 ;
; Time - Fit Attempt 1 ; 0 ;
+------------------------------------+-------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Mon Mar 07 09:09:54 2022
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off register_8b -c register_8b
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Info: Selected device EP2C8Q208C8 for design "register_8b"
Info: Low junction temperature is 0 degrees C
Info: High junction temperature is 85 degrees C
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EP2C5Q208C8 is compatible
Info: Device EP2C5Q208I8 is compatible
Info: Device EP2C8Q208I8 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
Info: Pin ~ASDO~ is reserved at location 1
Info: Pin ~nCSO~ is reserved at location 2
Info: Pin ~LVDS54p/nCEO~ is reserved at location 108
Warning: No exact pin location assignment(s) for 18 pins of 18 total pins
Info: Pin Q7 not assigned to an exact location on the device
Info: Pin Q6 not assigned to an exact location on the device
Info: Pin Q5 not assigned to an exact location on the device
Info: Pin Q4 not assigned to an exact location on the device
Info: Pin Q3 not assigned to an exact location on the device
Info: Pin Q2 not assigned to an exact location on the device
Info: Pin Q1 not assigned to an exact location on the device
Info: Pin Q0 not assigned to an exact location on the device
Info: Pin D7 not assigned to an exact location on the device
Info: Pin CP not assigned to an exact location on the device
Info: Pin CLR not assigned to an exact location on the device
Info: Pin D6 not assigned to an exact location on the device
Info: Pin D5 not assigned to an exact location on the device
Info: Pin D4 not assigned to an exact location on the device
Info: Pin D3 not assigned to an exact location on the device
Info: Pin D2 not assigned to an exact location on the device
Info: Pin D1 not assigned to an exact location on the device
Info: Pin D0 not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Automatically promoted node CP (placed in PIN 23 (CLK0, LVDSCLK0p, Input))
Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
Info: Automatically promoted node CLR (placed in PIN 24 (CLK1, LVDSCLK0n, Input))
Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1
Info: Starting register packing
Info: Finished register packing
Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info: Number of I/O pins in group: 16 (unused VREF, 3.3V VCCIO, 8 input, 8 output, 0 bidirectional)
Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 28 pins available
Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available
Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available
Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available
Info: Fitter preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources
Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X10_Y19
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 8 output pins without output pin load capacitance assignment
Info: Pin "Q7" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "Q6" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "Q5" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "Q4" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "Q3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "Q2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "Q1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "Q0" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Generated suppressed messages file D:/projects/quartus/register_8b/register_8b.fit.smsg
Info: Quartus II Fitter was successful. 0 errors, 3 warnings
Info: Peak virtual memory: 306 megabytes
Info: Processing ended: Mon Mar 07 09:09:55 2022
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in D:/projects/quartus/register_8b/register_8b.fit.smsg.

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Extra Info: Performing register packing on registers with non-logic cell location assignments
Extra Info: Completed register packing on registers with non-logic cell location assignments
Extra Info: Started Fast Input/Output/OE register processing
Extra Info: Finished Fast Input/Output/OE register processing
Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks

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Fitter Status : Successful - Mon Mar 07 09:09:55 2022
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : register_8b
Top-level Entity Name : register_8b
Family : Cyclone II
Device : EP2C8Q208C8
Timing Models : Final
Total logic elements : 8 / 8,256 ( < 1 % )
Total combinational functions : 0 / 8,256 ( 0 % )
Dedicated logic registers : 8 / 8,256 ( < 1 % )
Total registers : 8
Total pins : 18 / 138 ( 13 % )
Total virtual pins : 0
Total memory bits : 0 / 165,888 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )

120
register_8b/register_8b.flow.rpt Normal file
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Flow report for register_8b
Mon Mar 07 09:09:57 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+----------------------------------------------+
; Flow Status ; Successful - Mon Mar 07 09:09:57 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; register_8b ;
; Top-level Entity Name ; register_8b ;
; Family ; Cyclone II ;
; Device ; EP2C8Q208C8 ;
; Timing Models ; Final ;
; Met timing requirements ; Yes ;
; Total logic elements ; 8 / 8,256 ( < 1 % ) ;
; Total combinational functions ; 0 / 8,256 ( 0 % ) ;
; Dedicated logic registers ; 8 / 8,256 ( < 1 % ) ;
; Total registers ; 8 ;
; Total pins ; 18 / 138 ( 13 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 165,888 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
; Total PLLs ; 0 / 2 ( 0 % ) ;
+------------------------------------+----------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 03/07/2022 09:09:53 ;
; Main task ; Compilation ;
; Revision Name ; register_8b ;
+-------------------+---------------------+
+---------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+------------------------------------+---------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+------------------------------------+---------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 220283517943889.164661539321576 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
+------------------------------------+---------------------------------+---------------+-------------+----------------+
+-----------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 245 MB ; 00:00:00 ;
; Fitter ; 00:00:01 ; 1.0 ; 306 MB ; 00:00:01 ;
; Assembler ; 00:00:00 ; 1.0 ; 241 MB ; 00:00:00 ;
; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 198 MB ; 00:00:00 ;
; Total ; 00:00:01 ; -- ; -- ; 00:00:01 ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+------------------------------------------------------------------------------------------+
; Flow OS Summary ;
+-------------------------+------------------+---------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+-------------------------+------------------+---------------+------------+----------------+
; Analysis & Synthesis ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
; Fitter ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
; Assembler ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
; Classic Timing Analyzer ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
+-------------------------+------------------+---------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off register_8b -c register_8b
quartus_fit --read_settings_files=off --write_settings_files=off register_8b -c register_8b
quartus_asm --read_settings_files=off --write_settings_files=off register_8b -c register_8b
quartus_tan --read_settings_files=off --write_settings_files=off register_8b -c register_8b --timing_analysis_only

218
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Analysis & Synthesis report for register_8b
Mon Mar 07 09:09:53 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. General Register Statistics
8. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Mar 07 09:09:53 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; register_8b ;
; Top-level Entity Name ; register_8b ;
; Family ; Cyclone II ;
; Total logic elements ; 8 ;
; Total combinational functions ; 0 ;
; Dedicated logic registers ; 8 ;
; Total registers ; 8 ;
; Total pins ; 18 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
+------------------------------------+----------------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------+--------------------+--------------------+
; Device ; EP2C8Q208C8 ; ;
; Top-level entity name ; register_8b ; register_8b ;
; Family name ; Cyclone II ; Stratix II ;
; Use Generated Physical Constraints File ; Off ; ;
; Use smart compilation ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; Off ; Off ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
+--------------------------------------------------------------+--------------------+--------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+-------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+-------------------------------------------------+
; register_8b.bdf ; yes ; User Block Diagram/Schematic File ; D:/projects/quartus/register_8b/register_8b.bdf ;
+----------------------------------+-----------------+------------------------------------+-------------------------------------------------+
+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements ; 8 ;
; ; ;
; Total combinational functions ; 0 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 0 ;
; -- 3 input functions ; 0 ;
; -- <=2 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 0 ;
; -- arithmetic mode ; 0 ;
; ; ;
; Total registers ; 8 ;
; -- Dedicated logic registers ; 8 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 18 ;
; Maximum fan-out node ; CP ;
; Maximum fan-out ; 8 ;
; Total fan-out ; 32 ;
; Average fan-out ; 1.23 ;
+---------------------------------------------+-------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |register_8b ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 18 ; 0 ; |register_8b ; work ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 8 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 8 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Mon Mar 07 09:09:53 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off register_8b -c register_8b
Info: Found 1 design units, including 1 entities, in source file register_8b.bdf
Info: Found entity 1: register_8b
Info: Elaborating entity "register_8b" for the top level hierarchy
Info: Implemented 26 device resources after synthesis - the final resource count might be different
Info: Implemented 10 input pins
Info: Implemented 8 output pins
Info: Implemented 8 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 248 megabytes
Info: Processing ended: Mon Mar 07 09:09:53 2022
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00

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Analysis & Synthesis Status : Successful - Mon Mar 07 09:09:53 2022
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : register_8b
Top-level Entity Name : register_8b
Family : Cyclone II
Total logic elements : 8
Total combinational functions : 0
Dedicated logic registers : 8
Total registers : 8
Total pins : 18
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0

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-- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
-- Bank 2: 3.3V
-- Bank 3: 3.3V
-- Bank 4: 3.3V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17),
-- connect each pin marked GND* either individually through a 10k Ohm resistor
-- to GND or tie all pins together and connect through a single 10k Ohm resistor
-- to GND.
-- For non-transceiver I/O banks, connect each pin marked GND* directly to GND
-- or leave it unconnected.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
CHIP "register_8b" ASSIGNED TO AN: EP2C8Q208C8
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVTTL : : 1 : N
~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVTTL : : 1 : N
GND* : 3 : : : : 1 :
GND* : 4 : : : : 1 :
GND* : 5 : : : : 1 :
GND* : 6 : : : : 1 :
VCCIO1 : 7 : power : : 3.3V : 1 :
GND* : 8 : : : : 1 :
GND : 9 : gnd : : : :
GND* : 10 : : : : 1 :
GND* : 11 : : : : 1 :
GND* : 12 : : : : 1 :
GND* : 13 : : : : 1 :
Q1 : 14 : output : 3.3-V LVTTL : : 1 : N
D4 : 15 : input : 3.3-V LVTTL : : 1 : N
TDO : 16 : output : : : 1 :
TMS : 17 : input : : : 1 :
TCK : 18 : input : : : 1 :
TDI : 19 : input : : : 1 :
DATA0 : 20 : input : : : 1 :
DCLK : 21 : : : : 1 :
nCE : 22 : : : : 1 :
CP : 23 : input : 3.3-V LVTTL : : 1 : N
CLR : 24 : input : 3.3-V LVTTL : : 1 : N
GND : 25 : gnd : : : :
nCONFIG : 26 : : : : 1 :
D2 : 27 : input : 3.3-V LVTTL : : 1 : N
D1 : 28 : input : 3.3-V LVTTL : : 1 : N
VCCIO1 : 29 : power : : 3.3V : 1 :
GND* : 30 : : : : 1 :
GND* : 31 : : : : 1 :
VCCINT : 32 : power : : 1.2V : :
GND* : 33 : : : : 1 :
D6 : 34 : input : 3.3-V LVTTL : : 1 : N
GND* : 35 : : : : 1 :
GND : 36 : gnd : : : :
GND* : 37 : : : : 1 :
GND : 38 : gnd : : : :
GND* : 39 : : : : 1 :
GND* : 40 : : : : 1 :
GND* : 41 : : : : 1 :
VCCIO1 : 42 : power : : 3.3V : 1 :
GND* : 43 : : : : 1 :
GND* : 44 : : : : 1 :
Q0 : 45 : output : 3.3-V LVTTL : : 1 : N
GND* : 46 : : : : 1 :
Q5 : 47 : output : 3.3-V LVTTL : : 1 : N
D7 : 48 : input : 3.3-V LVTTL : : 1 : N
GND : 49 : gnd : : : :
GND_PLL1 : 50 : gnd : : : :
VCCD_PLL1 : 51 : power : : 1.2V : :
GND_PLL1 : 52 : gnd : : : :
VCCA_PLL1 : 53 : power : : 1.2V : :
GNDA_PLL1 : 54 : gnd : : : :
GND : 55 : gnd : : : :
Q7 : 56 : output : 3.3-V LVTTL : : 4 : N
GND* : 57 : : : : 4 :
GND* : 58 : : : : 4 :
GND* : 59 : : : : 4 :
GND* : 60 : : : : 4 :
GND* : 61 : : : : 4 :
VCCIO4 : 62 : power : : 3.3V : 4 :
GND* : 63 : : : : 4 :
GND* : 64 : : : : 4 :
GND : 65 : gnd : : : :
VCCINT : 66 : power : : 1.2V : :
GND* : 67 : : : : 4 :
D5 : 68 : input : 3.3-V LVTTL : : 4 : N
GND* : 69 : : : : 4 :
GND* : 70 : : : : 4 :
VCCIO4 : 71 : power : : 3.3V : 4 :
GND* : 72 : : : : 4 :
GND : 73 : gnd : : : :
Q6 : 74 : output : 3.3-V LVTTL : : 4 : N
GND* : 75 : : : : 4 :
GND* : 76 : : : : 4 :
GND* : 77 : : : : 4 :
GND : 78 : gnd : : : :
VCCINT : 79 : power : : 1.2V : :
GND* : 80 : : : : 4 :
GND* : 81 : : : : 4 :
GND* : 82 : : : : 4 :
VCCIO4 : 83 : power : : 3.3V : 4 :
GND* : 84 : : : : 4 :
GND : 85 : gnd : : : :
GND* : 86 : : : : 4 :
GND* : 87 : : : : 4 :
GND* : 88 : : : : 4 :
GND* : 89 : : : : 4 :
GND* : 90 : : : : 4 :
VCCIO4 : 91 : power : : 3.3V : 4 :
GND* : 92 : : : : 4 :
GND : 93 : gnd : : : :
GND* : 94 : : : : 4 :
GND* : 95 : : : : 4 :
D3 : 96 : input : 3.3-V LVTTL : : 4 : N
GND* : 97 : : : : 4 :
VCCIO4 : 98 : power : : 3.3V : 4 :
GND* : 99 : : : : 4 :
GND : 100 : gnd : : : :
GND* : 101 : : : : 4 :
GND* : 102 : : : : 4 :
GND* : 103 : : : : 4 :
GND* : 104 : : : : 4 :
GND* : 105 : : : : 3 :
GND* : 106 : : : : 3 :
GND* : 107 : : : : 3 :
~LVDS54p/nCEO~ : 108 : output : 3.3-V LVTTL : : 3 : N
VCCIO3 : 109 : power : : 3.3V : 3 :
GND* : 110 : : : : 3 :
GND : 111 : gnd : : : :
GND* : 112 : : : : 3 :
GND* : 113 : : : : 3 :
GND* : 114 : : : : 3 :
GND* : 115 : : : : 3 :
GND* : 116 : : : : 3 :
GND* : 117 : : : : 3 :
GND* : 118 : : : : 3 :
GND : 119 : gnd : : : :
VCCINT : 120 : power : : 1.2V : :
nSTATUS : 121 : : : : 3 :
VCCIO3 : 122 : power : : 3.3V : 3 :
CONF_DONE : 123 : : : : 3 :
GND : 124 : gnd : : : :
MSEL1 : 125 : : : : 3 :
MSEL0 : 126 : : : : 3 :
GND* : 127 : : : : 3 :
GND* : 128 : : : : 3 :
GND+ : 129 : : : : 3 :
GND+ : 130 : : : : 3 :
GND+ : 131 : : : : 3 :
GND+ : 132 : : : : 3 :
GND* : 133 : : : : 3 :
GND* : 134 : : : : 3 :
GND* : 135 : : : : 3 :
VCCIO3 : 136 : power : : 3.3V : 3 :
GND* : 137 : : : : 3 :
GND* : 138 : : : : 3 :
GND* : 139 : : : : 3 :
GND : 140 : gnd : : : :
GND* : 141 : : : : 3 :
GND* : 142 : : : : 3 :
GND* : 143 : : : : 3 :
GND* : 144 : : : : 3 :
Q4 : 145 : output : 3.3-V LVTTL : : 3 : N
GND* : 146 : : : : 3 :
Q3 : 147 : output : 3.3-V LVTTL : : 3 : N
VCCIO3 : 148 : power : : 3.3V : 3 :
GND* : 149 : : : : 3 :
GND* : 150 : : : : 3 :
GND* : 151 : : : : 3 :
GND* : 152 : : : : 3 :
GND : 153 : gnd : : : :
GND_PLL2 : 154 : gnd : : : :
VCCD_PLL2 : 155 : power : : 1.2V : :
GND_PLL2 : 156 : gnd : : : :
VCCA_PLL2 : 157 : power : : 1.2V : :
GNDA_PLL2 : 158 : gnd : : : :
GND : 159 : gnd : : : :
GND* : 160 : : : : 2 :
GND* : 161 : : : : 2 :
GND* : 162 : : : : 2 :
GND* : 163 : : : : 2 :
GND* : 164 : : : : 2 :
GND* : 165 : : : : 2 :
VCCIO2 : 166 : power : : 3.3V : 2 :
GND : 167 : gnd : : : :
GND* : 168 : : : : 2 :
GND* : 169 : : : : 2 :
GND* : 170 : : : : 2 :
GND* : 171 : : : : 2 :
VCCIO2 : 172 : power : : 3.3V : 2 :
GND* : 173 : : : : 2 :
GND : 174 : gnd : : : :
GND* : 175 : : : : 2 :
GND* : 176 : : : : 2 :
GND : 177 : gnd : : : :
VCCINT : 178 : power : : 1.2V : :
GND* : 179 : : : : 2 :
GND* : 180 : : : : 2 :
GND* : 181 : : : : 2 :
GND* : 182 : : : : 2 :
VCCIO2 : 183 : power : : 3.3V : 2 :
GND : 184 : gnd : : : :
GND* : 185 : : : : 2 :
GND : 186 : gnd : : : :
GND* : 187 : : : : 2 :
Q2 : 188 : output : 3.3-V LVTTL : : 2 : N
GND* : 189 : : : : 2 :
VCCINT : 190 : power : : 1.2V : :
GND* : 191 : : : : 2 :
GND* : 192 : : : : 2 :
GND* : 193 : : : : 2 :
VCCIO2 : 194 : power : : 3.3V : 2 :
GND* : 195 : : : : 2 :
GND : 196 : gnd : : : :
GND* : 197 : : : : 2 :
GND* : 198 : : : : 2 :
GND* : 199 : : : : 2 :
GND* : 200 : : : : 2 :
GND* : 201 : : : : 2 :
VCCIO2 : 202 : power : : 3.3V : 2 :
GND* : 203 : : : : 2 :
GND : 204 : gnd : : : :
D0 : 205 : input : 3.3-V LVTTL : : 2 : N
GND* : 206 : : : : 2 :
GND* : 207 : : : : 2 :
GND* : 208 : : : : 2 :

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 09:08:50 March 07, 2022
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "9.0"
DATE = "09:08:50 March 07, 2022"
# Revisions
PROJECT_REVISION = "register_8b"

53
register_8b/register_8b.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 09:08:50 March 07, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# register_8b_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C8Q208C8
set_global_assignment -name TOP_LEVEL_ENTITY register_8b
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:08:50 MARCH 07, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name BDF_FILE register_8b.bdf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"

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register_8b/register_8b.tan.rpt Normal file
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Classic Timing Analyzer report for register_8b
Mon Mar 07 09:09:57 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Parallel Compilation
6. tsu
7. tco
8. th
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+-------+-------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+-------+-------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 4.872 ns ; D3 ; inst5 ; -- ; CP ; 0 ;
; Worst-case tco ; N/A ; None ; 8.228 ns ; inst3 ; Q5 ; CP ; -- ; 0 ;
; Worst-case th ; N/A ; None ; 0.406 ns ; D1 ; inst7 ; -- ; CP ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+-------+-------+------------+----------+--------------+
+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C8Q208C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Minimum Core Junction Temperature ; 0 ; ; ; ;
; Maximum Core Junction Temperature ; 85 ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; On ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
; Output I/O Timing Endpoint ; Near End ; ; ; ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CP ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; 1 processor ; 100.0% ;
; 2-4 processors ; 0.0% ;
+----------------------------+-------------+
+-------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+------+-------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+------+-------+----------+
; N/A ; None ; 4.872 ns ; D3 ; inst5 ; CP ;
; N/A ; None ; 4.693 ns ; D0 ; inst8 ; CP ;
; N/A ; None ; 4.628 ns ; D4 ; inst4 ; CP ;
; N/A ; None ; 4.577 ns ; D6 ; inst2 ; CP ;
; N/A ; None ; 4.264 ns ; D5 ; inst3 ; CP ;
; N/A ; None ; 4.007 ns ; D7 ; inst ; CP ;
; N/A ; None ; 1.029 ns ; D2 ; inst6 ; CP ;
; N/A ; None ; -0.140 ns ; D1 ; inst7 ; CP ;
+-------+--------------+------------+------+-------+----------+
+-------------------------------------------------------------+
; tco ;
+-------+--------------+------------+-------+----+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+-------+----+------------+
; N/A ; None ; 8.228 ns ; inst3 ; Q5 ; CP ;
; N/A ; None ; 8.096 ns ; inst2 ; Q6 ; CP ;
; N/A ; None ; 7.981 ns ; inst4 ; Q4 ; CP ;
; N/A ; None ; 7.359 ns ; inst6 ; Q2 ; CP ;
; N/A ; None ; 7.354 ns ; inst ; Q7 ; CP ;
; N/A ; None ; 7.258 ns ; inst5 ; Q3 ; CP ;
; N/A ; None ; 6.982 ns ; inst8 ; Q0 ; CP ;
; N/A ; None ; 6.969 ns ; inst7 ; Q1 ; CP ;
+-------+--------------+------------+-------+----+------------+
+-------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+------+-------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+------+-------+----------+
; N/A ; None ; 0.406 ns ; D1 ; inst7 ; CP ;
; N/A ; None ; -0.763 ns ; D2 ; inst6 ; CP ;
; N/A ; None ; -3.741 ns ; D7 ; inst ; CP ;
; N/A ; None ; -3.998 ns ; D5 ; inst3 ; CP ;
; N/A ; None ; -4.311 ns ; D6 ; inst2 ; CP ;
; N/A ; None ; -4.362 ns ; D4 ; inst4 ; CP ;
; N/A ; None ; -4.427 ns ; D0 ; inst8 ; CP ;
; N/A ; None ; -4.606 ns ; D3 ; inst5 ; CP ;
+---------------+-------------+-----------+------+-------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Mon Mar 07 09:09:57 2022
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off register_8b -c register_8b --timing_analysis_only
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "CP" is an undefined clock
Info: No valid register-to-register data paths exist for clock "CP"
Info: tsu for register "inst5" (data pin = "D3", clock pin = "CP") is 4.872 ns
Info: + Longest pin to register delay is 7.782 ns
Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_96; Fanout = 1; PIN Node = 'D3'
Info: 2: + IC(6.338 ns) + CELL(0.460 ns) = 7.782 ns; Loc. = LCFF_X32_Y15_N17; Fanout = 1; REG Node = 'inst5'
Info: Total cell delay = 1.444 ns ( 18.56 % )
Info: Total interconnect delay = 6.338 ns ( 81.44 % )
Info: + Micro setup delay of destination is -0.040 ns
Info: - Shortest clock path from clock "CP" to destination register is 2.870 ns
Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CP'
Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CP~clkctrl'
Info: 3: + IC(0.925 ns) + CELL(0.666 ns) = 2.870 ns; Loc. = LCFF_X32_Y15_N17; Fanout = 1; REG Node = 'inst5'
Info: Total cell delay = 1.806 ns ( 62.93 % )
Info: Total interconnect delay = 1.064 ns ( 37.07 % )
Info: tco from clock "CP" to destination pin "Q5" through register "inst3" is 8.228 ns
Info: + Longest clock path from clock "CP" to source register is 2.879 ns
Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CP'
Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CP~clkctrl'
Info: 3: + IC(0.934 ns) + CELL(0.666 ns) = 2.879 ns; Loc. = LCFF_X12_Y2_N9; Fanout = 1; REG Node = 'inst3'
Info: Total cell delay = 1.806 ns ( 62.73 % )
Info: Total interconnect delay = 1.073 ns ( 37.27 % )
Info: + Micro clock to output delay of source is 0.304 ns
Info: + Longest register to pin delay is 5.045 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y2_N9; Fanout = 1; REG Node = 'inst3'
Info: 2: + IC(1.765 ns) + CELL(3.280 ns) = 5.045 ns; Loc. = PIN_47; Fanout = 0; PIN Node = 'Q5'
Info: Total cell delay = 3.280 ns ( 65.01 % )
Info: Total interconnect delay = 1.765 ns ( 34.99 % )
Info: th for register "inst7" (data pin = "D1", clock pin = "CP") is 0.406 ns
Info: + Longest clock path from clock "CP" to destination register is 2.855 ns
Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CP'
Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CP~clkctrl'
Info: 3: + IC(0.910 ns) + CELL(0.666 ns) = 2.855 ns; Loc. = LCFF_X1_Y14_N17; Fanout = 1; REG Node = 'inst7'
Info: Total cell delay = 1.806 ns ( 63.26 % )
Info: Total interconnect delay = 1.049 ns ( 36.74 % )
Info: + Micro hold delay of destination is 0.306 ns
Info: - Shortest pin to register delay is 2.755 ns
Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_28; Fanout = 1; PIN Node = 'D1'
Info: 2: + IC(1.301 ns) + CELL(0.206 ns) = 2.647 ns; Loc. = LCCOMB_X1_Y14_N16; Fanout = 1; COMB Node = 'inst7~feeder'
Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 2.755 ns; Loc. = LCFF_X1_Y14_N17; Fanout = 1; REG Node = 'inst7'
Info: Total cell delay = 1.454 ns ( 52.78 % )
Info: Total interconnect delay = 1.301 ns ( 47.22 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 212 megabytes
Info: Processing ended: Mon Mar 07 09:09:57 2022
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00

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register_8b/register_8b.tan.summary Normal file
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--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------
Type : Worst-case tsu
Slack : N/A
Required Time : None
Actual Time : 4.872 ns
From : D3
To : inst5
From Clock : --
To Clock : CP
Failed Paths : 0
Type : Worst-case tco
Slack : N/A
Required Time : None
Actual Time : 8.228 ns
From : inst3
To : Q5
From Clock : CP
To Clock : --
Failed Paths : 0
Type : Worst-case th
Slack : N/A
Required Time : None
Actual Time : 0.406 ns
From : D1
To : inst7
From Clock : --
To Clock : CP
Failed Paths : 0
Type : Total number of failed paths
Slack :
Required Time :
Actual Time :
From :
To :
From Clock :
To Clock :
Failed Paths : 0
--------------------------------------------------------------------------------------