diff --git a/38_decoder/38_decoder.asm.rpt b/38_decoder/38_decoder.asm.rpt index 4daad42..c616fae 100644 --- a/38_decoder/38_decoder.asm.rpt +++ b/38_decoder/38_decoder.asm.rpt @@ -1,5 +1,5 @@ Assembler report for 38_decoder -Mon Mar 07 09:13:07 2022 +Tue Mar 08 15:12:41 2022 Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition @@ -38,7 +38,7 @@ applicable agreement for further details. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Mon Mar 07 09:13:07 2022 ; +; Assembler Status ; Successful - Tue Mar 08 15:12:41 2022 ; ; Revision Name ; 38_decoder ; ; Top-level Entity Name ; 38_decoder ; ; Family ; Cyclone II ; @@ -93,7 +93,7 @@ applicable agreement for further details. +----------------+--------------------------------------------------------+ ; Device ; EP2C8Q208C8 ; ; JTAG usercode ; 0xFFFFFFFF ; -; Checksum ; 0x000C6513 ; +; Checksum ; 0x000C10D6 ; +----------------+--------------------------------------------------------+ @@ -104,7 +104,7 @@ applicable agreement for further details. +--------------------+----------------------------------------------------+ ; Device ; EPCS4 ; ; JTAG usercode ; 0x00000000 ; -; Checksum ; 0x06F0CA55 ; +; Checksum ; 0x06F0221B ; ; Compression Ratio ; 3 ; +--------------------+----------------------------------------------------+ @@ -115,14 +115,14 @@ applicable agreement for further details. Info: ******************************************************************* Info: Running Quartus II Assembler Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Mon Mar 07 09:13:07 2022 + Info: Processing started: Tue Mar 08 15:12:41 2022 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder Info: Writing out detailed assembly data for power analysis Info: Assembler is generating device programming files Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled Info: Quartus II Assembler was successful. 0 errors, 0 warnings Info: Peak virtual memory: 241 megabytes - Info: Processing ended: Mon Mar 07 09:13:07 2022 + Info: Processing ended: Tue Mar 08 15:12:41 2022 Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:00 diff --git a/38_decoder/38_decoder.done b/38_decoder/38_decoder.done index 508b5d2..fcc5548 100644 --- a/38_decoder/38_decoder.done +++ b/38_decoder/38_decoder.done @@ -1 +1 @@ -Mon Mar 07 09:13:09 2022 +Tue Mar 08 15:12:42 2022 diff --git a/38_decoder/38_decoder.fit.rpt b/38_decoder/38_decoder.fit.rpt index f8fbfd4..24201f7 100644 --- a/38_decoder/38_decoder.fit.rpt +++ b/38_decoder/38_decoder.fit.rpt @@ -1,5 +1,5 @@ Fitter report for 38_decoder -Mon Mar 07 09:13:06 2022 +Tue Mar 08 15:12:40 2022 Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition @@ -63,7 +63,7 @@ applicable agreement for further details. +-----------------------------------------------------------------------------------+ ; Fitter Summary ; +------------------------------------+----------------------------------------------+ -; Fitter Status ; Successful - Mon Mar 07 09:13:06 2022 ; +; Fitter Status ; Successful - Tue Mar 08 15:12:40 2022 ; ; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; ; Revision Name ; 38_decoder ; ; Top-level Entity Name ; 38_decoder ; @@ -91,6 +91,7 @@ applicable agreement for further details. ; Minimum Core Junction Temperature ; 0 ; ; ; Maximum Core Junction Temperature ; 85 ; ; ; Fit Attempts to Skip ; 0 ; 0.0 ; +; Device I/O Standard ; 3.3-V LVTTL ; ; ; Use smart compilation ; Off ; Off ; ; Use TimeQuest Timing Analyzer ; Off ; Off ; ; Router Timing Optimization Level ; Normal ; Normal ; @@ -245,9 +246,9 @@ The pin-out file can be found in D:/projects/quartus/38_decoder/38_decoder.pin. +------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ; +------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ -; I0 ; 35 ; 1 ; 0 ; 7 ; 1 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; I1 ; 14 ; 1 ; 0 ; 14 ; 2 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; I2 ; 41 ; 1 ; 0 ; 4 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; I0 ; 77 ; 4 ; 18 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; I1 ; 80 ; 4 ; 23 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; I2 ; 81 ; 4 ; 23 ; 0 ; 1 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ @@ -256,27 +257,27 @@ The pin-out file can be found in D:/projects/quartus/38_decoder/38_decoder.pin. +------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; +------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ -; Y0 ; 45 ; 1 ; 0 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; -; Y1 ; 37 ; 1 ; 0 ; 6 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; -; Y2 ; 195 ; 2 ; 9 ; 19 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; -; Y3 ; 33 ; 1 ; 0 ; 8 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; -; Y4 ; 30 ; 1 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; -; Y5 ; 208 ; 2 ; 1 ; 19 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; -; Y6 ; 34 ; 1 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; -; Y7 ; 39 ; 1 ; 0 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Y0 ; 142 ; 3 ; 34 ; 12 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; +; Y1 ; 143 ; 3 ; 34 ; 13 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; +; Y2 ; 144 ; 3 ; 34 ; 13 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; +; Y3 ; 145 ; 3 ; 34 ; 14 ; 4 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; +; Y4 ; 146 ; 3 ; 34 ; 15 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; +; Y5 ; 147 ; 3 ; 34 ; 15 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; +; Y6 ; 149 ; 3 ; 34 ; 16 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; +; Y7 ; 150 ; 3 ; 34 ; 16 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; +------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ -+------------------------------------------------------------+ -; I/O Bank Usage ; -+----------+------------------+---------------+--------------+ -; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; -+----------+------------------+---------------+--------------+ -; 1 ; 11 / 32 ( 34 % ) ; 3.3V ; -- ; -; 2 ; 2 / 35 ( 6 % ) ; 3.3V ; -- ; -; 3 ; 1 / 35 ( 3 % ) ; 3.3V ; -- ; -; 4 ; 0 / 36 ( 0 % ) ; 3.3V ; -- ; -+----------+------------------+---------------+--------------+ ++-----------------------------------------------------------+ +; I/O Bank Usage ; ++----------+-----------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+-----------------+---------------+--------------+ +; 1 ; 2 / 32 ( 6 % ) ; 3.3V ; -- ; +; 2 ; 0 / 35 ( 0 % ) ; 3.3V ; -- ; +; 3 ; 9 / 35 ( 26 % ) ; 3.3V ; -- ; +; 4 ; 3 / 36 ( 8 % ) ; 3.3V ; -- ; ++----------+-----------------+---------------+--------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -286,19 +287,19 @@ The pin-out file can be found in D:/projects/quartus/38_decoder/38_decoder.pin. +----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ ; 1 ; 0 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; ; 2 ; 1 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; -; 3 ; 2 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 4 ; 3 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 5 ; 4 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 6 ; 5 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 3 ; 2 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 4 ; 3 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 5 ; 4 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 6 ; 5 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 8 ; 6 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 8 ; 6 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 10 ; 7 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 11 ; 8 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 12 ; 9 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 13 ; 10 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 14 ; 18 ; 1 ; I1 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 15 ; 19 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 10 ; 7 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 11 ; 8 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 12 ; 9 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 13 ; 10 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 14 ; 18 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 15 ; 19 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; ; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; ; 18 ; 22 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; @@ -313,25 +314,25 @@ The pin-out file can be found in D:/projects/quartus/38_decoder/38_decoder.pin. ; 27 ; 30 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; ; 28 ; 31 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; ; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 30 ; 32 ; 1 ; Y4 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 31 ; 33 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 30 ; 32 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 31 ; 33 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 33 ; 35 ; 1 ; Y3 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 34 ; 36 ; 1 ; Y6 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 35 ; 37 ; 1 ; I0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 33 ; 35 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 34 ; 36 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 35 ; 37 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 37 ; 39 ; 1 ; Y1 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 37 ; 39 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 39 ; 43 ; 1 ; Y7 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 40 ; 44 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 41 ; 45 ; 1 ; I2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 39 ; 43 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 40 ; 44 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 41 ; 45 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 42 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 43 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 44 ; 49 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 45 ; 50 ; 1 ; Y0 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 46 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 47 ; 52 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 48 ; 53 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 43 ; 48 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 44 ; 49 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 45 ; 50 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 46 ; 51 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 47 ; 52 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 48 ; 53 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 49 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; 50 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; ; 51 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; @@ -339,69 +340,69 @@ The pin-out file can be found in D:/projects/quartus/38_decoder/38_decoder.pin. ; 53 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; 54 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; ; 55 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 56 ; 54 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 57 ; 55 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 58 ; 56 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 59 ; 57 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 60 ; 58 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 61 ; 59 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 56 ; 54 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 57 ; 55 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 58 ; 56 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 59 ; 57 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 60 ; 58 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 61 ; 59 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 63 ; 60 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 64 ; 61 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 63 ; 60 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 64 ; 61 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 67 ; 69 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 68 ; 70 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 69 ; 71 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 70 ; 74 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 67 ; 69 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 68 ; 70 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 69 ; 71 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 70 ; 74 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 71 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 72 ; 75 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 72 ; 75 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 74 ; 76 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 75 ; 77 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 76 ; 78 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 77 ; 79 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 74 ; 76 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 75 ; 77 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 76 ; 78 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 77 ; 79 ; 4 ; I0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; ; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 80 ; 82 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 81 ; 83 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 82 ; 84 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 80 ; 82 ; 4 ; I1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 81 ; 83 ; 4 ; I2 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 82 ; 84 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 83 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 84 ; 85 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 84 ; 85 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 85 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 86 ; 86 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 87 ; 87 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 88 ; 88 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 89 ; 89 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 90 ; 90 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 86 ; 86 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 87 ; 87 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 88 ; 88 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 89 ; 89 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 90 ; 90 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 91 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 92 ; 91 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 92 ; 91 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 94 ; 92 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 95 ; 93 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 96 ; 94 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 97 ; 95 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 94 ; 92 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 95 ; 93 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 96 ; 94 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 97 ; 95 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 98 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 99 ; 96 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 99 ; 96 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 100 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 101 ; 97 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 102 ; 98 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 103 ; 99 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 104 ; 100 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 105 ; 101 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 106 ; 102 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 107 ; 105 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 101 ; 97 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 102 ; 98 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 103 ; 99 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 104 ; 100 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 105 ; 101 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 106 ; 102 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 107 ; 105 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 108 ; 106 ; 3 ; ~LVDS54p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; ; 109 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 110 ; 107 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 110 ; 107 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 111 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 112 ; 108 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 113 ; 109 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 114 ; 110 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 115 ; 112 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 116 ; 113 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 117 ; 114 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 118 ; 117 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 112 ; 108 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 113 ; 109 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 114 ; 110 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 115 ; 112 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 116 ; 113 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 117 ; 114 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 118 ; 117 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 119 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; 120 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; 121 ; 121 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; @@ -410,32 +411,32 @@ The pin-out file can be found in D:/projects/quartus/38_decoder/38_decoder.pin. ; 124 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; 125 ; 123 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; ; 126 ; 124 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; -; 127 ; 125 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 128 ; 126 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 127 ; 125 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 128 ; 126 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 129 ; 127 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; ; 130 ; 128 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; ; 131 ; 129 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; ; 132 ; 130 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 133 ; 131 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 134 ; 132 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 135 ; 133 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 133 ; 131 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 134 ; 132 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 135 ; 133 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 136 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 137 ; 134 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 138 ; 135 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 139 ; 136 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 137 ; 134 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 138 ; 135 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 139 ; 136 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 141 ; 137 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 142 ; 138 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 143 ; 141 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 144 ; 142 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 145 ; 143 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 146 ; 149 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 147 ; 150 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 141 ; 137 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 142 ; 138 ; 3 ; Y0 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 143 ; 141 ; 3 ; Y1 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 144 ; 142 ; 3 ; Y2 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 145 ; 143 ; 3 ; Y3 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 146 ; 149 ; 3 ; Y4 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 147 ; 150 ; 3 ; Y5 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; 148 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 149 ; 151 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 150 ; 152 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 151 ; 153 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 152 ; 154 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 149 ; 151 ; 3 ; Y6 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 150 ; 152 ; 3 ; Y7 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 151 ; 153 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 152 ; 154 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 153 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; 154 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; ; 155 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; @@ -443,55 +444,55 @@ The pin-out file can be found in D:/projects/quartus/38_decoder/38_decoder.pin. ; 157 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; 158 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; ; 159 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 160 ; 155 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 161 ; 156 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 162 ; 157 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 163 ; 158 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 164 ; 159 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 165 ; 160 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 160 ; 155 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 161 ; 156 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 162 ; 157 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 163 ; 158 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 164 ; 159 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 165 ; 160 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 166 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; 167 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 168 ; 161 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 169 ; 162 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 170 ; 163 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 171 ; 164 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 168 ; 161 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 169 ; 162 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 170 ; 163 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 171 ; 164 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 172 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 173 ; 165 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 173 ; 165 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 174 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 175 ; 168 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 176 ; 169 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 175 ; 168 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 176 ; 169 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 177 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; 178 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 179 ; 173 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 180 ; 174 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 181 ; 175 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 182 ; 176 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 179 ; 173 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 180 ; 174 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 181 ; 175 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 182 ; 176 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 183 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; 184 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 185 ; 180 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 185 ; 180 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 186 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 187 ; 181 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 188 ; 182 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 189 ; 183 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 187 ; 181 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 188 ; 182 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 189 ; 183 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 190 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 191 ; 184 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 192 ; 185 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 193 ; 186 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 191 ; 184 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 192 ; 185 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 193 ; 186 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 194 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 195 ; 187 ; 2 ; Y2 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 195 ; 187 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 196 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 197 ; 191 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 198 ; 192 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 199 ; 195 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 200 ; 196 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 201 ; 197 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 197 ; 191 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 198 ; 192 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 199 ; 195 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 200 ; 196 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 201 ; 197 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 202 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 203 ; 198 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 203 ; 198 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 204 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 205 ; 199 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 206 ; 200 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 207 ; 201 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 208 ; 202 ; 2 ; Y5 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 205 ; 199 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 206 ; 200 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 207 ; 201 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 208 ; 202 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ Note: Pin directions (input, output or bidir) are based on device operating in user mode. @@ -568,15 +569,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Source Pin / Fanout ; Pad To Core Index ; Setting ; +---------------------+-------------------+---------+ ; I2 ; ; ; -; - inst10~0 ; 1 ; 6 ; -; - inst10~1 ; 1 ; 6 ; -; - inst10~2 ; 1 ; 6 ; -; - inst10~3 ; 1 ; 6 ; -; - inst10~4 ; 1 ; 6 ; -; - inst10~5 ; 1 ; 6 ; -; - inst10~6 ; 1 ; 6 ; -; - inst10~7 ; 1 ; 6 ; -; I0 ; ; ; ; - inst10~0 ; 0 ; 6 ; ; - inst10~1 ; 0 ; 6 ; ; - inst10~2 ; 0 ; 6 ; @@ -585,6 +577,15 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; - inst10~5 ; 0 ; 6 ; ; - inst10~6 ; 0 ; 6 ; ; - inst10~7 ; 0 ; 6 ; +; I0 ; ; ; +; - inst10~0 ; 1 ; 6 ; +; - inst10~1 ; 1 ; 6 ; +; - inst10~2 ; 1 ; 6 ; +; - inst10~3 ; 1 ; 6 ; +; - inst10~4 ; 1 ; 6 ; +; - inst10~5 ; 1 ; 6 ; +; - inst10~6 ; 1 ; 6 ; +; - inst10~7 ; 1 ; 6 ; ; I1 ; ; ; ; - inst10~0 ; 1 ; 6 ; ; - inst10~1 ; 1 ; 6 ; @@ -622,13 +623,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Interconnect Resource Type ; Usage ; +----------------------------+-----------------------+ ; Block interconnects ; 11 / 26,052 ( < 1 % ) ; -; C16 interconnects ; 0 / 1,156 ( 0 % ) ; -; C4 interconnects ; 13 / 17,952 ( < 1 % ) ; -; Direct links ; 1 / 26,052 ( < 1 % ) ; +; C16 interconnects ; 4 / 1,156 ( < 1 % ) ; +; C4 interconnects ; 9 / 17,952 ( < 1 % ) ; +; Direct links ; 2 / 26,052 ( < 1 % ) ; ; Global clocks ; 0 / 8 ( 0 % ) ; ; Local interconnects ; 0 / 8,256 ( 0 % ) ; -; R24 interconnects ; 0 / 1,020 ( 0 % ) ; -; R4 interconnects ; 4 / 22,440 ( < 1 % ) ; +; R24 interconnects ; 3 / 1,020 ( < 1 % ) ; +; R4 interconnects ; 1 / 22,440 ( < 1 % ) ; +----------------------------+-----------------------+ @@ -715,7 +716,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Error detection CRC ; Off ; ; nCEO ; As output driving ground ; ; ASDO,nCSO ; As input tri-stated ; -; Reserve all unused pins ; As output driving ground ; +; Reserve all unused pins ; As input tri-stated ; ; Base pin-out file on sameframe device ; Off ; +----------------------------------------------+--------------------------+ @@ -810,20 +811,19 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +------------------------------------+------------+ -+---------------------------------------------------+ -; Advanced Data - Routing ; -+-------------------------------------+-------------+ -; Name ; Value ; -+-------------------------------------+-------------+ -; Early Slack - Fit Attempt 1 ; 2147483639 ; -; Mid Slack - Fit Attempt 1 ; 2147483639 ; -; Late Slack - Fit Attempt 1 ; -2147483648 ; -; Early Wire Use - Fit Attempt 1 ; 0 ; -; Peak Regional Wire - Fit Attempt 1 ; 0 ; -; Late Wire Use - Fit Attempt 1 ; 0 ; -; Time - Fit Attempt 1 ; 0 ; -; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016 ; -+-------------------------------------+-------------+ ++--------------------------------------------------+ +; Advanced Data - Routing ; ++------------------------------------+-------------+ +; Name ; Value ; ++------------------------------------+-------------+ +; Early Slack - Fit Attempt 1 ; 2147483639 ; +; Mid Slack - Fit Attempt 1 ; 2147483639 ; +; Late Slack - Fit Attempt 1 ; -2147483648 ; +; Early Wire Use - Fit Attempt 1 ; 0 ; +; Peak Regional Wire - Fit Attempt 1 ; 0 ; +; Late Wire Use - Fit Attempt 1 ; 0 ; +; Time - Fit Attempt 1 ; 0 ; ++------------------------------------+-------------+ +-----------------+ @@ -832,7 +832,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi Info: ******************************************************************* Info: Running Quartus II Fitter Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Mon Mar 07 09:13:05 2022 + Info: Processing started: Tue Mar 08 15:12:39 2022 Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder Info: Parallel compilation is enabled and will use 4 of the 4 processors detected Info: Selected device EP2C8Q208C8 for design "38_decoder" @@ -847,32 +847,11 @@ Info: Fitter converted 3 user pins into dedicated programming pins Info: Pin ~ASDO~ is reserved at location 1 Info: Pin ~nCSO~ is reserved at location 2 Info: Pin ~LVDS54p/nCEO~ is reserved at location 108 -Warning: No exact pin location assignment(s) for 11 pins of 11 total pins - Info: Pin Y7 not assigned to an exact location on the device - Info: Pin Y0 not assigned to an exact location on the device - Info: Pin Y1 not assigned to an exact location on the device - Info: Pin Y2 not assigned to an exact location on the device - Info: Pin Y3 not assigned to an exact location on the device - Info: Pin Y4 not assigned to an exact location on the device - Info: Pin Y5 not assigned to an exact location on the device - Info: Pin Y6 not assigned to an exact location on the device - Info: Pin I2 not assigned to an exact location on the device - Info: Pin I0 not assigned to an exact location on the device - Info: Pin I1 not assigned to an exact location on the device Info: Fitter is using the Classic Timing Analyzer Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time. Info: Starting register packing Info: Finished register packing Extra Info: No registers were packed into other blocks -Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement - Info: Number of I/O pins in group: 11 (unused VREF, 3.3V VCCIO, 3 input, 8 output, 0 bidirectional) - Info: I/O standards used: 3.3-V LVTTL. -Info: I/O bank details before I/O pin placement - Info: Statistics of I/O banks - Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available - Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available - Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available - Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available Info: Fitter preparation operations ending: elapsed time is 00:00:00 Info: Fitter placement preparation operations beginning Info: Fitter placement preparation operations ending: elapsed time is 00:00:00 @@ -881,7 +860,7 @@ Info: Fitter placement was successful Info: Fitter placement operations ending: elapsed time is 00:00:00 Info: Fitter routing operations beginning Info: Average interconnect usage is 0% of the available device resources - Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9 + Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y10 to location X34_Y19 Info: Fitter routing operations ending: elapsed time is 00:00:00 Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info: Optimizations that may affect the design's routability were skipped @@ -897,11 +876,10 @@ Warning: Found 8 output pins without output pin load capacitance assignment Info: Pin "Y5" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Y6" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Delay annotation completed successfully -Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. Info: Generated suppressed messages file D:/projects/quartus/38_decoder/38_decoder.fit.smsg -Info: Quartus II Fitter was successful. 0 errors, 3 warnings - Info: Peak virtual memory: 306 megabytes - Info: Processing ended: Mon Mar 07 09:13:06 2022 +Info: Quartus II Fitter was successful. 0 errors, 1 warning + Info: Peak virtual memory: 305 megabytes + Info: Processing ended: Tue Mar 08 15:12:40 2022 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/38_decoder/38_decoder.fit.summary b/38_decoder/38_decoder.fit.summary index 23abfbc..7cbb3c9 100644 --- a/38_decoder/38_decoder.fit.summary +++ b/38_decoder/38_decoder.fit.summary @@ -1,4 +1,4 @@ -Fitter Status : Successful - Mon Mar 07 09:13:06 2022 +Fitter Status : Successful - Tue Mar 08 15:12:40 2022 Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition Revision Name : 38_decoder Top-level Entity Name : 38_decoder diff --git a/38_decoder/38_decoder.flow.rpt b/38_decoder/38_decoder.flow.rpt index 3452d9e..b8b1298 100644 --- a/38_decoder/38_decoder.flow.rpt +++ b/38_decoder/38_decoder.flow.rpt @@ -1,5 +1,5 @@ Flow report for 38_decoder -Mon Mar 07 09:13:08 2022 +Tue Mar 08 15:12:42 2022 Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition @@ -38,7 +38,7 @@ applicable agreement for further details. +-----------------------------------------------------------------------------------+ ; Flow Summary ; +------------------------------------+----------------------------------------------+ -; Flow Status ; Successful - Mon Mar 07 09:13:08 2022 ; +; Flow Status ; Successful - Tue Mar 08 15:12:42 2022 ; ; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; ; Revision Name ; 38_decoder ; ; Top-level Entity Name ; 38_decoder ; @@ -63,7 +63,7 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 03/07/2022 09:13:04 ; +; Start date & time ; 03/08/2022 15:12:38 ; ; Main task ; Compilation ; ; Revision Name ; 38_decoder ; +-------------------+---------------------+ @@ -74,7 +74,7 @@ applicable agreement for further details. +------------------------------------+-----------------------------------------------+---------------+-------------+----------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +------------------------------------+-----------------------------------------------+---------------+-------------+----------------+ -; COMPILER_SIGNATURE_ID ; 220283517943889.164661558410840 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 220283517943889.164672355814724 ; -- ; -- ; -- ; ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; ; MISC_FILE ; D:/projects/quartus/38_decoder/38_decoder.dpf ; -- ; -- ; -- ; @@ -89,8 +89,8 @@ applicable agreement for further details. +-------------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +-------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 245 MB ; 00:00:00 ; -; Fitter ; 00:00:01 ; 1.0 ; 306 MB ; 00:00:01 ; +; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 246 MB ; 00:00:00 ; +; Fitter ; 00:00:01 ; 1.0 ; 305 MB ; 00:00:01 ; ; Assembler ; 00:00:00 ; 1.0 ; 241 MB ; 00:00:00 ; ; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 198 MB ; 00:00:00 ; ; Total ; 00:00:01 ; -- ; -- ; 00:00:01 ; diff --git a/38_decoder/38_decoder.map.rpt b/38_decoder/38_decoder.map.rpt index ee4c415..6f633ef 100644 --- a/38_decoder/38_decoder.map.rpt +++ b/38_decoder/38_decoder.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for 38_decoder -Mon Mar 07 09:13:04 2022 +Tue Mar 08 15:12:38 2022 Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition @@ -39,7 +39,7 @@ applicable agreement for further details. +-----------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +------------------------------------+----------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Mon Mar 07 09:13:04 2022 ; +; Analysis & Synthesis Status ; Successful - Tue Mar 08 15:12:38 2022 ; ; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; ; Revision Name ; 38_decoder ; ; Top-level Entity Name ; 38_decoder ; @@ -200,7 +200,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi Info: ******************************************************************* Info: Running Quartus II Analysis & Synthesis Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Mon Mar 07 09:13:04 2022 + Info: Processing started: Tue Mar 08 15:12:38 2022 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off 38_decoder -c 38_decoder Info: Found 1 design units, including 1 entities, in source file 38_decoder.bdf Info: Found entity 1: 38_decoder @@ -210,8 +210,8 @@ Info: Implemented 19 device resources after synthesis - the final resource count Info: Implemented 8 output pins Info: Implemented 8 logic cells Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 248 megabytes - Info: Processing ended: Mon Mar 07 09:13:04 2022 + Info: Peak virtual memory: 250 megabytes + Info: Processing ended: Tue Mar 08 15:12:38 2022 Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:00 diff --git a/38_decoder/38_decoder.map.summary b/38_decoder/38_decoder.map.summary index 20c6ab9..e76f577 100644 --- a/38_decoder/38_decoder.map.summary +++ b/38_decoder/38_decoder.map.summary @@ -1,4 +1,4 @@ -Analysis & Synthesis Status : Successful - Mon Mar 07 09:13:04 2022 +Analysis & Synthesis Status : Successful - Tue Mar 08 15:12:38 2022 Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition Revision Name : 38_decoder Top-level Entity Name : 38_decoder diff --git a/38_decoder/38_decoder.pin b/38_decoder/38_decoder.pin index 32bdd6e..0a6f10c 100644 --- a/38_decoder/38_decoder.pin +++ b/38_decoder/38_decoder.pin @@ -70,19 +70,19 @@ Pin Name/Usage : Location : Dir. : I/O Standard : Voltage ------------------------------------------------------------------------------------------------------------- ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVTTL : : 1 : N ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVTTL : : 1 : N -GND* : 3 : : : : 1 : -GND* : 4 : : : : 1 : -GND* : 5 : : : : 1 : -GND* : 6 : : : : 1 : +RESERVED_INPUT : 3 : : : : 1 : +RESERVED_INPUT : 4 : : : : 1 : +RESERVED_INPUT : 5 : : : : 1 : +RESERVED_INPUT : 6 : : : : 1 : VCCIO1 : 7 : power : : 3.3V : 1 : -GND* : 8 : : : : 1 : +RESERVED_INPUT : 8 : : : : 1 : GND : 9 : gnd : : : : -GND* : 10 : : : : 1 : -GND* : 11 : : : : 1 : -GND* : 12 : : : : 1 : -GND* : 13 : : : : 1 : -I1 : 14 : input : 3.3-V LVTTL : : 1 : N -GND* : 15 : : : : 1 : +RESERVED_INPUT : 10 : : : : 1 : +RESERVED_INPUT : 11 : : : : 1 : +RESERVED_INPUT : 12 : : : : 1 : +RESERVED_INPUT : 13 : : : : 1 : +RESERVED_INPUT : 14 : : : : 1 : +RESERVED_INPUT : 15 : : : : 1 : TDO : 16 : output : : : 1 : TMS : 17 : input : : : 1 : TCK : 18 : input : : : 1 : @@ -97,25 +97,25 @@ nCONFIG : 26 : : : GND+ : 27 : : : : 1 : GND+ : 28 : : : : 1 : VCCIO1 : 29 : power : : 3.3V : 1 : -Y4 : 30 : output : 3.3-V LVTTL : : 1 : N -GND* : 31 : : : : 1 : +RESERVED_INPUT : 30 : : : : 1 : +RESERVED_INPUT : 31 : : : : 1 : VCCINT : 32 : power : : 1.2V : : -Y3 : 33 : output : 3.3-V LVTTL : : 1 : N -Y6 : 34 : output : 3.3-V LVTTL : : 1 : N -I0 : 35 : input : 3.3-V LVTTL : : 1 : N +RESERVED_INPUT : 33 : : : : 1 : +RESERVED_INPUT : 34 : : : : 1 : +RESERVED_INPUT : 35 : : : : 1 : GND : 36 : gnd : : : : -Y1 : 37 : output : 3.3-V LVTTL : : 1 : N +RESERVED_INPUT : 37 : : : : 1 : GND : 38 : gnd : : : : -Y7 : 39 : output : 3.3-V LVTTL : : 1 : N -GND* : 40 : : : : 1 : -I2 : 41 : input : 3.3-V LVTTL : : 1 : N +RESERVED_INPUT : 39 : : : : 1 : +RESERVED_INPUT : 40 : : : : 1 : +RESERVED_INPUT : 41 : : : : 1 : VCCIO1 : 42 : power : : 3.3V : 1 : -GND* : 43 : : : : 1 : -GND* : 44 : : : : 1 : -Y0 : 45 : output : 3.3-V LVTTL : : 1 : N -GND* : 46 : : : : 1 : -GND* : 47 : : : : 1 : -GND* : 48 : : : : 1 : +RESERVED_INPUT : 43 : : : : 1 : +RESERVED_INPUT : 44 : : : : 1 : +RESERVED_INPUT : 45 : : : : 1 : +RESERVED_INPUT : 46 : : : : 1 : +RESERVED_INPUT : 47 : : : : 1 : +RESERVED_INPUT : 48 : : : : 1 : GND : 49 : gnd : : : : GND_PLL1 : 50 : gnd : : : : VCCD_PLL1 : 51 : power : : 1.2V : : @@ -123,69 +123,69 @@ GND_PLL1 : 52 : gnd : : VCCA_PLL1 : 53 : power : : 1.2V : : GNDA_PLL1 : 54 : gnd : : : : GND : 55 : gnd : : : : -GND* : 56 : : : : 4 : -GND* : 57 : : : : 4 : -GND* : 58 : : : : 4 : -GND* : 59 : : : : 4 : -GND* : 60 : : : : 4 : -GND* : 61 : : : : 4 : +RESERVED_INPUT : 56 : : : : 4 : +RESERVED_INPUT : 57 : : : : 4 : +RESERVED_INPUT : 58 : : : : 4 : +RESERVED_INPUT : 59 : : : : 4 : +RESERVED_INPUT : 60 : : : : 4 : +RESERVED_INPUT : 61 : : : : 4 : VCCIO4 : 62 : power : : 3.3V : 4 : -GND* : 63 : : : : 4 : -GND* : 64 : : : : 4 : +RESERVED_INPUT : 63 : : : : 4 : +RESERVED_INPUT : 64 : : : : 4 : GND : 65 : gnd : : : : VCCINT : 66 : power : : 1.2V : : -GND* : 67 : : : : 4 : -GND* : 68 : : : : 4 : -GND* : 69 : : : : 4 : -GND* : 70 : : : : 4 : +RESERVED_INPUT : 67 : : : : 4 : +RESERVED_INPUT : 68 : : : : 4 : +RESERVED_INPUT : 69 : : : : 4 : +RESERVED_INPUT : 70 : : : : 4 : VCCIO4 : 71 : power : : 3.3V : 4 : -GND* : 72 : : : : 4 : +RESERVED_INPUT : 72 : : : : 4 : GND : 73 : gnd : : : : -GND* : 74 : : : : 4 : -GND* : 75 : : : : 4 : -GND* : 76 : : : : 4 : -GND* : 77 : : : : 4 : +RESERVED_INPUT : 74 : : : : 4 : +RESERVED_INPUT : 75 : : : : 4 : +RESERVED_INPUT : 76 : : : : 4 : +I0 : 77 : input : 3.3-V LVTTL : : 4 : Y GND : 78 : gnd : : : : VCCINT : 79 : power : : 1.2V : : -GND* : 80 : : : : 4 : -GND* : 81 : : : : 4 : -GND* : 82 : : : : 4 : +I1 : 80 : input : 3.3-V LVTTL : : 4 : Y +I2 : 81 : input : 3.3-V LVTTL : : 4 : Y +RESERVED_INPUT : 82 : : : : 4 : VCCIO4 : 83 : power : : 3.3V : 4 : -GND* : 84 : : : : 4 : +RESERVED_INPUT : 84 : : : : 4 : GND : 85 : gnd : : : : -GND* : 86 : : : : 4 : -GND* : 87 : : : : 4 : -GND* : 88 : : : : 4 : -GND* : 89 : : : : 4 : -GND* : 90 : : : : 4 : +RESERVED_INPUT : 86 : : : : 4 : +RESERVED_INPUT : 87 : : : : 4 : +RESERVED_INPUT : 88 : : : : 4 : +RESERVED_INPUT : 89 : : : : 4 : +RESERVED_INPUT : 90 : : : : 4 : VCCIO4 : 91 : power : : 3.3V : 4 : -GND* : 92 : : : : 4 : +RESERVED_INPUT : 92 : : : : 4 : GND : 93 : gnd : : : : -GND* : 94 : : : : 4 : -GND* : 95 : : : : 4 : -GND* : 96 : : : : 4 : -GND* : 97 : : : : 4 : +RESERVED_INPUT : 94 : : : : 4 : +RESERVED_INPUT : 95 : : : : 4 : +RESERVED_INPUT : 96 : : : : 4 : +RESERVED_INPUT : 97 : : : : 4 : VCCIO4 : 98 : power : : 3.3V : 4 : -GND* : 99 : : : : 4 : +RESERVED_INPUT : 99 : : : : 4 : GND : 100 : gnd : : : : -GND* : 101 : : : : 4 : -GND* : 102 : : : : 4 : -GND* : 103 : : : : 4 : -GND* : 104 : : : : 4 : -GND* : 105 : : : : 3 : -GND* : 106 : : : : 3 : -GND* : 107 : : : : 3 : +RESERVED_INPUT : 101 : : : : 4 : +RESERVED_INPUT : 102 : : : : 4 : +RESERVED_INPUT : 103 : : : : 4 : +RESERVED_INPUT : 104 : : : : 4 : +RESERVED_INPUT : 105 : : : : 3 : +RESERVED_INPUT : 106 : : : : 3 : +RESERVED_INPUT : 107 : : : : 3 : ~LVDS54p/nCEO~ : 108 : output : 3.3-V LVTTL : : 3 : N VCCIO3 : 109 : power : : 3.3V : 3 : -GND* : 110 : : : : 3 : +RESERVED_INPUT : 110 : : : : 3 : GND : 111 : gnd : : : : -GND* : 112 : : : : 3 : -GND* : 113 : : : : 3 : -GND* : 114 : : : : 3 : -GND* : 115 : : : : 3 : -GND* : 116 : : : : 3 : -GND* : 117 : : : : 3 : -GND* : 118 : : : : 3 : +RESERVED_INPUT : 112 : : : : 3 : +RESERVED_INPUT : 113 : : : : 3 : +RESERVED_INPUT : 114 : : : : 3 : +RESERVED_INPUT : 115 : : : : 3 : +RESERVED_INPUT : 116 : : : : 3 : +RESERVED_INPUT : 117 : : : : 3 : +RESERVED_INPUT : 118 : : : : 3 : GND : 119 : gnd : : : : VCCINT : 120 : power : : 1.2V : : nSTATUS : 121 : : : : 3 : @@ -194,32 +194,32 @@ CONF_DONE : 123 : : : GND : 124 : gnd : : : : MSEL1 : 125 : : : : 3 : MSEL0 : 126 : : : : 3 : -GND* : 127 : : : : 3 : -GND* : 128 : : : : 3 : +RESERVED_INPUT : 127 : : : : 3 : +RESERVED_INPUT : 128 : : : : 3 : GND+ : 129 : : : : 3 : GND+ : 130 : : : : 3 : GND+ : 131 : : : : 3 : GND+ : 132 : : : : 3 : -GND* : 133 : : : : 3 : -GND* : 134 : : : : 3 : -GND* : 135 : : : : 3 : +RESERVED_INPUT : 133 : : : : 3 : +RESERVED_INPUT : 134 : : : : 3 : +RESERVED_INPUT : 135 : : : : 3 : VCCIO3 : 136 : power : : 3.3V : 3 : -GND* : 137 : : : : 3 : -GND* : 138 : : : : 3 : -GND* : 139 : : : : 3 : +RESERVED_INPUT : 137 : : : : 3 : +RESERVED_INPUT : 138 : : : : 3 : +RESERVED_INPUT : 139 : : : : 3 : GND : 140 : gnd : : : : -GND* : 141 : : : : 3 : -GND* : 142 : : : : 3 : -GND* : 143 : : : : 3 : -GND* : 144 : : : : 3 : -GND* : 145 : : : : 3 : -GND* : 146 : : : : 3 : -GND* : 147 : : : : 3 : +RESERVED_INPUT : 141 : : : : 3 : +Y0 : 142 : output : 3.3-V LVTTL : : 3 : Y +Y1 : 143 : output : 3.3-V LVTTL : : 3 : Y +Y2 : 144 : output : 3.3-V LVTTL : : 3 : Y +Y3 : 145 : output : 3.3-V LVTTL : : 3 : Y +Y4 : 146 : output : 3.3-V LVTTL : : 3 : Y +Y5 : 147 : output : 3.3-V LVTTL : : 3 : Y VCCIO3 : 148 : power : : 3.3V : 3 : -GND* : 149 : : : : 3 : -GND* : 150 : : : : 3 : -GND* : 151 : : : : 3 : -GND* : 152 : : : : 3 : +Y6 : 149 : output : 3.3-V LVTTL : : 3 : Y +Y7 : 150 : output : 3.3-V LVTTL : : 3 : Y +RESERVED_INPUT : 151 : : : : 3 : +RESERVED_INPUT : 152 : : : : 3 : GND : 153 : gnd : : : : GND_PLL2 : 154 : gnd : : : : VCCD_PLL2 : 155 : power : : 1.2V : : @@ -227,52 +227,52 @@ GND_PLL2 : 156 : gnd : : VCCA_PLL2 : 157 : power : : 1.2V : : GNDA_PLL2 : 158 : gnd : : : : GND : 159 : gnd : : : : -GND* : 160 : : : : 2 : -GND* : 161 : : : : 2 : -GND* : 162 : : : : 2 : -GND* : 163 : : : : 2 : -GND* : 164 : : : : 2 : -GND* : 165 : : : : 2 : +RESERVED_INPUT : 160 : : : : 2 : +RESERVED_INPUT : 161 : : : : 2 : +RESERVED_INPUT : 162 : : : : 2 : +RESERVED_INPUT : 163 : : : : 2 : +RESERVED_INPUT : 164 : : : : 2 : +RESERVED_INPUT : 165 : : : : 2 : VCCIO2 : 166 : power : : 3.3V : 2 : GND : 167 : gnd : : : : -GND* : 168 : : : : 2 : -GND* : 169 : : : : 2 : -GND* : 170 : : : : 2 : -GND* : 171 : : : : 2 : +RESERVED_INPUT : 168 : : : : 2 : +RESERVED_INPUT : 169 : : : : 2 : +RESERVED_INPUT : 170 : : : : 2 : +RESERVED_INPUT : 171 : : : : 2 : VCCIO2 : 172 : power : : 3.3V : 2 : -GND* : 173 : : : : 2 : +RESERVED_INPUT : 173 : : : : 2 : GND : 174 : gnd : : : : -GND* : 175 : : : : 2 : -GND* : 176 : : : : 2 : +RESERVED_INPUT : 175 : : : : 2 : +RESERVED_INPUT : 176 : : : : 2 : GND : 177 : gnd : : : : VCCINT : 178 : power : : 1.2V : : -GND* : 179 : : : : 2 : -GND* : 180 : : : : 2 : -GND* : 181 : : : : 2 : -GND* : 182 : : : : 2 : +RESERVED_INPUT : 179 : : : : 2 : +RESERVED_INPUT : 180 : : : : 2 : +RESERVED_INPUT : 181 : : : : 2 : +RESERVED_INPUT : 182 : : : : 2 : VCCIO2 : 183 : power : : 3.3V : 2 : GND : 184 : gnd : : : : -GND* : 185 : : : : 2 : +RESERVED_INPUT : 185 : : : : 2 : GND : 186 : gnd : : : : -GND* : 187 : : : : 2 : -GND* : 188 : : : : 2 : -GND* : 189 : : : : 2 : +RESERVED_INPUT : 187 : : : : 2 : +RESERVED_INPUT : 188 : : : : 2 : +RESERVED_INPUT : 189 : : : : 2 : VCCINT : 190 : power : : 1.2V : : -GND* : 191 : : : : 2 : -GND* : 192 : : : : 2 : -GND* : 193 : : : : 2 : +RESERVED_INPUT : 191 : : : : 2 : +RESERVED_INPUT : 192 : : : : 2 : +RESERVED_INPUT : 193 : : : : 2 : VCCIO2 : 194 : power : : 3.3V : 2 : -Y2 : 195 : output : 3.3-V LVTTL : : 2 : N +RESERVED_INPUT : 195 : : : : 2 : GND : 196 : gnd : : : : -GND* : 197 : : : : 2 : -GND* : 198 : : : : 2 : -GND* : 199 : : : : 2 : -GND* : 200 : : : : 2 : -GND* : 201 : : : : 2 : +RESERVED_INPUT : 197 : : : : 2 : +RESERVED_INPUT : 198 : : : : 2 : +RESERVED_INPUT : 199 : : : : 2 : +RESERVED_INPUT : 200 : : : : 2 : +RESERVED_INPUT : 201 : : : : 2 : VCCIO2 : 202 : power : : 3.3V : 2 : -GND* : 203 : : : : 2 : +RESERVED_INPUT : 203 : : : : 2 : GND : 204 : gnd : : : : -GND* : 205 : : : : 2 : -GND* : 206 : : : : 2 : -GND* : 207 : : : : 2 : -Y5 : 208 : output : 3.3-V LVTTL : : 2 : N +RESERVED_INPUT : 205 : : : : 2 : +RESERVED_INPUT : 206 : : : : 2 : +RESERVED_INPUT : 207 : : : : 2 : +RESERVED_INPUT : 208 : : : : 2 : diff --git a/38_decoder/38_decoder.pof b/38_decoder/38_decoder.pof index bbba2ec..5959345 100644 Binary files a/38_decoder/38_decoder.pof and b/38_decoder/38_decoder.pof differ diff --git a/38_decoder/38_decoder.qsf b/38_decoder/38_decoder.qsf index c51ed34..bc0dcab 100644 --- a/38_decoder/38_decoder.qsf +++ b/38_decoder/38_decoder.qsf @@ -51,4 +51,18 @@ set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" \ No newline at end of file +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_location_assignment PIN_77 -to I0 +set_location_assignment PIN_80 -to I1 +set_location_assignment PIN_81 -to I2 +set_location_assignment PIN_142 -to Y0 +set_location_assignment PIN_143 -to Y1 +set_location_assignment PIN_144 -to Y2 +set_location_assignment PIN_145 -to Y3 +set_location_assignment PIN_146 -to Y4 +set_location_assignment PIN_147 -to Y5 +set_location_assignment PIN_149 -to Y6 +set_location_assignment PIN_150 -to Y7 \ No newline at end of file diff --git a/38_decoder/38_decoder.sof b/38_decoder/38_decoder.sof index 44209ac..d8f3d1a 100644 Binary files a/38_decoder/38_decoder.sof and b/38_decoder/38_decoder.sof differ diff --git a/38_decoder/38_decoder.tan.rpt b/38_decoder/38_decoder.tan.rpt index c0b61b4..08fe936 100644 --- a/38_decoder/38_decoder.tan.rpt +++ b/38_decoder/38_decoder.tan.rpt @@ -1,5 +1,5 @@ Classic Timing Analyzer report for 38_decoder -Mon Mar 07 09:13:08 2022 +Tue Mar 08 15:12:42 2022 Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition @@ -39,7 +39,7 @@ applicable agreement for further details. +------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ ; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; +------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ -; Worst-case tpd ; N/A ; None ; 13.383 ns ; I2 ; Y2 ; -- ; -- ; 0 ; +; Worst-case tpd ; N/A ; None ; 13.172 ns ; I2 ; Y4 ; -- ; -- ; 0 ; ; Total number of failed paths ; ; ; ; ; ; ; ; 0 ; +------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ @@ -98,30 +98,30 @@ applicable agreement for further details. +-------+-------------------+-----------------+------+----+ ; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ; +-------+-------------------+-----------------+------+----+ -; N/A ; None ; 13.383 ns ; I2 ; Y2 ; -; N/A ; None ; 13.370 ns ; I1 ; Y2 ; -; N/A ; None ; 12.806 ns ; I0 ; Y2 ; -; N/A ; None ; 12.348 ns ; I2 ; Y5 ; -; N/A ; None ; 12.185 ns ; I1 ; Y5 ; -; N/A ; None ; 11.620 ns ; I0 ; Y5 ; -; N/A ; None ; 11.545 ns ; I2 ; Y4 ; -; N/A ; None ; 11.530 ns ; I2 ; Y7 ; -; N/A ; None ; 11.492 ns ; I2 ; Y0 ; -; N/A ; None ; 11.439 ns ; I1 ; Y0 ; -; N/A ; None ; 11.438 ns ; I2 ; Y1 ; -; N/A ; None ; 11.402 ns ; I1 ; Y7 ; -; N/A ; None ; 11.395 ns ; I1 ; Y4 ; -; N/A ; None ; 11.382 ns ; I1 ; Y1 ; -; N/A ; None ; 11.296 ns ; I1 ; Y3 ; -; N/A ; None ; 11.292 ns ; I2 ; Y3 ; -; N/A ; None ; 11.129 ns ; I2 ; Y6 ; -; N/A ; None ; 11.012 ns ; I1 ; Y6 ; -; N/A ; None ; 10.880 ns ; I0 ; Y0 ; -; N/A ; None ; 10.837 ns ; I0 ; Y7 ; -; N/A ; None ; 10.822 ns ; I0 ; Y1 ; -; N/A ; None ; 10.819 ns ; I0 ; Y4 ; -; N/A ; None ; 10.717 ns ; I0 ; Y3 ; -; N/A ; None ; 10.444 ns ; I0 ; Y6 ; +; N/A ; None ; 13.172 ns ; I2 ; Y4 ; +; N/A ; None ; 13.161 ns ; I2 ; Y6 ; +; N/A ; None ; 13.141 ns ; I2 ; Y5 ; +; N/A ; None ; 13.095 ns ; I2 ; Y7 ; +; N/A ; None ; 13.009 ns ; I2 ; Y3 ; +; N/A ; None ; 12.995 ns ; I2 ; Y0 ; +; N/A ; None ; 12.674 ns ; I1 ; Y6 ; +; N/A ; None ; 12.658 ns ; I0 ; Y5 ; +; N/A ; None ; 12.658 ns ; I1 ; Y4 ; +; N/A ; None ; 12.648 ns ; I1 ; Y3 ; +; N/A ; None ; 12.647 ns ; I2 ; Y1 ; +; N/A ; None ; 12.636 ns ; I0 ; Y3 ; +; N/A ; None ; 12.623 ns ; I1 ; Y7 ; +; N/A ; None ; 12.619 ns ; I0 ; Y7 ; +; N/A ; None ; 12.614 ns ; I0 ; Y4 ; +; N/A ; None ; 12.612 ns ; I1 ; Y5 ; +; N/A ; None ; 12.594 ns ; I0 ; Y6 ; +; N/A ; None ; 12.580 ns ; I1 ; Y0 ; +; N/A ; None ; 12.560 ns ; I2 ; Y2 ; +; N/A ; None ; 12.535 ns ; I0 ; Y0 ; +; N/A ; None ; 12.270 ns ; I0 ; Y1 ; +; N/A ; None ; 12.241 ns ; I1 ; Y1 ; +; N/A ; None ; 12.201 ns ; I1 ; Y2 ; +; N/A ; None ; 12.104 ns ; I0 ; Y2 ; +-------+-------------------+-----------------+------+----+ @@ -131,18 +131,18 @@ applicable agreement for further details. Info: ******************************************************************* Info: Running Quartus II Classic Timing Analyzer Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Mon Mar 07 09:13:08 2022 + Info: Processing started: Tue Mar 08 15:12:42 2022 Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder --timing_analysis_only Info: Parallel compilation is enabled and will use 4 of the 4 processors detected -Info: Longest tpd from source pin "I2" to destination pin "Y2" is 13.383 ns - Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_41; Fanout = 8; PIN Node = 'I2' - Info: 2: + IC(5.786 ns) + CELL(0.499 ns) = 7.280 ns; Loc. = LCCOMB_X1_Y7_N22; Fanout = 1; COMB Node = 'inst10~3' - Info: 3: + IC(2.847 ns) + CELL(3.256 ns) = 13.383 ns; Loc. = PIN_195; Fanout = 0; PIN Node = 'Y2' - Info: Total cell delay = 4.750 ns ( 35.49 % ) - Info: Total interconnect delay = 8.633 ns ( 64.51 % ) +Info: Longest tpd from source pin "I2" to destination pin "Y4" is 13.172 ns + Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_81; Fanout = 8; PIN Node = 'I2' + Info: 2: + IC(7.387 ns) + CELL(0.651 ns) = 9.012 ns; Loc. = LCCOMB_X33_Y13_N2; Fanout = 1; COMB Node = 'inst10~5' + Info: 3: + IC(1.054 ns) + CELL(3.106 ns) = 13.172 ns; Loc. = PIN_146; Fanout = 0; PIN Node = 'Y4' + Info: Total cell delay = 4.731 ns ( 35.92 % ) + Info: Total interconnect delay = 8.441 ns ( 64.08 % ) Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings Info: Peak virtual memory: 212 megabytes - Info: Processing ended: Mon Mar 07 09:13:08 2022 + Info: Processing ended: Tue Mar 08 15:12:42 2022 Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:00 diff --git a/38_decoder/38_decoder.tan.summary b/38_decoder/38_decoder.tan.summary index 372a7d7..beb25fd 100644 --- a/38_decoder/38_decoder.tan.summary +++ b/38_decoder/38_decoder.tan.summary @@ -5,9 +5,9 @@ Timing Analyzer Summary Type : Worst-case tpd Slack : N/A Required Time : None -Actual Time : 13.383 ns +Actual Time : 13.172 ns From : I2 -To : Y2 +To : Y4 From Clock : -- To Clock : -- Failed Paths : 0 diff --git a/38_decoder/db/38_decoder.asm.qmsg b/38_decoder/db/38_decoder.asm.qmsg index 9297466..1c22f03 100644 --- a/38_decoder/db/38_decoder.asm.qmsg +++ b/38_decoder/db/38_decoder.asm.qmsg @@ -1,7 +1,7 @@ { "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 09:13:07 2022 " "Info: Processing started: Mon Mar 07 09:13:07 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:12:41 2022 " "Info: Processing started: Tue Mar 08 15:12:41 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} { "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1} { "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1} { "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 09:13:07 2022 " "Info: Processing ended: Mon Mar 07 09:13:07 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:12:41 2022 " "Info: Processing ended: Tue Mar 08 15:12:41 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/38_decoder/db/38_decoder.asm_labs.ddb b/38_decoder/db/38_decoder.asm_labs.ddb index cf5c209..5227a15 100644 Binary files a/38_decoder/db/38_decoder.asm_labs.ddb and b/38_decoder/db/38_decoder.asm_labs.ddb differ diff --git a/38_decoder/db/38_decoder.cmp.bpm b/38_decoder/db/38_decoder.cmp.bpm index 8c0b460..a588ab5 100644 Binary files a/38_decoder/db/38_decoder.cmp.bpm and b/38_decoder/db/38_decoder.cmp.bpm differ diff --git a/38_decoder/db/38_decoder.cmp.cdb b/38_decoder/db/38_decoder.cmp.cdb index 6a432b9..3dc02b1 100644 Binary files a/38_decoder/db/38_decoder.cmp.cdb and b/38_decoder/db/38_decoder.cmp.cdb differ diff --git a/38_decoder/db/38_decoder.cmp.hdb b/38_decoder/db/38_decoder.cmp.hdb index 47b0a26..eeda646 100644 Binary files a/38_decoder/db/38_decoder.cmp.hdb and b/38_decoder/db/38_decoder.cmp.hdb differ diff --git a/38_decoder/db/38_decoder.cmp.rdb b/38_decoder/db/38_decoder.cmp.rdb index 8a84e47..a939741 100644 Binary files a/38_decoder/db/38_decoder.cmp.rdb and b/38_decoder/db/38_decoder.cmp.rdb differ diff --git a/38_decoder/db/38_decoder.cmp.tdb b/38_decoder/db/38_decoder.cmp.tdb index 7da23b4..b4c7911 100644 Binary files a/38_decoder/db/38_decoder.cmp.tdb and b/38_decoder/db/38_decoder.cmp.tdb differ diff --git a/38_decoder/db/38_decoder.cmp0.ddb b/38_decoder/db/38_decoder.cmp0.ddb index 2d674db..2fb1195 100644 Binary files a/38_decoder/db/38_decoder.cmp0.ddb and b/38_decoder/db/38_decoder.cmp0.ddb differ diff --git a/38_decoder/db/38_decoder.cmp2.ddb b/38_decoder/db/38_decoder.cmp2.ddb index 1a4c4ba..982346f 100644 Binary files a/38_decoder/db/38_decoder.cmp2.ddb and b/38_decoder/db/38_decoder.cmp2.ddb differ diff --git a/38_decoder/db/38_decoder.fit.qmsg b/38_decoder/db/38_decoder.fit.qmsg index a04d2f2..b7a5094 100644 --- a/38_decoder/db/38_decoder.fit.qmsg +++ b/38_decoder/db/38_decoder.fit.qmsg @@ -1,5 +1,5 @@ { "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 09:13:05 2022 " "Info: Processing started: Mon Mar 07 09:13:05 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:12:39 2022 " "Info: Processing started: Tue Mar 08 15:12:39 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} { "Info" "IMPP_MPP_USER_DEVICE" "38_decoder EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"38_decoder\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} @@ -8,7 +8,6 @@ { "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1} -{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "11 11 " "Warning: No exact pin location assignment(s) for 11 pins of 11 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y7 " "Info: Pin Y7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y7 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 40 664 840 56 "Y7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y0 " "Info: Pin Y0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y0 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 376 664 840 392 "Y0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y1 " "Info: Pin Y1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y1 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 328 664 840 344 "Y1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y2 " "Info: Pin Y2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y2 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 280 664 840 296 "Y2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y3 " "Info: Pin Y3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y3 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 232 664 840 248 "Y3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y4 " "Info: Pin Y4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y4 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 184 664 840 200 "Y4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y5 " "Info: Pin Y5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y5 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 136 664 840 152 "Y5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y6 " "Info: Pin Y6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y6 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 88 664 840 104 "Y6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "I2 " "Info: Pin I2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { I2 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 144 32 200 160 "I2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "I0 " "Info: Pin I0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { I0 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 328 32 200 344 "I0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "I1 " "Info: Pin I1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { I1 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 240 32 200 256 "I1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1} { "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1} { "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1} @@ -19,8 +18,6 @@ { "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1} { "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1} { "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "11 unused 3.3V 3 8 0 " "Info: Number of I/O pins in group: 11 (unused VREF, 3.3V VCCIO, 3 input, 8 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 2 30 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 35 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 34 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 36 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1} { "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} @@ -28,12 +25,11 @@ { "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X10_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y10 X34_Y19 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y10 to location X34_Y19" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1} { "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y7 0 " "Info: Pin \"Y7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y0 0 " "Info: Pin \"Y0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y1 0 " "Info: Pin \"Y1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y2 0 " "Info: Pin \"Y2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y3 0 " "Info: Pin \"Y3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y4 0 " "Info: Pin \"Y4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y5 0 " "Info: Pin \"Y5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y6 0 " "Info: Pin \"Y6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1} { "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1} { "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/38_decoder/38_decoder.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/38_decoder/38_decoder.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "306 " "Info: Peak virtual memory: 306 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 09:13:06 2022 " "Info: Processing ended: Mon Mar 07 09:13:06 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "305 " "Info: Peak virtual memory: 305 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:12:40 2022 " "Info: Processing ended: Tue Mar 08 15:12:40 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/38_decoder/db/38_decoder.map.bpm b/38_decoder/db/38_decoder.map.bpm index ec26f38..a561200 100644 Binary files a/38_decoder/db/38_decoder.map.bpm and b/38_decoder/db/38_decoder.map.bpm differ diff --git a/38_decoder/db/38_decoder.map.cdb b/38_decoder/db/38_decoder.map.cdb index 453776c..39e2f5e 100644 Binary files a/38_decoder/db/38_decoder.map.cdb and b/38_decoder/db/38_decoder.map.cdb differ diff --git a/38_decoder/db/38_decoder.map.hdb b/38_decoder/db/38_decoder.map.hdb index b3363bc..ae5facc 100644 Binary files a/38_decoder/db/38_decoder.map.hdb and b/38_decoder/db/38_decoder.map.hdb differ diff --git a/38_decoder/db/38_decoder.map.qmsg b/38_decoder/db/38_decoder.map.qmsg index bba0833..7d51101 100644 --- a/38_decoder/db/38_decoder.map.qmsg +++ b/38_decoder/db/38_decoder.map.qmsg @@ -1,7 +1,7 @@ { "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 09:13:04 2022 " "Info: Processing started: Mon Mar 07 09:13:04 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:12:38 2022 " "Info: Processing started: Tue Mar 08 15:12:38 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off 38_decoder -c 38_decoder " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off 38_decoder -c 38_decoder" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "38_decoder.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file 38_decoder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 38_decoder " "Info: Found entity 1: 38_decoder" { } { { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} { "Info" "ISGN_START_ELABORATION_TOP" "38_decoder " "Info: Elaborating entity \"38_decoder\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_SUMMARY" "19 " "Info: Implemented 19 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Info: Implemented 3 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "248 " "Info: Peak virtual memory: 248 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 09:13:04 2022 " "Info: Processing ended: Mon Mar 07 09:13:04 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:12:38 2022 " "Info: Processing ended: Tue Mar 08 15:12:38 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/38_decoder/db/38_decoder.map_bb.cdb b/38_decoder/db/38_decoder.map_bb.cdb index f5593b6..52e3520 100644 Binary files a/38_decoder/db/38_decoder.map_bb.cdb and b/38_decoder/db/38_decoder.map_bb.cdb differ diff --git a/38_decoder/db/38_decoder.map_bb.hdb b/38_decoder/db/38_decoder.map_bb.hdb index 7a55a4a..871b480 100644 Binary files a/38_decoder/db/38_decoder.map_bb.hdb and b/38_decoder/db/38_decoder.map_bb.hdb differ diff --git a/38_decoder/db/38_decoder.pre_map.cdb b/38_decoder/db/38_decoder.pre_map.cdb index a1e0f2b..8928020 100644 Binary files a/38_decoder/db/38_decoder.pre_map.cdb and b/38_decoder/db/38_decoder.pre_map.cdb differ diff --git a/38_decoder/db/38_decoder.pre_map.hdb b/38_decoder/db/38_decoder.pre_map.hdb index 755d0df..41e732f 100644 Binary files a/38_decoder/db/38_decoder.pre_map.hdb and b/38_decoder/db/38_decoder.pre_map.hdb differ diff --git a/38_decoder/db/38_decoder.rtlv.hdb b/38_decoder/db/38_decoder.rtlv.hdb index ddf7de4..c506974 100644 Binary files a/38_decoder/db/38_decoder.rtlv.hdb and b/38_decoder/db/38_decoder.rtlv.hdb differ diff --git a/38_decoder/db/38_decoder.rtlv_sg.cdb b/38_decoder/db/38_decoder.rtlv_sg.cdb index f1f7e31..294d082 100644 Binary files a/38_decoder/db/38_decoder.rtlv_sg.cdb and b/38_decoder/db/38_decoder.rtlv_sg.cdb differ diff --git a/38_decoder/db/38_decoder.sgdiff.cdb b/38_decoder/db/38_decoder.sgdiff.cdb index a321ed4..b12c775 100644 Binary files a/38_decoder/db/38_decoder.sgdiff.cdb and b/38_decoder/db/38_decoder.sgdiff.cdb differ diff --git a/38_decoder/db/38_decoder.sgdiff.hdb b/38_decoder/db/38_decoder.sgdiff.hdb index f17bae6..7b35d44 100644 Binary files a/38_decoder/db/38_decoder.sgdiff.hdb and b/38_decoder/db/38_decoder.sgdiff.hdb differ diff --git a/38_decoder/db/38_decoder.tan.qmsg b/38_decoder/db/38_decoder.tan.qmsg index a205924..0d4dd5e 100644 --- a/38_decoder/db/38_decoder.tan.qmsg +++ b/38_decoder/db/38_decoder.tan.qmsg @@ -1,6 +1,6 @@ { "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 09:13:08 2022 " "Info: Processing started: Mon Mar 07 09:13:08 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:12:42 2022 " "Info: Processing started: Tue Mar 08 15:12:42 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "ITDB_FULL_TPD_RESULT" "I2 Y2 13.383 ns Longest " "Info: Longest tpd from source pin \"I2\" to destination pin \"Y2\" is 13.383 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns I2 1 PIN PIN_41 8 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_41; Fanout = 8; PIN Node = 'I2'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2 } "NODE_NAME" } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 144 32 200 160 "I2" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.786 ns) + CELL(0.499 ns) 7.280 ns inst10~3 2 COMB LCCOMB_X1_Y7_N22 1 " "Info: 2: + IC(5.786 ns) + CELL(0.499 ns) = 7.280 ns; Loc. = LCCOMB_X1_Y7_N22; Fanout = 1; COMB Node = 'inst10~3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.285 ns" { I2 inst10~3 } "NODE_NAME" } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 360 544 608 408 "inst10" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.847 ns) + CELL(3.256 ns) 13.383 ns Y2 3 PIN PIN_195 0 " "Info: 3: + IC(2.847 ns) + CELL(3.256 ns) = 13.383 ns; Loc. = PIN_195; Fanout = 0; PIN Node = 'Y2'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.103 ns" { inst10~3 Y2 } "NODE_NAME" } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 280 664 840 296 "Y2" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.750 ns ( 35.49 % ) " "Info: Total cell delay = 4.750 ns ( 35.49 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.633 ns ( 64.51 % ) " "Info: Total interconnect delay = 8.633 ns ( 64.51 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "13.383 ns" { I2 inst10~3 Y2 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "13.383 ns" { I2 {} I2~combout {} inst10~3 {} Y2 {} } { 0.000ns 0.000ns 5.786ns 2.847ns } { 0.000ns 0.995ns 0.499ns 3.256ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 09:13:08 2022 " "Info: Processing ended: Mon Mar 07 09:13:08 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_TPD_RESULT" "I2 Y4 13.172 ns Longest " "Info: Longest tpd from source pin \"I2\" to destination pin \"Y4\" is 13.172 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns I2 1 PIN PIN_81 8 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_81; Fanout = 8; PIN Node = 'I2'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2 } "NODE_NAME" } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 144 32 200 160 "I2" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(7.387 ns) + CELL(0.651 ns) 9.012 ns inst10~5 2 COMB LCCOMB_X33_Y13_N2 1 " "Info: 2: + IC(7.387 ns) + CELL(0.651 ns) = 9.012 ns; Loc. = LCCOMB_X33_Y13_N2; Fanout = 1; COMB Node = 'inst10~5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.038 ns" { I2 inst10~5 } "NODE_NAME" } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 360 544 608 408 "inst10" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.054 ns) + CELL(3.106 ns) 13.172 ns Y4 3 PIN PIN_146 0 " "Info: 3: + IC(1.054 ns) + CELL(3.106 ns) = 13.172 ns; Loc. = PIN_146; Fanout = 0; PIN Node = 'Y4'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.160 ns" { inst10~5 Y4 } "NODE_NAME" } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 184 664 840 200 "Y4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.731 ns ( 35.92 % ) " "Info: Total cell delay = 4.731 ns ( 35.92 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.441 ns ( 64.08 % ) " "Info: Total interconnect delay = 8.441 ns ( 64.08 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "13.172 ns" { I2 inst10~5 Y4 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "13.172 ns" { I2 {} I2~combout {} inst10~5 {} Y4 {} } { 0.000ns 0.000ns 7.387ns 1.054ns } { 0.000ns 0.974ns 0.651ns 3.106ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:12:42 2022 " "Info: Processing ended: Tue Mar 08 15:12:42 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/38_decoder/db/38_decoder.tmw_info b/38_decoder/db/38_decoder.tmw_info index 15a6255..6516e48 100644 --- a/38_decoder/db/38_decoder.tmw_info +++ b/38_decoder/db/38_decoder.tmw_info @@ -1,6 +1,6 @@ start_full_compilation:s:00:00:05 -start_analysis_synthesis:s:00:00:01-start_full_compilation +start_analysis_synthesis:s:00:00:02-start_full_compilation start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:02-start_full_compilation -start_assembler:s:00:00:01-start_full_compilation -start_timing_analyzer:s:00:00:01-start_full_compilation +start_fitter:s:00:00:01-start_full_compilation +start_assembler:s:00:00:02-start_full_compilation +start_timing_analyzer:s:00:00:00-start_full_compilation diff --git a/38_decoder/db/prev_cmp_38_decoder.asm.qmsg b/38_decoder/db/prev_cmp_38_decoder.asm.qmsg new file mode 100644 index 0000000..9297466 --- /dev/null +++ b/38_decoder/db/prev_cmp_38_decoder.asm.qmsg @@ -0,0 +1,7 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 09:13:07 2022 " "Info: Processing started: Mon Mar 07 09:13:07 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1} +{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 09:13:07 2022 " "Info: Processing ended: Mon Mar 07 09:13:07 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/38_decoder/db/prev_cmp_38_decoder.fit.qmsg b/38_decoder/db/prev_cmp_38_decoder.fit.qmsg new file mode 100644 index 0000000..a04d2f2 --- /dev/null +++ b/38_decoder/db/prev_cmp_38_decoder.fit.qmsg @@ -0,0 +1,39 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 09:13:05 2022 " "Info: Processing started: Mon Mar 07 09:13:05 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} +{ "Info" "IMPP_MPP_USER_DEVICE" "38_decoder EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"38_decoder\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1} +{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "11 11 " "Warning: No exact pin location assignment(s) for 11 pins of 11 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y7 " "Info: Pin Y7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y7 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 40 664 840 56 "Y7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y0 " "Info: Pin Y0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y0 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 376 664 840 392 "Y0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y1 " "Info: Pin Y1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y1 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 328 664 840 344 "Y1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y2 " "Info: Pin Y2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y2 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 280 664 840 296 "Y2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y3 " "Info: Pin Y3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y3 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 232 664 840 248 "Y3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y4 " "Info: Pin Y4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y4 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 184 664 840 200 "Y4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y5 " "Info: Pin Y5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y5 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 136 664 840 152 "Y5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y6 " "Info: Pin Y6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y6 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 88 664 840 104 "Y6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "I2 " "Info: Pin I2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { I2 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 144 32 200 160 "I2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "I0 " "Info: Pin I0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { I0 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 328 32 200 344 "I0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "I1 " "Info: Pin I1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { I1 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 240 32 200 256 "I1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1} +{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1} +{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "11 unused 3.3V 3 8 0 " "Info: Number of I/O pins in group: 11 (unused VREF, 3.3V VCCIO, 3 input, 8 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 2 30 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 35 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 34 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 36 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X10_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1} +{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} +{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y7 0 " "Info: Pin \"Y7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y0 0 " "Info: Pin \"Y0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y1 0 " "Info: Pin \"Y1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y2 0 " "Info: Pin \"Y2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y3 0 " "Info: Pin \"Y3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y4 0 " "Info: Pin \"Y4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y5 0 " "Info: Pin \"Y5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y6 0 " "Info: Pin \"Y6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1} +{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/38_decoder/38_decoder.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/38_decoder/38_decoder.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "306 " "Info: Peak virtual memory: 306 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 09:13:06 2022 " "Info: Processing ended: Mon Mar 07 09:13:06 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/38_decoder/db/prev_cmp_38_decoder.map.qmsg b/38_decoder/db/prev_cmp_38_decoder.map.qmsg new file mode 100644 index 0000000..bba0833 --- /dev/null +++ b/38_decoder/db/prev_cmp_38_decoder.map.qmsg @@ -0,0 +1,7 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 09:13:04 2022 " "Info: Processing started: Mon Mar 07 09:13:04 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off 38_decoder -c 38_decoder " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off 38_decoder -c 38_decoder" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "38_decoder.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file 38_decoder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 38_decoder " "Info: Found entity 1: 38_decoder" { } { { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_TOP" "38_decoder " "Info: Elaborating entity \"38_decoder\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} +{ "Info" "ICUT_CUT_TM_SUMMARY" "19 " "Info: Implemented 19 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Info: Implemented 3 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "248 " "Info: Peak virtual memory: 248 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 09:13:04 2022 " "Info: Processing ended: Mon Mar 07 09:13:04 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/38_decoder/db/prev_cmp_38_decoder.tan.qmsg b/38_decoder/db/prev_cmp_38_decoder.tan.qmsg new file mode 100644 index 0000000..a205924 --- /dev/null +++ b/38_decoder/db/prev_cmp_38_decoder.tan.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 09:13:08 2022 " "Info: Processing started: Mon Mar 07 09:13:08 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_TPD_RESULT" "I2 Y2 13.383 ns Longest " "Info: Longest tpd from source pin \"I2\" to destination pin \"Y2\" is 13.383 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns I2 1 PIN PIN_41 8 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_41; Fanout = 8; PIN Node = 'I2'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2 } "NODE_NAME" } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 144 32 200 160 "I2" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.786 ns) + CELL(0.499 ns) 7.280 ns inst10~3 2 COMB LCCOMB_X1_Y7_N22 1 " "Info: 2: + IC(5.786 ns) + CELL(0.499 ns) = 7.280 ns; Loc. = LCCOMB_X1_Y7_N22; Fanout = 1; COMB Node = 'inst10~3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.285 ns" { I2 inst10~3 } "NODE_NAME" } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 360 544 608 408 "inst10" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.847 ns) + CELL(3.256 ns) 13.383 ns Y2 3 PIN PIN_195 0 " "Info: 3: + IC(2.847 ns) + CELL(3.256 ns) = 13.383 ns; Loc. = PIN_195; Fanout = 0; PIN Node = 'Y2'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.103 ns" { inst10~3 Y2 } "NODE_NAME" } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 280 664 840 296 "Y2" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.750 ns ( 35.49 % ) " "Info: Total cell delay = 4.750 ns ( 35.49 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.633 ns ( 64.51 % ) " "Info: Total interconnect delay = 8.633 ns ( 64.51 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "13.383 ns" { I2 inst10~3 Y2 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "13.383 ns" { I2 {} I2~combout {} inst10~3 {} Y2 {} } { 0.000ns 0.000ns 5.786ns 2.847ns } { 0.000ns 0.995ns 0.499ns 3.256ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 09:13:08 2022 " "Info: Processing ended: Mon Mar 07 09:13:08 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.atm b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.atm index a62601d..120c51a 100644 Binary files a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.atm and b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.atm differ diff --git a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.hdbx b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.hdbx index 71a9612..815ddb3 100644 Binary files a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.hdbx and b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.hdbx differ diff --git a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.rcf b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.rcf index 9615120..7ee905b 100644 Binary files a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.rcf and b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.rcf differ diff --git a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.atm b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.atm index 150c3be..e564434 100644 Binary files a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.atm and b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.atm differ diff --git a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.hdbx b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.hdbx index 7484251..57e6d02 100644 Binary files a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.hdbx and b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.hdbx differ diff --git a/README.md b/README.md index 46dfc5c..462bc05 100644 --- a/README.md +++ b/README.md @@ -2,6 +2,10 @@ 计组课设。 +``` +板上实际元件: 电路虚拟元件 +``` + ### adder_8b 8位加法计算器。 @@ -43,6 +47,11 @@ LR0~LR7: Q0~Q7 3-8译码器。 +``` +K0~K2: I0~I2 +LR0~LR7: Y0~Y7 +``` + ### triple_selector_8b 8位数据选择器（三选一）。