From 65d1ef1509bf67b2070eb08c84d394ab697d827a Mon Sep 17 00:00:00 2001 From: wzhqwq Date: Thu, 17 Mar 2022 16:34:02 +0800 Subject: [PATCH] =?UTF-8?q?=E5=AE=8C=E6=88=90=E6=96=B0=E7=9A=84ALU?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- ALU_3_in_1/ALU_3_in_1.bdf | 1554 ++++++++++++++++++++ ALU_3_in_1/ALU_3_in_1.bsf | 225 +++ ALU_3_in_1/ALU_3_in_1.qpf | 30 + ALU_3_in_1/ALU_3_in_1.qsf | 53 + ALU_3_in_1/ALU_parallel_8b.bdf | 2111 +++++++++++++++++++++++++++ ALU_3_in_1/ALU_parallel_8b.bsf | 246 ++++ ALU_3_in_1/register_8b.bdf | 1004 +++++++++++++ ALU_3_in_1/register_8b.bsf | 155 ++ ALU_parallel_8b/ALU_parallel_8b.bsf | 254 ++-- 9 files changed, 5505 insertions(+), 127 deletions(-) create mode 100644 ALU_3_in_1/ALU_3_in_1.bdf create mode 100644 ALU_3_in_1/ALU_3_in_1.bsf create mode 100644 ALU_3_in_1/ALU_3_in_1.qpf create mode 100644 ALU_3_in_1/ALU_3_in_1.qsf create mode 100644 ALU_3_in_1/ALU_parallel_8b.bdf create mode 100644 ALU_3_in_1/ALU_parallel_8b.bsf create mode 100644 ALU_3_in_1/register_8b.bdf create mode 100644 ALU_3_in_1/register_8b.bsf diff --git a/ALU_3_in_1/ALU_3_in_1.bdf b/ALU_3_in_1/ALU_3_in_1.bdf new file mode 100644 index 0000000..878376d --- /dev/null +++ b/ALU_3_in_1/ALU_3_in_1.bdf @@ -0,0 +1,1554 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. 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information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +# Date created = 16:10:13 March 17, 2022 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "9.0" +DATE = "16:10:13 March 17, 2022" + +# Revisions + +PROJECT_REVISION = "ALU_3_in_1" diff --git a/ALU_3_in_1/ALU_3_in_1.qsf b/ALU_3_in_1/ALU_3_in_1.qsf new file mode 100644 index 0000000..a454524 --- /dev/null +++ b/ALU_3_in_1/ALU_3_in_1.qsf @@ -0,0 +1,53 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition +# Date created = 16:10:13 March 17, 2022 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# ALU_3_in_1_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone II" +set_global_assignment -name DEVICE EP2C8Q208C8 +set_global_assignment -name TOP_LEVEL_ENTITY ALU_3_in_1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:10:13 MARCH 17, 2022" +set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2" +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name BDF_FILE ALU_3_in_1.bdf +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" \ No newline at end of file diff --git a/ALU_3_in_1/ALU_parallel_8b.bdf b/ALU_3_in_1/ALU_parallel_8b.bdf new file mode 100644 index 0000000..9c6f09a --- /dev/null +++ b/ALU_3_in_1/ALU_parallel_8b.bdf @@ -0,0 +1,2111 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. 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input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. 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file mode 100644 index 0000000..938b8cc --- /dev/null +++ b/ALU_3_in_1/register_8b.bsf @@ -0,0 +1,155 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. 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