From 4f25cc83918658562a36d37c904671d74fe75451 Mon Sep 17 00:00:00 2001
From: juzeon <812312770@qq.com>
Date: Thu, 10 Mar 2022 21:06:06 +0800
Subject: [PATCH] add adder_suber_8b

---
 README.md                                 |   12 +-
 adder_suber_8b/adder_8b.bdf               | 2906 +++++++++++++++++++++
 adder_suber_8b/adder_8b.bsf               |  211 ++
 adder_suber_8b/adder_suber_8b.bdf         | 1236 +++++++++
 adder_suber_8b/adder_suber_8b.dpf         |   12 +
 adder_suber_8b/adder_suber_8b.qpf         |   30 +
 adder_suber_8b/adder_suber_8b.qsf         |   80 +
 shiftable_register/shiftable_register.qsf |    2 +-
 8 files changed, 4487 insertions(+), 2 deletions(-)
 create mode 100644 adder_suber_8b/adder_8b.bdf
 create mode 100644 adder_suber_8b/adder_8b.bsf
 create mode 100644 adder_suber_8b/adder_suber_8b.bdf
 create mode 100644 adder_suber_8b/adder_suber_8b.dpf
 create mode 100644 adder_suber_8b/adder_suber_8b.qpf
 create mode 100644 adder_suber_8b/adder_suber_8b.qsf

diff --git a/README.md b/README.md
index 16a48e8..470aabe 100644
--- a/README.md
+++ b/README.md
@@ -18,6 +18,16 @@ LR0~LR7: S0~S7
 LR8: CO
 ```
 
+### adder_suber_8b
+
+```
+K0~K7: A0~A7
+K8~K15: B0~B7
+K16: SUB
+LR0~LR7: S0~S7
+LR8: CO
+```
+
 ### double_selector_8b
 
 8位数据选择器（二选一）。
@@ -95,8 +105,8 @@ K9: DM
 K10: LM
 K11: R
 K12: L
-单脉冲: CK
 K13: CLR
+K14: CK
 LR0~LR7: Y0~Y7
 ```
 
diff --git a/adder_suber_8b/adder_8b.bdf b/adder_suber_8b/adder_8b.bdf
new file mode 100644
index 0000000..1a7ed04
--- /dev/null
+++ b/adder_suber_8b/adder_8b.bdf
@@ -0,0 +1,2906 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
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diff --git a/adder_suber_8b/adder_8b.bsf b/adder_suber_8b/adder_8b.bsf
new file mode 100644
index 0000000..bc579e4
--- /dev/null
+++ b/adder_suber_8b/adder_8b.bsf
@@ -0,0 +1,211 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 112 336)
+	(text "adder_8b" (rect 5 0 59 14)(font "Arial" (font_size 8)))
+	(text "inst" (rect 8 304 25 316)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "A7" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "A7" (rect 21 27 37 41)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "B7" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "B7" (rect 21 43 36 57)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "A6" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "A6" (rect 21 59 37 73)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "B6" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "B6" (rect 21 75 36 89)(font "Arial" (font_size 8)))
+		(line (pt 0 80)(pt 16 80)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "A5" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "A5" (rect 21 91 37 105)(font "Arial" (font_size 8)))
+		(line (pt 0 96)(pt 16 96)(line_width 1))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "B5" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "B5" (rect 21 107 36 121)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 16 112)(line_width 1))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "A4" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "A4" (rect 21 123 37 137)(font "Arial" (font_size 8)))
+		(line (pt 0 128)(pt 16 128)(line_width 1))
+	)
+	(port
+		(pt 0 144)
+		(input)
+		(text "B4" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "B4" (rect 21 139 36 153)(font "Arial" (font_size 8)))
+		(line (pt 0 144)(pt 16 144)(line_width 1))
+	)
+	(port
+		(pt 0 160)
+		(input)
+		(text "A3" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "A3" (rect 21 155 37 169)(font "Arial" (font_size 8)))
+		(line (pt 0 160)(pt 16 160)(line_width 1))
+	)
+	(port
+		(pt 0 176)
+		(input)
+		(text "B3" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "B3" (rect 21 171 36 185)(font "Arial" (font_size 8)))
+		(line (pt 0 176)(pt 16 176)(line_width 1))
+	)
+	(port
+		(pt 0 192)
+		(input)
+		(text "A2" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "A2" (rect 21 187 37 201)(font "Arial" (font_size 8)))
+		(line (pt 0 192)(pt 16 192)(line_width 1))
+	)
+	(port
+		(pt 0 208)
+		(input)
+		(text "B2" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "B2" (rect 21 203 36 217)(font "Arial" (font_size 8)))
+		(line (pt 0 208)(pt 16 208)(line_width 1))
+	)
+	(port
+		(pt 0 224)
+		(input)
+		(text "A1" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "A1" (rect 21 219 37 233)(font "Arial" (font_size 8)))
+		(line (pt 0 224)(pt 16 224)(line_width 1))
+	)
+	(port
+		(pt 0 240)
+		(input)
+		(text "B1" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "B1" (rect 21 235 36 249)(font "Arial" (font_size 8)))
+		(line (pt 0 240)(pt 16 240)(line_width 1))
+	)
+	(port
+		(pt 0 256)
+		(input)
+		(text "A0" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "A0" (rect 21 251 37 265)(font "Arial" (font_size 8)))
+		(line (pt 0 256)(pt 16 256)(line_width 1))
+	)
+	(port
+		(pt 0 272)
+		(input)
+		(text "B0" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "B0" (rect 21 267 36 281)(font "Arial" (font_size 8)))
+		(line (pt 0 272)(pt 16 272)(line_width 1))
+	)
+	(port
+		(pt 0 288)
+		(input)
+		(text "CI" (rect 0 0 10 14)(font "Arial" (font_size 8)))
+		(text "CI" (rect 21 283 31 297)(font "Arial" (font_size 8)))
+		(line (pt 0 288)(pt 16 288)(line_width 1))
+	)
+	(port
+		(pt 96 32)
+		(output)
+		(text "CO" (rect 0 0 17 14)(font "Arial" (font_size 8)))
+		(text "CO" (rect 58 27 75 41)(font "Arial" (font_size 8)))
+		(line (pt 96 32)(pt 80 32)(line_width 1))
+	)
+	(port
+		(pt 96 48)
+		(output)
+		(text "S7" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "S7" (rect 60 43 75 57)(font "Arial" (font_size 8)))
+		(line (pt 96 48)(pt 80 48)(line_width 1))
+	)
+	(port
+		(pt 96 64)
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+	)
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+		(text "S5" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "S5" (rect 60 75 75 89)(font "Arial" (font_size 8)))
+		(line (pt 96 80)(pt 80 80)(line_width 1))
+	)
+	(port
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+		(text "S4" (rect 60 91 75 105)(font "Arial" (font_size 8)))
+		(line (pt 96 96)(pt 80 96)(line_width 1))
+	)
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+		(text "S3" (rect 60 107 75 121)(font "Arial" (font_size 8)))
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+		(text "S2" (rect 60 123 75 137)(font "Arial" (font_size 8)))
+		(line (pt 96 128)(pt 80 128)(line_width 1))
+	)
+	(port
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+		(text "S1" (rect 60 139 75 153)(font "Arial" (font_size 8)))
+		(line (pt 96 144)(pt 80 144)(line_width 1))
+	)
+	(port
+		(pt 96 160)
+		(output)
+		(text "S0" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "S0" (rect 60 155 75 169)(font "Arial" (font_size 8)))
+		(line (pt 96 160)(pt 80 160)(line_width 1))
+	)
+	(drawing
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+	)
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diff --git a/adder_suber_8b/adder_suber_8b.bdf b/adder_suber_8b/adder_suber_8b.bdf
new file mode 100644
index 0000000..4e111dc
--- /dev/null
+++ b/adder_suber_8b/adder_suber_8b.bdf
@@ -0,0 +1,1236 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+//#pragma file_not_in_maxplusii_format
+(header "graphic" (version "1.3"))
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+	(text "A1" (rect 5 0 17 12)(font "Arial" ))
+	(pt 168 8)
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+		(line (pt 92 4)(pt 117 4)(line_width 1))
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+		(line (pt 92 12)(pt 92 4)(line_width 1))
+		(line (pt 117 4)(pt 121 8)(line_width 1))
+		(line (pt 117 12)(pt 121 8)(line_width 1))
+	)
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+)
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+		(line (pt 117 12)(pt 121 8)(line_width 1))
+	)
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+)
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+)
+(connector
+	(pt 352 344)
+	(pt 288 344)
+)
+(connector
+	(pt 352 408)
+	(pt 288 408)
+)
+(connector
+	(pt 600 448)
+	(pt 288 448)
+)
+(connector
+	(pt 456 416)
+	(pt 456 384)
+)
+(connector
+	(pt 456 384)
+	(pt 288 384)
+)
+(connector
+	(pt 472 320)
+	(pt 288 320)
+)
+(connector
+	(pt 488 256)
+	(pt 288 256)
+)
+(connector
+	(pt 504 192)
+	(pt 288 192)
+)
+(connector
+	(pt 520 128)
+	(pt 288 128)
+)
+(connector
+	(pt 536 64)
+	(pt 288 64)
+)
+(connector
+	(pt 552 0)
+	(pt 288 0)
+)
+(connector
+	(pt 472 384)
+	(pt 472 320)
+)
+(connector
+	(pt 488 352)
+	(pt 488 256)
+)
+(connector
+	(pt 504 320)
+	(pt 504 192)
+)
+(connector
+	(pt 520 288)
+	(pt 520 128)
+)
+(connector
+	(pt 536 256)
+	(pt 536 64)
+)
+(connector
+	(pt 552 224)
+	(pt 552 0)
+)
+(connector
+	(pt 352 -24)
+	(pt 320 -24)
+)
+(connector
+	(pt 320 504)
+	(pt 288 504)
+)
+(connector
+	(pt 352 232)
+	(pt 320 232)
+)
+(connector
+	(pt 352 296)
+	(pt 320 296)
+)
+(connector
+	(pt 352 360)
+	(pt 320 360)
+)
+(connector
+	(pt 352 424)
+	(pt 320 424)
+)
+(connector
+	(pt 600 464)
+	(pt 320 464)
+)
+(connector
+	(pt 320 296)
+	(pt 320 360)
+)
+(connector
+	(pt 320 232)
+	(pt 320 296)
+)
+(connector
+	(pt 320 168)
+	(pt 320 232)
+)
+(connector
+	(pt 320 -24)
+	(pt 320 40)
+)
+(connector
+	(pt 320 40)
+	(pt 320 104)
+)
+(connector
+	(pt 320 104)
+	(pt 320 168)
+)
+(connector
+	(pt 320 360)
+	(pt 320 424)
+)
+(connector
+	(pt 320 424)
+	(pt 320 464)
+)
+(connector
+	(pt 320 464)
+	(pt 320 504)
+)
+(junction (pt 320 360))
+(junction (pt 320 424))
+(junction (pt 320 296))
+(junction (pt 320 232))
+(junction (pt 320 168))
+(junction (pt 320 104))
+(junction (pt 320 40))
+(junction (pt 320 464))
diff --git a/adder_suber_8b/adder_suber_8b.dpf b/adder_suber_8b/adder_suber_8b.dpf
new file mode 100644
index 0000000..abe19d9
--- /dev/null
+++ b/adder_suber_8b/adder_suber_8b.dpf
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<pin_planner>
+	<pin_info>
+	</pin_info>
+	<buses>
+	</buses>
+	<group_file_association>
+	</group_file_association>
+	<pin_planner_file_specifies>
+	</pin_planner_file_specifies>
+</pin_planner>
diff --git a/adder_suber_8b/adder_suber_8b.qpf b/adder_suber_8b/adder_suber_8b.qpf
new file mode 100644
index 0000000..9c909b3
--- /dev/null
+++ b/adder_suber_8b/adder_suber_8b.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+# Date created = 20:42:00  March 10, 2022
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "9.0"
+DATE = "20:42:00  March 10, 2022"
+
+# Revisions
+
+PROJECT_REVISION = "adder_suber_8b"
diff --git a/adder_suber_8b/adder_suber_8b.qsf b/adder_suber_8b/adder_suber_8b.qsf
new file mode 100644
index 0000000..2dbf0a7
--- /dev/null
+++ b/adder_suber_8b/adder_suber_8b.qsf
@@ -0,0 +1,80 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+# Date created = 20:42:00  March 10, 2022
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		adder_suber_8b_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone II"
+set_global_assignment -name DEVICE EP2C8Q208C8
+set_global_assignment -name TOP_LEVEL_ENTITY adder_suber_8b
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:42:00  MARCH 10, 2022"
+set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2"
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name BDF_FILE adder_suber_8b.bdf
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_location_assignment PIN_77 -to A0
+set_location_assignment PIN_80 -to A1
+set_location_assignment PIN_81 -to A2
+set_location_assignment PIN_82 -to A3
+set_location_assignment PIN_84 -to A4
+set_location_assignment PIN_86 -to A5
+set_location_assignment PIN_87 -to A6
+set_location_assignment PIN_88 -to A7
+set_location_assignment PIN_67 -to B0
+set_location_assignment PIN_68 -to B1
+set_location_assignment PIN_69 -to B2
+set_location_assignment PIN_70 -to B3
+set_location_assignment PIN_72 -to B4
+set_location_assignment PIN_74 -to B5
+set_location_assignment PIN_75 -to B6
+set_location_assignment PIN_76 -to B7
+set_location_assignment PIN_23 -to SUB
+set_location_assignment PIN_142 -to S0
+set_location_assignment PIN_143 -to S1
+set_location_assignment PIN_144 -to S2
+set_location_assignment PIN_145 -to S3
+set_location_assignment PIN_146 -to S4
+set_location_assignment PIN_147 -to S5
+set_location_assignment PIN_149 -to S6
+set_location_assignment PIN_150 -to S7
+set_location_assignment PIN_151 -to CO
\ No newline at end of file
diff --git a/shiftable_register/shiftable_register.qsf b/shiftable_register/shiftable_register.qsf
index f44bfcb..0fcec57 100644
--- a/shiftable_register/shiftable_register.qsf
+++ b/shiftable_register/shiftable_register.qsf
@@ -62,7 +62,7 @@ set_location_assignment PIN_84 -to D4
 set_location_assignment PIN_86 -to D5
 set_location_assignment PIN_87 -to D6
 set_location_assignment PIN_88 -to D7
-set_location_assignment PIN_132 -to CK
+set_location_assignment PIN_75 -to CK
 set_location_assignment PIN_74 -to CLR
 set_location_assignment PIN_68 -to DM
 set_location_assignment PIN_72 -to L