untrack all ignored files
此提交包含在：
@@ -1,129 +0,0 @@
|
||||
Assembler report for adder_8b
|
||||
Mon Mar 07 11:28:58 2022
|
||||
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
; Table of Contents ;
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. Assembler Summary
|
||||
3. Assembler Settings
|
||||
4. Assembler Generated Files
|
||||
5. Assembler Device Options: D:/projects/quartus/adder_8b/adder_8b.sof
|
||||
6. Assembler Device Options: D:/projects/quartus/adder_8b/adder_8b.pof
|
||||
7. Assembler Messages
|
||||
|
||||
|
||||
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 1991-2009 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
+---------------------------------------------------------------+
|
||||
; Assembler Summary ;
|
||||
+-----------------------+---------------------------------------+
|
||||
; Assembler Status ; Successful - Mon Mar 07 11:28:58 2022 ;
|
||||
; Revision Name ; adder_8b ;
|
||||
; Top-level Entity Name ; adder_8b ;
|
||||
; Family ; Cyclone II ;
|
||||
; Device ; EP2C8Q208C8 ;
|
||||
+-----------------------+---------------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------+
|
||||
; Assembler Settings ;
|
||||
+-----------------------------------------------------------------------------+----------+---------------+
|
||||
; Option ; Setting ; Default Value ;
|
||||
+-----------------------------------------------------------------------------+----------+---------------+
|
||||
; Use smart compilation ; Off ; Off ;
|
||||
; Generate compressed bitstreams ; On ; On ;
|
||||
; Compression mode ; Off ; Off ;
|
||||
; Clock source for configuration device ; Internal ; Internal ;
|
||||
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
|
||||
; Divide clock frequency by ; 1 ; 1 ;
|
||||
; Auto user code ; Off ; Off ;
|
||||
; Use configuration device ; On ; On ;
|
||||
; Configuration device ; Auto ; Auto ;
|
||||
; Configuration device auto user code ; Off ; Off ;
|
||||
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
|
||||
; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
|
||||
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
|
||||
; Hexadecimal Output File start address ; 0 ; 0 ;
|
||||
; Hexadecimal Output File count direction ; Up ; Up ;
|
||||
; Release clears before tri-states ; Off ; Off ;
|
||||
; Auto-restart configuration after error ; On ; On ;
|
||||
; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ;
|
||||
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
|
||||
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
|
||||
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
|
||||
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
|
||||
+-----------------------------------------------------------------------------+----------+---------------+
|
||||
|
||||
|
||||
+-------------------------------------------+
|
||||
; Assembler Generated Files ;
|
||||
+-------------------------------------------+
|
||||
; File Name ;
|
||||
+-------------------------------------------+
|
||||
; D:/projects/quartus/adder_8b/adder_8b.sof ;
|
||||
; D:/projects/quartus/adder_8b/adder_8b.pof ;
|
||||
+-------------------------------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------+
|
||||
; Assembler Device Options: D:/projects/quartus/adder_8b/adder_8b.sof ;
|
||||
+----------------+----------------------------------------------------+
|
||||
; Option ; Setting ;
|
||||
+----------------+----------------------------------------------------+
|
||||
; Device ; EP2C8Q208C8 ;
|
||||
; JTAG usercode ; 0xFFFFFFFF ;
|
||||
; Checksum ; 0x000C3C8E ;
|
||||
+----------------+----------------------------------------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------+
|
||||
; Assembler Device Options: D:/projects/quartus/adder_8b/adder_8b.pof ;
|
||||
+--------------------+------------------------------------------------+
|
||||
; Option ; Setting ;
|
||||
+--------------------+------------------------------------------------+
|
||||
; Device ; EPCS4 ;
|
||||
; JTAG usercode ; 0x00000000 ;
|
||||
; Checksum ; 0x06EFBA32 ;
|
||||
; Compression Ratio ; 3 ;
|
||||
+--------------------+------------------------------------------------+
|
||||
|
||||
|
||||
+--------------------+
|
||||
; Assembler Messages ;
|
||||
+--------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II Assembler
|
||||
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
|
||||
Info: Processing started: Mon Mar 07 11:28:58 2022
|
||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b
|
||||
Info: Writing out detailed assembly data for power analysis
|
||||
Info: Assembler is generating device programming files
|
||||
Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled
|
||||
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 242 megabytes
|
||||
Info: Processing ended: Mon Mar 07 11:28:58 2022
|
||||
Info: Elapsed time: 00:00:00
|
||||
Info: Total CPU time (on all processors): 00:00:00
|
||||
|
||||
|
||||
@@ -1 +0,0 @@
|
||||
Mon Mar 07 11:29:00 2022
|
||||
檔案差異因為檔案過大而無法顯示
載入差異
@@ -1,6 +0,0 @@
|
||||
Extra Info: Performing register packing on registers with non-logic cell location assignments
|
||||
Extra Info: Completed register packing on registers with non-logic cell location assignments
|
||||
Extra Info: Started Fast Input/Output/OE register processing
|
||||
Extra Info: Finished Fast Input/Output/OE register processing
|
||||
Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
|
||||
Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
|
||||
@@ -1,16 +0,0 @@
|
||||
Fitter Status : Successful - Mon Mar 07 11:28:57 2022
|
||||
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
|
||||
Revision Name : adder_8b
|
||||
Top-level Entity Name : adder_8b
|
||||
Family : Cyclone II
|
||||
Device : EP2C8Q208C8
|
||||
Timing Models : Final
|
||||
Total logic elements : 21 / 8,256 ( < 1 % )
|
||||
Total combinational functions : 21 / 8,256 ( < 1 % )
|
||||
Dedicated logic registers : 0 / 8,256 ( 0 % )
|
||||
Total registers : 0
|
||||
Total pins : 26 / 138 ( 19 % )
|
||||
Total virtual pins : 0
|
||||
Total memory bits : 0 / 165,888 ( 0 % )
|
||||
Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % )
|
||||
Total PLLs : 0 / 2 ( 0 % )
|
||||
@@ -1,121 +0,0 @@
|
||||
Flow report for adder_8b
|
||||
Mon Mar 07 11:28:59 2022
|
||||
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
; Table of Contents ;
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. Flow Summary
|
||||
3. Flow Settings
|
||||
4. Flow Non-Default Global Settings
|
||||
5. Flow Elapsed Time
|
||||
6. Flow OS Summary
|
||||
7. Flow Log
|
||||
|
||||
|
||||
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 1991-2009 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+------------------------------------+----------------------------------------------+
|
||||
; Flow Status ; Successful - Mon Mar 07 11:28:59 2022 ;
|
||||
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
|
||||
; Revision Name ; adder_8b ;
|
||||
; Top-level Entity Name ; adder_8b ;
|
||||
; Family ; Cyclone II ;
|
||||
; Device ; EP2C8Q208C8 ;
|
||||
; Timing Models ; Final ;
|
||||
; Met timing requirements ; Yes ;
|
||||
; Total logic elements ; 21 / 8,256 ( < 1 % ) ;
|
||||
; Total combinational functions ; 21 / 8,256 ( < 1 % ) ;
|
||||
; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ;
|
||||
; Total registers ; 0 ;
|
||||
; Total pins ; 26 / 138 ( 19 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; Total memory bits ; 0 / 165,888 ( 0 % ) ;
|
||||
; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
|
||||
; Total PLLs ; 0 / 2 ( 0 % ) ;
|
||||
+------------------------------------+----------------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------+
|
||||
; Flow Settings ;
|
||||
+-------------------+---------------------+
|
||||
; Option ; Setting ;
|
||||
+-------------------+---------------------+
|
||||
; Start date & time ; 03/07/2022 11:28:55 ;
|
||||
; Main task ; Compilation ;
|
||||
; Revision Name ; adder_8b ;
|
||||
+-------------------+---------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Flow Non-Default Global Settings ;
|
||||
+------------------------------------+-------------------------------------------+---------------+-------------+----------------+
|
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||
+------------------------------------+-------------------------------------------+---------------+-------------+----------------+
|
||||
; COMPILER_SIGNATURE_ID ; 220283517943889.164662373514744 ; -- ; -- ; -- ;
|
||||
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||||
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
||||
; MISC_FILE ; D:/projects/quartus/adder_8b/adder_8b.dpf ; -- ; -- ; -- ;
|
||||
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
|
||||
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
|
||||
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
|
||||
+------------------------------------+-------------------------------------------+---------------+-------------+----------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------------------------------+
|
||||
; Flow Elapsed Time ;
|
||||
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 246 MB ; 00:00:00 ;
|
||||
; Fitter ; 00:00:01 ; 1.0 ; 305 MB ; 00:00:01 ;
|
||||
; Assembler ; 00:00:00 ; 1.0 ; 242 MB ; 00:00:00 ;
|
||||
; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 199 MB ; 00:00:00 ;
|
||||
; Total ; 00:00:02 ; -- ; -- ; 00:00:01 ;
|
||||
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------+
|
||||
; Flow OS Summary ;
|
||||
+-------------------------+------------------+---------------+------------+----------------+
|
||||
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
|
||||
+-------------------------+------------------+---------------+------------+----------------+
|
||||
; Analysis & Synthesis ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
|
||||
; Fitter ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
|
||||
; Assembler ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
|
||||
; Classic Timing Analyzer ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
|
||||
+-------------------------+------------------+---------------+------------+----------------+
|
||||
|
||||
|
||||
------------
|
||||
; Flow Log ;
|
||||
------------
|
||||
quartus_map --read_settings_files=on --write_settings_files=off adder_8b -c adder_8b
|
||||
quartus_fit --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b
|
||||
quartus_asm --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b
|
||||
quartus_tan --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b --timing_analysis_only
|
||||
|
||||
|
||||
|
||||
@@ -1,240 +0,0 @@
|
||||
Analysis & Synthesis report for adder_8b
|
||||
Mon Mar 07 11:28:55 2022
|
||||
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
; Table of Contents ;
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. Analysis & Synthesis Summary
|
||||
3. Analysis & Synthesis Settings
|
||||
4. Analysis & Synthesis Source Files Read
|
||||
5. Analysis & Synthesis Resource Usage Summary
|
||||
6. Analysis & Synthesis Resource Utilization by Entity
|
||||
7. General Register Statistics
|
||||
8. Analysis & Synthesis Messages
|
||||
|
||||
|
||||
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 1991-2009 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+------------------------------------+----------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Mon Mar 07 11:28:55 2022 ;
|
||||
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
|
||||
; Revision Name ; adder_8b ;
|
||||
; Top-level Entity Name ; adder_8b ;
|
||||
; Family ; Cyclone II ;
|
||||
; Total logic elements ; 21 ;
|
||||
; Total combinational functions ; 21 ;
|
||||
; Dedicated logic registers ; 0 ;
|
||||
; Total registers ; 0 ;
|
||||
; Total pins ; 26 ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; Total memory bits ; 0 ;
|
||||
; Embedded Multiplier 9-bit elements ; 0 ;
|
||||
; Total PLLs ; 0 ;
|
||||
+------------------------------------+----------------------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Settings ;
|
||||
+--------------------------------------------------------------+--------------------+--------------------+
|
||||
; Option ; Setting ; Default Value ;
|
||||
+--------------------------------------------------------------+--------------------+--------------------+
|
||||
; Device ; EP2C8Q208C8 ; ;
|
||||
; Top-level entity name ; adder_8b ; adder_8b ;
|
||||
; Family name ; Cyclone II ; Stratix II ;
|
||||
; Use Generated Physical Constraints File ; Off ; ;
|
||||
; Use smart compilation ; Off ; Off ;
|
||||
; Restructure Multiplexers ; Auto ; Auto ;
|
||||
; Create Debugging Nodes for IP Cores ; Off ; Off ;
|
||||
; Preserve fewer node names ; On ; On ;
|
||||
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
|
||||
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
|
||||
; VHDL Version ; VHDL93 ; VHDL93 ;
|
||||
; State Machine Processing ; Auto ; Auto ;
|
||||
; Safe State Machine ; Off ; Off ;
|
||||
; Extract Verilog State Machines ; On ; On ;
|
||||
; Extract VHDL State Machines ; On ; On ;
|
||||
; Ignore Verilog initial constructs ; Off ; Off ;
|
||||
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
|
||||
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
|
||||
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
|
||||
; Parallel Synthesis ; Off ; Off ;
|
||||
; DSP Block Balancing ; Auto ; Auto ;
|
||||
; NOT Gate Push-Back ; On ; On ;
|
||||
; Power-Up Don't Care ; On ; On ;
|
||||
; Remove Redundant Logic Cells ; Off ; Off ;
|
||||
; Remove Duplicate Registers ; On ; On ;
|
||||
; Ignore CARRY Buffers ; Off ; Off ;
|
||||
; Ignore CASCADE Buffers ; Off ; Off ;
|
||||
; Ignore GLOBAL Buffers ; Off ; Off ;
|
||||
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
|
||||
; Ignore LCELL Buffers ; Off ; Off ;
|
||||
; Ignore SOFT Buffers ; On ; On ;
|
||||
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
|
||||
; Optimization Technique ; Balanced ; Balanced ;
|
||||
; Carry Chain Length ; 70 ; 70 ;
|
||||
; Auto Carry Chains ; On ; On ;
|
||||
; Auto Open-Drain Pins ; On ; On ;
|
||||
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
|
||||
; Auto ROM Replacement ; On ; On ;
|
||||
; Auto RAM Replacement ; On ; On ;
|
||||
; Auto Shift Register Replacement ; Auto ; Auto ;
|
||||
; Auto Clock Enable Replacement ; On ; On ;
|
||||
; Strict RAM Replacement ; Off ; Off ;
|
||||
; Allow Synchronous Control Signals ; On ; On ;
|
||||
; Force Use of Synchronous Clear Signals ; Off ; Off ;
|
||||
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
|
||||
; Auto Resource Sharing ; Off ; Off ;
|
||||
; Allow Any RAM Size For Recognition ; Off ; Off ;
|
||||
; Allow Any ROM Size For Recognition ; Off ; Off ;
|
||||
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
|
||||
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
|
||||
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
|
||||
; Timing-Driven Synthesis ; Off ; Off ;
|
||||
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
|
||||
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
|
||||
; Synchronization Register Chain Length ; 2 ; 2 ;
|
||||
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
|
||||
; HDL message level ; Level2 ; Level2 ;
|
||||
; Suppress Register Optimization Related Messages ; Off ; Off ;
|
||||
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
|
||||
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
|
||||
; Clock MUX Protection ; On ; On ;
|
||||
; Auto Gated Clock Conversion ; Off ; Off ;
|
||||
; Block Design Naming ; Auto ; Auto ;
|
||||
; SDC constraint protection ; Off ; Off ;
|
||||
; Synthesis Effort ; Auto ; Auto ;
|
||||
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
|
||||
; Analysis & Synthesis Message Level ; Medium ; Medium ;
|
||||
+--------------------------------------------------------------+--------------------+--------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Source Files Read ;
|
||||
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------+
|
||||
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
|
||||
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------+
|
||||
; adder_8b.bdf ; yes ; User Block Diagram/Schematic File ; D:/projects/quartus/adder_8b/adder_8b.bdf ;
|
||||
; 7400.bdf ; yes ; Megafunction ; d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf ;
|
||||
; 7486.bdf ; yes ; Megafunction ; d:/altera/90sp2/quartus/libraries/others/maxplus2/7486.bdf ;
|
||||
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------+
|
||||
; Analysis & Synthesis Resource Usage Summary ;
|
||||
+---------------------------------------------+----------------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+----------------+
|
||||
; Estimated Total logic elements ; 21 ;
|
||||
; ; ;
|
||||
; Total combinational functions ; 21 ;
|
||||
; Logic element usage by number of LUT inputs ; ;
|
||||
; -- 4 input functions ; 9 ;
|
||||
; -- 3 input functions ; 9 ;
|
||||
; -- <=2 input functions ; 3 ;
|
||||
; ; ;
|
||||
; Logic elements by mode ; ;
|
||||
; -- normal mode ; 21 ;
|
||||
; -- arithmetic mode ; 0 ;
|
||||
; ; ;
|
||||
; Total registers ; 0 ;
|
||||
; -- Dedicated logic registers ; 0 ;
|
||||
; -- I/O registers ; 0 ;
|
||||
; ; ;
|
||||
; I/O pins ; 26 ;
|
||||
; Maximum fan-out node ; 7400:inst8|4~0 ;
|
||||
; Maximum fan-out ; 4 ;
|
||||
; Total fan-out ; 78 ;
|
||||
; Average fan-out ; 1.66 ;
|
||||
+---------------------------------------------+----------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Resource Utilization by Entity ;
|
||||
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------+--------------+
|
||||
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
|
||||
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------+--------------+
|
||||
; |adder_8b ; 21 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 26 ; 0 ; |adder_8b ; work ;
|
||||
; |7400:inst13| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7400:inst13 ; work ;
|
||||
; |7400:inst18| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7400:inst18 ; work ;
|
||||
; |7400:inst23| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7400:inst23 ; work ;
|
||||
; |7400:inst28| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7400:inst28 ; work ;
|
||||
; |7400:inst33| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7400:inst33 ; work ;
|
||||
; |7400:inst38| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7400:inst38 ; work ;
|
||||
; |7400:inst3| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7400:inst3 ; work ;
|
||||
; |7400:inst8| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7400:inst8 ; work ;
|
||||
; |7486:inst10| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7486:inst10 ; work ;
|
||||
; |7486:inst15| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7486:inst15 ; work ;
|
||||
; |7486:inst20| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7486:inst20 ; work ;
|
||||
; |7486:inst25| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7486:inst25 ; work ;
|
||||
; |7486:inst30| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7486:inst30 ; work ;
|
||||
; |7486:inst35| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7486:inst35 ; work ;
|
||||
; |7486:inst40| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7486:inst40 ; work ;
|
||||
; |7486:inst5| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7486:inst5 ; work ;
|
||||
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------+--------------+
|
||||
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
||||
|
||||
|
||||
+------------------------------------------------------+
|
||||
; General Register Statistics ;
|
||||
+----------------------------------------------+-------+
|
||||
; Statistic ; Value ;
|
||||
+----------------------------------------------+-------+
|
||||
; Total registers ; 0 ;
|
||||
; Number of registers using Synchronous Clear ; 0 ;
|
||||
; Number of registers using Synchronous Load ; 0 ;
|
||||
; Number of registers using Asynchronous Clear ; 0 ;
|
||||
; Number of registers using Asynchronous Load ; 0 ;
|
||||
; Number of registers using Clock Enable ; 0 ;
|
||||
; Number of registers using Preset ; 0 ;
|
||||
+----------------------------------------------+-------+
|
||||
|
||||
|
||||
+-------------------------------+
|
||||
; Analysis & Synthesis Messages ;
|
||||
+-------------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II Analysis & Synthesis
|
||||
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
|
||||
Info: Processing started: Mon Mar 07 11:28:54 2022
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adder_8b -c adder_8b
|
||||
Info: Found 1 design units, including 1 entities, in source file adder_8b.bdf
|
||||
Info: Found entity 1: adder_8b
|
||||
Info: Elaborating entity "adder_8b" for the top level hierarchy
|
||||
Info: Elaborating entity "7400" for hierarchy "7400:inst38"
|
||||
Info: Elaborated megafunction instantiation "7400:inst38"
|
||||
Info: Elaborating entity "7486" for hierarchy "7486:inst"
|
||||
Info: Elaborated megafunction instantiation "7486:inst"
|
||||
Info: Implemented 47 device resources after synthesis - the final resource count might be different
|
||||
Info: Implemented 17 input pins
|
||||
Info: Implemented 9 output pins
|
||||
Info: Implemented 21 logic cells
|
||||
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 250 megabytes
|
||||
Info: Processing ended: Mon Mar 07 11:28:55 2022
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
|
||||
@@ -1,14 +0,0 @@
|
||||
Analysis & Synthesis Status : Successful - Mon Mar 07 11:28:55 2022
|
||||
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
|
||||
Revision Name : adder_8b
|
||||
Top-level Entity Name : adder_8b
|
||||
Family : Cyclone II
|
||||
Total logic elements : 21
|
||||
Total combinational functions : 21
|
||||
Dedicated logic registers : 0
|
||||
Total registers : 0
|
||||
Total pins : 26
|
||||
Total virtual pins : 0
|
||||
Total memory bits : 0
|
||||
Embedded Multiplier 9-bit elements : 0
|
||||
Total PLLs : 0
|
||||
@@ -1,278 +0,0 @@
|
||||
-- Copyright (C) 1991-2009 Altera Corporation
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, Altera MegaCore Function License
|
||||
-- Agreement, or other applicable license agreement, including,
|
||||
-- without limitation, that your use is for the sole purpose of
|
||||
-- programming logic devices manufactured by Altera and sold by
|
||||
-- Altera or its authorized distributors. Please refer to the
|
||||
-- applicable agreement for further details.
|
||||
--
|
||||
-- This is a Quartus II output file. It is for reporting purposes only, and is
|
||||
-- not intended for use as a Quartus II input file. This file cannot be used
|
||||
-- to make Quartus II pin assignments - for instructions on how to make pin
|
||||
-- assignments, please see Quartus II help.
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
-- NC : No Connect. This pin has no internal connection to the device.
|
||||
-- DNU : Do Not Use. This pin MUST NOT be connected.
|
||||
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
|
||||
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
|
||||
-- of its bank.
|
||||
-- Bank 1: 3.3V
|
||||
-- Bank 2: 3.3V
|
||||
-- Bank 3: 3.3V
|
||||
-- Bank 4: 3.3V
|
||||
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
|
||||
-- It can also be used to report unused dedicated pins. The connection
|
||||
-- on the board for unused dedicated pins depends on whether this will
|
||||
-- be used in a future design. One example is device migration. When
|
||||
-- using device migration, refer to the device pin-tables. If it is a
|
||||
-- GND pin in the pin table or if it will not be used in a future design
|
||||
-- for another purpose the it MUST be connected to GND. If it is an unused
|
||||
-- dedicated pin, then it can be connected to a valid signal on the board
|
||||
-- (low, high, or toggling) if that signal is required for a different
|
||||
-- revision of the design.
|
||||
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
|
||||
-- This pin should be connected to GND. It may also be connected to a
|
||||
-- valid signal on the board (low, high, or toggling) if that signal
|
||||
-- is required for a different revision of the design.
|
||||
-- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17),
|
||||
-- connect each pin marked GND* either individually through a 10k Ohm resistor
|
||||
-- to GND or tie all pins together and connect through a single 10k Ohm resistor
|
||||
-- to GND.
|
||||
-- For non-transceiver I/O banks, connect each pin marked GND* directly to GND
|
||||
-- or leave it unconnected.
|
||||
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
|
||||
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
|
||||
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
|
||||
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
|
||||
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
-- Pin directions (input, output or bidir) are based on device operating in user mode.
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
|
||||
CHIP "adder_8b" ASSIGNED TO AN: EP2C8Q208C8
|
||||
|
||||
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
|
||||
-------------------------------------------------------------------------------------------------------------
|
||||
~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVTTL : : 1 : N
|
||||
~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVTTL : : 1 : N
|
||||
RESERVED_INPUT : 3 : : : : 1 :
|
||||
RESERVED_INPUT : 4 : : : : 1 :
|
||||
RESERVED_INPUT : 5 : : : : 1 :
|
||||
RESERVED_INPUT : 6 : : : : 1 :
|
||||
VCCIO1 : 7 : power : : 3.3V : 1 :
|
||||
RESERVED_INPUT : 8 : : : : 1 :
|
||||
GND : 9 : gnd : : : :
|
||||
RESERVED_INPUT : 10 : : : : 1 :
|
||||
RESERVED_INPUT : 11 : : : : 1 :
|
||||
RESERVED_INPUT : 12 : : : : 1 :
|
||||
RESERVED_INPUT : 13 : : : : 1 :
|
||||
RESERVED_INPUT : 14 : : : : 1 :
|
||||
RESERVED_INPUT : 15 : : : : 1 :
|
||||
TDO : 16 : output : : : 1 :
|
||||
TMS : 17 : input : : : 1 :
|
||||
TCK : 18 : input : : : 1 :
|
||||
TDI : 19 : input : : : 1 :
|
||||
DATA0 : 20 : input : : : 1 :
|
||||
DCLK : 21 : : : : 1 :
|
||||
nCE : 22 : : : : 1 :
|
||||
CI : 23 : input : 3.3-V LVTTL : : 1 : Y
|
||||
GND+ : 24 : : : : 1 :
|
||||
GND : 25 : gnd : : : :
|
||||
nCONFIG : 26 : : : : 1 :
|
||||
GND+ : 27 : : : : 1 :
|
||||
GND+ : 28 : : : : 1 :
|
||||
VCCIO1 : 29 : power : : 3.3V : 1 :
|
||||
RESERVED_INPUT : 30 : : : : 1 :
|
||||
RESERVED_INPUT : 31 : : : : 1 :
|
||||
VCCINT : 32 : power : : 1.2V : :
|
||||
RESERVED_INPUT : 33 : : : : 1 :
|
||||
RESERVED_INPUT : 34 : : : : 1 :
|
||||
RESERVED_INPUT : 35 : : : : 1 :
|
||||
GND : 36 : gnd : : : :
|
||||
RESERVED_INPUT : 37 : : : : 1 :
|
||||
GND : 38 : gnd : : : :
|
||||
RESERVED_INPUT : 39 : : : : 1 :
|
||||
RESERVED_INPUT : 40 : : : : 1 :
|
||||
RESERVED_INPUT : 41 : : : : 1 :
|
||||
VCCIO1 : 42 : power : : 3.3V : 1 :
|
||||
RESERVED_INPUT : 43 : : : : 1 :
|
||||
RESERVED_INPUT : 44 : : : : 1 :
|
||||
RESERVED_INPUT : 45 : : : : 1 :
|
||||
RESERVED_INPUT : 46 : : : : 1 :
|
||||
RESERVED_INPUT : 47 : : : : 1 :
|
||||
RESERVED_INPUT : 48 : : : : 1 :
|
||||
GND : 49 : gnd : : : :
|
||||
GND_PLL1 : 50 : gnd : : : :
|
||||
VCCD_PLL1 : 51 : power : : 1.2V : :
|
||||
GND_PLL1 : 52 : gnd : : : :
|
||||
VCCA_PLL1 : 53 : power : : 1.2V : :
|
||||
GNDA_PLL1 : 54 : gnd : : : :
|
||||
GND : 55 : gnd : : : :
|
||||
RESERVED_INPUT : 56 : : : : 4 :
|
||||
RESERVED_INPUT : 57 : : : : 4 :
|
||||
RESERVED_INPUT : 58 : : : : 4 :
|
||||
RESERVED_INPUT : 59 : : : : 4 :
|
||||
RESERVED_INPUT : 60 : : : : 4 :
|
||||
RESERVED_INPUT : 61 : : : : 4 :
|
||||
VCCIO4 : 62 : power : : 3.3V : 4 :
|
||||
RESERVED_INPUT : 63 : : : : 4 :
|
||||
RESERVED_INPUT : 64 : : : : 4 :
|
||||
GND : 65 : gnd : : : :
|
||||
VCCINT : 66 : power : : 1.2V : :
|
||||
B0 : 67 : input : 3.3-V LVTTL : : 4 : Y
|
||||
B1 : 68 : input : 3.3-V LVTTL : : 4 : Y
|
||||
B2 : 69 : input : 3.3-V LVTTL : : 4 : Y
|
||||
B3 : 70 : input : 3.3-V LVTTL : : 4 : Y
|
||||
VCCIO4 : 71 : power : : 3.3V : 4 :
|
||||
B4 : 72 : input : 3.3-V LVTTL : : 4 : Y
|
||||
GND : 73 : gnd : : : :
|
||||
B5 : 74 : input : 3.3-V LVTTL : : 4 : Y
|
||||
B6 : 75 : input : 3.3-V LVTTL : : 4 : Y
|
||||
B7 : 76 : input : 3.3-V LVTTL : : 4 : Y
|
||||
A0 : 77 : input : 3.3-V LVTTL : : 4 : Y
|
||||
GND : 78 : gnd : : : :
|
||||
VCCINT : 79 : power : : 1.2V : :
|
||||
A1 : 80 : input : 3.3-V LVTTL : : 4 : Y
|
||||
A2 : 81 : input : 3.3-V LVTTL : : 4 : Y
|
||||
A3 : 82 : input : 3.3-V LVTTL : : 4 : Y
|
||||
VCCIO4 : 83 : power : : 3.3V : 4 :
|
||||
A4 : 84 : input : 3.3-V LVTTL : : 4 : Y
|
||||
GND : 85 : gnd : : : :
|
||||
A5 : 86 : input : 3.3-V LVTTL : : 4 : Y
|
||||
A6 : 87 : input : 3.3-V LVTTL : : 4 : Y
|
||||
A7 : 88 : input : 3.3-V LVTTL : : 4 : Y
|
||||
RESERVED_INPUT : 89 : : : : 4 :
|
||||
RESERVED_INPUT : 90 : : : : 4 :
|
||||
VCCIO4 : 91 : power : : 3.3V : 4 :
|
||||
RESERVED_INPUT : 92 : : : : 4 :
|
||||
GND : 93 : gnd : : : :
|
||||
RESERVED_INPUT : 94 : : : : 4 :
|
||||
RESERVED_INPUT : 95 : : : : 4 :
|
||||
RESERVED_INPUT : 96 : : : : 4 :
|
||||
RESERVED_INPUT : 97 : : : : 4 :
|
||||
VCCIO4 : 98 : power : : 3.3V : 4 :
|
||||
RESERVED_INPUT : 99 : : : : 4 :
|
||||
GND : 100 : gnd : : : :
|
||||
RESERVED_INPUT : 101 : : : : 4 :
|
||||
RESERVED_INPUT : 102 : : : : 4 :
|
||||
RESERVED_INPUT : 103 : : : : 4 :
|
||||
RESERVED_INPUT : 104 : : : : 4 :
|
||||
RESERVED_INPUT : 105 : : : : 3 :
|
||||
RESERVED_INPUT : 106 : : : : 3 :
|
||||
RESERVED_INPUT : 107 : : : : 3 :
|
||||
~LVDS54p/nCEO~ : 108 : output : 3.3-V LVTTL : : 3 : N
|
||||
VCCIO3 : 109 : power : : 3.3V : 3 :
|
||||
RESERVED_INPUT : 110 : : : : 3 :
|
||||
GND : 111 : gnd : : : :
|
||||
RESERVED_INPUT : 112 : : : : 3 :
|
||||
RESERVED_INPUT : 113 : : : : 3 :
|
||||
RESERVED_INPUT : 114 : : : : 3 :
|
||||
RESERVED_INPUT : 115 : : : : 3 :
|
||||
RESERVED_INPUT : 116 : : : : 3 :
|
||||
RESERVED_INPUT : 117 : : : : 3 :
|
||||
RESERVED_INPUT : 118 : : : : 3 :
|
||||
GND : 119 : gnd : : : :
|
||||
VCCINT : 120 : power : : 1.2V : :
|
||||
nSTATUS : 121 : : : : 3 :
|
||||
VCCIO3 : 122 : power : : 3.3V : 3 :
|
||||
CONF_DONE : 123 : : : : 3 :
|
||||
GND : 124 : gnd : : : :
|
||||
MSEL1 : 125 : : : : 3 :
|
||||
MSEL0 : 126 : : : : 3 :
|
||||
RESERVED_INPUT : 127 : : : : 3 :
|
||||
RESERVED_INPUT : 128 : : : : 3 :
|
||||
GND+ : 129 : : : : 3 :
|
||||
GND+ : 130 : : : : 3 :
|
||||
GND+ : 131 : : : : 3 :
|
||||
GND+ : 132 : : : : 3 :
|
||||
RESERVED_INPUT : 133 : : : : 3 :
|
||||
RESERVED_INPUT : 134 : : : : 3 :
|
||||
RESERVED_INPUT : 135 : : : : 3 :
|
||||
VCCIO3 : 136 : power : : 3.3V : 3 :
|
||||
RESERVED_INPUT : 137 : : : : 3 :
|
||||
RESERVED_INPUT : 138 : : : : 3 :
|
||||
RESERVED_INPUT : 139 : : : : 3 :
|
||||
GND : 140 : gnd : : : :
|
||||
RESERVED_INPUT : 141 : : : : 3 :
|
||||
S0 : 142 : output : 3.3-V LVTTL : : 3 : Y
|
||||
S1 : 143 : output : 3.3-V LVTTL : : 3 : Y
|
||||
S2 : 144 : output : 3.3-V LVTTL : : 3 : Y
|
||||
S3 : 145 : output : 3.3-V LVTTL : : 3 : Y
|
||||
S4 : 146 : output : 3.3-V LVTTL : : 3 : Y
|
||||
S5 : 147 : output : 3.3-V LVTTL : : 3 : Y
|
||||
VCCIO3 : 148 : power : : 3.3V : 3 :
|
||||
S6 : 149 : output : 3.3-V LVTTL : : 3 : Y
|
||||
S7 : 150 : output : 3.3-V LVTTL : : 3 : Y
|
||||
CO : 151 : output : 3.3-V LVTTL : : 3 : Y
|
||||
RESERVED_INPUT : 152 : : : : 3 :
|
||||
GND : 153 : gnd : : : :
|
||||
GND_PLL2 : 154 : gnd : : : :
|
||||
VCCD_PLL2 : 155 : power : : 1.2V : :
|
||||
GND_PLL2 : 156 : gnd : : : :
|
||||
VCCA_PLL2 : 157 : power : : 1.2V : :
|
||||
GNDA_PLL2 : 158 : gnd : : : :
|
||||
GND : 159 : gnd : : : :
|
||||
RESERVED_INPUT : 160 : : : : 2 :
|
||||
RESERVED_INPUT : 161 : : : : 2 :
|
||||
RESERVED_INPUT : 162 : : : : 2 :
|
||||
RESERVED_INPUT : 163 : : : : 2 :
|
||||
RESERVED_INPUT : 164 : : : : 2 :
|
||||
RESERVED_INPUT : 165 : : : : 2 :
|
||||
VCCIO2 : 166 : power : : 3.3V : 2 :
|
||||
GND : 167 : gnd : : : :
|
||||
RESERVED_INPUT : 168 : : : : 2 :
|
||||
RESERVED_INPUT : 169 : : : : 2 :
|
||||
RESERVED_INPUT : 170 : : : : 2 :
|
||||
RESERVED_INPUT : 171 : : : : 2 :
|
||||
VCCIO2 : 172 : power : : 3.3V : 2 :
|
||||
RESERVED_INPUT : 173 : : : : 2 :
|
||||
GND : 174 : gnd : : : :
|
||||
RESERVED_INPUT : 175 : : : : 2 :
|
||||
RESERVED_INPUT : 176 : : : : 2 :
|
||||
GND : 177 : gnd : : : :
|
||||
VCCINT : 178 : power : : 1.2V : :
|
||||
RESERVED_INPUT : 179 : : : : 2 :
|
||||
RESERVED_INPUT : 180 : : : : 2 :
|
||||
RESERVED_INPUT : 181 : : : : 2 :
|
||||
RESERVED_INPUT : 182 : : : : 2 :
|
||||
VCCIO2 : 183 : power : : 3.3V : 2 :
|
||||
GND : 184 : gnd : : : :
|
||||
RESERVED_INPUT : 185 : : : : 2 :
|
||||
GND : 186 : gnd : : : :
|
||||
RESERVED_INPUT : 187 : : : : 2 :
|
||||
RESERVED_INPUT : 188 : : : : 2 :
|
||||
RESERVED_INPUT : 189 : : : : 2 :
|
||||
VCCINT : 190 : power : : 1.2V : :
|
||||
RESERVED_INPUT : 191 : : : : 2 :
|
||||
RESERVED_INPUT : 192 : : : : 2 :
|
||||
RESERVED_INPUT : 193 : : : : 2 :
|
||||
VCCIO2 : 194 : power : : 3.3V : 2 :
|
||||
RESERVED_INPUT : 195 : : : : 2 :
|
||||
GND : 196 : gnd : : : :
|
||||
RESERVED_INPUT : 197 : : : : 2 :
|
||||
RESERVED_INPUT : 198 : : : : 2 :
|
||||
RESERVED_INPUT : 199 : : : : 2 :
|
||||
RESERVED_INPUT : 200 : : : : 2 :
|
||||
RESERVED_INPUT : 201 : : : : 2 :
|
||||
VCCIO2 : 202 : power : : 3.3V : 2 :
|
||||
RESERVED_INPUT : 203 : : : : 2 :
|
||||
GND : 204 : gnd : : : :
|
||||
RESERVED_INPUT : 205 : : : : 2 :
|
||||
RESERVED_INPUT : 206 : : : : 2 :
|
||||
RESERVED_INPUT : 207 : : : : 2 :
|
||||
RESERVED_INPUT : 208 : : : : 2 :
|
||||
未顯示二進位檔案。
@@ -1,14 +0,0 @@
|
||||
[ProjectWorkspace]
|
||||
ptn_Child1=Frames
|
||||
[ProjectWorkspace.Frames]
|
||||
ptn_Child1=ChildFrames
|
||||
[ProjectWorkspace.Frames.ChildFrames]
|
||||
ptn_Child1=Document-0
|
||||
[ProjectWorkspace.Frames.ChildFrames.Document-0]
|
||||
ptn_Child1=ViewFrame-0
|
||||
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
|
||||
DocPathName=adder_8b.bdf
|
||||
DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde}
|
||||
IsChildFrameDetached=False
|
||||
IsActiveChildFrame=True
|
||||
ptn_Child1=StateMap
|
||||
未顯示二進位檔案。
@@ -1,229 +0,0 @@
|
||||
Classic Timing Analyzer report for adder_8b
|
||||
Mon Mar 07 11:28:59 2022
|
||||
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
|
||||
|
||||
|
||||
---------------------
|
||||
; Table of Contents ;
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. Timing Analyzer Summary
|
||||
3. Timing Analyzer Settings
|
||||
4. Parallel Compilation
|
||||
5. tpd
|
||||
6. Timing Analyzer Messages
|
||||
|
||||
|
||||
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 1991-2009 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------------------------+
|
||||
; Timing Analyzer Summary ;
|
||||
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
|
||||
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
|
||||
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
|
||||
; Worst-case tpd ; N/A ; None ; 22.018 ns ; B0 ; CO ; -- ; -- ; 0 ;
|
||||
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
|
||||
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------+
|
||||
; Timing Analyzer Settings ;
|
||||
+---------------------------------------------------------------------+--------------------+------+----+-------------+
|
||||
; Option ; Setting ; From ; To ; Entity Name ;
|
||||
+---------------------------------------------------------------------+--------------------+------+----+-------------+
|
||||
; Device Name ; EP2C8Q208C8 ; ; ; ;
|
||||
; Timing Models ; Final ; ; ; ;
|
||||
; Default hold multicycle ; Same as Multicycle ; ; ; ;
|
||||
; Cut paths between unrelated clock domains ; On ; ; ; ;
|
||||
; Cut off read during write signal paths ; On ; ; ; ;
|
||||
; Cut off feedback from I/O pins ; On ; ; ; ;
|
||||
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
|
||||
; Ignore Clock Settings ; Off ; ; ; ;
|
||||
; Analyze latches as synchronous elements ; On ; ; ; ;
|
||||
; Enable Recovery/Removal analysis ; Off ; ; ; ;
|
||||
; Enable Clock Latency ; Off ; ; ; ;
|
||||
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
|
||||
; Minimum Core Junction Temperature ; 0 ; ; ; ;
|
||||
; Maximum Core Junction Temperature ; 85 ; ; ; ;
|
||||
; Number of source nodes to report per destination node ; 10 ; ; ; ;
|
||||
; Number of destination nodes to report ; 10 ; ; ; ;
|
||||
; Number of paths to report ; 200 ; ; ; ;
|
||||
; Report Minimum Timing Checks ; Off ; ; ; ;
|
||||
; Use Fast Timing Models ; Off ; ; ; ;
|
||||
; Report IO Paths Separately ; Off ; ; ; ;
|
||||
; Perform Multicorner Analysis ; On ; ; ; ;
|
||||
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
|
||||
; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
|
||||
; Output I/O Timing Endpoint ; Near End ; ; ; ;
|
||||
+---------------------------------------------------------------------+--------------------+------+----+-------------+
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
; Parallel Compilation ;
|
||||
+----------------------------+-------------+
|
||||
; Processors ; Number ;
|
||||
+----------------------------+-------------+
|
||||
; Number detected on machine ; 4 ;
|
||||
; Maximum allowed ; 4 ;
|
||||
; ; ;
|
||||
; Average used ; 1.00 ;
|
||||
; Maximum used ; 1 ;
|
||||
; ; ;
|
||||
; Usage by Processor ; % Time Used ;
|
||||
; 1 processor ; 100.0% ;
|
||||
; 2-4 processors ; 0.0% ;
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------+
|
||||
; tpd ;
|
||||
+-------+-------------------+-----------------+------+----+
|
||||
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
|
||||
+-------+-------------------+-----------------+------+----+
|
||||
; N/A ; None ; 22.018 ns ; B0 ; CO ;
|
||||
; N/A ; None ; 21.780 ns ; B0 ; S7 ;
|
||||
; N/A ; None ; 21.052 ns ; B1 ; CO ;
|
||||
; N/A ; None ; 20.864 ns ; A0 ; CO ;
|
||||
; N/A ; None ; 20.814 ns ; B1 ; S7 ;
|
||||
; N/A ; None ; 20.626 ns ; A0 ; S7 ;
|
||||
; N/A ; None ; 20.579 ns ; A1 ; CO ;
|
||||
; N/A ; None ; 20.442 ns ; B0 ; S6 ;
|
||||
; N/A ; None ; 20.341 ns ; A1 ; S7 ;
|
||||
; N/A ; None ; 20.259 ns ; B2 ; CO ;
|
||||
; N/A ; None ; 20.021 ns ; B2 ; S7 ;
|
||||
; N/A ; None ; 19.812 ns ; A2 ; CO ;
|
||||
; N/A ; None ; 19.574 ns ; A2 ; S7 ;
|
||||
; N/A ; None ; 19.476 ns ; B1 ; S6 ;
|
||||
; N/A ; None ; 19.288 ns ; A0 ; S6 ;
|
||||
; N/A ; None ; 19.089 ns ; B0 ; S5 ;
|
||||
; N/A ; None ; 19.003 ns ; A1 ; S6 ;
|
||||
; N/A ; None ; 18.831 ns ; B3 ; CO ;
|
||||
; N/A ; None ; 18.728 ns ; A3 ; CO ;
|
||||
; N/A ; None ; 18.683 ns ; B2 ; S6 ;
|
||||
; N/A ; None ; 18.593 ns ; B3 ; S7 ;
|
||||
; N/A ; None ; 18.490 ns ; A3 ; S7 ;
|
||||
; N/A ; None ; 18.303 ns ; B0 ; S4 ;
|
||||
; N/A ; None ; 18.291 ns ; A4 ; CO ;
|
||||
; N/A ; None ; 18.236 ns ; A2 ; S6 ;
|
||||
; N/A ; None ; 18.123 ns ; B1 ; S5 ;
|
||||
; N/A ; None ; 18.053 ns ; A4 ; S7 ;
|
||||
; N/A ; None ; 17.935 ns ; A0 ; S5 ;
|
||||
; N/A ; None ; 17.650 ns ; A1 ; S5 ;
|
||||
; N/A ; None ; 17.587 ns ; B4 ; CO ;
|
||||
; N/A ; None ; 17.447 ns ; CI ; CO ;
|
||||
; N/A ; None ; 17.370 ns ; B0 ; S3 ;
|
||||
; N/A ; None ; 17.349 ns ; B4 ; S7 ;
|
||||
; N/A ; None ; 17.337 ns ; B1 ; S4 ;
|
||||
; N/A ; None ; 17.330 ns ; B2 ; S5 ;
|
||||
; N/A ; None ; 17.255 ns ; B3 ; S6 ;
|
||||
; N/A ; None ; 17.209 ns ; CI ; S7 ;
|
||||
; N/A ; None ; 17.202 ns ; A5 ; CO ;
|
||||
; N/A ; None ; 17.152 ns ; A3 ; S6 ;
|
||||
; N/A ; None ; 17.149 ns ; A0 ; S4 ;
|
||||
; N/A ; None ; 16.987 ns ; B5 ; CO ;
|
||||
; N/A ; None ; 16.964 ns ; A5 ; S7 ;
|
||||
; N/A ; None ; 16.883 ns ; A2 ; S5 ;
|
||||
; N/A ; None ; 16.864 ns ; A1 ; S4 ;
|
||||
; N/A ; None ; 16.749 ns ; B5 ; S7 ;
|
||||
; N/A ; None ; 16.715 ns ; A4 ; S6 ;
|
||||
; N/A ; None ; 16.544 ns ; B2 ; S4 ;
|
||||
; N/A ; None ; 16.404 ns ; B1 ; S3 ;
|
||||
; N/A ; None ; 16.306 ns ; B0 ; S2 ;
|
||||
; N/A ; None ; 16.216 ns ; A0 ; S3 ;
|
||||
; N/A ; None ; 16.097 ns ; A2 ; S4 ;
|
||||
; N/A ; None ; 16.011 ns ; B4 ; S6 ;
|
||||
; N/A ; None ; 15.931 ns ; A1 ; S3 ;
|
||||
; N/A ; None ; 15.902 ns ; B3 ; S5 ;
|
||||
; N/A ; None ; 15.871 ns ; CI ; S6 ;
|
||||
; N/A ; None ; 15.799 ns ; A3 ; S5 ;
|
||||
; N/A ; None ; 15.626 ns ; A5 ; S6 ;
|
||||
; N/A ; None ; 15.611 ns ; B2 ; S3 ;
|
||||
; N/A ; None ; 15.411 ns ; B5 ; S6 ;
|
||||
; N/A ; None ; 15.366 ns ; A4 ; S5 ;
|
||||
; N/A ; None ; 15.340 ns ; B1 ; S2 ;
|
||||
; N/A ; None ; 15.164 ns ; A2 ; S3 ;
|
||||
; N/A ; None ; 15.152 ns ; A0 ; S2 ;
|
||||
; N/A ; None ; 15.116 ns ; B3 ; S4 ;
|
||||
; N/A ; None ; 15.042 ns ; B6 ; CO ;
|
||||
; N/A ; None ; 15.013 ns ; A3 ; S4 ;
|
||||
; N/A ; None ; 14.892 ns ; B0 ; S1 ;
|
||||
; N/A ; None ; 14.867 ns ; A1 ; S2 ;
|
||||
; N/A ; None ; 14.804 ns ; B6 ; S7 ;
|
||||
; N/A ; None ; 14.658 ns ; B4 ; S5 ;
|
||||
; N/A ; None ; 14.543 ns ; B2 ; S2 ;
|
||||
; N/A ; None ; 14.518 ns ; CI ; S5 ;
|
||||
; N/A ; None ; 14.282 ns ; A5 ; S5 ;
|
||||
; N/A ; None ; 14.173 ns ; B3 ; S3 ;
|
||||
; N/A ; None ; 14.162 ns ; B0 ; S0 ;
|
||||
; N/A ; None ; 14.098 ns ; A2 ; S2 ;
|
||||
; N/A ; None ; 14.088 ns ; A4 ; S4 ;
|
||||
; N/A ; None ; 14.077 ns ; A3 ; S3 ;
|
||||
; N/A ; None ; 14.063 ns ; B5 ; S5 ;
|
||||
; N/A ; None ; 14.043 ns ; B7 ; CO ;
|
||||
; N/A ; None ; 13.974 ns ; A6 ; CO ;
|
||||
; N/A ; None ; 13.933 ns ; B1 ; S1 ;
|
||||
; N/A ; None ; 13.865 ns ; B4 ; S4 ;
|
||||
; N/A ; None ; 13.816 ns ; B7 ; S7 ;
|
||||
; N/A ; None ; 13.738 ns ; A0 ; S1 ;
|
||||
; N/A ; None ; 13.736 ns ; A6 ; S7 ;
|
||||
; N/A ; None ; 13.732 ns ; CI ; S4 ;
|
||||
; N/A ; None ; 13.470 ns ; A1 ; S1 ;
|
||||
; N/A ; None ; 13.462 ns ; B6 ; S6 ;
|
||||
; N/A ; None ; 13.415 ns ; A7 ; CO ;
|
||||
; N/A ; None ; 13.184 ns ; A7 ; S7 ;
|
||||
; N/A ; None ; 13.004 ns ; A0 ; S0 ;
|
||||
; N/A ; None ; 12.799 ns ; CI ; S3 ;
|
||||
; N/A ; None ; 12.403 ns ; A6 ; S6 ;
|
||||
; N/A ; None ; 11.735 ns ; CI ; S2 ;
|
||||
; N/A ; None ; 10.321 ns ; CI ; S1 ;
|
||||
; N/A ; None ; 9.587 ns ; CI ; S0 ;
|
||||
+-------+-------------------+-----------------+------+----+
|
||||
|
||||
|
||||
+--------------------------+
|
||||
; Timing Analyzer Messages ;
|
||||
+--------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II Classic Timing Analyzer
|
||||
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
|
||||
Info: Processing started: Mon Mar 07 11:28:59 2022
|
||||
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b --timing_analysis_only
|
||||
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
|
||||
Info: Longest tpd from source pin "B0" to destination pin "CO" is 22.018 ns
|
||||
Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 2; PIN Node = 'B0'
|
||||
Info: 2: + IC(6.491 ns) + CELL(0.624 ns) = 8.109 ns; Loc. = LCCOMB_X18_Y4_N2; Fanout = 2; COMB Node = '7400:inst3|4~1'
|
||||
Info: 3: + IC(0.373 ns) + CELL(0.624 ns) = 9.106 ns; Loc. = LCCOMB_X18_Y4_N20; Fanout = 4; COMB Node = '7400:inst8|4~0'
|
||||
Info: 4: + IC(0.407 ns) + CELL(0.370 ns) = 9.883 ns; Loc. = LCCOMB_X18_Y4_N16; Fanout = 2; COMB Node = '7400:inst13|4~1'
|
||||
Info: 5: + IC(0.426 ns) + CELL(0.650 ns) = 10.959 ns; Loc. = LCCOMB_X18_Y4_N12; Fanout = 2; COMB Node = '7400:inst18|4~0'
|
||||
Info: 6: + IC(0.408 ns) + CELL(0.650 ns) = 12.017 ns; Loc. = LCCOMB_X18_Y4_N30; Fanout = 2; COMB Node = '7400:inst23|4~9'
|
||||
Info: 7: + IC(0.365 ns) + CELL(0.206 ns) = 12.588 ns; Loc. = LCCOMB_X18_Y4_N0; Fanout = 3; COMB Node = '7400:inst28|4~0'
|
||||
Info: 8: + IC(2.636 ns) + CELL(0.370 ns) = 15.594 ns; Loc. = LCCOMB_X28_Y11_N26; Fanout = 2; COMB Node = '7400:inst33|4~1'
|
||||
Info: 9: + IC(0.370 ns) + CELL(0.624 ns) = 16.588 ns; Loc. = LCCOMB_X28_Y11_N12; Fanout = 1; COMB Node = '7400:inst38|4~0'
|
||||
Info: 10: + IC(2.150 ns) + CELL(3.280 ns) = 22.018 ns; Loc. = PIN_151; Fanout = 0; PIN Node = 'CO'
|
||||
Info: Total cell delay = 8.392 ns ( 38.11 % )
|
||||
Info: Total interconnect delay = 13.626 ns ( 61.89 % )
|
||||
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 213 megabytes
|
||||
Info: Processing ended: Mon Mar 07 11:28:59 2022
|
||||
Info: Elapsed time: 00:00:00
|
||||
Info: Total CPU time (on all processors): 00:00:00
|
||||
|
||||
|
||||
@@ -1,26 +0,0 @@
|
||||
--------------------------------------------------------------------------------------
|
||||
Timing Analyzer Summary
|
||||
--------------------------------------------------------------------------------------
|
||||
|
||||
Type : Worst-case tpd
|
||||
Slack : N/A
|
||||
Required Time : None
|
||||
Actual Time : 22.018 ns
|
||||
From : B0
|
||||
To : CO
|
||||
From Clock : --
|
||||
To Clock : --
|
||||
Failed Paths : 0
|
||||
|
||||
Type : Total number of failed paths
|
||||
Slack :
|
||||
Required Time :
|
||||
Actual Time :
|
||||
From :
|
||||
To :
|
||||
From Clock :
|
||||
To Clock :
|
||||
Failed Paths : 0
|
||||
|
||||
--------------------------------------------------------------------------------------
|
||||
|
||||
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
@@ -1,7 +0,0 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:28:58 2022 " "Info: Processing started: Mon Mar 07 11:28:58 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
|
||||
{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "242 " "Info: Peak virtual memory: 242 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:28:58 2022 " "Info: Processing ended: Mon Mar 07 11:28:58 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
|
||||
未顯示二進位檔案。
@@ -1,5 +0,0 @@
|
||||
<?xml version="1.0" ?>
|
||||
<LOG_ROOT>
|
||||
<PROJECT NAME="adder_8b">
|
||||
</PROJECT>
|
||||
</LOG_ROOT>
|
||||
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
@@ -1,10 +0,0 @@
|
||||
<kpt_db name="adder_8b.cmp" kpt_version="1.1">
|
||||
<key_points_set type="reference" hier_sep="|">
|
||||
</key_points_set>
|
||||
<key_points_set type="transition" hier_sep="|">
|
||||
</key_points_set>
|
||||
<key_points_set type="transformed" hier_sep="|">
|
||||
</key_points_set>
|
||||
<transformations_set hier_sep="|">
|
||||
</transformations_set>
|
||||
</kpt_db>
|
||||
@@ -1 +0,0 @@
|
||||
v1
|
||||
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
@@ -1,10 +0,0 @@
|
||||
<kpt_db name="adder_8b.cmp_merge" kpt_version="1.1">
|
||||
<key_points_set type="reference" hier_sep="|">
|
||||
</key_points_set>
|
||||
<key_points_set type="transition" hier_sep="|">
|
||||
</key_points_set>
|
||||
<key_points_set type="transformed" hier_sep="|">
|
||||
</key_points_set>
|
||||
<transformations_set hier_sep="|">
|
||||
</transformations_set>
|
||||
</kpt_db>
|
||||
@@ -1,3 +0,0 @@
|
||||
Quartus_Version = Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
|
||||
Version_Index = 167832322
|
||||
Creation_Time = Mon Mar 07 10:21:41 2022
|
||||
未顯示二進位檔案。
@@ -1,35 +0,0 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:28:56 2022 " "Info: Processing started: Mon Mar 07 11:28:56 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
|
||||
{ "Info" "IMPP_MPP_USER_DEVICE" "adder_8b EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"adder_8b\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
|
||||
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
|
||||
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
|
||||
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
|
||||
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
|
||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
|
||||
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
|
||||
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
|
||||
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
|
||||
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
|
||||
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
|
||||
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
|
||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
|
||||
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
|
||||
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X11_Y0 X22_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
|
||||
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
|
||||
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "9 " "Warning: Found 9 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "CO 0 " "Info: Pin \"CO\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S7 0 " "Info: Pin \"S7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S0 0 " "Info: Pin \"S0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S1 0 " "Info: Pin \"S1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S2 0 " "Info: Pin \"S2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S3 0 " "Info: Pin \"S3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S4 0 " "Info: Pin \"S4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S5 0 " "Info: Pin \"S5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S6 0 " "Info: Pin \"S6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
|
||||
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
|
||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/adder_8b/adder_8b.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/adder_8b/adder_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "305 " "Info: Peak virtual memory: 305 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:28:57 2022 " "Info: Processing ended: Mon Mar 07 11:28:57 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
|
||||
@@ -1,286 +0,0 @@
|
||||
|adder_8b
|
||||
CO <= 7400:inst38.1
|
||||
A7 => 7400:inst39.3
|
||||
A7 => 7486:inst36.2
|
||||
B7 => 7400:inst39.2
|
||||
B7 => 7486:inst36.3
|
||||
A6 => 7400:inst34.3
|
||||
A6 => 7486:inst31.2
|
||||
B6 => 7400:inst34.2
|
||||
B6 => 7486:inst31.3
|
||||
A5 => 7400:inst29.3
|
||||
A5 => 7486:inst26.2
|
||||
B5 => 7400:inst29.2
|
||||
B5 => 7486:inst26.3
|
||||
A4 => 7400:inst24.3
|
||||
A4 => 7486:inst21.2
|
||||
B4 => 7400:inst24.2
|
||||
B4 => 7486:inst21.3
|
||||
A3 => 7400:inst19.3
|
||||
A3 => 7486:inst16.2
|
||||
B3 => 7400:inst19.2
|
||||
B3 => 7486:inst16.3
|
||||
A2 => 7400:inst14.3
|
||||
A2 => 7486:inst11.2
|
||||
B2 => 7400:inst14.2
|
||||
B2 => 7486:inst11.3
|
||||
A1 => 7400:inst9.3
|
||||
A1 => 7486:inst6.2
|
||||
B1 => 7400:inst9.2
|
||||
B1 => 7486:inst6.3
|
||||
A0 => 7400:inst4.3
|
||||
A0 => 7486:inst.2
|
||||
B0 => 7400:inst4.2
|
||||
B0 => 7486:inst.3
|
||||
CI => 7400:inst2.3
|
||||
CI => 7486:inst5.3
|
||||
S7 <= 7486:inst40.1
|
||||
S0 <= 7486:inst5.1
|
||||
S1 <= 7486:inst10.1
|
||||
S2 <= 7486:inst15.1
|
||||
S3 <= 7486:inst20.1
|
||||
S4 <= 7486:inst25.1
|
||||
S5 <= 7486:inst30.1
|
||||
S6 <= 7486:inst35.1
|
||||
|
||||
|
||||
|adder_8b|7400:inst38
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7400:inst39
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7400:inst37
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7400:inst33
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7400:inst34
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7400:inst32
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7400:inst28
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7400:inst29
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7400:inst27
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7400:inst23
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7400:inst24
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7400:inst22
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7400:inst18
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7400:inst19
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7400:inst17
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7400:inst13
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7400:inst14
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7400:inst12
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7400:inst8
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7400:inst9
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7400:inst7
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7400:inst3
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7400:inst4
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7400:inst2
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7486:inst
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7486:inst6
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7486:inst11
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7486:inst16
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7486:inst21
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7486:inst26
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7486:inst31
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7486:inst36
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7486:inst40
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7486:inst5
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7486:inst10
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7486:inst15
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7486:inst20
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7486:inst25
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7486:inst30
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
|adder_8b|7486:inst35
|
||||
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
2 => 4.IN0
|
||||
3 => 4.IN1
|
||||
|
||||
|
||||
@@ -1,120 +0,0 @@
|
||||
Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
|
||||
11
|
||||
936
|
||||
OFF
|
||||
OFF
|
||||
OFF
|
||||
ON
|
||||
ON
|
||||
ON
|
||||
FV_OFF
|
||||
Level2
|
||||
0
|
||||
0
|
||||
VRSM_ON
|
||||
VHSM_ON
|
||||
0
|
||||
-- Start Library Paths --
|
||||
-- End Library Paths --
|
||||
-- Start VHDL Libraries --
|
||||
-- End VHDL Libraries --
|
||||
# entity
|
||||
adder_8b
|
||||
# storage
|
||||
db|adder_8b.(0).cnf
|
||||
db|adder_8b.(0).cnf
|
||||
# case_insensitive
|
||||
# source_file
|
||||
adder_8b.bdf
|
||||
a2e51ddcd21f2ca4364ec3cc2afc185
|
||||
26
|
||||
# internal_option {
|
||||
BLOCK_DESIGN_NAMING
|
||||
AUTO
|
||||
}
|
||||
# hierarchies {
|
||||
|
|
||||
}
|
||||
# macro_sequence
|
||||
|
||||
# end
|
||||
# entity
|
||||
7400
|
||||
# storage
|
||||
db|adder_8b.(1).cnf
|
||||
db|adder_8b.(1).cnf
|
||||
# case_insensitive
|
||||
# source_file
|
||||
..|..|..|altera|90sp2|quartus|libraries|others|maxplus2|7400.bdf
|
||||
2bbb3be4da5c8a854468ca6be3dac
|
||||
26
|
||||
# internal_option {
|
||||
BLOCK_DESIGN_NAMING
|
||||
AUTO
|
||||
}
|
||||
# hierarchies {
|
||||
7400:inst38
|
||||
7400:inst39
|
||||
7400:inst37
|
||||
7400:inst33
|
||||
7400:inst34
|
||||
7400:inst32
|
||||
7400:inst28
|
||||
7400:inst29
|
||||
7400:inst27
|
||||
7400:inst23
|
||||
7400:inst24
|
||||
7400:inst22
|
||||
7400:inst18
|
||||
7400:inst19
|
||||
7400:inst17
|
||||
7400:inst13
|
||||
7400:inst14
|
||||
7400:inst12
|
||||
7400:inst8
|
||||
7400:inst9
|
||||
7400:inst7
|
||||
7400:inst3
|
||||
7400:inst4
|
||||
7400:inst2
|
||||
}
|
||||
# macro_sequence
|
||||
|
||||
# end
|
||||
# entity
|
||||
7486
|
||||
# storage
|
||||
db|adder_8b.(2).cnf
|
||||
db|adder_8b.(2).cnf
|
||||
# case_insensitive
|
||||
# source_file
|
||||
..|..|..|altera|90sp2|quartus|libraries|others|maxplus2|7486.bdf
|
||||
66760dceba984b0dca8067dd21fcf
|
||||
26
|
||||
# internal_option {
|
||||
BLOCK_DESIGN_NAMING
|
||||
AUTO
|
||||
}
|
||||
# hierarchies {
|
||||
7486:inst
|
||||
7486:inst6
|
||||
7486:inst11
|
||||
7486:inst16
|
||||
7486:inst21
|
||||
7486:inst26
|
||||
7486:inst31
|
||||
7486:inst36
|
||||
7486:inst40
|
||||
7486:inst5
|
||||
7486:inst10
|
||||
7486:inst15
|
||||
7486:inst20
|
||||
7486:inst25
|
||||
7486:inst30
|
||||
7486:inst35
|
||||
}
|
||||
# macro_sequence
|
||||
|
||||
# end
|
||||
# complete
|
||||
|
||||
@@ -1,18 +0,0 @@
|
||||
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
|
||||
<TR valign="middle" bgcolor="#C0C0C0">
|
||||
<TH>Hierarchy</TH>
|
||||
<TH>Input</TH>
|
||||
<TH>Constant Input</TH>
|
||||
<TH>Unused Input</TH>
|
||||
<TH>Floating Input</TH>
|
||||
<TH>Output</TH>
|
||||
<TH>Constant Output</TH>
|
||||
<TH>Unused Output</TH>
|
||||
<TH>Floating Output</TH>
|
||||
<TH>Bidir</TH>
|
||||
<TH>Constant Bidir</TH>
|
||||
<TH>Unused Bidir</TH>
|
||||
<TH>Input only Bidir</TH>
|
||||
<TH>Output only Bidir</TH>
|
||||
</TR>
|
||||
</TABLE>
|
||||
未顯示二進位檔案。
@@ -1,5 +0,0 @@
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Legal Partition Candidates ;
|
||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
|
||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
@@ -1,10 +0,0 @@
|
||||
<kpt_db name="adder_8b.map" kpt_version="1.1">
|
||||
<key_points_set type="reference" hier_sep="/">
|
||||
</key_points_set>
|
||||
<key_points_set type="transition" hier_sep="|">
|
||||
</key_points_set>
|
||||
<key_points_set type="transformed" hier_sep="|">
|
||||
</key_points_set>
|
||||
<transformations_set hier_sep="|">
|
||||
</transformations_set>
|
||||
</kpt_db>
|
||||
@@ -1 +0,0 @@
|
||||
v1
|
||||
@@ -1,11 +0,0 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:28:54 2022 " "Info: Processing started: Mon Mar 07 11:28:54 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off adder_8b -c adder_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adder_8b -c adder_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adder_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file adder_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 adder_8b " "Info: Found entity 1: adder_8b" { } { { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "adder_8b " "Info: Elaborating entity \"adder_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7400 7400:inst38 " "Info: Elaborating entity \"7400\" for hierarchy \"7400:inst38\"" { } { { "adder_8b.bdf" "inst38" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 184 400 464 224 "inst38" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
|
||||
{ "Info" "ISGN_ELABORATION_HEADER" "7400:inst38 " "Info: Elaborated megafunction instantiation \"7400:inst38\"" { } { { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 184 400 464 224 "inst38" "" } } } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7486 7486:inst " "Info: Elaborating entity \"7486\" for hierarchy \"7486:inst\"" { } { { "adder_8b.bdf" "inst" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2096 272 336 2136 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
|
||||
{ "Info" "ISGN_ELABORATION_HEADER" "7486:inst " "Info: Elaborated megafunction instantiation \"7486:inst\"" { } { { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2096 272 336 2136 "inst" "" } } } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "47 " "Info: Implemented 47 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "17 " "Info: Implemented 17 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Info: Implemented 9 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "21 " "Info: Implemented 21 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:28:55 2022 " "Info: Processing ended: Mon Mar 07 11:28:55 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
|
||||
未顯示二進位檔案。
未顯示二進位檔案。
@@ -1 +0,0 @@
|
||||
v1
|
||||
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
檔案差異因為一行或多行太長而無法顯示
未顯示二進位檔案。
@@ -1,6 +0,0 @@
|
||||
start_full_compilation:s:00:00:06
|
||||
start_analysis_synthesis:s:00:00:02-start_full_compilation
|
||||
start_analysis_elaboration:s-start_full_compilation
|
||||
start_fitter:s:00:00:02-start_full_compilation
|
||||
start_assembler:s:00:00:01-start_full_compilation
|
||||
start_timing_analyzer:s:00:00:01-start_full_compilation
|
||||
@@ -1,7 +0,0 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:22:24 2022 " "Info: Processing started: Mon Mar 07 10:22:24 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
|
||||
{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "242 " "Info: Peak virtual memory: 242 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 10:22:24 2022 " "Info: Processing ended: Mon Mar 07 10:22:24 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
|
||||
檔案差異因為一行或多行太長而無法顯示
@@ -1,11 +0,0 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:22:20 2022 " "Info: Processing started: Mon Mar 07 10:22:20 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off adder_8b -c adder_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adder_8b -c adder_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adder_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file adder_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 adder_8b " "Info: Found entity 1: adder_8b" { } { { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "adder_8b " "Info: Elaborating entity \"adder_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7400 7400:inst38 " "Info: Elaborating entity \"7400\" for hierarchy \"7400:inst38\"" { } { { "adder_8b.bdf" "inst38" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 184 400 464 224 "inst38" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
|
||||
{ "Info" "ISGN_ELABORATION_HEADER" "7400:inst38 " "Info: Elaborated megafunction instantiation \"7400:inst38\"" { } { { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 184 400 464 224 "inst38" "" } } } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7486 7486:inst " "Info: Elaborating entity \"7486\" for hierarchy \"7486:inst\"" { } { { "adder_8b.bdf" "inst" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2096 272 336 2136 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
|
||||
{ "Info" "ISGN_ELABORATION_HEADER" "7486:inst " "Info: Elaborated megafunction instantiation \"7486:inst\"" { } { { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2096 272 336 2136 "inst" "" } } } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "47 " "Info: Implemented 47 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "17 " "Info: Implemented 17 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Info: Implemented 9 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "21 " "Info: Implemented 21 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "248 " "Info: Peak virtual memory: 248 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 10:22:21 2022 " "Info: Processing ended: Mon Mar 07 10:22:21 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
|
||||
檔案差異因為一行或多行太長而無法顯示
@@ -1,11 +0,0 @@
|
||||
This folder contains data for incremental compilation.
|
||||
|
||||
The compiled_partitions sub-folder contains previous compilation results for each partition.
|
||||
As long as this folder is preserved, incremental compilation results from earlier compiles
|
||||
can be re-used. To perform a clean compilation from source files for all partitions, both
|
||||
the db and incremental_db folder should be removed.
|
||||
|
||||
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
|
||||
As long as this folder is preserved, imported partitions will be automatically re-imported
|
||||
when the db or incremental_db/compiled_partitions folders are removed.
|
||||
|
||||
@@ -1,10 +0,0 @@
|
||||
<kpt_db name="root_partition" kpt_version="1.1">
|
||||
<key_points_set type="reference" hier_sep="|">
|
||||
</key_points_set>
|
||||
<key_points_set type="transition" hier_sep="|">
|
||||
</key_points_set>
|
||||
<key_points_set type="transformed" hier_sep="|">
|
||||
</key_points_set>
|
||||
<transformations_set hier_sep="|">
|
||||
</transformations_set>
|
||||
</kpt_db>
|
||||
@@ -1 +0,0 @@
|
||||
v1
|
||||
@@ -1,10 +0,0 @@
|
||||
<kpt_db name="adder_8b.map_bb" kpt_version="1.1">
|
||||
<key_points_set type="reference" hier_sep="/">
|
||||
</key_points_set>
|
||||
<key_points_set type="transition" hier_sep="|">
|
||||
</key_points_set>
|
||||
<key_points_set type="transformed" hier_sep="|">
|
||||
</key_points_set>
|
||||
<transformations_set hier_sep="|">
|
||||
</transformations_set>
|
||||
</kpt_db>
|
||||
新增問題並參考
封鎖使用者