diff --git a/38_decoder/38_decoder.asm.rpt b/38_decoder/38_decoder.asm.rpt
index 4daad42..c616fae 100644
--- a/38_decoder/38_decoder.asm.rpt
+++ b/38_decoder/38_decoder.asm.rpt
@@ -1,5 +1,5 @@
Assembler report for 38_decoder
-Mon Mar 07 09:13:07 2022
+Tue Mar 08 15:12:41 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@@ -38,7 +38,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Mon Mar 07 09:13:07 2022 ;
+; Assembler Status ; Successful - Tue Mar 08 15:12:41 2022 ;
; Revision Name ; 38_decoder ;
; Top-level Entity Name ; 38_decoder ;
; Family ; Cyclone II ;
@@ -93,7 +93,7 @@ applicable agreement for further details.
+----------------+--------------------------------------------------------+
; Device ; EP2C8Q208C8 ;
; JTAG usercode ; 0xFFFFFFFF ;
-; Checksum ; 0x000C6513 ;
+; Checksum ; 0x000C10D6 ;
+----------------+--------------------------------------------------------+
@@ -104,7 +104,7 @@ applicable agreement for further details.
+--------------------+----------------------------------------------------+
; Device ; EPCS4 ;
; JTAG usercode ; 0x00000000 ;
-; Checksum ; 0x06F0CA55 ;
+; Checksum ; 0x06F0221B ;
; Compression Ratio ; 3 ;
+--------------------+----------------------------------------------------+
@@ -115,14 +115,14 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
- Info: Processing started: Mon Mar 07 09:13:07 2022
+ Info: Processing started: Tue Mar 08 15:12:41 2022
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder
Info: Writing out detailed assembly data for power analysis
Info: Assembler is generating device programming files
Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 241 megabytes
- Info: Processing ended: Mon Mar 07 09:13:07 2022
+ Info: Processing ended: Tue Mar 08 15:12:41 2022
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00
diff --git a/38_decoder/38_decoder.done b/38_decoder/38_decoder.done
index 508b5d2..fcc5548 100644
--- a/38_decoder/38_decoder.done
+++ b/38_decoder/38_decoder.done
@@ -1 +1 @@
-Mon Mar 07 09:13:09 2022
+Tue Mar 08 15:12:42 2022
diff --git a/38_decoder/38_decoder.fit.rpt b/38_decoder/38_decoder.fit.rpt
index f8fbfd4..24201f7 100644
--- a/38_decoder/38_decoder.fit.rpt
+++ b/38_decoder/38_decoder.fit.rpt
@@ -1,5 +1,5 @@
Fitter report for 38_decoder
-Mon Mar 07 09:13:06 2022
+Tue Mar 08 15:12:40 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@@ -63,7 +63,7 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+----------------------------------------------+
-; Fitter Status ; Successful - Mon Mar 07 09:13:06 2022 ;
+; Fitter Status ; Successful - Tue Mar 08 15:12:40 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; 38_decoder ;
; Top-level Entity Name ; 38_decoder ;
@@ -91,6 +91,7 @@ applicable agreement for further details.
; Minimum Core Junction Temperature ; 0 ; ;
; Maximum Core Junction Temperature ; 85 ; ;
; Fit Attempts to Skip ; 0 ; 0.0 ;
+; Device I/O Standard ; 3.3-V LVTTL ; ;
; Use smart compilation ; Off ; Off ;
; Use TimeQuest Timing Analyzer ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
@@ -245,9 +246,9 @@ The pin-out file can be found in D:/projects/quartus/38_decoder/38_decoder.pin.
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
-; I0 ; 35 ; 1 ; 0 ; 7 ; 1 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; I1 ; 14 ; 1 ; 0 ; 14 ; 2 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; I2 ; 41 ; 1 ; 0 ; 4 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; I0 ; 77 ; 4 ; 18 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; I1 ; 80 ; 4 ; 23 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; I2 ; 81 ; 4 ; 23 ; 0 ; 1 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
@@ -256,27 +257,27 @@ The pin-out file can be found in D:/projects/quartus/38_decoder/38_decoder.pin.
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
-; Y0 ; 45 ; 1 ; 0 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; Y1 ; 37 ; 1 ; 0 ; 6 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; Y2 ; 195 ; 2 ; 9 ; 19 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; Y3 ; 33 ; 1 ; 0 ; 8 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; Y4 ; 30 ; 1 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; Y5 ; 208 ; 2 ; 1 ; 19 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; Y6 ; 34 ; 1 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; Y7 ; 39 ; 1 ; 0 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; Y0 ; 142 ; 3 ; 34 ; 12 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; Y1 ; 143 ; 3 ; 34 ; 13 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; Y2 ; 144 ; 3 ; 34 ; 13 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; Y3 ; 145 ; 3 ; 34 ; 14 ; 4 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; Y4 ; 146 ; 3 ; 34 ; 15 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; Y5 ; 147 ; 3 ; 34 ; 15 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; Y6 ; 149 ; 3 ; 34 ; 16 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; Y7 ; 150 ; 3 ; 34 ; 16 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
-+------------------------------------------------------------+
-; I/O Bank Usage ;
-+----------+------------------+---------------+--------------+
-; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
-+----------+------------------+---------------+--------------+
-; 1 ; 11 / 32 ( 34 % ) ; 3.3V ; -- ;
-; 2 ; 2 / 35 ( 6 % ) ; 3.3V ; -- ;
-; 3 ; 1 / 35 ( 3 % ) ; 3.3V ; -- ;
-; 4 ; 0 / 36 ( 0 % ) ; 3.3V ; -- ;
-+----------+------------------+---------------+--------------+
++-----------------------------------------------------------+
+; I/O Bank Usage ;
++----------+-----------------+---------------+--------------+
+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
++----------+-----------------+---------------+--------------+
+; 1 ; 2 / 32 ( 6 % ) ; 3.3V ; -- ;
+; 2 ; 0 / 35 ( 0 % ) ; 3.3V ; -- ;
+; 3 ; 9 / 35 ( 26 % ) ; 3.3V ; -- ;
+; 4 ; 3 / 36 ( 8 % ) ; 3.3V ; -- ;
++----------+-----------------+---------------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -286,19 +287,19 @@ The pin-out file can be found in D:/projects/quartus/38_decoder/38_decoder.pin.
+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; 1 ; 0 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
; 2 ; 1 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
-; 3 ; 2 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 4 ; 3 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 5 ; 4 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 6 ; 5 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 3 ; 2 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 4 ; 3 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 5 ; 4 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 6 ; 5 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 8 ; 6 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 8 ; 6 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 10 ; 7 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 11 ; 8 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 12 ; 9 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 13 ; 10 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 14 ; 18 ; 1 ; I1 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 15 ; 19 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 10 ; 7 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 11 ; 8 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 12 ; 9 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 13 ; 10 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 14 ; 18 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 15 ; 19 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
; 18 ; 22 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
@@ -313,25 +314,25 @@ The pin-out file can be found in D:/projects/quartus/38_decoder/38_decoder.pin.
; 27 ; 30 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 28 ; 31 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 30 ; 32 ; 1 ; Y4 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 31 ; 33 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 30 ; 32 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 31 ; 33 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 33 ; 35 ; 1 ; Y3 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 34 ; 36 ; 1 ; Y6 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 35 ; 37 ; 1 ; I0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 33 ; 35 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 34 ; 36 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 35 ; 37 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 37 ; 39 ; 1 ; Y1 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 37 ; 39 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 39 ; 43 ; 1 ; Y7 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 40 ; 44 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 41 ; 45 ; 1 ; I2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 39 ; 43 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 40 ; 44 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 41 ; 45 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 42 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 43 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 44 ; 49 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 45 ; 50 ; 1 ; Y0 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 46 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 47 ; 52 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 48 ; 53 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 43 ; 48 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 44 ; 49 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 45 ; 50 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 46 ; 51 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 47 ; 52 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 48 ; 53 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 49 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 50 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
; 51 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
@@ -339,69 +340,69 @@ The pin-out file can be found in D:/projects/quartus/38_decoder/38_decoder.pin.
; 53 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 54 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
; 55 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 56 ; 54 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 57 ; 55 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 58 ; 56 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 59 ; 57 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 60 ; 58 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 61 ; 59 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 56 ; 54 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 57 ; 55 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 58 ; 56 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 59 ; 57 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 60 ; 58 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 61 ; 59 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 63 ; 60 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 64 ; 61 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 63 ; 60 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 64 ; 61 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 67 ; 69 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 68 ; 70 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 69 ; 71 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 70 ; 74 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 67 ; 69 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 68 ; 70 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 69 ; 71 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 70 ; 74 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 71 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 72 ; 75 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 72 ; 75 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 74 ; 76 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 75 ; 77 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 76 ; 78 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 77 ; 79 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 74 ; 76 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 75 ; 77 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 76 ; 78 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 77 ; 79 ; 4 ; I0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 80 ; 82 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 81 ; 83 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 82 ; 84 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 80 ; 82 ; 4 ; I1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 81 ; 83 ; 4 ; I2 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 82 ; 84 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 83 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 84 ; 85 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 84 ; 85 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 85 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 86 ; 86 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 87 ; 87 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 88 ; 88 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 89 ; 89 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 90 ; 90 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 86 ; 86 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 87 ; 87 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 88 ; 88 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 89 ; 89 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 90 ; 90 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 91 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 92 ; 91 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 92 ; 91 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 94 ; 92 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 95 ; 93 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 96 ; 94 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 97 ; 95 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 94 ; 92 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 95 ; 93 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 96 ; 94 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 97 ; 95 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 98 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 99 ; 96 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 99 ; 96 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 100 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 101 ; 97 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 102 ; 98 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 103 ; 99 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 104 ; 100 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 105 ; 101 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 106 ; 102 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 107 ; 105 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 101 ; 97 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 102 ; 98 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 103 ; 99 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 104 ; 100 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 105 ; 101 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 106 ; 102 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 107 ; 105 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 108 ; 106 ; 3 ; ~LVDS54p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 109 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 110 ; 107 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 110 ; 107 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 111 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 112 ; 108 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 113 ; 109 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 114 ; 110 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 115 ; 112 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 116 ; 113 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 117 ; 114 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 118 ; 117 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 112 ; 108 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 113 ; 109 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 114 ; 110 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 115 ; 112 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 116 ; 113 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 117 ; 114 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 118 ; 117 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 119 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 120 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 121 ; 121 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
@@ -410,32 +411,32 @@ The pin-out file can be found in D:/projects/quartus/38_decoder/38_decoder.pin.
; 124 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 125 ; 123 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
; 126 ; 124 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
-; 127 ; 125 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 128 ; 126 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 127 ; 125 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 128 ; 126 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 129 ; 127 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 130 ; 128 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 131 ; 129 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 132 ; 130 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; 133 ; 131 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 134 ; 132 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 135 ; 133 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 133 ; 131 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 134 ; 132 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 135 ; 133 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 136 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 137 ; 134 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 138 ; 135 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 139 ; 136 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 137 ; 134 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 138 ; 135 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 139 ; 136 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 141 ; 137 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 142 ; 138 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 143 ; 141 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 144 ; 142 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 145 ; 143 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 146 ; 149 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 147 ; 150 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 141 ; 137 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 142 ; 138 ; 3 ; Y0 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 143 ; 141 ; 3 ; Y1 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 144 ; 142 ; 3 ; Y2 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 145 ; 143 ; 3 ; Y3 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 146 ; 149 ; 3 ; Y4 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 147 ; 150 ; 3 ; Y5 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 148 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 149 ; 151 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 150 ; 152 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 151 ; 153 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 152 ; 154 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 149 ; 151 ; 3 ; Y6 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 150 ; 152 ; 3 ; Y7 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 151 ; 153 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 152 ; 154 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 153 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 154 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
; 155 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
@@ -443,55 +444,55 @@ The pin-out file can be found in D:/projects/quartus/38_decoder/38_decoder.pin.
; 157 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 158 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
; 159 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 160 ; 155 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 161 ; 156 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 162 ; 157 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 163 ; 158 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 164 ; 159 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 165 ; 160 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 160 ; 155 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 161 ; 156 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 162 ; 157 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 163 ; 158 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 164 ; 159 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 165 ; 160 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 166 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 167 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 168 ; 161 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 169 ; 162 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 170 ; 163 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 171 ; 164 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 168 ; 161 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 169 ; 162 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 170 ; 163 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 171 ; 164 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 172 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 173 ; 165 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 173 ; 165 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 174 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 175 ; 168 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 176 ; 169 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 175 ; 168 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 176 ; 169 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 177 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 178 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 179 ; 173 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 180 ; 174 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 181 ; 175 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 182 ; 176 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 179 ; 173 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 180 ; 174 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 181 ; 175 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 182 ; 176 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 183 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 184 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 185 ; 180 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 185 ; 180 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 186 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 187 ; 181 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 188 ; 182 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 189 ; 183 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 187 ; 181 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 188 ; 182 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 189 ; 183 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 190 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 191 ; 184 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 192 ; 185 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 193 ; 186 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 191 ; 184 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 192 ; 185 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 193 ; 186 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 194 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 195 ; 187 ; 2 ; Y2 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 195 ; 187 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 196 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 197 ; 191 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 198 ; 192 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 199 ; 195 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 200 ; 196 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 201 ; 197 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 197 ; 191 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 198 ; 192 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 199 ; 195 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 200 ; 196 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 201 ; 197 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 202 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 203 ; 198 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 203 ; 198 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 204 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 205 ; 199 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 206 ; 200 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 207 ; 201 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 208 ; 202 ; 2 ; Y5 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 205 ; 199 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 206 ; 200 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 207 ; 201 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 208 ; 202 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
@@ -568,15 +569,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
+---------------------+-------------------+---------+
; I2 ; ; ;
-; - inst10~0 ; 1 ; 6 ;
-; - inst10~1 ; 1 ; 6 ;
-; - inst10~2 ; 1 ; 6 ;
-; - inst10~3 ; 1 ; 6 ;
-; - inst10~4 ; 1 ; 6 ;
-; - inst10~5 ; 1 ; 6 ;
-; - inst10~6 ; 1 ; 6 ;
-; - inst10~7 ; 1 ; 6 ;
-; I0 ; ; ;
; - inst10~0 ; 0 ; 6 ;
; - inst10~1 ; 0 ; 6 ;
; - inst10~2 ; 0 ; 6 ;
@@ -585,6 +577,15 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; - inst10~5 ; 0 ; 6 ;
; - inst10~6 ; 0 ; 6 ;
; - inst10~7 ; 0 ; 6 ;
+; I0 ; ; ;
+; - inst10~0 ; 1 ; 6 ;
+; - inst10~1 ; 1 ; 6 ;
+; - inst10~2 ; 1 ; 6 ;
+; - inst10~3 ; 1 ; 6 ;
+; - inst10~4 ; 1 ; 6 ;
+; - inst10~5 ; 1 ; 6 ;
+; - inst10~6 ; 1 ; 6 ;
+; - inst10~7 ; 1 ; 6 ;
; I1 ; ; ;
; - inst10~0 ; 1 ; 6 ;
; - inst10~1 ; 1 ; 6 ;
@@ -622,13 +623,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Interconnect Resource Type ; Usage ;
+----------------------------+-----------------------+
; Block interconnects ; 11 / 26,052 ( < 1 % ) ;
-; C16 interconnects ; 0 / 1,156 ( 0 % ) ;
-; C4 interconnects ; 13 / 17,952 ( < 1 % ) ;
-; Direct links ; 1 / 26,052 ( < 1 % ) ;
+; C16 interconnects ; 4 / 1,156 ( < 1 % ) ;
+; C4 interconnects ; 9 / 17,952 ( < 1 % ) ;
+; Direct links ; 2 / 26,052 ( < 1 % ) ;
; Global clocks ; 0 / 8 ( 0 % ) ;
; Local interconnects ; 0 / 8,256 ( 0 % ) ;
-; R24 interconnects ; 0 / 1,020 ( 0 % ) ;
-; R4 interconnects ; 4 / 22,440 ( < 1 % ) ;
+; R24 interconnects ; 3 / 1,020 ( < 1 % ) ;
+; R4 interconnects ; 1 / 22,440 ( < 1 % ) ;
+----------------------------+-----------------------+
@@ -715,7 +716,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Error detection CRC ; Off ;
; nCEO ; As output driving ground ;
; ASDO,nCSO ; As input tri-stated ;
-; Reserve all unused pins ; As output driving ground ;
+; Reserve all unused pins ; As input tri-stated ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+--------------------------+
@@ -810,20 +811,19 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+------------------------------------+------------+
-+---------------------------------------------------+
-; Advanced Data - Routing ;
-+-------------------------------------+-------------+
-; Name ; Value ;
-+-------------------------------------+-------------+
-; Early Slack - Fit Attempt 1 ; 2147483639 ;
-; Mid Slack - Fit Attempt 1 ; 2147483639 ;
-; Late Slack - Fit Attempt 1 ; -2147483648 ;
-; Early Wire Use - Fit Attempt 1 ; 0 ;
-; Peak Regional Wire - Fit Attempt 1 ; 0 ;
-; Late Wire Use - Fit Attempt 1 ; 0 ;
-; Time - Fit Attempt 1 ; 0 ;
-; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016 ;
-+-------------------------------------+-------------+
++--------------------------------------------------+
+; Advanced Data - Routing ;
++------------------------------------+-------------+
+; Name ; Value ;
++------------------------------------+-------------+
+; Early Slack - Fit Attempt 1 ; 2147483639 ;
+; Mid Slack - Fit Attempt 1 ; 2147483639 ;
+; Late Slack - Fit Attempt 1 ; -2147483648 ;
+; Early Wire Use - Fit Attempt 1 ; 0 ;
+; Peak Regional Wire - Fit Attempt 1 ; 0 ;
+; Late Wire Use - Fit Attempt 1 ; 0 ;
+; Time - Fit Attempt 1 ; 0 ;
++------------------------------------+-------------+
+-----------------+
@@ -832,7 +832,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
- Info: Processing started: Mon Mar 07 09:13:05 2022
+ Info: Processing started: Tue Mar 08 15:12:39 2022
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Info: Selected device EP2C8Q208C8 for design "38_decoder"
@@ -847,32 +847,11 @@ Info: Fitter converted 3 user pins into dedicated programming pins
Info: Pin ~ASDO~ is reserved at location 1
Info: Pin ~nCSO~ is reserved at location 2
Info: Pin ~LVDS54p/nCEO~ is reserved at location 108
-Warning: No exact pin location assignment(s) for 11 pins of 11 total pins
- Info: Pin Y7 not assigned to an exact location on the device
- Info: Pin Y0 not assigned to an exact location on the device
- Info: Pin Y1 not assigned to an exact location on the device
- Info: Pin Y2 not assigned to an exact location on the device
- Info: Pin Y3 not assigned to an exact location on the device
- Info: Pin Y4 not assigned to an exact location on the device
- Info: Pin Y5 not assigned to an exact location on the device
- Info: Pin Y6 not assigned to an exact location on the device
- Info: Pin I2 not assigned to an exact location on the device
- Info: Pin I0 not assigned to an exact location on the device
- Info: Pin I1 not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Starting register packing
Info: Finished register packing
Extra Info: No registers were packed into other blocks
-Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
- Info: Number of I/O pins in group: 11 (unused VREF, 3.3V VCCIO, 3 input, 8 output, 0 bidirectional)
- Info: I/O standards used: 3.3-V LVTTL.
-Info: I/O bank details before I/O pin placement
- Info: Statistics of I/O banks
- Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available
- Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available
- Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available
- Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available
Info: Fitter preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
@@ -881,7 +860,7 @@ Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources
- Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9
+ Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y10 to location X34_Y19
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
@@ -897,11 +876,10 @@ Warning: Found 8 output pins without output pin load capacitance assignment
Info: Pin "Y5" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "Y6" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
-Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Generated suppressed messages file D:/projects/quartus/38_decoder/38_decoder.fit.smsg
-Info: Quartus II Fitter was successful. 0 errors, 3 warnings
- Info: Peak virtual memory: 306 megabytes
- Info: Processing ended: Mon Mar 07 09:13:06 2022
+Info: Quartus II Fitter was successful. 0 errors, 1 warning
+ Info: Peak virtual memory: 305 megabytes
+ Info: Processing ended: Tue Mar 08 15:12:40 2022
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
diff --git a/38_decoder/38_decoder.fit.summary b/38_decoder/38_decoder.fit.summary
index 23abfbc..7cbb3c9 100644
--- a/38_decoder/38_decoder.fit.summary
+++ b/38_decoder/38_decoder.fit.summary
@@ -1,4 +1,4 @@
-Fitter Status : Successful - Mon Mar 07 09:13:06 2022
+Fitter Status : Successful - Tue Mar 08 15:12:40 2022
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : 38_decoder
Top-level Entity Name : 38_decoder
diff --git a/38_decoder/38_decoder.flow.rpt b/38_decoder/38_decoder.flow.rpt
index 3452d9e..b8b1298 100644
--- a/38_decoder/38_decoder.flow.rpt
+++ b/38_decoder/38_decoder.flow.rpt
@@ -1,5 +1,5 @@
Flow report for 38_decoder
-Mon Mar 07 09:13:08 2022
+Tue Mar 08 15:12:42 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@@ -38,7 +38,7 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+----------------------------------------------+
-; Flow Status ; Successful - Mon Mar 07 09:13:08 2022 ;
+; Flow Status ; Successful - Tue Mar 08 15:12:42 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; 38_decoder ;
; Top-level Entity Name ; 38_decoder ;
@@ -63,7 +63,7 @@ applicable agreement for further details.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
-; Start date & time ; 03/07/2022 09:13:04 ;
+; Start date & time ; 03/08/2022 15:12:38 ;
; Main task ; Compilation ;
; Revision Name ; 38_decoder ;
+-------------------+---------------------+
@@ -74,7 +74,7 @@ applicable agreement for further details.
+------------------------------------+-----------------------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+------------------------------------+-----------------------------------------------+---------------+-------------+----------------+
-; COMPILER_SIGNATURE_ID ; 220283517943889.164661558410840 ; -- ; -- ; -- ;
+; COMPILER_SIGNATURE_ID ; 220283517943889.164672355814724 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; MISC_FILE ; D:/projects/quartus/38_decoder/38_decoder.dpf ; -- ; -- ; -- ;
@@ -89,8 +89,8 @@ applicable agreement for further details.
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 245 MB ; 00:00:00 ;
-; Fitter ; 00:00:01 ; 1.0 ; 306 MB ; 00:00:01 ;
+; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 246 MB ; 00:00:00 ;
+; Fitter ; 00:00:01 ; 1.0 ; 305 MB ; 00:00:01 ;
; Assembler ; 00:00:00 ; 1.0 ; 241 MB ; 00:00:00 ;
; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 198 MB ; 00:00:00 ;
; Total ; 00:00:01 ; -- ; -- ; 00:00:01 ;
diff --git a/38_decoder/38_decoder.map.rpt b/38_decoder/38_decoder.map.rpt
index ee4c415..6f633ef 100644
--- a/38_decoder/38_decoder.map.rpt
+++ b/38_decoder/38_decoder.map.rpt
@@ -1,5 +1,5 @@
Analysis & Synthesis report for 38_decoder
-Mon Mar 07 09:13:04 2022
+Tue Mar 08 15:12:38 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@@ -39,7 +39,7 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+----------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Mon Mar 07 09:13:04 2022 ;
+; Analysis & Synthesis Status ; Successful - Tue Mar 08 15:12:38 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; 38_decoder ;
; Top-level Entity Name ; 38_decoder ;
@@ -200,7 +200,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
- Info: Processing started: Mon Mar 07 09:13:04 2022
+ Info: Processing started: Tue Mar 08 15:12:38 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off 38_decoder -c 38_decoder
Info: Found 1 design units, including 1 entities, in source file 38_decoder.bdf
Info: Found entity 1: 38_decoder
@@ -210,8 +210,8 @@ Info: Implemented 19 device resources after synthesis - the final resource count
Info: Implemented 8 output pins
Info: Implemented 8 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
- Info: Peak virtual memory: 248 megabytes
- Info: Processing ended: Mon Mar 07 09:13:04 2022
+ Info: Peak virtual memory: 250 megabytes
+ Info: Processing ended: Tue Mar 08 15:12:38 2022
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00
diff --git a/38_decoder/38_decoder.map.summary b/38_decoder/38_decoder.map.summary
index 20c6ab9..e76f577 100644
--- a/38_decoder/38_decoder.map.summary
+++ b/38_decoder/38_decoder.map.summary
@@ -1,4 +1,4 @@
-Analysis & Synthesis Status : Successful - Mon Mar 07 09:13:04 2022
+Analysis & Synthesis Status : Successful - Tue Mar 08 15:12:38 2022
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : 38_decoder
Top-level Entity Name : 38_decoder
diff --git a/38_decoder/38_decoder.pin b/38_decoder/38_decoder.pin
index 32bdd6e..0a6f10c 100644
--- a/38_decoder/38_decoder.pin
+++ b/38_decoder/38_decoder.pin
@@ -70,19 +70,19 @@ Pin Name/Usage : Location : Dir. : I/O Standard : Voltage
-------------------------------------------------------------------------------------------------------------
~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVTTL : : 1 : N
~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVTTL : : 1 : N
-GND* : 3 : : : : 1 :
-GND* : 4 : : : : 1 :
-GND* : 5 : : : : 1 :
-GND* : 6 : : : : 1 :
+RESERVED_INPUT : 3 : : : : 1 :
+RESERVED_INPUT : 4 : : : : 1 :
+RESERVED_INPUT : 5 : : : : 1 :
+RESERVED_INPUT : 6 : : : : 1 :
VCCIO1 : 7 : power : : 3.3V : 1 :
-GND* : 8 : : : : 1 :
+RESERVED_INPUT : 8 : : : : 1 :
GND : 9 : gnd : : : :
-GND* : 10 : : : : 1 :
-GND* : 11 : : : : 1 :
-GND* : 12 : : : : 1 :
-GND* : 13 : : : : 1 :
-I1 : 14 : input : 3.3-V LVTTL : : 1 : N
-GND* : 15 : : : : 1 :
+RESERVED_INPUT : 10 : : : : 1 :
+RESERVED_INPUT : 11 : : : : 1 :
+RESERVED_INPUT : 12 : : : : 1 :
+RESERVED_INPUT : 13 : : : : 1 :
+RESERVED_INPUT : 14 : : : : 1 :
+RESERVED_INPUT : 15 : : : : 1 :
TDO : 16 : output : : : 1 :
TMS : 17 : input : : : 1 :
TCK : 18 : input : : : 1 :
@@ -97,25 +97,25 @@ nCONFIG : 26 : : :
GND+ : 27 : : : : 1 :
GND+ : 28 : : : : 1 :
VCCIO1 : 29 : power : : 3.3V : 1 :
-Y4 : 30 : output : 3.3-V LVTTL : : 1 : N
-GND* : 31 : : : : 1 :
+RESERVED_INPUT : 30 : : : : 1 :
+RESERVED_INPUT : 31 : : : : 1 :
VCCINT : 32 : power : : 1.2V : :
-Y3 : 33 : output : 3.3-V LVTTL : : 1 : N
-Y6 : 34 : output : 3.3-V LVTTL : : 1 : N
-I0 : 35 : input : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 33 : : : : 1 :
+RESERVED_INPUT : 34 : : : : 1 :
+RESERVED_INPUT : 35 : : : : 1 :
GND : 36 : gnd : : : :
-Y1 : 37 : output : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 37 : : : : 1 :
GND : 38 : gnd : : : :
-Y7 : 39 : output : 3.3-V LVTTL : : 1 : N
-GND* : 40 : : : : 1 :
-I2 : 41 : input : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 39 : : : : 1 :
+RESERVED_INPUT : 40 : : : : 1 :
+RESERVED_INPUT : 41 : : : : 1 :
VCCIO1 : 42 : power : : 3.3V : 1 :
-GND* : 43 : : : : 1 :
-GND* : 44 : : : : 1 :
-Y0 : 45 : output : 3.3-V LVTTL : : 1 : N
-GND* : 46 : : : : 1 :
-GND* : 47 : : : : 1 :
-GND* : 48 : : : : 1 :
+RESERVED_INPUT : 43 : : : : 1 :
+RESERVED_INPUT : 44 : : : : 1 :
+RESERVED_INPUT : 45 : : : : 1 :
+RESERVED_INPUT : 46 : : : : 1 :
+RESERVED_INPUT : 47 : : : : 1 :
+RESERVED_INPUT : 48 : : : : 1 :
GND : 49 : gnd : : : :
GND_PLL1 : 50 : gnd : : : :
VCCD_PLL1 : 51 : power : : 1.2V : :
@@ -123,69 +123,69 @@ GND_PLL1 : 52 : gnd : :
VCCA_PLL1 : 53 : power : : 1.2V : :
GNDA_PLL1 : 54 : gnd : : : :
GND : 55 : gnd : : : :
-GND* : 56 : : : : 4 :
-GND* : 57 : : : : 4 :
-GND* : 58 : : : : 4 :
-GND* : 59 : : : : 4 :
-GND* : 60 : : : : 4 :
-GND* : 61 : : : : 4 :
+RESERVED_INPUT : 56 : : : : 4 :
+RESERVED_INPUT : 57 : : : : 4 :
+RESERVED_INPUT : 58 : : : : 4 :
+RESERVED_INPUT : 59 : : : : 4 :
+RESERVED_INPUT : 60 : : : : 4 :
+RESERVED_INPUT : 61 : : : : 4 :
VCCIO4 : 62 : power : : 3.3V : 4 :
-GND* : 63 : : : : 4 :
-GND* : 64 : : : : 4 :
+RESERVED_INPUT : 63 : : : : 4 :
+RESERVED_INPUT : 64 : : : : 4 :
GND : 65 : gnd : : : :
VCCINT : 66 : power : : 1.2V : :
-GND* : 67 : : : : 4 :
-GND* : 68 : : : : 4 :
-GND* : 69 : : : : 4 :
-GND* : 70 : : : : 4 :
+RESERVED_INPUT : 67 : : : : 4 :
+RESERVED_INPUT : 68 : : : : 4 :
+RESERVED_INPUT : 69 : : : : 4 :
+RESERVED_INPUT : 70 : : : : 4 :
VCCIO4 : 71 : power : : 3.3V : 4 :
-GND* : 72 : : : : 4 :
+RESERVED_INPUT : 72 : : : : 4 :
GND : 73 : gnd : : : :
-GND* : 74 : : : : 4 :
-GND* : 75 : : : : 4 :
-GND* : 76 : : : : 4 :
-GND* : 77 : : : : 4 :
+RESERVED_INPUT : 74 : : : : 4 :
+RESERVED_INPUT : 75 : : : : 4 :
+RESERVED_INPUT : 76 : : : : 4 :
+I0 : 77 : input : 3.3-V LVTTL : : 4 : Y
GND : 78 : gnd : : : :
VCCINT : 79 : power : : 1.2V : :
-GND* : 80 : : : : 4 :
-GND* : 81 : : : : 4 :
-GND* : 82 : : : : 4 :
+I1 : 80 : input : 3.3-V LVTTL : : 4 : Y
+I2 : 81 : input : 3.3-V LVTTL : : 4 : Y
+RESERVED_INPUT : 82 : : : : 4 :
VCCIO4 : 83 : power : : 3.3V : 4 :
-GND* : 84 : : : : 4 :
+RESERVED_INPUT : 84 : : : : 4 :
GND : 85 : gnd : : : :
-GND* : 86 : : : : 4 :
-GND* : 87 : : : : 4 :
-GND* : 88 : : : : 4 :
-GND* : 89 : : : : 4 :
-GND* : 90 : : : : 4 :
+RESERVED_INPUT : 86 : : : : 4 :
+RESERVED_INPUT : 87 : : : : 4 :
+RESERVED_INPUT : 88 : : : : 4 :
+RESERVED_INPUT : 89 : : : : 4 :
+RESERVED_INPUT : 90 : : : : 4 :
VCCIO4 : 91 : power : : 3.3V : 4 :
-GND* : 92 : : : : 4 :
+RESERVED_INPUT : 92 : : : : 4 :
GND : 93 : gnd : : : :
-GND* : 94 : : : : 4 :
-GND* : 95 : : : : 4 :
-GND* : 96 : : : : 4 :
-GND* : 97 : : : : 4 :
+RESERVED_INPUT : 94 : : : : 4 :
+RESERVED_INPUT : 95 : : : : 4 :
+RESERVED_INPUT : 96 : : : : 4 :
+RESERVED_INPUT : 97 : : : : 4 :
VCCIO4 : 98 : power : : 3.3V : 4 :
-GND* : 99 : : : : 4 :
+RESERVED_INPUT : 99 : : : : 4 :
GND : 100 : gnd : : : :
-GND* : 101 : : : : 4 :
-GND* : 102 : : : : 4 :
-GND* : 103 : : : : 4 :
-GND* : 104 : : : : 4 :
-GND* : 105 : : : : 3 :
-GND* : 106 : : : : 3 :
-GND* : 107 : : : : 3 :
+RESERVED_INPUT : 101 : : : : 4 :
+RESERVED_INPUT : 102 : : : : 4 :
+RESERVED_INPUT : 103 : : : : 4 :
+RESERVED_INPUT : 104 : : : : 4 :
+RESERVED_INPUT : 105 : : : : 3 :
+RESERVED_INPUT : 106 : : : : 3 :
+RESERVED_INPUT : 107 : : : : 3 :
~LVDS54p/nCEO~ : 108 : output : 3.3-V LVTTL : : 3 : N
VCCIO3 : 109 : power : : 3.3V : 3 :
-GND* : 110 : : : : 3 :
+RESERVED_INPUT : 110 : : : : 3 :
GND : 111 : gnd : : : :
-GND* : 112 : : : : 3 :
-GND* : 113 : : : : 3 :
-GND* : 114 : : : : 3 :
-GND* : 115 : : : : 3 :
-GND* : 116 : : : : 3 :
-GND* : 117 : : : : 3 :
-GND* : 118 : : : : 3 :
+RESERVED_INPUT : 112 : : : : 3 :
+RESERVED_INPUT : 113 : : : : 3 :
+RESERVED_INPUT : 114 : : : : 3 :
+RESERVED_INPUT : 115 : : : : 3 :
+RESERVED_INPUT : 116 : : : : 3 :
+RESERVED_INPUT : 117 : : : : 3 :
+RESERVED_INPUT : 118 : : : : 3 :
GND : 119 : gnd : : : :
VCCINT : 120 : power : : 1.2V : :
nSTATUS : 121 : : : : 3 :
@@ -194,32 +194,32 @@ CONF_DONE : 123 : : :
GND : 124 : gnd : : : :
MSEL1 : 125 : : : : 3 :
MSEL0 : 126 : : : : 3 :
-GND* : 127 : : : : 3 :
-GND* : 128 : : : : 3 :
+RESERVED_INPUT : 127 : : : : 3 :
+RESERVED_INPUT : 128 : : : : 3 :
GND+ : 129 : : : : 3 :
GND+ : 130 : : : : 3 :
GND+ : 131 : : : : 3 :
GND+ : 132 : : : : 3 :
-GND* : 133 : : : : 3 :
-GND* : 134 : : : : 3 :
-GND* : 135 : : : : 3 :
+RESERVED_INPUT : 133 : : : : 3 :
+RESERVED_INPUT : 134 : : : : 3 :
+RESERVED_INPUT : 135 : : : : 3 :
VCCIO3 : 136 : power : : 3.3V : 3 :
-GND* : 137 : : : : 3 :
-GND* : 138 : : : : 3 :
-GND* : 139 : : : : 3 :
+RESERVED_INPUT : 137 : : : : 3 :
+RESERVED_INPUT : 138 : : : : 3 :
+RESERVED_INPUT : 139 : : : : 3 :
GND : 140 : gnd : : : :
-GND* : 141 : : : : 3 :
-GND* : 142 : : : : 3 :
-GND* : 143 : : : : 3 :
-GND* : 144 : : : : 3 :
-GND* : 145 : : : : 3 :
-GND* : 146 : : : : 3 :
-GND* : 147 : : : : 3 :
+RESERVED_INPUT : 141 : : : : 3 :
+Y0 : 142 : output : 3.3-V LVTTL : : 3 : Y
+Y1 : 143 : output : 3.3-V LVTTL : : 3 : Y
+Y2 : 144 : output : 3.3-V LVTTL : : 3 : Y
+Y3 : 145 : output : 3.3-V LVTTL : : 3 : Y
+Y4 : 146 : output : 3.3-V LVTTL : : 3 : Y
+Y5 : 147 : output : 3.3-V LVTTL : : 3 : Y
VCCIO3 : 148 : power : : 3.3V : 3 :
-GND* : 149 : : : : 3 :
-GND* : 150 : : : : 3 :
-GND* : 151 : : : : 3 :
-GND* : 152 : : : : 3 :
+Y6 : 149 : output : 3.3-V LVTTL : : 3 : Y
+Y7 : 150 : output : 3.3-V LVTTL : : 3 : Y
+RESERVED_INPUT : 151 : : : : 3 :
+RESERVED_INPUT : 152 : : : : 3 :
GND : 153 : gnd : : : :
GND_PLL2 : 154 : gnd : : : :
VCCD_PLL2 : 155 : power : : 1.2V : :
@@ -227,52 +227,52 @@ GND_PLL2 : 156 : gnd : :
VCCA_PLL2 : 157 : power : : 1.2V : :
GNDA_PLL2 : 158 : gnd : : : :
GND : 159 : gnd : : : :
-GND* : 160 : : : : 2 :
-GND* : 161 : : : : 2 :
-GND* : 162 : : : : 2 :
-GND* : 163 : : : : 2 :
-GND* : 164 : : : : 2 :
-GND* : 165 : : : : 2 :
+RESERVED_INPUT : 160 : : : : 2 :
+RESERVED_INPUT : 161 : : : : 2 :
+RESERVED_INPUT : 162 : : : : 2 :
+RESERVED_INPUT : 163 : : : : 2 :
+RESERVED_INPUT : 164 : : : : 2 :
+RESERVED_INPUT : 165 : : : : 2 :
VCCIO2 : 166 : power : : 3.3V : 2 :
GND : 167 : gnd : : : :
-GND* : 168 : : : : 2 :
-GND* : 169 : : : : 2 :
-GND* : 170 : : : : 2 :
-GND* : 171 : : : : 2 :
+RESERVED_INPUT : 168 : : : : 2 :
+RESERVED_INPUT : 169 : : : : 2 :
+RESERVED_INPUT : 170 : : : : 2 :
+RESERVED_INPUT : 171 : : : : 2 :
VCCIO2 : 172 : power : : 3.3V : 2 :
-GND* : 173 : : : : 2 :
+RESERVED_INPUT : 173 : : : : 2 :
GND : 174 : gnd : : : :
-GND* : 175 : : : : 2 :
-GND* : 176 : : : : 2 :
+RESERVED_INPUT : 175 : : : : 2 :
+RESERVED_INPUT : 176 : : : : 2 :
GND : 177 : gnd : : : :
VCCINT : 178 : power : : 1.2V : :
-GND* : 179 : : : : 2 :
-GND* : 180 : : : : 2 :
-GND* : 181 : : : : 2 :
-GND* : 182 : : : : 2 :
+RESERVED_INPUT : 179 : : : : 2 :
+RESERVED_INPUT : 180 : : : : 2 :
+RESERVED_INPUT : 181 : : : : 2 :
+RESERVED_INPUT : 182 : : : : 2 :
VCCIO2 : 183 : power : : 3.3V : 2 :
GND : 184 : gnd : : : :
-GND* : 185 : : : : 2 :
+RESERVED_INPUT : 185 : : : : 2 :
GND : 186 : gnd : : : :
-GND* : 187 : : : : 2 :
-GND* : 188 : : : : 2 :
-GND* : 189 : : : : 2 :
+RESERVED_INPUT : 187 : : : : 2 :
+RESERVED_INPUT : 188 : : : : 2 :
+RESERVED_INPUT : 189 : : : : 2 :
VCCINT : 190 : power : : 1.2V : :
-GND* : 191 : : : : 2 :
-GND* : 192 : : : : 2 :
-GND* : 193 : : : : 2 :
+RESERVED_INPUT : 191 : : : : 2 :
+RESERVED_INPUT : 192 : : : : 2 :
+RESERVED_INPUT : 193 : : : : 2 :
VCCIO2 : 194 : power : : 3.3V : 2 :
-Y2 : 195 : output : 3.3-V LVTTL : : 2 : N
+RESERVED_INPUT : 195 : : : : 2 :
GND : 196 : gnd : : : :
-GND* : 197 : : : : 2 :
-GND* : 198 : : : : 2 :
-GND* : 199 : : : : 2 :
-GND* : 200 : : : : 2 :
-GND* : 201 : : : : 2 :
+RESERVED_INPUT : 197 : : : : 2 :
+RESERVED_INPUT : 198 : : : : 2 :
+RESERVED_INPUT : 199 : : : : 2 :
+RESERVED_INPUT : 200 : : : : 2 :
+RESERVED_INPUT : 201 : : : : 2 :
VCCIO2 : 202 : power : : 3.3V : 2 :
-GND* : 203 : : : : 2 :
+RESERVED_INPUT : 203 : : : : 2 :
GND : 204 : gnd : : : :
-GND* : 205 : : : : 2 :
-GND* : 206 : : : : 2 :
-GND* : 207 : : : : 2 :
-Y5 : 208 : output : 3.3-V LVTTL : : 2 : N
+RESERVED_INPUT : 205 : : : : 2 :
+RESERVED_INPUT : 206 : : : : 2 :
+RESERVED_INPUT : 207 : : : : 2 :
+RESERVED_INPUT : 208 : : : : 2 :
diff --git a/38_decoder/38_decoder.pof b/38_decoder/38_decoder.pof
index bbba2ec..5959345 100644
Binary files a/38_decoder/38_decoder.pof and b/38_decoder/38_decoder.pof differ
diff --git a/38_decoder/38_decoder.qsf b/38_decoder/38_decoder.qsf
index c51ed34..bc0dcab 100644
--- a/38_decoder/38_decoder.qsf
+++ b/38_decoder/38_decoder.qsf
@@ -51,4 +51,18 @@ set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
\ No newline at end of file
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_location_assignment PIN_77 -to I0
+set_location_assignment PIN_80 -to I1
+set_location_assignment PIN_81 -to I2
+set_location_assignment PIN_142 -to Y0
+set_location_assignment PIN_143 -to Y1
+set_location_assignment PIN_144 -to Y2
+set_location_assignment PIN_145 -to Y3
+set_location_assignment PIN_146 -to Y4
+set_location_assignment PIN_147 -to Y5
+set_location_assignment PIN_149 -to Y6
+set_location_assignment PIN_150 -to Y7
\ No newline at end of file
diff --git a/38_decoder/38_decoder.sof b/38_decoder/38_decoder.sof
index 44209ac..d8f3d1a 100644
Binary files a/38_decoder/38_decoder.sof and b/38_decoder/38_decoder.sof differ
diff --git a/38_decoder/38_decoder.tan.rpt b/38_decoder/38_decoder.tan.rpt
index c0b61b4..08fe936 100644
--- a/38_decoder/38_decoder.tan.rpt
+++ b/38_decoder/38_decoder.tan.rpt
@@ -1,5 +1,5 @@
Classic Timing Analyzer report for 38_decoder
-Mon Mar 07 09:13:08 2022
+Tue Mar 08 15:12:42 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@@ -39,7 +39,7 @@ applicable agreement for further details.
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
-; Worst-case tpd ; N/A ; None ; 13.383 ns ; I2 ; Y2 ; -- ; -- ; 0 ;
+; Worst-case tpd ; N/A ; None ; 13.172 ns ; I2 ; Y4 ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
@@ -98,30 +98,30 @@ applicable agreement for further details.
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
-; N/A ; None ; 13.383 ns ; I2 ; Y2 ;
-; N/A ; None ; 13.370 ns ; I1 ; Y2 ;
-; N/A ; None ; 12.806 ns ; I0 ; Y2 ;
-; N/A ; None ; 12.348 ns ; I2 ; Y5 ;
-; N/A ; None ; 12.185 ns ; I1 ; Y5 ;
-; N/A ; None ; 11.620 ns ; I0 ; Y5 ;
-; N/A ; None ; 11.545 ns ; I2 ; Y4 ;
-; N/A ; None ; 11.530 ns ; I2 ; Y7 ;
-; N/A ; None ; 11.492 ns ; I2 ; Y0 ;
-; N/A ; None ; 11.439 ns ; I1 ; Y0 ;
-; N/A ; None ; 11.438 ns ; I2 ; Y1 ;
-; N/A ; None ; 11.402 ns ; I1 ; Y7 ;
-; N/A ; None ; 11.395 ns ; I1 ; Y4 ;
-; N/A ; None ; 11.382 ns ; I1 ; Y1 ;
-; N/A ; None ; 11.296 ns ; I1 ; Y3 ;
-; N/A ; None ; 11.292 ns ; I2 ; Y3 ;
-; N/A ; None ; 11.129 ns ; I2 ; Y6 ;
-; N/A ; None ; 11.012 ns ; I1 ; Y6 ;
-; N/A ; None ; 10.880 ns ; I0 ; Y0 ;
-; N/A ; None ; 10.837 ns ; I0 ; Y7 ;
-; N/A ; None ; 10.822 ns ; I0 ; Y1 ;
-; N/A ; None ; 10.819 ns ; I0 ; Y4 ;
-; N/A ; None ; 10.717 ns ; I0 ; Y3 ;
-; N/A ; None ; 10.444 ns ; I0 ; Y6 ;
+; N/A ; None ; 13.172 ns ; I2 ; Y4 ;
+; N/A ; None ; 13.161 ns ; I2 ; Y6 ;
+; N/A ; None ; 13.141 ns ; I2 ; Y5 ;
+; N/A ; None ; 13.095 ns ; I2 ; Y7 ;
+; N/A ; None ; 13.009 ns ; I2 ; Y3 ;
+; N/A ; None ; 12.995 ns ; I2 ; Y0 ;
+; N/A ; None ; 12.674 ns ; I1 ; Y6 ;
+; N/A ; None ; 12.658 ns ; I0 ; Y5 ;
+; N/A ; None ; 12.658 ns ; I1 ; Y4 ;
+; N/A ; None ; 12.648 ns ; I1 ; Y3 ;
+; N/A ; None ; 12.647 ns ; I2 ; Y1 ;
+; N/A ; None ; 12.636 ns ; I0 ; Y3 ;
+; N/A ; None ; 12.623 ns ; I1 ; Y7 ;
+; N/A ; None ; 12.619 ns ; I0 ; Y7 ;
+; N/A ; None ; 12.614 ns ; I0 ; Y4 ;
+; N/A ; None ; 12.612 ns ; I1 ; Y5 ;
+; N/A ; None ; 12.594 ns ; I0 ; Y6 ;
+; N/A ; None ; 12.580 ns ; I1 ; Y0 ;
+; N/A ; None ; 12.560 ns ; I2 ; Y2 ;
+; N/A ; None ; 12.535 ns ; I0 ; Y0 ;
+; N/A ; None ; 12.270 ns ; I0 ; Y1 ;
+; N/A ; None ; 12.241 ns ; I1 ; Y1 ;
+; N/A ; None ; 12.201 ns ; I1 ; Y2 ;
+; N/A ; None ; 12.104 ns ; I0 ; Y2 ;
+-------+-------------------+-----------------+------+----+
@@ -131,18 +131,18 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
- Info: Processing started: Mon Mar 07 09:13:08 2022
+ Info: Processing started: Tue Mar 08 15:12:42 2022
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder --timing_analysis_only
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info: Longest tpd from source pin "I2" to destination pin "Y2" is 13.383 ns
- Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_41; Fanout = 8; PIN Node = 'I2'
- Info: 2: + IC(5.786 ns) + CELL(0.499 ns) = 7.280 ns; Loc. = LCCOMB_X1_Y7_N22; Fanout = 1; COMB Node = 'inst10~3'
- Info: 3: + IC(2.847 ns) + CELL(3.256 ns) = 13.383 ns; Loc. = PIN_195; Fanout = 0; PIN Node = 'Y2'
- Info: Total cell delay = 4.750 ns ( 35.49 % )
- Info: Total interconnect delay = 8.633 ns ( 64.51 % )
+Info: Longest tpd from source pin "I2" to destination pin "Y4" is 13.172 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_81; Fanout = 8; PIN Node = 'I2'
+ Info: 2: + IC(7.387 ns) + CELL(0.651 ns) = 9.012 ns; Loc. = LCCOMB_X33_Y13_N2; Fanout = 1; COMB Node = 'inst10~5'
+ Info: 3: + IC(1.054 ns) + CELL(3.106 ns) = 13.172 ns; Loc. = PIN_146; Fanout = 0; PIN Node = 'Y4'
+ Info: Total cell delay = 4.731 ns ( 35.92 % )
+ Info: Total interconnect delay = 8.441 ns ( 64.08 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 212 megabytes
- Info: Processing ended: Mon Mar 07 09:13:08 2022
+ Info: Processing ended: Tue Mar 08 15:12:42 2022
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00
diff --git a/38_decoder/38_decoder.tan.summary b/38_decoder/38_decoder.tan.summary
index 372a7d7..beb25fd 100644
--- a/38_decoder/38_decoder.tan.summary
+++ b/38_decoder/38_decoder.tan.summary
@@ -5,9 +5,9 @@ Timing Analyzer Summary
Type : Worst-case tpd
Slack : N/A
Required Time : None
-Actual Time : 13.383 ns
+Actual Time : 13.172 ns
From : I2
-To : Y2
+To : Y4
From Clock : --
To Clock : --
Failed Paths : 0
diff --git a/38_decoder/db/38_decoder.asm.qmsg b/38_decoder/db/38_decoder.asm.qmsg
index 9297466..1c22f03 100644
--- a/38_decoder/db/38_decoder.asm.qmsg
+++ b/38_decoder/db/38_decoder.asm.qmsg
@@ -1,7 +1,7 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 09:13:07 2022 " "Info: Processing started: Mon Mar 07 09:13:07 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:12:41 2022 " "Info: Processing started: Tue Mar 08 15:12:41 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 09:13:07 2022 " "Info: Processing ended: Mon Mar 07 09:13:07 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:12:41 2022 " "Info: Processing ended: Tue Mar 08 15:12:41 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/38_decoder/db/38_decoder.asm_labs.ddb b/38_decoder/db/38_decoder.asm_labs.ddb
index cf5c209..5227a15 100644
Binary files a/38_decoder/db/38_decoder.asm_labs.ddb and b/38_decoder/db/38_decoder.asm_labs.ddb differ
diff --git a/38_decoder/db/38_decoder.cmp.bpm b/38_decoder/db/38_decoder.cmp.bpm
index 8c0b460..a588ab5 100644
Binary files a/38_decoder/db/38_decoder.cmp.bpm and b/38_decoder/db/38_decoder.cmp.bpm differ
diff --git a/38_decoder/db/38_decoder.cmp.cdb b/38_decoder/db/38_decoder.cmp.cdb
index 6a432b9..3dc02b1 100644
Binary files a/38_decoder/db/38_decoder.cmp.cdb and b/38_decoder/db/38_decoder.cmp.cdb differ
diff --git a/38_decoder/db/38_decoder.cmp.hdb b/38_decoder/db/38_decoder.cmp.hdb
index 47b0a26..eeda646 100644
Binary files a/38_decoder/db/38_decoder.cmp.hdb and b/38_decoder/db/38_decoder.cmp.hdb differ
diff --git a/38_decoder/db/38_decoder.cmp.rdb b/38_decoder/db/38_decoder.cmp.rdb
index 8a84e47..a939741 100644
Binary files a/38_decoder/db/38_decoder.cmp.rdb and b/38_decoder/db/38_decoder.cmp.rdb differ
diff --git a/38_decoder/db/38_decoder.cmp.tdb b/38_decoder/db/38_decoder.cmp.tdb
index 7da23b4..b4c7911 100644
Binary files a/38_decoder/db/38_decoder.cmp.tdb and b/38_decoder/db/38_decoder.cmp.tdb differ
diff --git a/38_decoder/db/38_decoder.cmp0.ddb b/38_decoder/db/38_decoder.cmp0.ddb
index 2d674db..2fb1195 100644
Binary files a/38_decoder/db/38_decoder.cmp0.ddb and b/38_decoder/db/38_decoder.cmp0.ddb differ
diff --git a/38_decoder/db/38_decoder.cmp2.ddb b/38_decoder/db/38_decoder.cmp2.ddb
index 1a4c4ba..982346f 100644
Binary files a/38_decoder/db/38_decoder.cmp2.ddb and b/38_decoder/db/38_decoder.cmp2.ddb differ
diff --git a/38_decoder/db/38_decoder.fit.qmsg b/38_decoder/db/38_decoder.fit.qmsg
index a04d2f2..b7a5094 100644
--- a/38_decoder/db/38_decoder.fit.qmsg
+++ b/38_decoder/db/38_decoder.fit.qmsg
@@ -1,5 +1,5 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 09:13:05 2022 " "Info: Processing started: Mon Mar 07 09:13:05 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:12:39 2022 " "Info: Processing started: Tue Mar 08 15:12:39 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "IMPP_MPP_USER_DEVICE" "38_decoder EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"38_decoder\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
@@ -8,7 +8,6 @@
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
-{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "11 11 " "Warning: No exact pin location assignment(s) for 11 pins of 11 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y7 " "Info: Pin Y7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y7 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 40 664 840 56 "Y7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y0 " "Info: Pin Y0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y0 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 376 664 840 392 "Y0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y1 " "Info: Pin Y1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y1 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 328 664 840 344 "Y1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y2 " "Info: Pin Y2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y2 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 280 664 840 296 "Y2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y3 " "Info: Pin Y3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y3 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 232 664 840 248 "Y3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y4 " "Info: Pin Y4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y4 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 184 664 840 200 "Y4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y5 " "Info: Pin Y5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y5 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 136 664 840 152 "Y5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y6 " "Info: Pin Y6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y6 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 88 664 840 104 "Y6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "I2 " "Info: Pin I2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { I2 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 144 32 200 160 "I2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "I0 " "Info: Pin I0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { I0 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 328 32 200 344 "I0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "I1 " "Info: Pin I1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { I1 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 240 32 200 256 "I1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
@@ -19,8 +18,6 @@
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
-{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "11 unused 3.3V 3 8 0 " "Info: Number of I/O pins in group: 11 (unused VREF, 3.3V VCCIO, 3 input, 8 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
-{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 2 30 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 35 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 34 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 36 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
@@ -28,12 +25,11 @@
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X10_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y10 X34_Y19 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y10 to location X34_Y19" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y7 0 " "Info: Pin \"Y7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y0 0 " "Info: Pin \"Y0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y1 0 " "Info: Pin \"Y1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y2 0 " "Info: Pin \"Y2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y3 0 " "Info: Pin \"Y3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y4 0 " "Info: Pin \"Y4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y5 0 " "Info: Pin \"Y5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y6 0 " "Info: Pin \"Y6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
-{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/38_decoder/38_decoder.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/38_decoder/38_decoder.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "306 " "Info: Peak virtual memory: 306 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 09:13:06 2022 " "Info: Processing ended: Mon Mar 07 09:13:06 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "305 " "Info: Peak virtual memory: 305 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:12:40 2022 " "Info: Processing ended: Tue Mar 08 15:12:40 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/38_decoder/db/38_decoder.map.bpm b/38_decoder/db/38_decoder.map.bpm
index ec26f38..a561200 100644
Binary files a/38_decoder/db/38_decoder.map.bpm and b/38_decoder/db/38_decoder.map.bpm differ
diff --git a/38_decoder/db/38_decoder.map.cdb b/38_decoder/db/38_decoder.map.cdb
index 453776c..39e2f5e 100644
Binary files a/38_decoder/db/38_decoder.map.cdb and b/38_decoder/db/38_decoder.map.cdb differ
diff --git a/38_decoder/db/38_decoder.map.hdb b/38_decoder/db/38_decoder.map.hdb
index b3363bc..ae5facc 100644
Binary files a/38_decoder/db/38_decoder.map.hdb and b/38_decoder/db/38_decoder.map.hdb differ
diff --git a/38_decoder/db/38_decoder.map.qmsg b/38_decoder/db/38_decoder.map.qmsg
index bba0833..7d51101 100644
--- a/38_decoder/db/38_decoder.map.qmsg
+++ b/38_decoder/db/38_decoder.map.qmsg
@@ -1,7 +1,7 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 09:13:04 2022 " "Info: Processing started: Mon Mar 07 09:13:04 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:12:38 2022 " "Info: Processing started: Tue Mar 08 15:12:38 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off 38_decoder -c 38_decoder " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off 38_decoder -c 38_decoder" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "38_decoder.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file 38_decoder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 38_decoder " "Info: Found entity 1: 38_decoder" { } { { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "38_decoder " "Info: Elaborating entity \"38_decoder\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "19 " "Info: Implemented 19 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Info: Implemented 3 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "248 " "Info: Peak virtual memory: 248 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 09:13:04 2022 " "Info: Processing ended: Mon Mar 07 09:13:04 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:12:38 2022 " "Info: Processing ended: Tue Mar 08 15:12:38 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/38_decoder/db/38_decoder.map_bb.cdb b/38_decoder/db/38_decoder.map_bb.cdb
index f5593b6..52e3520 100644
Binary files a/38_decoder/db/38_decoder.map_bb.cdb and b/38_decoder/db/38_decoder.map_bb.cdb differ
diff --git a/38_decoder/db/38_decoder.map_bb.hdb b/38_decoder/db/38_decoder.map_bb.hdb
index 7a55a4a..871b480 100644
Binary files a/38_decoder/db/38_decoder.map_bb.hdb and b/38_decoder/db/38_decoder.map_bb.hdb differ
diff --git a/38_decoder/db/38_decoder.pre_map.cdb b/38_decoder/db/38_decoder.pre_map.cdb
index a1e0f2b..8928020 100644
Binary files a/38_decoder/db/38_decoder.pre_map.cdb and b/38_decoder/db/38_decoder.pre_map.cdb differ
diff --git a/38_decoder/db/38_decoder.pre_map.hdb b/38_decoder/db/38_decoder.pre_map.hdb
index 755d0df..41e732f 100644
Binary files a/38_decoder/db/38_decoder.pre_map.hdb and b/38_decoder/db/38_decoder.pre_map.hdb differ
diff --git a/38_decoder/db/38_decoder.rtlv.hdb b/38_decoder/db/38_decoder.rtlv.hdb
index ddf7de4..c506974 100644
Binary files a/38_decoder/db/38_decoder.rtlv.hdb and b/38_decoder/db/38_decoder.rtlv.hdb differ
diff --git a/38_decoder/db/38_decoder.rtlv_sg.cdb b/38_decoder/db/38_decoder.rtlv_sg.cdb
index f1f7e31..294d082 100644
Binary files a/38_decoder/db/38_decoder.rtlv_sg.cdb and b/38_decoder/db/38_decoder.rtlv_sg.cdb differ
diff --git a/38_decoder/db/38_decoder.sgdiff.cdb b/38_decoder/db/38_decoder.sgdiff.cdb
index a321ed4..b12c775 100644
Binary files a/38_decoder/db/38_decoder.sgdiff.cdb and b/38_decoder/db/38_decoder.sgdiff.cdb differ
diff --git a/38_decoder/db/38_decoder.sgdiff.hdb b/38_decoder/db/38_decoder.sgdiff.hdb
index f17bae6..7b35d44 100644
Binary files a/38_decoder/db/38_decoder.sgdiff.hdb and b/38_decoder/db/38_decoder.sgdiff.hdb differ
diff --git a/38_decoder/db/38_decoder.tan.qmsg b/38_decoder/db/38_decoder.tan.qmsg
index a205924..0d4dd5e 100644
--- a/38_decoder/db/38_decoder.tan.qmsg
+++ b/38_decoder/db/38_decoder.tan.qmsg
@@ -1,6 +1,6 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 09:13:08 2022 " "Info: Processing started: Mon Mar 07 09:13:08 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:12:42 2022 " "Info: Processing started: Tue Mar 08 15:12:42 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
-{ "Info" "ITDB_FULL_TPD_RESULT" "I2 Y2 13.383 ns Longest " "Info: Longest tpd from source pin \"I2\" to destination pin \"Y2\" is 13.383 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns I2 1 PIN PIN_41 8 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_41; Fanout = 8; PIN Node = 'I2'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2 } "NODE_NAME" } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 144 32 200 160 "I2" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.786 ns) + CELL(0.499 ns) 7.280 ns inst10~3 2 COMB LCCOMB_X1_Y7_N22 1 " "Info: 2: + IC(5.786 ns) + CELL(0.499 ns) = 7.280 ns; Loc. = LCCOMB_X1_Y7_N22; Fanout = 1; COMB Node = 'inst10~3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.285 ns" { I2 inst10~3 } "NODE_NAME" } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 360 544 608 408 "inst10" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.847 ns) + CELL(3.256 ns) 13.383 ns Y2 3 PIN PIN_195 0 " "Info: 3: + IC(2.847 ns) + CELL(3.256 ns) = 13.383 ns; Loc. = PIN_195; Fanout = 0; PIN Node = 'Y2'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.103 ns" { inst10~3 Y2 } "NODE_NAME" } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 280 664 840 296 "Y2" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.750 ns ( 35.49 % ) " "Info: Total cell delay = 4.750 ns ( 35.49 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.633 ns ( 64.51 % ) " "Info: Total interconnect delay = 8.633 ns ( 64.51 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "13.383 ns" { I2 inst10~3 Y2 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "13.383 ns" { I2 {} I2~combout {} inst10~3 {} Y2 {} } { 0.000ns 0.000ns 5.786ns 2.847ns } { 0.000ns 0.995ns 0.499ns 3.256ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 09:13:08 2022 " "Info: Processing ended: Mon Mar 07 09:13:08 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TPD_RESULT" "I2 Y4 13.172 ns Longest " "Info: Longest tpd from source pin \"I2\" to destination pin \"Y4\" is 13.172 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns I2 1 PIN PIN_81 8 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_81; Fanout = 8; PIN Node = 'I2'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2 } "NODE_NAME" } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 144 32 200 160 "I2" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(7.387 ns) + CELL(0.651 ns) 9.012 ns inst10~5 2 COMB LCCOMB_X33_Y13_N2 1 " "Info: 2: + IC(7.387 ns) + CELL(0.651 ns) = 9.012 ns; Loc. = LCCOMB_X33_Y13_N2; Fanout = 1; COMB Node = 'inst10~5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.038 ns" { I2 inst10~5 } "NODE_NAME" } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 360 544 608 408 "inst10" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.054 ns) + CELL(3.106 ns) 13.172 ns Y4 3 PIN PIN_146 0 " "Info: 3: + IC(1.054 ns) + CELL(3.106 ns) = 13.172 ns; Loc. = PIN_146; Fanout = 0; PIN Node = 'Y4'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.160 ns" { inst10~5 Y4 } "NODE_NAME" } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 184 664 840 200 "Y4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.731 ns ( 35.92 % ) " "Info: Total cell delay = 4.731 ns ( 35.92 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.441 ns ( 64.08 % ) " "Info: Total interconnect delay = 8.441 ns ( 64.08 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "13.172 ns" { I2 inst10~5 Y4 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "13.172 ns" { I2 {} I2~combout {} inst10~5 {} Y4 {} } { 0.000ns 0.000ns 7.387ns 1.054ns } { 0.000ns 0.974ns 0.651ns 3.106ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:12:42 2022 " "Info: Processing ended: Tue Mar 08 15:12:42 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/38_decoder/db/38_decoder.tmw_info b/38_decoder/db/38_decoder.tmw_info
index 15a6255..6516e48 100644
--- a/38_decoder/db/38_decoder.tmw_info
+++ b/38_decoder/db/38_decoder.tmw_info
@@ -1,6 +1,6 @@
start_full_compilation:s:00:00:05
-start_analysis_synthesis:s:00:00:01-start_full_compilation
+start_analysis_synthesis:s:00:00:02-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:02-start_full_compilation
-start_assembler:s:00:00:01-start_full_compilation
-start_timing_analyzer:s:00:00:01-start_full_compilation
+start_fitter:s:00:00:01-start_full_compilation
+start_assembler:s:00:00:02-start_full_compilation
+start_timing_analyzer:s:00:00:00-start_full_compilation
diff --git a/38_decoder/db/prev_cmp_38_decoder.asm.qmsg b/38_decoder/db/prev_cmp_38_decoder.asm.qmsg
new file mode 100644
index 0000000..9297466
--- /dev/null
+++ b/38_decoder/db/prev_cmp_38_decoder.asm.qmsg
@@ -0,0 +1,7 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 09:13:07 2022 " "Info: Processing started: Mon Mar 07 09:13:07 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
+{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 09:13:07 2022 " "Info: Processing ended: Mon Mar 07 09:13:07 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/38_decoder/db/prev_cmp_38_decoder.fit.qmsg b/38_decoder/db/prev_cmp_38_decoder.fit.qmsg
new file mode 100644
index 0000000..a04d2f2
--- /dev/null
+++ b/38_decoder/db/prev_cmp_38_decoder.fit.qmsg
@@ -0,0 +1,39 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 09:13:05 2022 " "Info: Processing started: Mon Mar 07 09:13:05 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "IMPP_MPP_USER_DEVICE" "38_decoder EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"38_decoder\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "11 11 " "Warning: No exact pin location assignment(s) for 11 pins of 11 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y7 " "Info: Pin Y7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y7 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 40 664 840 56 "Y7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y0 " "Info: Pin Y0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y0 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 376 664 840 392 "Y0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y1 " "Info: Pin Y1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y1 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 328 664 840 344 "Y1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y2 " "Info: Pin Y2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y2 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 280 664 840 296 "Y2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y3 " "Info: Pin Y3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y3 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 232 664 840 248 "Y3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y4 " "Info: Pin Y4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y4 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 184 664 840 200 "Y4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y5 " "Info: Pin Y5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y5 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 136 664 840 152 "Y5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y6 " "Info: Pin Y6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y6 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 88 664 840 104 "Y6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "I2 " "Info: Pin I2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { I2 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 144 32 200 160 "I2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "I0 " "Info: Pin I0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { I0 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 328 32 200 344 "I0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "I1 " "Info: Pin I1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { I1 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 240 32 200 256 "I1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
+{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
+{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "11 unused 3.3V 3 8 0 " "Info: Number of I/O pins in group: 11 (unused VREF, 3.3V VCCIO, 3 input, 8 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 2 30 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 35 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 34 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 36 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X10_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
+{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y7 0 " "Info: Pin \"Y7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y0 0 " "Info: Pin \"Y0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y1 0 " "Info: Pin \"Y1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y2 0 " "Info: Pin \"Y2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y3 0 " "Info: Pin \"Y3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y4 0 " "Info: Pin \"Y4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y5 0 " "Info: Pin \"Y5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y6 0 " "Info: Pin \"Y6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/38_decoder/38_decoder.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/38_decoder/38_decoder.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "306 " "Info: Peak virtual memory: 306 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 09:13:06 2022 " "Info: Processing ended: Mon Mar 07 09:13:06 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/38_decoder/db/prev_cmp_38_decoder.map.qmsg b/38_decoder/db/prev_cmp_38_decoder.map.qmsg
new file mode 100644
index 0000000..bba0833
--- /dev/null
+++ b/38_decoder/db/prev_cmp_38_decoder.map.qmsg
@@ -0,0 +1,7 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 09:13:04 2022 " "Info: Processing started: Mon Mar 07 09:13:04 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off 38_decoder -c 38_decoder " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off 38_decoder -c 38_decoder" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "38_decoder.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file 38_decoder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 38_decoder " "Info: Found entity 1: 38_decoder" { } { { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_TOP" "38_decoder " "Info: Elaborating entity \"38_decoder\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "19 " "Info: Implemented 19 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Info: Implemented 3 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "248 " "Info: Peak virtual memory: 248 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 09:13:04 2022 " "Info: Processing ended: Mon Mar 07 09:13:04 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/38_decoder/db/prev_cmp_38_decoder.tan.qmsg b/38_decoder/db/prev_cmp_38_decoder.tan.qmsg
new file mode 100644
index 0000000..a205924
--- /dev/null
+++ b/38_decoder/db/prev_cmp_38_decoder.tan.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 09:13:08 2022 " "Info: Processing started: Mon Mar 07 09:13:08 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TPD_RESULT" "I2 Y2 13.383 ns Longest " "Info: Longest tpd from source pin \"I2\" to destination pin \"Y2\" is 13.383 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns I2 1 PIN PIN_41 8 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_41; Fanout = 8; PIN Node = 'I2'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2 } "NODE_NAME" } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 144 32 200 160 "I2" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.786 ns) + CELL(0.499 ns) 7.280 ns inst10~3 2 COMB LCCOMB_X1_Y7_N22 1 " "Info: 2: + IC(5.786 ns) + CELL(0.499 ns) = 7.280 ns; Loc. = LCCOMB_X1_Y7_N22; Fanout = 1; COMB Node = 'inst10~3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.285 ns" { I2 inst10~3 } "NODE_NAME" } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 360 544 608 408 "inst10" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.847 ns) + CELL(3.256 ns) 13.383 ns Y2 3 PIN PIN_195 0 " "Info: 3: + IC(2.847 ns) + CELL(3.256 ns) = 13.383 ns; Loc. = PIN_195; Fanout = 0; PIN Node = 'Y2'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.103 ns" { inst10~3 Y2 } "NODE_NAME" } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 280 664 840 296 "Y2" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.750 ns ( 35.49 % ) " "Info: Total cell delay = 4.750 ns ( 35.49 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.633 ns ( 64.51 % ) " "Info: Total interconnect delay = 8.633 ns ( 64.51 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "13.383 ns" { I2 inst10~3 Y2 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "13.383 ns" { I2 {} I2~combout {} inst10~3 {} Y2 {} } { 0.000ns 0.000ns 5.786ns 2.847ns } { 0.000ns 0.995ns 0.499ns 3.256ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 09:13:08 2022 " "Info: Processing ended: Mon Mar 07 09:13:08 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.atm b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.atm
index a62601d..120c51a 100644
Binary files a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.atm and b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.atm differ
diff --git a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.hdbx b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.hdbx
index 71a9612..815ddb3 100644
Binary files a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.hdbx and b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.hdbx differ
diff --git a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.rcf b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.rcf
index 9615120..7ee905b 100644
Binary files a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.rcf and b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.rcf differ
diff --git a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.atm b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.atm
index 150c3be..e564434 100644
Binary files a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.atm and b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.atm differ
diff --git a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.hdbx b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.hdbx
index 7484251..57e6d02 100644
Binary files a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.hdbx and b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.hdbx differ
diff --git a/README.md b/README.md
index 5aa7cad..a531c07 100644
--- a/README.md
+++ b/README.md
@@ -2,6 +2,10 @@
计组课设。
+```
+板上实际元件: 电路虚拟元件
+```
+
### adder_8b
8位加法计算器。
@@ -32,14 +36,35 @@ LR0~LR7: Y0~Y7
8位寄存器。
+```
+K0~K7: D0~D7
+K8: CP
+K9: CLR
+LR0~LR7: Q0~Q7
+```
+
### 38_decoder
3-8译码器。
+```
+K0~K2: I0~I2
+LR0~LR7: Y0~Y7
+```
+
### triple_selector_8b
8位数据选择器（三选一）。
### shifter_8b
-8位数据移位器。
\ No newline at end of file
+8位数据移位器。
+
+```
+K0~K7: A0~A7
+K8: RM
+K9: DM
+K10: LM
+LR0~LR7: Y0~Y7
+```
+
diff --git a/register_8b/db/prev_cmp_register_8b.asm.qmsg b/register_8b/db/prev_cmp_register_8b.asm.qmsg
new file mode 100644
index 0000000..6284d55
--- /dev/null
+++ b/register_8b/db/prev_cmp_register_8b.asm.qmsg
@@ -0,0 +1,7 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:08:36 2022 " "Info: Processing started: Tue Mar 08 15:08:36 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off register_8b -c register_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off register_8b -c register_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
+{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:08:36 2022 " "Info: Processing ended: Tue Mar 08 15:08:36 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/register_8b/db/prev_cmp_register_8b.fit.qmsg b/register_8b/db/prev_cmp_register_8b.fit.qmsg
new file mode 100644
index 0000000..35bea3b
--- /dev/null
+++ b/register_8b/db/prev_cmp_register_8b.fit.qmsg
@@ -0,0 +1,36 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:08:34 2022 " "Info: Processing started: Tue Mar 08 15:08:34 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off register_8b -c register_8b " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off register_8b -c register_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "IMPP_MPP_USER_DEVICE" "register_8b EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"register_8b\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
+{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
+{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y10 X34_Y19 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y10 to location X34_Y19" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
+{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q7 0 " "Info: Pin \"Q7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q6 0 " "Info: Pin \"Q6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q5 0 " "Info: Pin \"Q5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q4 0 " "Info: Pin \"Q4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q3 0 " "Info: Pin \"Q3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q2 0 " "Info: Pin \"Q2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q1 0 " "Info: Pin \"Q1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q0 0 " "Info: Pin \"Q0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/register_8b/register_8b.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/register_8b/register_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "306 " "Info: Peak virtual memory: 306 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:08:35 2022 " "Info: Processing ended: Tue Mar 08 15:08:35 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/register_8b/db/prev_cmp_register_8b.map.qmsg b/register_8b/db/prev_cmp_register_8b.map.qmsg
new file mode 100644
index 0000000..ca9da1d
--- /dev/null
+++ b/register_8b/db/prev_cmp_register_8b.map.qmsg
@@ -0,0 +1,7 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:08:32 2022 " "Info: Processing started: Tue Mar 08 15:08:32 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off register_8b -c register_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off register_8b -c register_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "register_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file register_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 register_8b " "Info: Found entity 1: register_8b" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_TOP" "register_8b " "Info: Elaborating entity \"register_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "26 " "Info: Implemented 26 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Info: Implemented 10 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:08:33 2022 " "Info: Processing ended: Tue Mar 08 15:08:33 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/register_8b/db/prev_cmp_register_8b.qmsg b/register_8b/db/prev_cmp_register_8b.qmsg
new file mode 100644
index 0000000..06cbfd4
--- /dev/null
+++ b/register_8b/db/prev_cmp_register_8b.qmsg
@@ -0,0 +1,61 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:08:32 2022 " "Info: Processing started: Tue Mar 08 15:08:32 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off register_8b -c register_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off register_8b -c register_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "register_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file register_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 register_8b " "Info: Found entity 1: register_8b" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_TOP" "register_8b " "Info: Elaborating entity \"register_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "26 " "Info: Implemented 26 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Info: Implemented 10 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:08:33 2022 " "Info: Processing ended: Tue Mar 08 15:08:33 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:08:34 2022 " "Info: Processing started: Tue Mar 08 15:08:34 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off register_8b -c register_8b " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off register_8b -c register_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "IMPP_MPP_USER_DEVICE" "register_8b EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"register_8b\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
+{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
+{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y10 X34_Y19 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y10 to location X34_Y19" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
+{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q7 0 " "Info: Pin \"Q7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q6 0 " "Info: Pin \"Q6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q5 0 " "Info: Pin \"Q5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q4 0 " "Info: Pin \"Q4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q3 0 " "Info: Pin \"Q3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q2 0 " "Info: Pin \"Q2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q1 0 " "Info: Pin \"Q1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q0 0 " "Info: Pin \"Q0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/register_8b/register_8b.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/register_8b/register_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "306 " "Info: Peak virtual memory: 306 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:08:35 2022 " "Info: Processing ended: Tue Mar 08 15:08:35 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:08:36 2022 " "Info: Processing started: Tue Mar 08 15:08:36 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off register_8b -c register_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off register_8b -c register_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
+{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:08:36 2022 " "Info: Processing ended: Tue Mar 08 15:08:36 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:08:37 2022 " "Info: Processing started: Tue Mar 08 15:08:37 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off register_8b -c register_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off register_8b -c register_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CP " "Info: Assuming node \"CP\" is an undefined clock" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } { "d:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CP" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
+{ "Info" "ITAN_NO_REG2REG_EXIST" "CP " "Info: No valid register-to-register data paths exist for clock \"CP\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ITDB_TSU_RESULT" "inst8 D0 CP 3.273 ns register " "Info: tsu for register \"inst8\" (data pin = \"D0\", clock pin = \"CP\") is 3.273 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.692 ns + Longest pin register " "Info: + Longest pin to register delay is 7.692 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns D0 1 PIN PIN_77 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_77; Fanout = 1; PIN Node = 'D0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { D0 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 752 32 200 768 "D0" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.404 ns) + CELL(0.206 ns) 7.584 ns inst8~feeder 2 COMB LCCOMB_X25_Y1_N22 1 " "Info: 2: + IC(6.404 ns) + CELL(0.206 ns) = 7.584 ns; Loc. = LCCOMB_X25_Y1_N22; Fanout = 1; COMB Node = 'inst8~feeder'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.610 ns" { D0 inst8~feeder } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 736 344 408 816 "inst8" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.692 ns inst8 3 REG LCFF_X25_Y1_N23 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.692 ns; Loc. = LCFF_X25_Y1_N23; Fanout = 1; REG Node = 'inst8'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { inst8~feeder inst8 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 736 344 408 816 "inst8" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.288 ns ( 16.74 % ) " "Info: Total cell delay = 1.288 ns ( 16.74 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.404 ns ( 83.26 % ) " "Info: Total interconnect delay = 6.404 ns ( 83.26 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.692 ns" { D0 inst8~feeder inst8 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "7.692 ns" { D0 {} D0~combout {} inst8~feeder {} inst8 {} } { 0.000ns 0.000ns 6.404ns 0.000ns } { 0.000ns 0.974ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 736 344 408 816 "inst8" "" } } } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CP destination 4.379 ns - Shortest register " "Info: - Shortest clock path from clock \"CP\" to destination register is 4.379 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns CP 1 CLK PIN_67 8 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CP } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.719 ns) + CELL(0.666 ns) 4.379 ns inst8 2 REG LCFF_X25_Y1_N23 1 " "Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N23; Fanout = 1; REG Node = 'inst8'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.385 ns" { CP inst8 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 736 344 408 816 "inst8" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 37.91 % ) " "Info: Total cell delay = 1.660 ns ( 37.91 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.719 ns ( 62.09 % ) " "Info: Total interconnect delay = 2.719 ns ( 62.09 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst8 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst8 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.692 ns" { D0 inst8~feeder inst8 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "7.692 ns" { D0 {} D0~combout {} inst8~feeder {} inst8 {} } { 0.000ns 0.000ns 6.404ns 0.000ns } { 0.000ns 0.974ns 0.206ns 0.108ns } "" } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst8 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst8 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TCO_RESULT" "CP Q5 inst3 11.227 ns register " "Info: tco from clock \"CP\" to destination pin \"Q5\" through register \"inst3\" is 11.227 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CP source 4.379 ns + Longest register " "Info: + Longest clock path from clock \"CP\" to source register is 4.379 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns CP 1 CLK PIN_67 8 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CP } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.719 ns) + CELL(0.666 ns) 4.379 ns inst3 2 REG LCFF_X25_Y1_N29 1 " "Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.385 ns" { CP inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 37.91 % ) " "Info: Total cell delay = 1.660 ns ( 37.91 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.719 ns ( 62.09 % ) " "Info: Total interconnect delay = 2.719 ns ( 62.09 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst3 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.544 ns + Longest register pin " "Info: + Longest register to pin delay is 6.544 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst3 1 REG LCFF_X25_Y1_N29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.428 ns) + CELL(3.116 ns) 6.544 ns Q5 2 PIN PIN_147 0 " "Info: 2: + IC(3.428 ns) + CELL(3.116 ns) = 6.544 ns; Loc. = PIN_147; Fanout = 0; PIN Node = 'Q5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.544 ns" { inst3 Q5 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 272 464 640 288 "Q5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.116 ns ( 47.62 % ) " "Info: Total cell delay = 3.116 ns ( 47.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.428 ns ( 52.38 % ) " "Info: Total interconnect delay = 3.428 ns ( 52.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.544 ns" { inst3 Q5 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.544 ns" { inst3 {} Q5 {} } { 0.000ns 3.428ns } { 0.000ns 3.116ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst3 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.544 ns" { inst3 Q5 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.544 ns" { inst3 {} Q5 {} } { 0.000ns 3.428ns } { 0.000ns 3.116ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_TH_RESULT" "inst3 D5 CP -2.294 ns register " "Info: th for register \"inst3\" (data pin = \"D5\", clock pin = \"CP\") is -2.294 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CP destination 4.379 ns + Longest register " "Info: + Longest clock path from clock \"CP\" to destination register is 4.379 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns CP 1 CLK PIN_67 8 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CP } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.719 ns) + CELL(0.666 ns) 4.379 ns inst3 2 REG LCFF_X25_Y1_N29 1 " "Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.385 ns" { CP inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 37.91 % ) " "Info: Total cell delay = 1.660 ns ( 37.91 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.719 ns ( 62.09 % ) " "Info: Total interconnect delay = 2.719 ns ( 62.09 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst3 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.979 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.979 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.964 ns) 0.964 ns D5 1 PIN PIN_86 1 " "Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_86; Fanout = 1; PIN Node = 'D5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { D5 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 272 32 200 288 "D5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.701 ns) + CELL(0.206 ns) 6.871 ns inst3~feeder 2 COMB LCCOMB_X25_Y1_N28 1 " "Info: 2: + IC(5.701 ns) + CELL(0.206 ns) = 6.871 ns; Loc. = LCCOMB_X25_Y1_N28; Fanout = 1; COMB Node = 'inst3~feeder'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.907 ns" { D5 inst3~feeder } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 6.979 ns inst3 3 REG LCFF_X25_Y1_N29 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 6.979 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { inst3~feeder inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.278 ns ( 18.31 % ) " "Info: Total cell delay = 1.278 ns ( 18.31 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.701 ns ( 81.69 % ) " "Info: Total interconnect delay = 5.701 ns ( 81.69 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.979 ns" { D5 inst3~feeder inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.979 ns" { D5 {} D5~combout {} inst3~feeder {} inst3 {} } { 0.000ns 0.000ns 5.701ns 0.000ns } { 0.000ns 0.964ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst3 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.979 ns" { D5 inst3~feeder inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.979 ns" { D5 {} D5~combout {} inst3~feeder {} inst3 {} } { 0.000ns 0.000ns 5.701ns 0.000ns } { 0.000ns 0.964ns 0.206ns 0.108ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:08:37 2022 " "Info: Processing ended: Tue Mar 08 15:08:37 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 3 s " "Info: Quartus II Full Compilation was successful. 0 errors, 3 warnings" { } { } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/register_8b/db/prev_cmp_register_8b.tan.qmsg b/register_8b/db/prev_cmp_register_8b.tan.qmsg
new file mode 100644
index 0000000..805fd16
--- /dev/null
+++ b/register_8b/db/prev_cmp_register_8b.tan.qmsg
@@ -0,0 +1,10 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:08:37 2022 " "Info: Processing started: Tue Mar 08 15:08:37 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off register_8b -c register_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off register_8b -c register_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CP " "Info: Assuming node \"CP\" is an undefined clock" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } { "d:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CP" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
+{ "Info" "ITAN_NO_REG2REG_EXIST" "CP " "Info: No valid register-to-register data paths exist for clock \"CP\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ITDB_TSU_RESULT" "inst8 D0 CP 3.273 ns register " "Info: tsu for register \"inst8\" (data pin = \"D0\", clock pin = \"CP\") is 3.273 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.692 ns + Longest pin register " "Info: + Longest pin to register delay is 7.692 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns D0 1 PIN PIN_77 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_77; Fanout = 1; PIN Node = 'D0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { D0 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 752 32 200 768 "D0" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.404 ns) + CELL(0.206 ns) 7.584 ns inst8~feeder 2 COMB LCCOMB_X25_Y1_N22 1 " "Info: 2: + IC(6.404 ns) + CELL(0.206 ns) = 7.584 ns; Loc. = LCCOMB_X25_Y1_N22; Fanout = 1; COMB Node = 'inst8~feeder'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.610 ns" { D0 inst8~feeder } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 736 344 408 816 "inst8" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.692 ns inst8 3 REG LCFF_X25_Y1_N23 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.692 ns; Loc. = LCFF_X25_Y1_N23; Fanout = 1; REG Node = 'inst8'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { inst8~feeder inst8 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 736 344 408 816 "inst8" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.288 ns ( 16.74 % ) " "Info: Total cell delay = 1.288 ns ( 16.74 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.404 ns ( 83.26 % ) " "Info: Total interconnect delay = 6.404 ns ( 83.26 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.692 ns" { D0 inst8~feeder inst8 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "7.692 ns" { D0 {} D0~combout {} inst8~feeder {} inst8 {} } { 0.000ns 0.000ns 6.404ns 0.000ns } { 0.000ns 0.974ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 736 344 408 816 "inst8" "" } } } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CP destination 4.379 ns - Shortest register " "Info: - Shortest clock path from clock \"CP\" to destination register is 4.379 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns CP 1 CLK PIN_67 8 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CP } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.719 ns) + CELL(0.666 ns) 4.379 ns inst8 2 REG LCFF_X25_Y1_N23 1 " "Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N23; Fanout = 1; REG Node = 'inst8'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.385 ns" { CP inst8 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 736 344 408 816 "inst8" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 37.91 % ) " "Info: Total cell delay = 1.660 ns ( 37.91 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.719 ns ( 62.09 % ) " "Info: Total interconnect delay = 2.719 ns ( 62.09 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst8 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst8 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.692 ns" { D0 inst8~feeder inst8 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "7.692 ns" { D0 {} D0~combout {} inst8~feeder {} inst8 {} } { 0.000ns 0.000ns 6.404ns 0.000ns } { 0.000ns 0.974ns 0.206ns 0.108ns } "" } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst8 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst8 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TCO_RESULT" "CP Q5 inst3 11.227 ns register " "Info: tco from clock \"CP\" to destination pin \"Q5\" through register \"inst3\" is 11.227 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CP source 4.379 ns + Longest register " "Info: + Longest clock path from clock \"CP\" to source register is 4.379 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns CP 1 CLK PIN_67 8 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CP } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.719 ns) + CELL(0.666 ns) 4.379 ns inst3 2 REG LCFF_X25_Y1_N29 1 " "Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.385 ns" { CP inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 37.91 % ) " "Info: Total cell delay = 1.660 ns ( 37.91 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.719 ns ( 62.09 % ) " "Info: Total interconnect delay = 2.719 ns ( 62.09 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst3 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.544 ns + Longest register pin " "Info: + Longest register to pin delay is 6.544 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst3 1 REG LCFF_X25_Y1_N29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.428 ns) + CELL(3.116 ns) 6.544 ns Q5 2 PIN PIN_147 0 " "Info: 2: + IC(3.428 ns) + CELL(3.116 ns) = 6.544 ns; Loc. = PIN_147; Fanout = 0; PIN Node = 'Q5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.544 ns" { inst3 Q5 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 272 464 640 288 "Q5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.116 ns ( 47.62 % ) " "Info: Total cell delay = 3.116 ns ( 47.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.428 ns ( 52.38 % ) " "Info: Total interconnect delay = 3.428 ns ( 52.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.544 ns" { inst3 Q5 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.544 ns" { inst3 {} Q5 {} } { 0.000ns 3.428ns } { 0.000ns 3.116ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst3 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.544 ns" { inst3 Q5 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.544 ns" { inst3 {} Q5 {} } { 0.000ns 3.428ns } { 0.000ns 3.116ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_TH_RESULT" "inst3 D5 CP -2.294 ns register " "Info: th for register \"inst3\" (data pin = \"D5\", clock pin = \"CP\") is -2.294 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CP destination 4.379 ns + Longest register " "Info: + Longest clock path from clock \"CP\" to destination register is 4.379 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns CP 1 CLK PIN_67 8 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CP } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.719 ns) + CELL(0.666 ns) 4.379 ns inst3 2 REG LCFF_X25_Y1_N29 1 " "Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.385 ns" { CP inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 37.91 % ) " "Info: Total cell delay = 1.660 ns ( 37.91 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.719 ns ( 62.09 % ) " "Info: Total interconnect delay = 2.719 ns ( 62.09 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst3 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.979 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.979 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.964 ns) 0.964 ns D5 1 PIN PIN_86 1 " "Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_86; Fanout = 1; PIN Node = 'D5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { D5 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 272 32 200 288 "D5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.701 ns) + CELL(0.206 ns) 6.871 ns inst3~feeder 2 COMB LCCOMB_X25_Y1_N28 1 " "Info: 2: + IC(5.701 ns) + CELL(0.206 ns) = 6.871 ns; Loc. = LCCOMB_X25_Y1_N28; Fanout = 1; COMB Node = 'inst3~feeder'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.907 ns" { D5 inst3~feeder } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 6.979 ns inst3 3 REG LCFF_X25_Y1_N29 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 6.979 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { inst3~feeder inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.278 ns ( 18.31 % ) " "Info: Total cell delay = 1.278 ns ( 18.31 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.701 ns ( 81.69 % ) " "Info: Total interconnect delay = 5.701 ns ( 81.69 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.979 ns" { D5 inst3~feeder inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.979 ns" { D5 {} D5~combout {} inst3~feeder {} inst3 {} } { 0.000ns 0.000ns 5.701ns 0.000ns } { 0.000ns 0.964ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst3 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.979 ns" { D5 inst3~feeder inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.979 ns" { D5 {} D5~combout {} inst3~feeder {} inst3 {} } { 0.000ns 0.000ns 5.701ns 0.000ns } { 0.000ns 0.964ns 0.206ns 0.108ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:08:37 2022 " "Info: Processing ended: Tue Mar 08 15:08:37 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/register_8b/db/register_8b.asm.qmsg b/register_8b/db/register_8b.asm.qmsg
index 5e7b877..e8d2711 100644
--- a/register_8b/db/register_8b.asm.qmsg
+++ b/register_8b/db/register_8b.asm.qmsg
@@ -1,7 +1,7 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 09:09:56 2022 " "Info: Processing started: Mon Mar 07 09:09:56 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:08:52 2022 " "Info: Processing started: Tue Mar 08 15:08:52 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off register_8b -c register_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off register_8b -c register_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 09:09:56 2022 " "Info: Processing ended: Mon Mar 07 09:09:56 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:08:53 2022 " "Info: Processing ended: Tue Mar 08 15:08:53 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/register_8b/db/register_8b.asm_labs.ddb b/register_8b/db/register_8b.asm_labs.ddb
index 16465da..9db65b1 100644
Binary files a/register_8b/db/register_8b.asm_labs.ddb and b/register_8b/db/register_8b.asm_labs.ddb differ
diff --git a/register_8b/db/register_8b.cmp.bpm b/register_8b/db/register_8b.cmp.bpm
index 384985c..ccaf79b 100644
Binary files a/register_8b/db/register_8b.cmp.bpm and b/register_8b/db/register_8b.cmp.bpm differ
diff --git a/register_8b/db/register_8b.cmp.cdb b/register_8b/db/register_8b.cmp.cdb
index 6930614..4b976f3 100644
Binary files a/register_8b/db/register_8b.cmp.cdb and b/register_8b/db/register_8b.cmp.cdb differ
diff --git a/register_8b/db/register_8b.cmp.hdb b/register_8b/db/register_8b.cmp.hdb
index 7665214..e0b4dcf 100644
Binary files a/register_8b/db/register_8b.cmp.hdb and b/register_8b/db/register_8b.cmp.hdb differ
diff --git a/register_8b/db/register_8b.cmp.rdb b/register_8b/db/register_8b.cmp.rdb
index 00cf8ad..73b57b3 100644
Binary files a/register_8b/db/register_8b.cmp.rdb and b/register_8b/db/register_8b.cmp.rdb differ
diff --git a/register_8b/db/register_8b.cmp.tdb b/register_8b/db/register_8b.cmp.tdb
index b291d0a..36da105 100644
Binary files a/register_8b/db/register_8b.cmp.tdb and b/register_8b/db/register_8b.cmp.tdb differ
diff --git a/register_8b/db/register_8b.cmp0.ddb b/register_8b/db/register_8b.cmp0.ddb
index 805b6c3..ca24315 100644
Binary files a/register_8b/db/register_8b.cmp0.ddb and b/register_8b/db/register_8b.cmp0.ddb differ
diff --git a/register_8b/db/register_8b.cmp2.ddb b/register_8b/db/register_8b.cmp2.ddb
index 6bc390f..59a9cbf 100644
Binary files a/register_8b/db/register_8b.cmp2.ddb and b/register_8b/db/register_8b.cmp2.ddb differ
diff --git a/register_8b/db/register_8b.fit.qmsg b/register_8b/db/register_8b.fit.qmsg
index a4e6793..6411368 100644
--- a/register_8b/db/register_8b.fit.qmsg
+++ b/register_8b/db/register_8b.fit.qmsg
@@ -1,5 +1,5 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 09:09:54 2022 " "Info: Processing started: Mon Mar 07 09:09:54 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:08:50 2022 " "Info: Processing started: Tue Mar 08 15:08:50 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off register_8b -c register_8b " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off register_8b -c register_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "IMPP_MPP_USER_DEVICE" "register_8b EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"register_8b\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
@@ -8,11 +8,8 @@
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
-{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "18 18 " "Warning: No exact pin location assignment(s) for 18 pins of 18 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Q7 " "Info: Pin Q7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Q7 } } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 80 464 640 96 "Q7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Q6 " "Info: Pin Q6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Q6 } } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 176 464 640 192 "Q6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Q5 " "Info: Pin Q5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Q5 } } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 272 464 640 288 "Q5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Q4 " "Info: Pin Q4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Q4 } } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 368 464 640 384 "Q4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Q3 " "Info: Pin Q3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Q3 } } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 464 464 640 480 "Q3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Q2 " "Info: Pin Q2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Q2 } } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 560 464 640 576 "Q2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Q1 " "Info: Pin Q1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Q1 } } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 656 464 640 672 "Q1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Q0 " "Info: Pin Q0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Q0 } } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 752 464 640 768 "Q0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "D7 " "Info: Pin D7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { D7 } } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 80 32 200 96 "D7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { D7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CP " "Info: Pin CP not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { CP } } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CP } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CLR " "Info: Pin CLR not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { CLR } } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 8 32 200 24 "CLR" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLR } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "D6 " "Info: Pin D6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { D6 } } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 176 32 200 192 "D6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { D6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "D5 " "Info: Pin D5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { D5 } } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 272 32 200 288 "D5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { D5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "D4 " "Info: Pin D4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { D4 } } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 368 32 200 384 "D4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { D4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "D3 " "Info: Pin D3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { D3 } } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 464 32 200 480 "D3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { D3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "D2 " "Info: Pin D2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { D2 } } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 560 32 200 576 "D2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { D2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "D1 " "Info: Pin D1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { D1 } } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 656 32 200 672 "D1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { D1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "D0 " "Info: Pin D0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { D0 } } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 752 32 200 768 "D0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { D0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
-{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CP (placed in PIN 23 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node CP (placed in PIN 23 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { CP } } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CP } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
-{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLR (placed in PIN 24 (CLK1, LVDSCLK0n, Input)) " "Info: Automatically promoted node CLR (placed in PIN 24 (CLK1, LVDSCLK0n, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G1 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { CLR } } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 8 32 200 24 "CLR" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLR } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
@@ -21,8 +18,6 @@
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
-{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "16 unused 3.3V 8 8 0 " "Info: Number of I/O pins in group: 16 (unused VREF, 3.3V VCCIO, 8 input, 8 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
-{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 4 28 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 28 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 35 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 34 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 36 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
@@ -30,12 +25,11 @@
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y10 X10_Y19 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X10_Y19" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y10 X34_Y19 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y10 to location X34_Y19" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q7 0 " "Info: Pin \"Q7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q6 0 " "Info: Pin \"Q6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q5 0 " "Info: Pin \"Q5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q4 0 " "Info: Pin \"Q4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q3 0 " "Info: Pin \"Q3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q2 0 " "Info: Pin \"Q2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q1 0 " "Info: Pin \"Q1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q0 0 " "Info: Pin \"Q0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
-{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/register_8b/register_8b.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/register_8b/register_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "306 " "Info: Peak virtual memory: 306 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 09:09:55 2022 " "Info: Processing ended: Mon Mar 07 09:09:55 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "306 " "Info: Peak virtual memory: 306 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:08:51 2022 " "Info: Processing ended: Tue Mar 08 15:08:51 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/register_8b/db/register_8b.map.bpm b/register_8b/db/register_8b.map.bpm
index 1f4ca92..42bbd6a 100644
Binary files a/register_8b/db/register_8b.map.bpm and b/register_8b/db/register_8b.map.bpm differ
diff --git a/register_8b/db/register_8b.map.cdb b/register_8b/db/register_8b.map.cdb
index 36223e0..230260c 100644
Binary files a/register_8b/db/register_8b.map.cdb and b/register_8b/db/register_8b.map.cdb differ
diff --git a/register_8b/db/register_8b.map.hdb b/register_8b/db/register_8b.map.hdb
index 85bbdfc..57c68ae 100644
Binary files a/register_8b/db/register_8b.map.hdb and b/register_8b/db/register_8b.map.hdb differ
diff --git a/register_8b/db/register_8b.map.kpt b/register_8b/db/register_8b.map.kpt
index fc29aa0..319f882 100644
--- a/register_8b/db/register_8b.map.kpt
+++ b/register_8b/db/register_8b.map.kpt
@@ -54,18 +54,6 @@
-
-
-
-
-
-
-
-
-
-
-
-
@@ -78,42 +66,6 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
@@ -138,6 +90,18 @@
+
+
+
+
+
+
+
+
+
+
+
+
@@ -150,5 +114,41 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/register_8b/db/register_8b.map.qmsg b/register_8b/db/register_8b.map.qmsg
index cb5edc6..5ac8713 100644
--- a/register_8b/db/register_8b.map.qmsg
+++ b/register_8b/db/register_8b.map.qmsg
@@ -1,7 +1,7 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 09:09:53 2022 " "Info: Processing started: Mon Mar 07 09:09:53 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:08:49 2022 " "Info: Processing started: Tue Mar 08 15:08:49 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off register_8b -c register_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off register_8b -c register_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "register_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file register_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 register_8b " "Info: Found entity 1: register_8b" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "register_8b " "Info: Elaborating entity \"register_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "26 " "Info: Implemented 26 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Info: Implemented 10 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "248 " "Info: Peak virtual memory: 248 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 09:09:53 2022 " "Info: Processing ended: Mon Mar 07 09:09:53 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:08:50 2022 " "Info: Processing ended: Tue Mar 08 15:08:50 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/register_8b/db/register_8b.map_bb.cdb b/register_8b/db/register_8b.map_bb.cdb
index fe2e820..73be0da 100644
Binary files a/register_8b/db/register_8b.map_bb.cdb and b/register_8b/db/register_8b.map_bb.cdb differ
diff --git a/register_8b/db/register_8b.map_bb.hdb b/register_8b/db/register_8b.map_bb.hdb
index bc9aee5..728c705 100644
Binary files a/register_8b/db/register_8b.map_bb.hdb and b/register_8b/db/register_8b.map_bb.hdb differ
diff --git a/register_8b/db/register_8b.pre_map.cdb b/register_8b/db/register_8b.pre_map.cdb
index 320a017..e0265a8 100644
Binary files a/register_8b/db/register_8b.pre_map.cdb and b/register_8b/db/register_8b.pre_map.cdb differ
diff --git a/register_8b/db/register_8b.pre_map.hdb b/register_8b/db/register_8b.pre_map.hdb
index 4315c91..53a2e71 100644
Binary files a/register_8b/db/register_8b.pre_map.hdb and b/register_8b/db/register_8b.pre_map.hdb differ
diff --git a/register_8b/db/register_8b.rtlv.hdb b/register_8b/db/register_8b.rtlv.hdb
index 9fd59c2..9d5eab4 100644
Binary files a/register_8b/db/register_8b.rtlv.hdb and b/register_8b/db/register_8b.rtlv.hdb differ
diff --git a/register_8b/db/register_8b.rtlv_sg.cdb b/register_8b/db/register_8b.rtlv_sg.cdb
index 85ebccf..7065a70 100644
Binary files a/register_8b/db/register_8b.rtlv_sg.cdb and b/register_8b/db/register_8b.rtlv_sg.cdb differ
diff --git a/register_8b/db/register_8b.sgdiff.cdb b/register_8b/db/register_8b.sgdiff.cdb
index f2ea8b6..9045fac 100644
Binary files a/register_8b/db/register_8b.sgdiff.cdb and b/register_8b/db/register_8b.sgdiff.cdb differ
diff --git a/register_8b/db/register_8b.sgdiff.hdb b/register_8b/db/register_8b.sgdiff.hdb
index 2a31ddf..eaba118 100644
Binary files a/register_8b/db/register_8b.sgdiff.hdb and b/register_8b/db/register_8b.sgdiff.hdb differ
diff --git a/register_8b/db/register_8b.tan.qmsg b/register_8b/db/register_8b.tan.qmsg
index 5f83fa3..fd4fe68 100644
--- a/register_8b/db/register_8b.tan.qmsg
+++ b/register_8b/db/register_8b.tan.qmsg
@@ -1,10 +1,10 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 09:09:57 2022 " "Info: Processing started: Mon Mar 07 09:09:57 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:08:53 2022 " "Info: Processing started: Tue Mar 08 15:08:53 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off register_8b -c register_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off register_8b -c register_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CP " "Info: Assuming node \"CP\" is an undefined clock" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } { "d:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CP" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
{ "Info" "ITAN_NO_REG2REG_EXIST" "CP " "Info: No valid register-to-register data paths exist for clock \"CP\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0 -1}
-{ "Info" "ITDB_TSU_RESULT" "inst5 D3 CP 4.872 ns register " "Info: tsu for register \"inst5\" (data pin = \"D3\", clock pin = \"CP\") is 4.872 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.782 ns + Longest pin register " "Info: + Longest pin to register delay is 7.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns D3 1 PIN PIN_96 1 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_96; Fanout = 1; PIN Node = 'D3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { D3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 464 32 200 480 "D3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.338 ns) + CELL(0.460 ns) 7.782 ns inst5 2 REG LCFF_X32_Y15_N17 1 " "Info: 2: + IC(6.338 ns) + CELL(0.460 ns) = 7.782 ns; Loc. = LCFF_X32_Y15_N17; Fanout = 1; REG Node = 'inst5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.798 ns" { D3 inst5 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 448 344 408 528 "inst5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.444 ns ( 18.56 % ) " "Info: Total cell delay = 1.444 ns ( 18.56 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.338 ns ( 81.44 % ) " "Info: Total interconnect delay = 6.338 ns ( 81.44 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.782 ns" { D3 inst5 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "7.782 ns" { D3 {} D3~combout {} inst5 {} } { 0.000ns 0.000ns 6.338ns } { 0.000ns 0.984ns 0.460ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 448 344 408 528 "inst5" "" } } } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CP destination 2.870 ns - Shortest register " "Info: - Shortest clock path from clock \"CP\" to destination register is 2.870 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CP 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CP'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CP } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns CP~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CP~clkctrl'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { CP CP~clkctrl } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.925 ns) + CELL(0.666 ns) 2.870 ns inst5 3 REG LCFF_X32_Y15_N17 1 " "Info: 3: + IC(0.925 ns) + CELL(0.666 ns) = 2.870 ns; Loc. = LCFF_X32_Y15_N17; Fanout = 1; REG Node = 'inst5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.591 ns" { CP~clkctrl inst5 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 448 344 408 528 "inst5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 62.93 % ) " "Info: Total cell delay = 1.806 ns ( 62.93 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.064 ns ( 37.07 % ) " "Info: Total interconnect delay = 1.064 ns ( 37.07 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.870 ns" { CP CP~clkctrl inst5 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.870 ns" { CP {} CP~combout {} CP~clkctrl {} inst5 {} } { 0.000ns 0.000ns 0.139ns 0.925ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.782 ns" { D3 inst5 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "7.782 ns" { D3 {} D3~combout {} inst5 {} } { 0.000ns 0.000ns 6.338ns } { 0.000ns 0.984ns 0.460ns } "" } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.870 ns" { CP CP~clkctrl inst5 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.870 ns" { CP {} CP~combout {} CP~clkctrl {} inst5 {} } { 0.000ns 0.000ns 0.139ns 0.925ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
-{ "Info" "ITDB_FULL_TCO_RESULT" "CP Q5 inst3 8.228 ns register " "Info: tco from clock \"CP\" to destination pin \"Q5\" through register \"inst3\" is 8.228 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CP source 2.879 ns + Longest register " "Info: + Longest clock path from clock \"CP\" to source register is 2.879 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CP 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CP'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CP } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns CP~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CP~clkctrl'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { CP CP~clkctrl } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.934 ns) + CELL(0.666 ns) 2.879 ns inst3 3 REG LCFF_X12_Y2_N9 1 " "Info: 3: + IC(0.934 ns) + CELL(0.666 ns) = 2.879 ns; Loc. = LCFF_X12_Y2_N9; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { CP~clkctrl inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 62.73 % ) " "Info: Total cell delay = 1.806 ns ( 62.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.073 ns ( 37.27 % ) " "Info: Total interconnect delay = 1.073 ns ( 37.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.879 ns" { CP CP~clkctrl inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.879 ns" { CP {} CP~combout {} CP~clkctrl {} inst3 {} } { 0.000ns 0.000ns 0.139ns 0.934ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.045 ns + Longest register pin " "Info: + Longest register to pin delay is 5.045 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst3 1 REG LCFF_X12_Y2_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y2_N9; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.765 ns) + CELL(3.280 ns) 5.045 ns Q5 2 PIN PIN_47 0 " "Info: 2: + IC(1.765 ns) + CELL(3.280 ns) = 5.045 ns; Loc. = PIN_47; Fanout = 0; PIN Node = 'Q5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.045 ns" { inst3 Q5 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 272 464 640 288 "Q5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.280 ns ( 65.01 % ) " "Info: Total cell delay = 3.280 ns ( 65.01 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.765 ns ( 34.99 % ) " "Info: Total interconnect delay = 1.765 ns ( 34.99 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.045 ns" { inst3 Q5 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "5.045 ns" { inst3 {} Q5 {} } { 0.000ns 1.765ns } { 0.000ns 3.280ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.879 ns" { CP CP~clkctrl inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.879 ns" { CP {} CP~combout {} CP~clkctrl {} inst3 {} } { 0.000ns 0.000ns 0.139ns 0.934ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.045 ns" { inst3 Q5 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "5.045 ns" { inst3 {} Q5 {} } { 0.000ns 1.765ns } { 0.000ns 3.280ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
-{ "Info" "ITDB_TH_RESULT" "inst7 D1 CP 0.406 ns register " "Info: th for register \"inst7\" (data pin = \"D1\", clock pin = \"CP\") is 0.406 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CP destination 2.855 ns + Longest register " "Info: + Longest clock path from clock \"CP\" to destination register is 2.855 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CP 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CP'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CP } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns CP~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CP~clkctrl'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { CP CP~clkctrl } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.910 ns) + CELL(0.666 ns) 2.855 ns inst7 3 REG LCFF_X1_Y14_N17 1 " "Info: 3: + IC(0.910 ns) + CELL(0.666 ns) = 2.855 ns; Loc. = LCFF_X1_Y14_N17; Fanout = 1; REG Node = 'inst7'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.576 ns" { CP~clkctrl inst7 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 640 344 408 720 "inst7" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.26 % ) " "Info: Total cell delay = 1.806 ns ( 63.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.049 ns ( 36.74 % ) " "Info: Total interconnect delay = 1.049 ns ( 36.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.855 ns" { CP CP~clkctrl inst7 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.855 ns" { CP {} CP~combout {} CP~clkctrl {} inst7 {} } { 0.000ns 0.000ns 0.139ns 0.910ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 640 344 408 720 "inst7" "" } } } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.755 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.755 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns D1 1 PIN PIN_28 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_28; Fanout = 1; PIN Node = 'D1'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { D1 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 656 32 200 672 "D1" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.301 ns) + CELL(0.206 ns) 2.647 ns inst7~feeder 2 COMB LCCOMB_X1_Y14_N16 1 " "Info: 2: + IC(1.301 ns) + CELL(0.206 ns) = 2.647 ns; Loc. = LCCOMB_X1_Y14_N16; Fanout = 1; COMB Node = 'inst7~feeder'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.507 ns" { D1 inst7~feeder } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 640 344 408 720 "inst7" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.755 ns inst7 3 REG LCFF_X1_Y14_N17 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 2.755 ns; Loc. = LCFF_X1_Y14_N17; Fanout = 1; REG Node = 'inst7'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { inst7~feeder inst7 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 640 344 408 720 "inst7" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.454 ns ( 52.78 % ) " "Info: Total cell delay = 1.454 ns ( 52.78 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.301 ns ( 47.22 % ) " "Info: Total interconnect delay = 1.301 ns ( 47.22 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.755 ns" { D1 inst7~feeder inst7 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.755 ns" { D1 {} D1~combout {} inst7~feeder {} inst7 {} } { 0.000ns 0.000ns 1.301ns 0.000ns } { 0.000ns 1.140ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.855 ns" { CP CP~clkctrl inst7 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.855 ns" { CP {} CP~combout {} CP~clkctrl {} inst7 {} } { 0.000ns 0.000ns 0.139ns 0.910ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.755 ns" { D1 inst7~feeder inst7 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "2.755 ns" { D1 {} D1~combout {} inst7~feeder {} inst7 {} } { 0.000ns 0.000ns 1.301ns 0.000ns } { 0.000ns 1.140ns 0.206ns 0.108ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 09:09:57 2022 " "Info: Processing ended: Mon Mar 07 09:09:57 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_TSU_RESULT" "inst8 D0 CP 3.273 ns register " "Info: tsu for register \"inst8\" (data pin = \"D0\", clock pin = \"CP\") is 3.273 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.692 ns + Longest pin register " "Info: + Longest pin to register delay is 7.692 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns D0 1 PIN PIN_77 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_77; Fanout = 1; PIN Node = 'D0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { D0 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 752 32 200 768 "D0" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.404 ns) + CELL(0.206 ns) 7.584 ns inst8~feeder 2 COMB LCCOMB_X25_Y1_N22 1 " "Info: 2: + IC(6.404 ns) + CELL(0.206 ns) = 7.584 ns; Loc. = LCCOMB_X25_Y1_N22; Fanout = 1; COMB Node = 'inst8~feeder'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.610 ns" { D0 inst8~feeder } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 736 344 408 816 "inst8" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.692 ns inst8 3 REG LCFF_X25_Y1_N23 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.692 ns; Loc. = LCFF_X25_Y1_N23; Fanout = 1; REG Node = 'inst8'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { inst8~feeder inst8 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 736 344 408 816 "inst8" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.288 ns ( 16.74 % ) " "Info: Total cell delay = 1.288 ns ( 16.74 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.404 ns ( 83.26 % ) " "Info: Total interconnect delay = 6.404 ns ( 83.26 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.692 ns" { D0 inst8~feeder inst8 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "7.692 ns" { D0 {} D0~combout {} inst8~feeder {} inst8 {} } { 0.000ns 0.000ns 6.404ns 0.000ns } { 0.000ns 0.974ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 736 344 408 816 "inst8" "" } } } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CP destination 4.379 ns - Shortest register " "Info: - Shortest clock path from clock \"CP\" to destination register is 4.379 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns CP 1 CLK PIN_67 8 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CP } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.719 ns) + CELL(0.666 ns) 4.379 ns inst8 2 REG LCFF_X25_Y1_N23 1 " "Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N23; Fanout = 1; REG Node = 'inst8'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.385 ns" { CP inst8 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 736 344 408 816 "inst8" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 37.91 % ) " "Info: Total cell delay = 1.660 ns ( 37.91 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.719 ns ( 62.09 % ) " "Info: Total interconnect delay = 2.719 ns ( 62.09 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst8 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst8 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.692 ns" { D0 inst8~feeder inst8 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "7.692 ns" { D0 {} D0~combout {} inst8~feeder {} inst8 {} } { 0.000ns 0.000ns 6.404ns 0.000ns } { 0.000ns 0.974ns 0.206ns 0.108ns } "" } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst8 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst8 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TCO_RESULT" "CP Q5 inst3 11.227 ns register " "Info: tco from clock \"CP\" to destination pin \"Q5\" through register \"inst3\" is 11.227 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CP source 4.379 ns + Longest register " "Info: + Longest clock path from clock \"CP\" to source register is 4.379 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns CP 1 CLK PIN_67 8 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CP } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.719 ns) + CELL(0.666 ns) 4.379 ns inst3 2 REG LCFF_X25_Y1_N29 1 " "Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.385 ns" { CP inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 37.91 % ) " "Info: Total cell delay = 1.660 ns ( 37.91 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.719 ns ( 62.09 % ) " "Info: Total interconnect delay = 2.719 ns ( 62.09 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst3 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.544 ns + Longest register pin " "Info: + Longest register to pin delay is 6.544 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst3 1 REG LCFF_X25_Y1_N29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.428 ns) + CELL(3.116 ns) 6.544 ns Q5 2 PIN PIN_147 0 " "Info: 2: + IC(3.428 ns) + CELL(3.116 ns) = 6.544 ns; Loc. = PIN_147; Fanout = 0; PIN Node = 'Q5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.544 ns" { inst3 Q5 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 272 464 640 288 "Q5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.116 ns ( 47.62 % ) " "Info: Total cell delay = 3.116 ns ( 47.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.428 ns ( 52.38 % ) " "Info: Total interconnect delay = 3.428 ns ( 52.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.544 ns" { inst3 Q5 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.544 ns" { inst3 {} Q5 {} } { 0.000ns 3.428ns } { 0.000ns 3.116ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst3 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.544 ns" { inst3 Q5 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.544 ns" { inst3 {} Q5 {} } { 0.000ns 3.428ns } { 0.000ns 3.116ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_TH_RESULT" "inst3 D5 CP -2.294 ns register " "Info: th for register \"inst3\" (data pin = \"D5\", clock pin = \"CP\") is -2.294 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CP destination 4.379 ns + Longest register " "Info: + Longest clock path from clock \"CP\" to destination register is 4.379 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns CP 1 CLK PIN_67 8 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CP } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.719 ns) + CELL(0.666 ns) 4.379 ns inst3 2 REG LCFF_X25_Y1_N29 1 " "Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.385 ns" { CP inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 37.91 % ) " "Info: Total cell delay = 1.660 ns ( 37.91 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.719 ns ( 62.09 % ) " "Info: Total interconnect delay = 2.719 ns ( 62.09 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst3 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.979 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.979 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.964 ns) 0.964 ns D5 1 PIN PIN_86 1 " "Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_86; Fanout = 1; PIN Node = 'D5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { D5 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 272 32 200 288 "D5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.701 ns) + CELL(0.206 ns) 6.871 ns inst3~feeder 2 COMB LCCOMB_X25_Y1_N28 1 " "Info: 2: + IC(5.701 ns) + CELL(0.206 ns) = 6.871 ns; Loc. = LCCOMB_X25_Y1_N28; Fanout = 1; COMB Node = 'inst3~feeder'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.907 ns" { D5 inst3~feeder } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 6.979 ns inst3 3 REG LCFF_X25_Y1_N29 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 6.979 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { inst3~feeder inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.278 ns ( 18.31 % ) " "Info: Total cell delay = 1.278 ns ( 18.31 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.701 ns ( 81.69 % ) " "Info: Total interconnect delay = 5.701 ns ( 81.69 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.979 ns" { D5 inst3~feeder inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.979 ns" { D5 {} D5~combout {} inst3~feeder {} inst3 {} } { 0.000ns 0.000ns 5.701ns 0.000ns } { 0.000ns 0.964ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst3 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.979 ns" { D5 inst3~feeder inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.979 ns" { D5 {} D5~combout {} inst3~feeder {} inst3 {} } { 0.000ns 0.000ns 5.701ns 0.000ns } { 0.000ns 0.964ns 0.206ns 0.108ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:08:53 2022 " "Info: Processing ended: Tue Mar 08 15:08:53 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.atm b/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.atm
index 63f53b7..b1349b4 100644
Binary files a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.atm and b/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.atm differ
diff --git a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.hdbx b/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.hdbx
index 1efc3f1..9050718 100644
Binary files a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.hdbx and b/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.hdbx differ
diff --git a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.rcf b/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.rcf
index b06e220..fbe14b8 100644
Binary files a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.rcf and b/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.rcf differ
diff --git a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.atm b/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.atm
index b389c90..b33cb9a 100644
Binary files a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.atm and b/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.atm differ
diff --git a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.hdbx b/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.hdbx
index bd0a41c..64c73f4 100644
Binary files a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.hdbx and b/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.hdbx differ
diff --git a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.kpt b/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.kpt
index 4f6b7e4..fb8eca1 100644
--- a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.kpt
+++ b/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.kpt
@@ -54,18 +54,6 @@
-
-
-
-
-
-
-
-
-
-
-
-
@@ -78,42 +66,6 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
@@ -138,6 +90,18 @@
+
+
+
+
+
+
+
+
+
+
+
+
@@ -150,5 +114,41 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/register_8b/register_8b.asm.rpt b/register_8b/register_8b.asm.rpt
index f1a493e..5aa1b55 100644
--- a/register_8b/register_8b.asm.rpt
+++ b/register_8b/register_8b.asm.rpt
@@ -1,5 +1,5 @@
Assembler report for register_8b
-Mon Mar 07 09:09:56 2022
+Tue Mar 08 15:08:53 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@@ -38,7 +38,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Mon Mar 07 09:09:56 2022 ;
+; Assembler Status ; Successful - Tue Mar 08 15:08:53 2022 ;
; Revision Name ; register_8b ;
; Top-level Entity Name ; register_8b ;
; Family ; Cyclone II ;
@@ -93,7 +93,7 @@ applicable agreement for further details.
+----------------+----------------------------------------------------------+
; Device ; EP2C8Q208C8 ;
; JTAG usercode ; 0xFFFFFFFF ;
-; Checksum ; 0x000C5E44 ;
+; Checksum ; 0x000C0DB2 ;
+----------------+----------------------------------------------------------+
@@ -104,7 +104,7 @@ applicable agreement for further details.
+--------------------+------------------------------------------------------+
; Device ; EPCS4 ;
; JTAG usercode ; 0x00000000 ;
-; Checksum ; 0x06F0F18E ;
+; Checksum ; 0x06F00D7C ;
; Compression Ratio ; 3 ;
+--------------------+------------------------------------------------------+
@@ -115,15 +115,15 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
- Info: Processing started: Mon Mar 07 09:09:56 2022
+ Info: Processing started: Tue Mar 08 15:08:52 2022
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off register_8b -c register_8b
Info: Writing out detailed assembly data for power analysis
Info: Assembler is generating device programming files
Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 241 megabytes
- Info: Processing ended: Mon Mar 07 09:09:56 2022
- Info: Elapsed time: 00:00:00
+ Info: Processing ended: Tue Mar 08 15:08:53 2022
+ Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:00
diff --git a/register_8b/register_8b.done b/register_8b/register_8b.done
index 3113f2a..d78deed 100644
--- a/register_8b/register_8b.done
+++ b/register_8b/register_8b.done
@@ -1 +1 @@
-Mon Mar 07 09:09:58 2022
+Tue Mar 08 15:08:54 2022
diff --git a/register_8b/register_8b.dpf b/register_8b/register_8b.dpf
new file mode 100644
index 0000000..abe19d9
--- /dev/null
+++ b/register_8b/register_8b.dpf
@@ -0,0 +1,12 @@
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/register_8b/register_8b.fit.rpt b/register_8b/register_8b.fit.rpt
index 3f251e1..74bf3d5 100644
--- a/register_8b/register_8b.fit.rpt
+++ b/register_8b/register_8b.fit.rpt
@@ -1,5 +1,5 @@
Fitter report for register_8b
-Mon Mar 07 09:09:55 2022
+Tue Mar 08 15:08:51 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@@ -24,23 +24,22 @@ Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
16. Delay Chain Summary
17. Pad To Core Delay Chain Fanout
18. Control Signals
- 19. Global & Other Fast Signals
- 20. Non-Global High Fan-Out Signals
- 21. Interconnect Usage Summary
- 22. LAB Logic Elements
- 23. LAB-wide Signals
- 24. LAB Signals Sourced
- 25. LAB Signals Sourced Out
- 26. LAB Distinct Inputs
- 27. Fitter Device Options
- 28. Operating Settings and Conditions
- 29. Estimated Delay Added for Hold Timing
- 30. Advanced Data - General
- 31. Advanced Data - Placement Preparation
- 32. Advanced Data - Placement
- 33. Advanced Data - Routing
- 34. Fitter Messages
- 35. Fitter Suppressed Messages
+ 19. Non-Global High Fan-Out Signals
+ 20. Interconnect Usage Summary
+ 21. LAB Logic Elements
+ 22. LAB-wide Signals
+ 23. LAB Signals Sourced
+ 24. LAB Signals Sourced Out
+ 25. LAB Distinct Inputs
+ 26. Fitter Device Options
+ 27. Operating Settings and Conditions
+ 28. Estimated Delay Added for Hold Timing
+ 29. Advanced Data - General
+ 30. Advanced Data - Placement Preparation
+ 31. Advanced Data - Placement
+ 32. Advanced Data - Routing
+ 33. Fitter Messages
+ 34. Fitter Suppressed Messages
@@ -66,7 +65,7 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+----------------------------------------------+
-; Fitter Status ; Successful - Mon Mar 07 09:09:55 2022 ;
+; Fitter Status ; Successful - Tue Mar 08 15:08:51 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; register_8b ;
; Top-level Entity Name ; register_8b ;
@@ -94,6 +93,7 @@ applicable agreement for further details.
; Minimum Core Junction Temperature ; 0 ; ;
; Maximum Core Junction Temperature ; 85 ; ;
; Fit Attempts to Skip ; 0 ; 0.0 ;
+; Device I/O Standard ; 3.3-V LVTTL ; ;
; Use smart compilation ; Off ; Off ;
; Use TimeQuest Timing Analyzer ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
@@ -215,29 +215,29 @@ The pin-out file can be found in D:/projects/quartus/register_8b/register_8b.pin
; -- Dedicated logic registers ; 8 / 8,256 ( < 1 % ) ;
; -- I/O registers ; 0 / 390 ( 0 % ) ;
; ; ;
-; Total LABs: partially or completely used ; 8 / 516 ( 2 % ) ;
+; Total LABs: partially or completely used ; 1 / 516 ( < 1 % ) ;
; User inserted logic elements ; 0 ;
; Virtual pins ; 0 ;
; I/O pins ; 18 / 138 ( 13 % ) ;
-; -- Clock pins ; 2 / 4 ( 50 % ) ;
-; Global signals ; 2 ;
+; -- Clock pins ; 0 / 4 ( 0 % ) ;
+; Global signals ; 0 ;
; M4Ks ; 0 / 36 ( 0 % ) ;
; Total block memory bits ; 0 / 165,888 ( 0 % ) ;
; Total block memory implementation bits ; 0 / 165,888 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
; PLLs ; 0 / 2 ( 0 % ) ;
-; Global clocks ; 2 / 8 ( 25 % ) ;
+; Global clocks ; 0 / 8 ( 0 % ) ;
; JTAGs ; 0 / 1 ( 0 % ) ;
; ASMI blocks ; 0 / 1 ( 0 % ) ;
; CRC blocks ; 0 / 1 ( 0 % ) ;
; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ;
; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ;
-; Maximum fan-out node ; CLR~clkctrl ;
+; Maximum fan-out node ; CP ;
; Maximum fan-out ; 8 ;
-; Highest non-global fan-out signal ; inst ;
-; Highest non-global fan-out ; 1 ;
-; Total fan-out ; 39 ;
-; Average fan-out ; 1.08 ;
+; Highest non-global fan-out signal ; CP ;
+; Highest non-global fan-out ; 8 ;
+; Total fan-out ; 38 ;
+; Average fan-out ; 1.09 ;
+---------------------------------------------+---------------------+
* Register count does not include registers inside RAM blocks or DSP blocks.
@@ -248,16 +248,16 @@ The pin-out file can be found in D:/projects/quartus/register_8b/register_8b.pin
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
-; CLR ; 24 ; 1 ; 0 ; 9 ; 1 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; CP ; 23 ; 1 ; 0 ; 9 ; 0 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; D0 ; 205 ; 2 ; 1 ; 19 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; D1 ; 28 ; 1 ; 0 ; 9 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; D2 ; 27 ; 1 ; 0 ; 9 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; D3 ; 96 ; 4 ; 30 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; D4 ; 15 ; 1 ; 0 ; 14 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; D5 ; 68 ; 4 ; 12 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; D6 ; 34 ; 1 ; 0 ; 7 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; D7 ; 48 ; 1 ; 0 ; 2 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; CLR ; 68 ; 4 ; 12 ; 0 ; 1 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; CP ; 67 ; 4 ; 9 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; D0 ; 77 ; 4 ; 18 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; D1 ; 80 ; 4 ; 23 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; D2 ; 81 ; 4 ; 23 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; D3 ; 82 ; 4 ; 23 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; D4 ; 84 ; 4 ; 25 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; D5 ; 86 ; 4 ; 25 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; D6 ; 87 ; 4 ; 25 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; D7 ; 88 ; 4 ; 25 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
@@ -266,14 +266,14 @@ The pin-out file can be found in D:/projects/quartus/register_8b/register_8b.pin
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
-; Q0 ; 45 ; 1 ; 0 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; Q1 ; 14 ; 1 ; 0 ; 14 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; Q2 ; 188 ; 2 ; 12 ; 19 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; Q3 ; 147 ; 3 ; 34 ; 15 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; Q4 ; 145 ; 3 ; 34 ; 14 ; 4 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; Q5 ; 47 ; 1 ; 0 ; 2 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; Q6 ; 74 ; 4 ; 16 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; Q7 ; 56 ; 4 ; 1 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; Q0 ; 142 ; 3 ; 34 ; 12 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; Q1 ; 143 ; 3 ; 34 ; 13 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; Q2 ; 144 ; 3 ; 34 ; 13 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; Q3 ; 145 ; 3 ; 34 ; 14 ; 4 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; Q4 ; 146 ; 3 ; 34 ; 15 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; Q5 ; 147 ; 3 ; 34 ; 15 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; Q6 ; 149 ; 3 ; 34 ; 16 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; Q7 ; 150 ; 3 ; 34 ; 16 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
@@ -282,10 +282,10 @@ The pin-out file can be found in D:/projects/quartus/register_8b/register_8b.pin
+----------+------------------+---------------+--------------+
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
+----------+------------------+---------------+--------------+
-; 1 ; 12 / 32 ( 38 % ) ; 3.3V ; -- ;
-; 2 ; 2 / 35 ( 6 % ) ; 3.3V ; -- ;
-; 3 ; 3 / 35 ( 9 % ) ; 3.3V ; -- ;
-; 4 ; 4 / 36 ( 11 % ) ; 3.3V ; -- ;
+; 1 ; 2 / 32 ( 6 % ) ; 3.3V ; -- ;
+; 2 ; 0 / 35 ( 0 % ) ; 3.3V ; -- ;
+; 3 ; 9 / 35 ( 26 % ) ; 3.3V ; -- ;
+; 4 ; 10 / 36 ( 28 % ) ; 3.3V ; -- ;
+----------+------------------+---------------+--------------+
@@ -296,19 +296,19 @@ The pin-out file can be found in D:/projects/quartus/register_8b/register_8b.pin
+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; 1 ; 0 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
; 2 ; 1 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
-; 3 ; 2 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 4 ; 3 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 5 ; 4 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 6 ; 5 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 3 ; 2 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 4 ; 3 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 5 ; 4 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 6 ; 5 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 8 ; 6 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 8 ; 6 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 10 ; 7 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 11 ; 8 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 12 ; 9 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 13 ; 10 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 14 ; 18 ; 1 ; Q1 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 15 ; 19 ; 1 ; D4 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 10 ; 7 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 11 ; 8 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 12 ; 9 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 13 ; 10 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 14 ; 18 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 15 ; 19 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
; 18 ; 22 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
@@ -316,32 +316,32 @@ The pin-out file can be found in D:/projects/quartus/register_8b/register_8b.pin
; 20 ; 24 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ;
; 21 ; 25 ; 1 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ;
; 22 ; 26 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
-; 23 ; 27 ; 1 ; CP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 24 ; 28 ; 1 ; CLR ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 23 ; 27 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; 24 ; 28 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 26 ; 29 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
-; 27 ; 30 ; 1 ; D2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 28 ; 31 ; 1 ; D1 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 27 ; 30 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; 28 ; 31 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 30 ; 32 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 31 ; 33 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 30 ; 32 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 31 ; 33 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 33 ; 35 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 34 ; 36 ; 1 ; D6 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 35 ; 37 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 33 ; 35 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 34 ; 36 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 35 ; 37 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 37 ; 39 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 37 ; 39 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 39 ; 43 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 40 ; 44 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 41 ; 45 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 39 ; 43 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 40 ; 44 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 41 ; 45 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 42 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 43 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 44 ; 49 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 45 ; 50 ; 1 ; Q0 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 46 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 47 ; 52 ; 1 ; Q5 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 48 ; 53 ; 1 ; D7 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 43 ; 48 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 44 ; 49 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 45 ; 50 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 46 ; 51 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 47 ; 52 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 48 ; 53 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 49 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 50 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
; 51 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
@@ -349,69 +349,69 @@ The pin-out file can be found in D:/projects/quartus/register_8b/register_8b.pin
; 53 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 54 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
; 55 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 56 ; 54 ; 4 ; Q7 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
-; 57 ; 55 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 58 ; 56 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 59 ; 57 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 60 ; 58 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 61 ; 59 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 56 ; 54 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 57 ; 55 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 58 ; 56 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 59 ; 57 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 60 ; 58 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 61 ; 59 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 63 ; 60 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 64 ; 61 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 63 ; 60 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 64 ; 61 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 67 ; 69 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 68 ; 70 ; 4 ; D5 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
-; 69 ; 71 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 70 ; 74 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 67 ; 69 ; 4 ; CP ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 68 ; 70 ; 4 ; CLR ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 69 ; 71 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 70 ; 74 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 71 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 72 ; 75 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 72 ; 75 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 74 ; 76 ; 4 ; Q6 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
-; 75 ; 77 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 76 ; 78 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 77 ; 79 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 74 ; 76 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 75 ; 77 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 76 ; 78 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 77 ; 79 ; 4 ; D0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 80 ; 82 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 81 ; 83 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 82 ; 84 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 80 ; 82 ; 4 ; D1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 81 ; 83 ; 4 ; D2 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 82 ; 84 ; 4 ; D3 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 83 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 84 ; 85 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 84 ; 85 ; 4 ; D4 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 85 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 86 ; 86 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 87 ; 87 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 88 ; 88 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 89 ; 89 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 90 ; 90 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 86 ; 86 ; 4 ; D5 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 87 ; 87 ; 4 ; D6 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 88 ; 88 ; 4 ; D7 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 89 ; 89 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 90 ; 90 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 91 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 92 ; 91 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 92 ; 91 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 94 ; 92 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 95 ; 93 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 96 ; 94 ; 4 ; D3 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
-; 97 ; 95 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 94 ; 92 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 95 ; 93 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 96 ; 94 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 97 ; 95 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 98 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 99 ; 96 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 99 ; 96 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 100 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 101 ; 97 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 102 ; 98 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 103 ; 99 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 104 ; 100 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 105 ; 101 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 106 ; 102 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 107 ; 105 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 101 ; 97 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 102 ; 98 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 103 ; 99 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 104 ; 100 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 105 ; 101 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 106 ; 102 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 107 ; 105 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 108 ; 106 ; 3 ; ~LVDS54p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 109 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 110 ; 107 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 110 ; 107 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 111 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 112 ; 108 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 113 ; 109 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 114 ; 110 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 115 ; 112 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 116 ; 113 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 117 ; 114 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 118 ; 117 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 112 ; 108 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 113 ; 109 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 114 ; 110 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 115 ; 112 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 116 ; 113 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 117 ; 114 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 118 ; 117 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 119 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 120 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 121 ; 121 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
@@ -420,32 +420,32 @@ The pin-out file can be found in D:/projects/quartus/register_8b/register_8b.pin
; 124 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 125 ; 123 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
; 126 ; 124 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
-; 127 ; 125 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 128 ; 126 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 127 ; 125 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 128 ; 126 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 129 ; 127 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 130 ; 128 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 131 ; 129 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 132 ; 130 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; 133 ; 131 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 134 ; 132 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 135 ; 133 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 133 ; 131 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 134 ; 132 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 135 ; 133 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 136 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 137 ; 134 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 138 ; 135 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 139 ; 136 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 137 ; 134 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 138 ; 135 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 139 ; 136 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 141 ; 137 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 142 ; 138 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 143 ; 141 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 144 ; 142 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 145 ; 143 ; 3 ; Q4 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 146 ; 149 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 147 ; 150 ; 3 ; Q3 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 141 ; 137 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 142 ; 138 ; 3 ; Q0 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 143 ; 141 ; 3 ; Q1 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 144 ; 142 ; 3 ; Q2 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 145 ; 143 ; 3 ; Q3 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 146 ; 149 ; 3 ; Q4 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 147 ; 150 ; 3 ; Q5 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 148 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 149 ; 151 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 150 ; 152 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 151 ; 153 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 152 ; 154 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 149 ; 151 ; 3 ; Q6 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 150 ; 152 ; 3 ; Q7 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 151 ; 153 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 152 ; 154 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 153 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 154 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
; 155 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
@@ -453,55 +453,55 @@ The pin-out file can be found in D:/projects/quartus/register_8b/register_8b.pin
; 157 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 158 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
; 159 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 160 ; 155 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 161 ; 156 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 162 ; 157 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 163 ; 158 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 164 ; 159 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 165 ; 160 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 160 ; 155 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 161 ; 156 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 162 ; 157 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 163 ; 158 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 164 ; 159 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 165 ; 160 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 166 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 167 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 168 ; 161 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 169 ; 162 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 170 ; 163 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 171 ; 164 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 168 ; 161 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 169 ; 162 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 170 ; 163 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 171 ; 164 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 172 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 173 ; 165 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 173 ; 165 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 174 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 175 ; 168 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 176 ; 169 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 175 ; 168 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 176 ; 169 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 177 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 178 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 179 ; 173 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 180 ; 174 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 181 ; 175 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 182 ; 176 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 179 ; 173 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 180 ; 174 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 181 ; 175 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 182 ; 176 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 183 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 184 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 185 ; 180 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 185 ; 180 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 186 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 187 ; 181 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 188 ; 182 ; 2 ; Q2 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
-; 189 ; 183 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 187 ; 181 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 188 ; 182 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 189 ; 183 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 190 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 191 ; 184 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 192 ; 185 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 193 ; 186 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 191 ; 184 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 192 ; 185 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 193 ; 186 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 194 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 195 ; 187 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 195 ; 187 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 196 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 197 ; 191 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 198 ; 192 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 199 ; 195 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 200 ; 196 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 201 ; 197 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 197 ; 191 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 198 ; 192 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 199 ; 195 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 200 ; 196 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 201 ; 197 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 202 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 203 ; 198 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 203 ; 198 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 204 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 205 ; 199 ; 2 ; D0 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
-; 206 ; 200 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 207 ; 201 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 208 ; 202 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 205 ; 199 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 206 ; 200 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 207 ; 201 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 208 ; 202 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
@@ -568,13 +568,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Q0 ; Output ; -- ; -- ; -- ; -- ;
; D7 ; Input ; 6 ; 6 ; -- ; -- ;
; CP ; Input ; 0 ; 0 ; -- ; -- ;
-; CLR ; Input ; 0 ; 0 ; -- ; -- ;
+; CLR ; Input ; 6 ; 6 ; -- ; -- ;
; D6 ; Input ; 6 ; 6 ; -- ; -- ;
; D5 ; Input ; 6 ; 6 ; -- ; -- ;
; D4 ; Input ; 6 ; 6 ; -- ; -- ;
; D3 ; Input ; 6 ; 6 ; -- ; -- ;
-; D2 ; Input ; 0 ; 0 ; -- ; -- ;
-; D1 ; Input ; 0 ; 0 ; -- ; -- ;
+; D2 ; Input ; 6 ; 6 ; -- ; -- ;
+; D1 ; Input ; 6 ; 6 ; -- ; -- ;
; D0 ; Input ; 6 ; 6 ; -- ; -- ;
+------+----------+---------------+---------------+-----------------------+-----+
@@ -585,19 +585,37 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
+---------------------+-------------------+---------+
; D7 ; ; ;
-; - inst~feeder ; 1 ; 6 ;
+; - inst ; 0 ; 6 ;
; CP ; ; ;
+; - inst ; 1 ; 0 ;
+; - inst2 ; 1 ; 0 ;
+; - inst3 ; 1 ; 0 ;
+; - inst4 ; 1 ; 0 ;
+; - inst5 ; 1 ; 0 ;
+; - inst6 ; 1 ; 0 ;
+; - inst7 ; 1 ; 0 ;
+; - inst8 ; 1 ; 0 ;
; CLR ; ; ;
+; - inst ; 0 ; 6 ;
+; - inst2 ; 0 ; 6 ;
+; - inst3 ; 0 ; 6 ;
+; - inst4 ; 0 ; 6 ;
+; - inst5 ; 0 ; 6 ;
+; - inst6 ; 0 ; 6 ;
+; - inst7 ; 0 ; 6 ;
+; - inst8 ; 0 ; 6 ;
; D6 ; ; ;
; - inst2~feeder ; 0 ; 6 ;
; D5 ; ; ;
-; - inst3 ; 0 ; 6 ;
+; - inst3~feeder ; 0 ; 6 ;
; D4 ; ; ;
-; - inst4~feeder ; 1 ; 6 ;
+; - inst4~feeder ; 0 ; 6 ;
; D3 ; ; ;
; - inst5 ; 0 ; 6 ;
; D2 ; ; ;
+; - inst6~feeder ; 1 ; 6 ;
; D1 ; ; ;
+; - inst7~feeder ; 0 ; 6 ;
; D0 ; ; ;
; - inst8~feeder ; 0 ; 6 ;
+---------------------+-------------------+---------+
@@ -608,26 +626,18 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+
-; CLR ; PIN_24 ; 8 ; Async. clear ; yes ; Global Clock ; GCLK1 ; -- ;
-; CP ; PIN_23 ; 8 ; Clock ; yes ; Global Clock ; GCLK2 ; -- ;
+; CLR ; PIN_68 ; 8 ; Async. clear ; no ; -- ; -- ; -- ;
+; CP ; PIN_67 ; 8 ; Clock ; no ; -- ; -- ; -- ;
+------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+
-+-------------------------------------------------------------------------------------------------+
-; Global & Other Fast Signals ;
-+------+----------+---------+----------------------+------------------+---------------------------+
-; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+------+----------+---------+----------------------+------------------+---------------------------+
-; CLR ; PIN_24 ; 8 ; Global Clock ; GCLK1 ; -- ;
-; CP ; PIN_23 ; 8 ; Global Clock ; GCLK2 ; -- ;
-+------+----------+---------+----------------------+------------------+---------------------------+
-
-
+---------------------------------+
; Non-Global High Fan-Out Signals ;
+-------+-------------------------+
; Name ; Fan-Out ;
+-------+-------------------------+
+; CLR ; 8 ;
+; CP ; 8 ;
; D0 ; 1 ;
; D1 ; 1 ;
; D2 ; 1 ;
@@ -652,30 +662,30 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------+-----------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+-----------------------+
-; Block interconnects ; 16 / 26,052 ( < 1 % ) ;
-; C16 interconnects ; 3 / 1,156 ( < 1 % ) ;
-; C4 interconnects ; 11 / 17,952 ( < 1 % ) ;
-; Direct links ; 2 / 26,052 ( < 1 % ) ;
-; Global clocks ; 2 / 8 ( 25 % ) ;
+; Block interconnects ; 18 / 26,052 ( < 1 % ) ;
+; C16 interconnects ; 0 / 1,156 ( 0 % ) ;
+; C4 interconnects ; 39 / 17,952 ( < 1 % ) ;
+; Direct links ; 0 / 26,052 ( 0 % ) ;
+; Global clocks ; 0 / 8 ( 0 % ) ;
; Local interconnects ; 0 / 8,256 ( 0 % ) ;
-; R24 interconnects ; 3 / 1,020 ( < 1 % ) ;
-; R4 interconnects ; 11 / 22,440 ( < 1 % ) ;
+; R24 interconnects ; 1 / 1,020 ( < 1 % ) ;
+; R4 interconnects ; 31 / 22,440 ( < 1 % ) ;
+----------------------------+-----------------------+
+--------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+-----------------------------+
-; Number of Logic Elements (Average = 1.00) ; Number of LABs (Total = 8) ;
+; Number of Logic Elements (Average = 8.00) ; Number of LABs (Total = 1) ;
+--------------------------------------------+-----------------------------+
-; 1 ; 8 ;
+; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
-; 8 ; 0 ;
+; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
@@ -690,44 +700,70 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+-----------------------------+
-; LAB-wide Signals (Average = 2.00) ; Number of LABs (Total = 8) ;
+; LAB-wide Signals (Average = 2.00) ; Number of LABs (Total = 1) ;
+------------------------------------+-----------------------------+
-; 1 Async. clear ; 8 ;
-; 1 Clock ; 8 ;
+; 1 Async. clear ; 1 ;
+; 1 Clock ; 1 ;
+------------------------------------+-----------------------------+
-+---------------------------------------------------------------------------+
-; LAB Signals Sourced ;
-+---------------------------------------------+-----------------------------+
-; Number of Signals Sourced (Average = 1.63) ; Number of LABs (Total = 8) ;
-+---------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 3 ;
-; 2 ; 5 ;
-+---------------------------------------------+-----------------------------+
++----------------------------------------------------------------------------+
+; LAB Signals Sourced ;
++----------------------------------------------+-----------------------------+
+; Number of Signals Sourced (Average = 14.00) ; Number of LABs (Total = 1) ;
++----------------------------------------------+-----------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 0 ;
+; 4 ; 0 ;
+; 5 ; 0 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 0 ;
+; 9 ; 0 ;
+; 10 ; 0 ;
+; 11 ; 0 ;
+; 12 ; 0 ;
+; 13 ; 0 ;
+; 14 ; 1 ;
++----------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-----------------------------+
-; Number of Signals Sourced Out (Average = 1.00) ; Number of LABs (Total = 8) ;
+; Number of Signals Sourced Out (Average = 8.00) ; Number of LABs (Total = 1) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 0 ;
-; 1 ; 8 ;
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 0 ;
+; 4 ; 0 ;
+; 5 ; 0 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 1 ;
+-------------------------------------------------+-----------------------------+
-+---------------------------------------------------------------------------+
-; LAB Distinct Inputs ;
-+---------------------------------------------+-----------------------------+
-; Number of Distinct Inputs (Average = 3.00) ; Number of LABs (Total = 8) ;
-+---------------------------------------------+-----------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 8 ;
-+---------------------------------------------+-----------------------------+
++----------------------------------------------------------------------------+
+; LAB Distinct Inputs ;
++----------------------------------------------+-----------------------------+
+; Number of Distinct Inputs (Average = 10.00) ; Number of LABs (Total = 1) ;
++----------------------------------------------+-----------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 0 ;
+; 4 ; 0 ;
+; 5 ; 0 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 0 ;
+; 9 ; 0 ;
+; 10 ; 1 ;
++----------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------+
@@ -743,7 +779,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Error detection CRC ; Off ;
; nCEO ; As output driving ground ;
; ASDO,nCSO ; As input tri-stated ;
-; Reserve all unused pins ; As output driving ground ;
+; Reserve all unused pins ; As input tri-stated ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+--------------------------+
@@ -787,23 +823,23 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Mid Slack - Fit Attempt 1 ; 2147483639 ;
; Internal Atom Count - Fit Attempt 1 ; 9 ;
; LE/ALM Count - Fit Attempt 1 ; 9 ;
-; LAB Count - Fit Attempt 1 ; 9 ;
-; Outputs per Lab - Fit Attempt 1 ; 0.889 ;
-; Inputs per LAB - Fit Attempt 1 ; 0.889 ;
-; Global Inputs per LAB - Fit Attempt 1 ; 1.778 ;
-; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:9 ;
-; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:9 ;
-; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:1;1:8 ;
-; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:9 ;
-; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:1;2:8 ;
-; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:9 ;
-; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:9 ;
-; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:1;1:8 ;
-; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:1;1:8 ;
-; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:9 ;
-; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:9 ;
-; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:9 ;
-; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:8 ;
+; LAB Count - Fit Attempt 1 ; 2 ;
+; Outputs per Lab - Fit Attempt 1 ; 4.000 ;
+; Inputs per LAB - Fit Attempt 1 ; 5.000 ;
+; Global Inputs per LAB - Fit Attempt 1 ; 0.000 ;
+; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:1;1:1 ;
+; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:1;2:1 ;
+; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:1;2:1 ;
+; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:1;2:1 ;
+; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:1;1:1 ;
+; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:1;1:1 ;
+; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:1;1:1 ;
+; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:1 ;
; LEs in Chains - Fit Attempt 1 ; 0 ;
; LEs in Long Chains - Fit Attempt 1 ; 0 ;
; LABs with Chains - Fit Attempt 1 ; 0 ;
@@ -818,6 +854,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Name ; Value ;
+------------------------------------+------------+
; Auto Fit Point 2 - Fit Attempt 1 ; ff ;
+; Early Wire Use - Fit Attempt 1 ; 0 ;
+; Early Slack - Fit Attempt 1 ; 2147483639 ;
; Auto Fit Point 5 - Fit Attempt 1 ; ff ;
; Mid Wire Use - Fit Attempt 1 ; 0 ;
; Mid Slack - Fit Attempt 1 ; 2147483639 ;
@@ -843,11 +881,11 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+------------------------------------+-------------+
; Name ; Value ;
+------------------------------------+-------------+
-; Early Wire Use - Fit Attempt 1 ; 0 ;
-; Peak Regional Wire - Fit Attempt 1 ; 0 ;
; Early Slack - Fit Attempt 1 ; 2147483639 ;
; Mid Slack - Fit Attempt 1 ; 2147483639 ;
; Late Slack - Fit Attempt 1 ; -2147483648 ;
+; Early Wire Use - Fit Attempt 1 ; 0 ;
+; Peak Regional Wire - Fit Attempt 1 ; 0 ;
; Late Wire Use - Fit Attempt 1 ; 0 ;
; Time - Fit Attempt 1 ; 0 ;
+------------------------------------+-------------+
@@ -859,7 +897,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
- Info: Processing started: Mon Mar 07 09:09:54 2022
+ Info: Processing started: Tue Mar 08 15:08:50 2022
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off register_8b -c register_8b
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Info: Selected device EP2C8Q208C8 for design "register_8b"
@@ -874,43 +912,11 @@ Info: Fitter converted 3 user pins into dedicated programming pins
Info: Pin ~ASDO~ is reserved at location 1
Info: Pin ~nCSO~ is reserved at location 2
Info: Pin ~LVDS54p/nCEO~ is reserved at location 108
-Warning: No exact pin location assignment(s) for 18 pins of 18 total pins
- Info: Pin Q7 not assigned to an exact location on the device
- Info: Pin Q6 not assigned to an exact location on the device
- Info: Pin Q5 not assigned to an exact location on the device
- Info: Pin Q4 not assigned to an exact location on the device
- Info: Pin Q3 not assigned to an exact location on the device
- Info: Pin Q2 not assigned to an exact location on the device
- Info: Pin Q1 not assigned to an exact location on the device
- Info: Pin Q0 not assigned to an exact location on the device
- Info: Pin D7 not assigned to an exact location on the device
- Info: Pin CP not assigned to an exact location on the device
- Info: Pin CLR not assigned to an exact location on the device
- Info: Pin D6 not assigned to an exact location on the device
- Info: Pin D5 not assigned to an exact location on the device
- Info: Pin D4 not assigned to an exact location on the device
- Info: Pin D3 not assigned to an exact location on the device
- Info: Pin D2 not assigned to an exact location on the device
- Info: Pin D1 not assigned to an exact location on the device
- Info: Pin D0 not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
-Info: Automatically promoted node CP (placed in PIN 23 (CLK0, LVDSCLK0p, Input))
- Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
-Info: Automatically promoted node CLR (placed in PIN 24 (CLK1, LVDSCLK0n, Input))
- Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1
Info: Starting register packing
Info: Finished register packing
Extra Info: No registers were packed into other blocks
-Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
- Info: Number of I/O pins in group: 16 (unused VREF, 3.3V VCCIO, 8 input, 8 output, 0 bidirectional)
- Info: I/O standards used: 3.3-V LVTTL.
-Info: I/O bank details before I/O pin placement
- Info: Statistics of I/O banks
- Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 28 pins available
- Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available
- Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available
- Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available
Info: Fitter preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
@@ -919,7 +925,7 @@ Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources
- Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X10_Y19
+ Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y10 to location X34_Y19
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
@@ -935,11 +941,10 @@ Warning: Found 8 output pins without output pin load capacitance assignment
Info: Pin "Q1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "Q0" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
-Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Generated suppressed messages file D:/projects/quartus/register_8b/register_8b.fit.smsg
-Info: Quartus II Fitter was successful. 0 errors, 3 warnings
+Info: Quartus II Fitter was successful. 0 errors, 1 warning
Info: Peak virtual memory: 306 megabytes
- Info: Processing ended: Mon Mar 07 09:09:55 2022
+ Info: Processing ended: Tue Mar 08 15:08:51 2022
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
diff --git a/register_8b/register_8b.fit.summary b/register_8b/register_8b.fit.summary
index 0cb89f1..bcfb082 100644
--- a/register_8b/register_8b.fit.summary
+++ b/register_8b/register_8b.fit.summary
@@ -1,4 +1,4 @@
-Fitter Status : Successful - Mon Mar 07 09:09:55 2022
+Fitter Status : Successful - Tue Mar 08 15:08:51 2022
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : register_8b
Top-level Entity Name : register_8b
diff --git a/register_8b/register_8b.flow.rpt b/register_8b/register_8b.flow.rpt
index 6fac536..1e8d711 100644
--- a/register_8b/register_8b.flow.rpt
+++ b/register_8b/register_8b.flow.rpt
@@ -1,5 +1,5 @@
Flow report for register_8b
-Mon Mar 07 09:09:57 2022
+Tue Mar 08 15:08:53 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@@ -38,7 +38,7 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+----------------------------------------------+
-; Flow Status ; Successful - Mon Mar 07 09:09:57 2022 ;
+; Flow Status ; Successful - Tue Mar 08 15:08:53 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; register_8b ;
; Top-level Entity Name ; register_8b ;
@@ -63,24 +63,25 @@ applicable agreement for further details.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
-; Start date & time ; 03/07/2022 09:09:53 ;
+; Start date & time ; 03/08/2022 15:08:49 ;
; Main task ; Compilation ;
; Revision Name ; register_8b ;
+-------------------+---------------------+
-+---------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+------------------------------------+---------------------------------+---------------+-------------+----------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+------------------------------------+---------------------------------+---------------+-------------+----------------+
-; COMPILER_SIGNATURE_ID ; 220283517943889.164661539321576 ; -- ; -- ; -- ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
-; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
-; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
-; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
-+------------------------------------+---------------------------------+---------------+-------------+----------------+
++-------------------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings ;
++------------------------------------+-------------------------------------------------+---------------+-------------+----------------+
+; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
++------------------------------------+-------------------------------------------------+---------------+-------------+----------------+
+; COMPILER_SIGNATURE_ID ; 220283517943889.164672332913524 ; -- ; -- ; -- ;
+; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
+; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
+; MISC_FILE ; D:/projects/quartus/register_8b/register_8b.dpf ; -- ; -- ; -- ;
+; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
+; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
+; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
++------------------------------------+-------------------------------------------------+---------------+-------------+----------------+
+-----------------------------------------------------------------------------------------------------------------------------+
@@ -88,11 +89,11 @@ applicable agreement for further details.
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 245 MB ; 00:00:00 ;
+; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 246 MB ; 00:00:00 ;
; Fitter ; 00:00:01 ; 1.0 ; 306 MB ; 00:00:01 ;
-; Assembler ; 00:00:00 ; 1.0 ; 241 MB ; 00:00:00 ;
+; Assembler ; 00:00:01 ; 1.0 ; 241 MB ; 00:00:00 ;
; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 198 MB ; 00:00:00 ;
-; Total ; 00:00:01 ; -- ; -- ; 00:00:01 ;
+; Total ; 00:00:03 ; -- ; -- ; 00:00:01 ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
diff --git a/register_8b/register_8b.map.rpt b/register_8b/register_8b.map.rpt
index f38816b..a3f4246 100644
--- a/register_8b/register_8b.map.rpt
+++ b/register_8b/register_8b.map.rpt
@@ -1,5 +1,5 @@
Analysis & Synthesis report for register_8b
-Mon Mar 07 09:09:53 2022
+Tue Mar 08 15:08:50 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@@ -39,7 +39,7 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+----------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Mon Mar 07 09:09:53 2022 ;
+; Analysis & Synthesis Status ; Successful - Tue Mar 08 15:08:50 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; register_8b ;
; Top-level Entity Name ; register_8b ;
@@ -200,7 +200,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
- Info: Processing started: Mon Mar 07 09:09:53 2022
+ Info: Processing started: Tue Mar 08 15:08:49 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off register_8b -c register_8b
Info: Found 1 design units, including 1 entities, in source file register_8b.bdf
Info: Found entity 1: register_8b
@@ -210,9 +210,9 @@ Info: Implemented 26 device resources after synthesis - the final resource count
Info: Implemented 8 output pins
Info: Implemented 8 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
- Info: Peak virtual memory: 248 megabytes
- Info: Processing ended: Mon Mar 07 09:09:53 2022
- Info: Elapsed time: 00:00:00
+ Info: Peak virtual memory: 250 megabytes
+ Info: Processing ended: Tue Mar 08 15:08:50 2022
+ Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:00
diff --git a/register_8b/register_8b.map.summary b/register_8b/register_8b.map.summary
index c976250..cd9157e 100644
--- a/register_8b/register_8b.map.summary
+++ b/register_8b/register_8b.map.summary
@@ -1,4 +1,4 @@
-Analysis & Synthesis Status : Successful - Mon Mar 07 09:09:53 2022
+Analysis & Synthesis Status : Successful - Tue Mar 08 15:08:50 2022
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : register_8b
Top-level Entity Name : register_8b
diff --git a/register_8b/register_8b.pin b/register_8b/register_8b.pin
index 1931bb2..df151d9 100644
--- a/register_8b/register_8b.pin
+++ b/register_8b/register_8b.pin
@@ -70,19 +70,19 @@ Pin Name/Usage : Location : Dir. : I/O Standard : Voltage
-------------------------------------------------------------------------------------------------------------
~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVTTL : : 1 : N
~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVTTL : : 1 : N
-GND* : 3 : : : : 1 :
-GND* : 4 : : : : 1 :
-GND* : 5 : : : : 1 :
-GND* : 6 : : : : 1 :
+RESERVED_INPUT : 3 : : : : 1 :
+RESERVED_INPUT : 4 : : : : 1 :
+RESERVED_INPUT : 5 : : : : 1 :
+RESERVED_INPUT : 6 : : : : 1 :
VCCIO1 : 7 : power : : 3.3V : 1 :
-GND* : 8 : : : : 1 :
+RESERVED_INPUT : 8 : : : : 1 :
GND : 9 : gnd : : : :
-GND* : 10 : : : : 1 :
-GND* : 11 : : : : 1 :
-GND* : 12 : : : : 1 :
-GND* : 13 : : : : 1 :
-Q1 : 14 : output : 3.3-V LVTTL : : 1 : N
-D4 : 15 : input : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 10 : : : : 1 :
+RESERVED_INPUT : 11 : : : : 1 :
+RESERVED_INPUT : 12 : : : : 1 :
+RESERVED_INPUT : 13 : : : : 1 :
+RESERVED_INPUT : 14 : : : : 1 :
+RESERVED_INPUT : 15 : : : : 1 :
TDO : 16 : output : : : 1 :
TMS : 17 : input : : : 1 :
TCK : 18 : input : : : 1 :
@@ -90,32 +90,32 @@ TDI : 19 : input : :
DATA0 : 20 : input : : : 1 :
DCLK : 21 : : : : 1 :
nCE : 22 : : : : 1 :
-CP : 23 : input : 3.3-V LVTTL : : 1 : N
-CLR : 24 : input : 3.3-V LVTTL : : 1 : N
+GND+ : 23 : : : : 1 :
+GND+ : 24 : : : : 1 :
GND : 25 : gnd : : : :
nCONFIG : 26 : : : : 1 :
-D2 : 27 : input : 3.3-V LVTTL : : 1 : N
-D1 : 28 : input : 3.3-V LVTTL : : 1 : N
+GND+ : 27 : : : : 1 :
+GND+ : 28 : : : : 1 :
VCCIO1 : 29 : power : : 3.3V : 1 :
-GND* : 30 : : : : 1 :
-GND* : 31 : : : : 1 :
+RESERVED_INPUT : 30 : : : : 1 :
+RESERVED_INPUT : 31 : : : : 1 :
VCCINT : 32 : power : : 1.2V : :
-GND* : 33 : : : : 1 :
-D6 : 34 : input : 3.3-V LVTTL : : 1 : N
-GND* : 35 : : : : 1 :
+RESERVED_INPUT : 33 : : : : 1 :
+RESERVED_INPUT : 34 : : : : 1 :
+RESERVED_INPUT : 35 : : : : 1 :
GND : 36 : gnd : : : :
-GND* : 37 : : : : 1 :
+RESERVED_INPUT : 37 : : : : 1 :
GND : 38 : gnd : : : :
-GND* : 39 : : : : 1 :
-GND* : 40 : : : : 1 :
-GND* : 41 : : : : 1 :
+RESERVED_INPUT : 39 : : : : 1 :
+RESERVED_INPUT : 40 : : : : 1 :
+RESERVED_INPUT : 41 : : : : 1 :
VCCIO1 : 42 : power : : 3.3V : 1 :
-GND* : 43 : : : : 1 :
-GND* : 44 : : : : 1 :
-Q0 : 45 : output : 3.3-V LVTTL : : 1 : N
-GND* : 46 : : : : 1 :
-Q5 : 47 : output : 3.3-V LVTTL : : 1 : N
-D7 : 48 : input : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 43 : : : : 1 :
+RESERVED_INPUT : 44 : : : : 1 :
+RESERVED_INPUT : 45 : : : : 1 :
+RESERVED_INPUT : 46 : : : : 1 :
+RESERVED_INPUT : 47 : : : : 1 :
+RESERVED_INPUT : 48 : : : : 1 :
GND : 49 : gnd : : : :
GND_PLL1 : 50 : gnd : : : :
VCCD_PLL1 : 51 : power : : 1.2V : :
@@ -123,69 +123,69 @@ GND_PLL1 : 52 : gnd : :
VCCA_PLL1 : 53 : power : : 1.2V : :
GNDA_PLL1 : 54 : gnd : : : :
GND : 55 : gnd : : : :
-Q7 : 56 : output : 3.3-V LVTTL : : 4 : N
-GND* : 57 : : : : 4 :
-GND* : 58 : : : : 4 :
-GND* : 59 : : : : 4 :
-GND* : 60 : : : : 4 :
-GND* : 61 : : : : 4 :
+RESERVED_INPUT : 56 : : : : 4 :
+RESERVED_INPUT : 57 : : : : 4 :
+RESERVED_INPUT : 58 : : : : 4 :
+RESERVED_INPUT : 59 : : : : 4 :
+RESERVED_INPUT : 60 : : : : 4 :
+RESERVED_INPUT : 61 : : : : 4 :
VCCIO4 : 62 : power : : 3.3V : 4 :
-GND* : 63 : : : : 4 :
-GND* : 64 : : : : 4 :
+RESERVED_INPUT : 63 : : : : 4 :
+RESERVED_INPUT : 64 : : : : 4 :
GND : 65 : gnd : : : :
VCCINT : 66 : power : : 1.2V : :
-GND* : 67 : : : : 4 :
-D5 : 68 : input : 3.3-V LVTTL : : 4 : N
-GND* : 69 : : : : 4 :
-GND* : 70 : : : : 4 :
+CP : 67 : input : 3.3-V LVTTL : : 4 : Y
+CLR : 68 : input : 3.3-V LVTTL : : 4 : Y
+RESERVED_INPUT : 69 : : : : 4 :
+RESERVED_INPUT : 70 : : : : 4 :
VCCIO4 : 71 : power : : 3.3V : 4 :
-GND* : 72 : : : : 4 :
+RESERVED_INPUT : 72 : : : : 4 :
GND : 73 : gnd : : : :
-Q6 : 74 : output : 3.3-V LVTTL : : 4 : N
-GND* : 75 : : : : 4 :
-GND* : 76 : : : : 4 :
-GND* : 77 : : : : 4 :
+RESERVED_INPUT : 74 : : : : 4 :
+RESERVED_INPUT : 75 : : : : 4 :
+RESERVED_INPUT : 76 : : : : 4 :
+D0 : 77 : input : 3.3-V LVTTL : : 4 : Y
GND : 78 : gnd : : : :
VCCINT : 79 : power : : 1.2V : :
-GND* : 80 : : : : 4 :
-GND* : 81 : : : : 4 :
-GND* : 82 : : : : 4 :
+D1 : 80 : input : 3.3-V LVTTL : : 4 : Y
+D2 : 81 : input : 3.3-V LVTTL : : 4 : Y
+D3 : 82 : input : 3.3-V LVTTL : : 4 : Y
VCCIO4 : 83 : power : : 3.3V : 4 :
-GND* : 84 : : : : 4 :
+D4 : 84 : input : 3.3-V LVTTL : : 4 : Y
GND : 85 : gnd : : : :
-GND* : 86 : : : : 4 :
-GND* : 87 : : : : 4 :
-GND* : 88 : : : : 4 :
-GND* : 89 : : : : 4 :
-GND* : 90 : : : : 4 :
+D5 : 86 : input : 3.3-V LVTTL : : 4 : Y
+D6 : 87 : input : 3.3-V LVTTL : : 4 : Y
+D7 : 88 : input : 3.3-V LVTTL : : 4 : Y
+RESERVED_INPUT : 89 : : : : 4 :
+RESERVED_INPUT : 90 : : : : 4 :
VCCIO4 : 91 : power : : 3.3V : 4 :
-GND* : 92 : : : : 4 :
+RESERVED_INPUT : 92 : : : : 4 :
GND : 93 : gnd : : : :
-GND* : 94 : : : : 4 :
-GND* : 95 : : : : 4 :
-D3 : 96 : input : 3.3-V LVTTL : : 4 : N
-GND* : 97 : : : : 4 :
+RESERVED_INPUT : 94 : : : : 4 :
+RESERVED_INPUT : 95 : : : : 4 :
+RESERVED_INPUT : 96 : : : : 4 :
+RESERVED_INPUT : 97 : : : : 4 :
VCCIO4 : 98 : power : : 3.3V : 4 :
-GND* : 99 : : : : 4 :
+RESERVED_INPUT : 99 : : : : 4 :
GND : 100 : gnd : : : :
-GND* : 101 : : : : 4 :
-GND* : 102 : : : : 4 :
-GND* : 103 : : : : 4 :
-GND* : 104 : : : : 4 :
-GND* : 105 : : : : 3 :
-GND* : 106 : : : : 3 :
-GND* : 107 : : : : 3 :
+RESERVED_INPUT : 101 : : : : 4 :
+RESERVED_INPUT : 102 : : : : 4 :
+RESERVED_INPUT : 103 : : : : 4 :
+RESERVED_INPUT : 104 : : : : 4 :
+RESERVED_INPUT : 105 : : : : 3 :
+RESERVED_INPUT : 106 : : : : 3 :
+RESERVED_INPUT : 107 : : : : 3 :
~LVDS54p/nCEO~ : 108 : output : 3.3-V LVTTL : : 3 : N
VCCIO3 : 109 : power : : 3.3V : 3 :
-GND* : 110 : : : : 3 :
+RESERVED_INPUT : 110 : : : : 3 :
GND : 111 : gnd : : : :
-GND* : 112 : : : : 3 :
-GND* : 113 : : : : 3 :
-GND* : 114 : : : : 3 :
-GND* : 115 : : : : 3 :
-GND* : 116 : : : : 3 :
-GND* : 117 : : : : 3 :
-GND* : 118 : : : : 3 :
+RESERVED_INPUT : 112 : : : : 3 :
+RESERVED_INPUT : 113 : : : : 3 :
+RESERVED_INPUT : 114 : : : : 3 :
+RESERVED_INPUT : 115 : : : : 3 :
+RESERVED_INPUT : 116 : : : : 3 :
+RESERVED_INPUT : 117 : : : : 3 :
+RESERVED_INPUT : 118 : : : : 3 :
GND : 119 : gnd : : : :
VCCINT : 120 : power : : 1.2V : :
nSTATUS : 121 : : : : 3 :
@@ -194,32 +194,32 @@ CONF_DONE : 123 : : :
GND : 124 : gnd : : : :
MSEL1 : 125 : : : : 3 :
MSEL0 : 126 : : : : 3 :
-GND* : 127 : : : : 3 :
-GND* : 128 : : : : 3 :
+RESERVED_INPUT : 127 : : : : 3 :
+RESERVED_INPUT : 128 : : : : 3 :
GND+ : 129 : : : : 3 :
GND+ : 130 : : : : 3 :
GND+ : 131 : : : : 3 :
GND+ : 132 : : : : 3 :
-GND* : 133 : : : : 3 :
-GND* : 134 : : : : 3 :
-GND* : 135 : : : : 3 :
+RESERVED_INPUT : 133 : : : : 3 :
+RESERVED_INPUT : 134 : : : : 3 :
+RESERVED_INPUT : 135 : : : : 3 :
VCCIO3 : 136 : power : : 3.3V : 3 :
-GND* : 137 : : : : 3 :
-GND* : 138 : : : : 3 :
-GND* : 139 : : : : 3 :
+RESERVED_INPUT : 137 : : : : 3 :
+RESERVED_INPUT : 138 : : : : 3 :
+RESERVED_INPUT : 139 : : : : 3 :
GND : 140 : gnd : : : :
-GND* : 141 : : : : 3 :
-GND* : 142 : : : : 3 :
-GND* : 143 : : : : 3 :
-GND* : 144 : : : : 3 :
-Q4 : 145 : output : 3.3-V LVTTL : : 3 : N
-GND* : 146 : : : : 3 :
-Q3 : 147 : output : 3.3-V LVTTL : : 3 : N
+RESERVED_INPUT : 141 : : : : 3 :
+Q0 : 142 : output : 3.3-V LVTTL : : 3 : Y
+Q1 : 143 : output : 3.3-V LVTTL : : 3 : Y
+Q2 : 144 : output : 3.3-V LVTTL : : 3 : Y
+Q3 : 145 : output : 3.3-V LVTTL : : 3 : Y
+Q4 : 146 : output : 3.3-V LVTTL : : 3 : Y
+Q5 : 147 : output : 3.3-V LVTTL : : 3 : Y
VCCIO3 : 148 : power : : 3.3V : 3 :
-GND* : 149 : : : : 3 :
-GND* : 150 : : : : 3 :
-GND* : 151 : : : : 3 :
-GND* : 152 : : : : 3 :
+Q6 : 149 : output : 3.3-V LVTTL : : 3 : Y
+Q7 : 150 : output : 3.3-V LVTTL : : 3 : Y
+RESERVED_INPUT : 151 : : : : 3 :
+RESERVED_INPUT : 152 : : : : 3 :
GND : 153 : gnd : : : :
GND_PLL2 : 154 : gnd : : : :
VCCD_PLL2 : 155 : power : : 1.2V : :
@@ -227,52 +227,52 @@ GND_PLL2 : 156 : gnd : :
VCCA_PLL2 : 157 : power : : 1.2V : :
GNDA_PLL2 : 158 : gnd : : : :
GND : 159 : gnd : : : :
-GND* : 160 : : : : 2 :
-GND* : 161 : : : : 2 :
-GND* : 162 : : : : 2 :
-GND* : 163 : : : : 2 :
-GND* : 164 : : : : 2 :
-GND* : 165 : : : : 2 :
+RESERVED_INPUT : 160 : : : : 2 :
+RESERVED_INPUT : 161 : : : : 2 :
+RESERVED_INPUT : 162 : : : : 2 :
+RESERVED_INPUT : 163 : : : : 2 :
+RESERVED_INPUT : 164 : : : : 2 :
+RESERVED_INPUT : 165 : : : : 2 :
VCCIO2 : 166 : power : : 3.3V : 2 :
GND : 167 : gnd : : : :
-GND* : 168 : : : : 2 :
-GND* : 169 : : : : 2 :
-GND* : 170 : : : : 2 :
-GND* : 171 : : : : 2 :
+RESERVED_INPUT : 168 : : : : 2 :
+RESERVED_INPUT : 169 : : : : 2 :
+RESERVED_INPUT : 170 : : : : 2 :
+RESERVED_INPUT : 171 : : : : 2 :
VCCIO2 : 172 : power : : 3.3V : 2 :
-GND* : 173 : : : : 2 :
+RESERVED_INPUT : 173 : : : : 2 :
GND : 174 : gnd : : : :
-GND* : 175 : : : : 2 :
-GND* : 176 : : : : 2 :
+RESERVED_INPUT : 175 : : : : 2 :
+RESERVED_INPUT : 176 : : : : 2 :
GND : 177 : gnd : : : :
VCCINT : 178 : power : : 1.2V : :
-GND* : 179 : : : : 2 :
-GND* : 180 : : : : 2 :
-GND* : 181 : : : : 2 :
-GND* : 182 : : : : 2 :
+RESERVED_INPUT : 179 : : : : 2 :
+RESERVED_INPUT : 180 : : : : 2 :
+RESERVED_INPUT : 181 : : : : 2 :
+RESERVED_INPUT : 182 : : : : 2 :
VCCIO2 : 183 : power : : 3.3V : 2 :
GND : 184 : gnd : : : :
-GND* : 185 : : : : 2 :
+RESERVED_INPUT : 185 : : : : 2 :
GND : 186 : gnd : : : :
-GND* : 187 : : : : 2 :
-Q2 : 188 : output : 3.3-V LVTTL : : 2 : N
-GND* : 189 : : : : 2 :
+RESERVED_INPUT : 187 : : : : 2 :
+RESERVED_INPUT : 188 : : : : 2 :
+RESERVED_INPUT : 189 : : : : 2 :
VCCINT : 190 : power : : 1.2V : :
-GND* : 191 : : : : 2 :
-GND* : 192 : : : : 2 :
-GND* : 193 : : : : 2 :
+RESERVED_INPUT : 191 : : : : 2 :
+RESERVED_INPUT : 192 : : : : 2 :
+RESERVED_INPUT : 193 : : : : 2 :
VCCIO2 : 194 : power : : 3.3V : 2 :
-GND* : 195 : : : : 2 :
+RESERVED_INPUT : 195 : : : : 2 :
GND : 196 : gnd : : : :
-GND* : 197 : : : : 2 :
-GND* : 198 : : : : 2 :
-GND* : 199 : : : : 2 :
-GND* : 200 : : : : 2 :
-GND* : 201 : : : : 2 :
+RESERVED_INPUT : 197 : : : : 2 :
+RESERVED_INPUT : 198 : : : : 2 :
+RESERVED_INPUT : 199 : : : : 2 :
+RESERVED_INPUT : 200 : : : : 2 :
+RESERVED_INPUT : 201 : : : : 2 :
VCCIO2 : 202 : power : : 3.3V : 2 :
-GND* : 203 : : : : 2 :
+RESERVED_INPUT : 203 : : : : 2 :
GND : 204 : gnd : : : :
-D0 : 205 : input : 3.3-V LVTTL : : 2 : N
-GND* : 206 : : : : 2 :
-GND* : 207 : : : : 2 :
-GND* : 208 : : : : 2 :
+RESERVED_INPUT : 205 : : : : 2 :
+RESERVED_INPUT : 206 : : : : 2 :
+RESERVED_INPUT : 207 : : : : 2 :
+RESERVED_INPUT : 208 : : : : 2 :
diff --git a/register_8b/register_8b.pof b/register_8b/register_8b.pof
index f3decea..ca378d9 100644
Binary files a/register_8b/register_8b.pof and b/register_8b/register_8b.pof differ
diff --git a/register_8b/register_8b.qsf b/register_8b/register_8b.qsf
index 5d3858a..a8b14c3 100644
--- a/register_8b/register_8b.qsf
+++ b/register_8b/register_8b.qsf
@@ -50,4 +50,26 @@ set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
\ No newline at end of file
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_location_assignment PIN_77 -to D0
+set_location_assignment PIN_80 -to D1
+set_location_assignment PIN_81 -to D2
+set_location_assignment PIN_82 -to D3
+set_location_assignment PIN_84 -to D4
+set_location_assignment PIN_86 -to D5
+set_location_assignment PIN_87 -to D6
+set_location_assignment PIN_88 -to D7
+set_location_assignment PIN_67 -to CP
+set_location_assignment PIN_68 -to CLR
+set_location_assignment PIN_142 -to Q0
+set_location_assignment PIN_143 -to Q1
+set_location_assignment PIN_144 -to Q2
+set_location_assignment PIN_145 -to Q3
+set_location_assignment PIN_146 -to Q4
+set_location_assignment PIN_147 -to Q5
+set_location_assignment PIN_149 -to Q6
+set_location_assignment PIN_150 -to Q7
+set_global_assignment -name MISC_FILE "D:/projects/quartus/register_8b/register_8b.dpf"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
\ No newline at end of file
diff --git a/register_8b/register_8b.qws b/register_8b/register_8b.qws
index fc216dc..d554e16 100644
--- a/register_8b/register_8b.qws
+++ b/register_8b/register_8b.qws
@@ -2,3 +2,13 @@
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
+[ProjectWorkspace.Frames.ChildFrames]
+ptn_Child1=Document-0
+[ProjectWorkspace.Frames.ChildFrames.Document-0]
+ptn_Child1=ViewFrame-0
+[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
+DocPathName=register_8b.bdf
+DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde}
+IsChildFrameDetached=False
+IsActiveChildFrame=True
+ptn_Child1=StateMap
diff --git a/register_8b/register_8b.sof b/register_8b/register_8b.sof
index 23918f3..61e382f 100644
Binary files a/register_8b/register_8b.sof and b/register_8b/register_8b.sof differ
diff --git a/register_8b/register_8b.tan.rpt b/register_8b/register_8b.tan.rpt
index 2dd1b82..8585e8f 100644
--- a/register_8b/register_8b.tan.rpt
+++ b/register_8b/register_8b.tan.rpt
@@ -1,5 +1,5 @@
Classic Timing Analyzer report for register_8b
-Mon Mar 07 09:09:57 2022
+Tue Mar 08 15:08:53 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@@ -42,9 +42,9 @@ applicable agreement for further details.
+------------------------------+-------+---------------+-------------+-------+-------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+-------+-------+------------+----------+--------------+
-; Worst-case tsu ; N/A ; None ; 4.872 ns ; D3 ; inst5 ; -- ; CP ; 0 ;
-; Worst-case tco ; N/A ; None ; 8.228 ns ; inst3 ; Q5 ; CP ; -- ; 0 ;
-; Worst-case th ; N/A ; None ; 0.406 ns ; D1 ; inst7 ; -- ; CP ; 0 ;
+; Worst-case tsu ; N/A ; None ; 3.273 ns ; D0 ; inst8 ; -- ; CP ; 0 ;
+; Worst-case tco ; N/A ; None ; 11.227 ns ; inst3 ; Q5 ; CP ; -- ; 0 ;
+; Worst-case th ; N/A ; None ; -2.294 ns ; D5 ; inst3 ; -- ; CP ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+-------+-------+------------+----------+--------------+
@@ -112,14 +112,14 @@ applicable agreement for further details.
+-------+--------------+------------+------+-------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+------+-------+----------+
-; N/A ; None ; 4.872 ns ; D3 ; inst5 ; CP ;
-; N/A ; None ; 4.693 ns ; D0 ; inst8 ; CP ;
-; N/A ; None ; 4.628 ns ; D4 ; inst4 ; CP ;
-; N/A ; None ; 4.577 ns ; D6 ; inst2 ; CP ;
-; N/A ; None ; 4.264 ns ; D5 ; inst3 ; CP ;
-; N/A ; None ; 4.007 ns ; D7 ; inst ; CP ;
-; N/A ; None ; 1.029 ns ; D2 ; inst6 ; CP ;
-; N/A ; None ; -0.140 ns ; D1 ; inst7 ; CP ;
+; N/A ; None ; 3.273 ns ; D0 ; inst8 ; CP ;
+; N/A ; None ; 2.730 ns ; D3 ; inst5 ; CP ;
+; N/A ; None ; 2.724 ns ; D7 ; inst ; CP ;
+; N/A ; None ; 2.599 ns ; D1 ; inst7 ; CP ;
+; N/A ; None ; 2.597 ns ; D2 ; inst6 ; CP ;
+; N/A ; None ; 2.569 ns ; D6 ; inst2 ; CP ;
+; N/A ; None ; 2.567 ns ; D4 ; inst4 ; CP ;
+; N/A ; None ; 2.560 ns ; D5 ; inst3 ; CP ;
+-------+--------------+------------+------+-------+----------+
@@ -128,14 +128,14 @@ applicable agreement for further details.
+-------+--------------+------------+-------+----+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+-------+----+------------+
-; N/A ; None ; 8.228 ns ; inst3 ; Q5 ; CP ;
-; N/A ; None ; 8.096 ns ; inst2 ; Q6 ; CP ;
-; N/A ; None ; 7.981 ns ; inst4 ; Q4 ; CP ;
-; N/A ; None ; 7.359 ns ; inst6 ; Q2 ; CP ;
-; N/A ; None ; 7.354 ns ; inst ; Q7 ; CP ;
-; N/A ; None ; 7.258 ns ; inst5 ; Q3 ; CP ;
-; N/A ; None ; 6.982 ns ; inst8 ; Q0 ; CP ;
-; N/A ; None ; 6.969 ns ; inst7 ; Q1 ; CP ;
+; N/A ; None ; 11.227 ns ; inst3 ; Q5 ; CP ;
+; N/A ; None ; 11.226 ns ; inst2 ; Q6 ; CP ;
+; N/A ; None ; 11.174 ns ; inst5 ; Q3 ; CP ;
+; N/A ; None ; 11.161 ns ; inst4 ; Q4 ; CP ;
+; N/A ; None ; 11.157 ns ; inst ; Q7 ; CP ;
+; N/A ; None ; 10.809 ns ; inst8 ; Q0 ; CP ;
+; N/A ; None ; 10.781 ns ; inst7 ; Q1 ; CP ;
+; N/A ; None ; 10.767 ns ; inst6 ; Q2 ; CP ;
+-------+--------------+------------+-------+----+------------+
@@ -144,14 +144,14 @@ applicable agreement for further details.
+---------------+-------------+-----------+------+-------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+------+-------+----------+
-; N/A ; None ; 0.406 ns ; D1 ; inst7 ; CP ;
-; N/A ; None ; -0.763 ns ; D2 ; inst6 ; CP ;
-; N/A ; None ; -3.741 ns ; D7 ; inst ; CP ;
-; N/A ; None ; -3.998 ns ; D5 ; inst3 ; CP ;
-; N/A ; None ; -4.311 ns ; D6 ; inst2 ; CP ;
-; N/A ; None ; -4.362 ns ; D4 ; inst4 ; CP ;
-; N/A ; None ; -4.427 ns ; D0 ; inst8 ; CP ;
-; N/A ; None ; -4.606 ns ; D3 ; inst5 ; CP ;
+; N/A ; None ; -2.294 ns ; D5 ; inst3 ; CP ;
+; N/A ; None ; -2.301 ns ; D4 ; inst4 ; CP ;
+; N/A ; None ; -2.303 ns ; D6 ; inst2 ; CP ;
+; N/A ; None ; -2.331 ns ; D2 ; inst6 ; CP ;
+; N/A ; None ; -2.333 ns ; D1 ; inst7 ; CP ;
+; N/A ; None ; -2.458 ns ; D7 ; inst ; CP ;
+; N/A ; None ; -2.464 ns ; D3 ; inst5 ; CP ;
+; N/A ; None ; -3.007 ns ; D0 ; inst8 ; CP ;
+---------------+-------------+-----------+------+-------+----------+
@@ -161,55 +161,53 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
- Info: Processing started: Mon Mar 07 09:09:57 2022
+ Info: Processing started: Tue Mar 08 15:08:53 2022
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off register_8b -c register_8b --timing_analysis_only
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "CP" is an undefined clock
Info: No valid register-to-register data paths exist for clock "CP"
-Info: tsu for register "inst5" (data pin = "D3", clock pin = "CP") is 4.872 ns
- Info: + Longest pin to register delay is 7.782 ns
- Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_96; Fanout = 1; PIN Node = 'D3'
- Info: 2: + IC(6.338 ns) + CELL(0.460 ns) = 7.782 ns; Loc. = LCFF_X32_Y15_N17; Fanout = 1; REG Node = 'inst5'
- Info: Total cell delay = 1.444 ns ( 18.56 % )
- Info: Total interconnect delay = 6.338 ns ( 81.44 % )
+Info: tsu for register "inst8" (data pin = "D0", clock pin = "CP") is 3.273 ns
+ Info: + Longest pin to register delay is 7.692 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_77; Fanout = 1; PIN Node = 'D0'
+ Info: 2: + IC(6.404 ns) + CELL(0.206 ns) = 7.584 ns; Loc. = LCCOMB_X25_Y1_N22; Fanout = 1; COMB Node = 'inst8~feeder'
+ Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.692 ns; Loc. = LCFF_X25_Y1_N23; Fanout = 1; REG Node = 'inst8'
+ Info: Total cell delay = 1.288 ns ( 16.74 % )
+ Info: Total interconnect delay = 6.404 ns ( 83.26 % )
Info: + Micro setup delay of destination is -0.040 ns
- Info: - Shortest clock path from clock "CP" to destination register is 2.870 ns
- Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CP'
- Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CP~clkctrl'
- Info: 3: + IC(0.925 ns) + CELL(0.666 ns) = 2.870 ns; Loc. = LCFF_X32_Y15_N17; Fanout = 1; REG Node = 'inst5'
- Info: Total cell delay = 1.806 ns ( 62.93 % )
- Info: Total interconnect delay = 1.064 ns ( 37.07 % )
-Info: tco from clock "CP" to destination pin "Q5" through register "inst3" is 8.228 ns
- Info: + Longest clock path from clock "CP" to source register is 2.879 ns
- Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CP'
- Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CP~clkctrl'
- Info: 3: + IC(0.934 ns) + CELL(0.666 ns) = 2.879 ns; Loc. = LCFF_X12_Y2_N9; Fanout = 1; REG Node = 'inst3'
- Info: Total cell delay = 1.806 ns ( 62.73 % )
- Info: Total interconnect delay = 1.073 ns ( 37.27 % )
+ Info: - Shortest clock path from clock "CP" to destination register is 4.379 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'
+ Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N23; Fanout = 1; REG Node = 'inst8'
+ Info: Total cell delay = 1.660 ns ( 37.91 % )
+ Info: Total interconnect delay = 2.719 ns ( 62.09 % )
+Info: tco from clock "CP" to destination pin "Q5" through register "inst3" is 11.227 ns
+ Info: + Longest clock path from clock "CP" to source register is 4.379 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'
+ Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'
+ Info: Total cell delay = 1.660 ns ( 37.91 % )
+ Info: Total interconnect delay = 2.719 ns ( 62.09 % )
Info: + Micro clock to output delay of source is 0.304 ns
- Info: + Longest register to pin delay is 5.045 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y2_N9; Fanout = 1; REG Node = 'inst3'
- Info: 2: + IC(1.765 ns) + CELL(3.280 ns) = 5.045 ns; Loc. = PIN_47; Fanout = 0; PIN Node = 'Q5'
- Info: Total cell delay = 3.280 ns ( 65.01 % )
- Info: Total interconnect delay = 1.765 ns ( 34.99 % )
-Info: th for register "inst7" (data pin = "D1", clock pin = "CP") is 0.406 ns
- Info: + Longest clock path from clock "CP" to destination register is 2.855 ns
- Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CP'
- Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CP~clkctrl'
- Info: 3: + IC(0.910 ns) + CELL(0.666 ns) = 2.855 ns; Loc. = LCFF_X1_Y14_N17; Fanout = 1; REG Node = 'inst7'
- Info: Total cell delay = 1.806 ns ( 63.26 % )
- Info: Total interconnect delay = 1.049 ns ( 36.74 % )
+ Info: + Longest register to pin delay is 6.544 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'
+ Info: 2: + IC(3.428 ns) + CELL(3.116 ns) = 6.544 ns; Loc. = PIN_147; Fanout = 0; PIN Node = 'Q5'
+ Info: Total cell delay = 3.116 ns ( 47.62 % )
+ Info: Total interconnect delay = 3.428 ns ( 52.38 % )
+Info: th for register "inst3" (data pin = "D5", clock pin = "CP") is -2.294 ns
+ Info: + Longest clock path from clock "CP" to destination register is 4.379 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'
+ Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'
+ Info: Total cell delay = 1.660 ns ( 37.91 % )
+ Info: Total interconnect delay = 2.719 ns ( 62.09 % )
Info: + Micro hold delay of destination is 0.306 ns
- Info: - Shortest pin to register delay is 2.755 ns
- Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_28; Fanout = 1; PIN Node = 'D1'
- Info: 2: + IC(1.301 ns) + CELL(0.206 ns) = 2.647 ns; Loc. = LCCOMB_X1_Y14_N16; Fanout = 1; COMB Node = 'inst7~feeder'
- Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 2.755 ns; Loc. = LCFF_X1_Y14_N17; Fanout = 1; REG Node = 'inst7'
- Info: Total cell delay = 1.454 ns ( 52.78 % )
- Info: Total interconnect delay = 1.301 ns ( 47.22 % )
+ Info: - Shortest pin to register delay is 6.979 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_86; Fanout = 1; PIN Node = 'D5'
+ Info: 2: + IC(5.701 ns) + CELL(0.206 ns) = 6.871 ns; Loc. = LCCOMB_X25_Y1_N28; Fanout = 1; COMB Node = 'inst3~feeder'
+ Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 6.979 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'
+ Info: Total cell delay = 1.278 ns ( 18.31 % )
+ Info: Total interconnect delay = 5.701 ns ( 81.69 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 212 megabytes
- Info: Processing ended: Mon Mar 07 09:09:57 2022
+ Info: Processing ended: Tue Mar 08 15:08:53 2022
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00
diff --git a/register_8b/register_8b.tan.summary b/register_8b/register_8b.tan.summary
index 02ebc11..3c39e13 100644
--- a/register_8b/register_8b.tan.summary
+++ b/register_8b/register_8b.tan.summary
@@ -5,9 +5,9 @@ Timing Analyzer Summary
Type : Worst-case tsu
Slack : N/A
Required Time : None
-Actual Time : 4.872 ns
-From : D3
-To : inst5
+Actual Time : 3.273 ns
+From : D0
+To : inst8
From Clock : --
To Clock : CP
Failed Paths : 0
@@ -15,7 +15,7 @@ Failed Paths : 0
Type : Worst-case tco
Slack : N/A
Required Time : None
-Actual Time : 8.228 ns
+Actual Time : 11.227 ns
From : inst3
To : Q5
From Clock : CP
@@ -25,9 +25,9 @@ Failed Paths : 0
Type : Worst-case th
Slack : N/A
Required Time : None
-Actual Time : 0.406 ns
-From : D1
-To : inst7
+Actual Time : -2.294 ns
+From : D5
+To : inst3
From Clock : --
To Clock : CP
Failed Paths : 0
diff --git a/shifter_8b/db/prev_cmp_shifter_8b.map.qmsg b/shifter_8b/db/prev_cmp_shifter_8b.map.qmsg
index 9687781..52c24e3 100644
--- a/shifter_8b/db/prev_cmp_shifter_8b.map.qmsg
+++ b/shifter_8b/db/prev_cmp_shifter_8b.map.qmsg
@@ -1,9 +1,9 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:15:53 2022 " "Info: Processing started: Mon Mar 07 11:15:53 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:17:07 2022 " "Info: Processing started: Mon Mar 07 11:17:07 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 shifter_8b " "Info: Found entity 1: shifter_8b" { } { { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "shifter_8b " "Info: Elaborating entity \"shifter_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "triple_selector_8b.bdf 1 1 " "Warning: Using design file triple_selector_8b.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 triple_selector_8b " "Info: Found entity 1: triple_selector_8b" { } { { "triple_selector_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/triple_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "triple_selector_8b triple_selector_8b:inst " "Info: Elaborating entity \"triple_selector_8b\" for hierarchy \"triple_selector_8b:inst\"" { } { { "shifter_8b.bdf" "inst" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 32 488 584 512 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "33 " "Info: Implemented 33 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Info: Implemented 11 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "14 " "Info: Implemented 14 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "229 " "Info: Peak virtual memory: 229 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:15:53 2022 " "Info: Processing ended: Mon Mar 07 11:15:53 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "229 " "Info: Peak virtual memory: 229 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:17:07 2022 " "Info: Processing ended: Mon Mar 07 11:17:07 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/shifter_8b/db/shifter_8b.(0).cnf.hdb b/shifter_8b/db/shifter_8b.(0).cnf.hdb
index 07be9fe..3174167 100644
Binary files a/shifter_8b/db/shifter_8b.(0).cnf.hdb and b/shifter_8b/db/shifter_8b.(0).cnf.hdb differ
diff --git a/shifter_8b/db/shifter_8b.asm.qmsg b/shifter_8b/db/shifter_8b.asm.qmsg
index 4449273..e680608 100644
--- a/shifter_8b/db/shifter_8b.asm.qmsg
+++ b/shifter_8b/db/shifter_8b.asm.qmsg
@@ -1,7 +1,7 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:15:56 2022 " "Info: Processing started: Mon Mar 07 11:15:56 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:17:18 2022 " "Info: Processing started: Tue Mar 08 15:17:18 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "221 " "Info: Peak virtual memory: 221 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:15:57 2022 " "Info: Processing ended: Mon Mar 07 11:15:57 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:17:18 2022 " "Info: Processing ended: Tue Mar 08 15:17:18 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/shifter_8b/db/shifter_8b.asm_labs.ddb b/shifter_8b/db/shifter_8b.asm_labs.ddb
new file mode 100644
index 0000000..8cd0a91
Binary files /dev/null and b/shifter_8b/db/shifter_8b.asm_labs.ddb differ
diff --git a/shifter_8b/db/shifter_8b.cmp.bpm b/shifter_8b/db/shifter_8b.cmp.bpm
new file mode 100644
index 0000000..d6e0bd5
Binary files /dev/null and b/shifter_8b/db/shifter_8b.cmp.bpm differ
diff --git a/shifter_8b/db/shifter_8b.cmp.cdb b/shifter_8b/db/shifter_8b.cmp.cdb
new file mode 100644
index 0000000..dada380
Binary files /dev/null and b/shifter_8b/db/shifter_8b.cmp.cdb differ
diff --git a/shifter_8b/db/shifter_8b.cmp.hdb b/shifter_8b/db/shifter_8b.cmp.hdb
new file mode 100644
index 0000000..e6663dd
Binary files /dev/null and b/shifter_8b/db/shifter_8b.cmp.hdb differ
diff --git a/shifter_8b/db/shifter_8b.cmp.logdb b/shifter_8b/db/shifter_8b.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/shifter_8b/db/shifter_8b.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/shifter_8b/db/shifter_8b.cmp.rdb b/shifter_8b/db/shifter_8b.cmp.rdb
index 5bfebce..fe318f8 100644
Binary files a/shifter_8b/db/shifter_8b.cmp.rdb and b/shifter_8b/db/shifter_8b.cmp.rdb differ
diff --git a/shifter_8b/db/shifter_8b.cmp.tdb b/shifter_8b/db/shifter_8b.cmp.tdb
new file mode 100644
index 0000000..7805610
Binary files /dev/null and b/shifter_8b/db/shifter_8b.cmp.tdb differ
diff --git a/shifter_8b/db/shifter_8b.cmp0.ddb b/shifter_8b/db/shifter_8b.cmp0.ddb
index 76611d0..37dd3bd 100644
Binary files a/shifter_8b/db/shifter_8b.cmp0.ddb and b/shifter_8b/db/shifter_8b.cmp0.ddb differ
diff --git a/shifter_8b/db/shifter_8b.cmp2.ddb b/shifter_8b/db/shifter_8b.cmp2.ddb
index d1cbd3a..d56bdc0 100644
Binary files a/shifter_8b/db/shifter_8b.cmp2.ddb and b/shifter_8b/db/shifter_8b.cmp2.ddb differ
diff --git a/shifter_8b/db/shifter_8b.eco.cdb b/shifter_8b/db/shifter_8b.eco.cdb
index eb283d9..6612017 100644
Binary files a/shifter_8b/db/shifter_8b.eco.cdb and b/shifter_8b/db/shifter_8b.eco.cdb differ
diff --git a/shifter_8b/db/shifter_8b.fit.qmsg b/shifter_8b/db/shifter_8b.fit.qmsg
index 26deb53..10af5de 100644
--- a/shifter_8b/db/shifter_8b.fit.qmsg
+++ b/shifter_8b/db/shifter_8b.fit.qmsg
@@ -1,14 +1,13 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:15:54 2022 " "Info: Processing started: Mon Mar 07 11:15:54 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:17:16 2022 " "Info: Processing started: Tue Mar 08 15:17:16 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 6 " "Info: Parallel compilation is enabled and will use 4 of the 6 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "IMPP_MPP_USER_DEVICE" "shifter_8b EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"shifter_8b\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
-{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "19 19 " "Warning: No exact pin location assignment(s) for 19 pins of 19 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y0 " "Info: Pin Y0 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y0 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 168 688 864 184 "Y0" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y1 " "Info: Pin Y1 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y1 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 152 688 864 168 "Y1" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y2 " "Info: Pin Y2 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y2 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 136 688 864 152 "Y2" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y3 " "Info: Pin Y3 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y3 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 120 688 864 136 "Y3" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y4 " "Info: Pin Y4 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y4 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 104 688 864 120 "Y4" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y5 " "Info: Pin Y5 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y5 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 88 688 864 104 "Y5" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y6 " "Info: Pin Y6 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y6 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 72 688 864 88 "Y6" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y7 " "Info: Pin Y7 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y7 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 56 688 864 72 "Y7" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A0 " "Info: Pin A0 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { A0 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 408 40 208 424 "A0" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A1 " "Info: Pin A1 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { A1 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 360 40 208 376 "A1" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RM " "Info: Pin RM not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { RM } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 552 40 208 568 "RM" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RM } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DM " "Info: Pin DM not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DM } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 504 40 208 520 "DM" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DM } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LM " "Info: Pin LM not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { LM } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 456 40 208 472 "LM" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LM } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A2 " "Info: Pin A2 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { A2 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 312 40 208 328 "A2" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A3 " "Info: Pin A3 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { A3 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 264 40 208 280 "A3" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A4 " "Info: Pin A4 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { A4 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 216 40 208 232 "A4" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A5 " "Info: Pin A5 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { A5 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 168 40 208 184 "A5" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A6 " "Info: Pin A6 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { A6 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 120 40 208 136 "A6" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A7 " "Info: Pin A7 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { A7 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 72 40 208 88 "A7" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
@@ -19,8 +18,6 @@
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
-{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "19 unused 3.3V 11 8 0 " "Info: Number of I/O pins in group: 19 (unused VREF, 3.3V VCCIO, 11 input, 8 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
-{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 2 30 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 35 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 34 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 36 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
@@ -28,12 +25,11 @@
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X10_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y0 X34_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X34_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y0 0 " "Info: Pin \"Y0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y1 0 " "Info: Pin \"Y1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y2 0 " "Info: Pin \"Y2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y3 0 " "Info: Pin \"Y3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y4 0 " "Info: Pin \"Y4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y5 0 " "Info: Pin \"Y5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y6 0 " "Info: Pin \"Y6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y7 0 " "Info: Pin \"Y7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
-{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/dev/quartus/shifter_8b/shifter_8b.fit.smsg " "Info: Generated suppressed messages file D:/dev/quartus/shifter_8b/shifter_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "286 " "Info: Peak virtual memory: 286 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:15:55 2022 " "Info: Processing ended: Mon Mar 07 11:15:55 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/shifter_8b/shifter_8b.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/shifter_8b/shifter_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "306 " "Info: Peak virtual memory: 306 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:17:17 2022 " "Info: Processing ended: Tue Mar 08 15:17:17 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/shifter_8b/db/shifter_8b.hif b/shifter_8b/db/shifter_8b.hif
index 2ef093c..67e4fda 100644
--- a/shifter_8b/db/shifter_8b.hif
+++ b/shifter_8b/db/shifter_8b.hif
@@ -19,26 +19,6 @@ VHSM_ON
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
-shifter_8b
-# storage
-db|shifter_8b.(0).cnf
-db|shifter_8b.(0).cnf
-# case_insensitive
-# source_file
-shifter_8b.bdf
-d6db26b9c5f411a913f215ffd97edb7d
-26
-# internal_option {
-BLOCK_DESIGN_NAMING
-AUTO
-}
-# hierarchies {
-|
-}
-# macro_sequence
-
-# end
-# entity
triple_selector_8b
# storage
db|shifter_8b.(1).cnf
@@ -57,6 +37,26 @@ triple_selector_8b:inst
}
# macro_sequence
+# end
+# entity
+shifter_8b
+# storage
+db|shifter_8b.(0).cnf
+db|shifter_8b.(0).cnf
+# case_insensitive
+# source_file
+shifter_8b.bdf
+48c3dd91b772b04158a51fc34d535c
+26
+# internal_option {
+BLOCK_DESIGN_NAMING
+AUTO
+}
+# hierarchies {
+|
+}
+# macro_sequence
+
# end
# complete
\ No newline at end of file
diff --git a/shifter_8b/db/shifter_8b.map.bpm b/shifter_8b/db/shifter_8b.map.bpm
index 4872f20..4e215f2 100644
Binary files a/shifter_8b/db/shifter_8b.map.bpm and b/shifter_8b/db/shifter_8b.map.bpm differ
diff --git a/shifter_8b/db/shifter_8b.map.cdb b/shifter_8b/db/shifter_8b.map.cdb
index 8671bce..a0b4dd5 100644
Binary files a/shifter_8b/db/shifter_8b.map.cdb and b/shifter_8b/db/shifter_8b.map.cdb differ
diff --git a/shifter_8b/db/shifter_8b.map.hdb b/shifter_8b/db/shifter_8b.map.hdb
index 366960c..97e63cb 100644
Binary files a/shifter_8b/db/shifter_8b.map.hdb and b/shifter_8b/db/shifter_8b.map.hdb differ
diff --git a/shifter_8b/db/shifter_8b.map.qmsg b/shifter_8b/db/shifter_8b.map.qmsg
index 52c24e3..4893583 100644
--- a/shifter_8b/db/shifter_8b.map.qmsg
+++ b/shifter_8b/db/shifter_8b.map.qmsg
@@ -1,9 +1,9 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:17:07 2022 " "Info: Processing started: Mon Mar 07 11:17:07 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:17:15 2022 " "Info: Processing started: Tue Mar 08 15:17:15 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 shifter_8b " "Info: Found entity 1: shifter_8b" { } { { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 shifter_8b " "Info: Found entity 1: shifter_8b" { } { { "shifter_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "shifter_8b " "Info: Elaborating entity \"shifter_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
-{ "Warning" "WSGN_SEARCH_FILE" "triple_selector_8b.bdf 1 1 " "Warning: Using design file triple_selector_8b.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 triple_selector_8b " "Info: Found entity 1: triple_selector_8b" { } { { "triple_selector_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/triple_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "triple_selector_8b triple_selector_8b:inst " "Info: Elaborating entity \"triple_selector_8b\" for hierarchy \"triple_selector_8b:inst\"" { } { { "shifter_8b.bdf" "inst" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 32 488 584 512 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Warning" "WSGN_SEARCH_FILE" "triple_selector_8b.bdf 1 1 " "Warning: Using design file triple_selector_8b.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 triple_selector_8b " "Info: Found entity 1: triple_selector_8b" { } { { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/triple_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "triple_selector_8b triple_selector_8b:inst " "Info: Elaborating entity \"triple_selector_8b\" for hierarchy \"triple_selector_8b:inst\"" { } { { "shifter_8b.bdf" "inst" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { { 32 488 584 512 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "33 " "Info: Implemented 33 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Info: Implemented 11 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "14 " "Info: Implemented 14 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "229 " "Info: Peak virtual memory: 229 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:17:07 2022 " "Info: Processing ended: Mon Mar 07 11:17:07 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:17:15 2022 " "Info: Processing ended: Tue Mar 08 15:17:15 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/shifter_8b/db/shifter_8b.map_bb.cdb b/shifter_8b/db/shifter_8b.map_bb.cdb
index 9abbc6a..55dd818 100644
Binary files a/shifter_8b/db/shifter_8b.map_bb.cdb and b/shifter_8b/db/shifter_8b.map_bb.cdb differ
diff --git a/shifter_8b/db/shifter_8b.map_bb.hdb b/shifter_8b/db/shifter_8b.map_bb.hdb
index edecfc4..28183aa 100644
Binary files a/shifter_8b/db/shifter_8b.map_bb.hdb and b/shifter_8b/db/shifter_8b.map_bb.hdb differ
diff --git a/shifter_8b/db/shifter_8b.pre_map.cdb b/shifter_8b/db/shifter_8b.pre_map.cdb
index e038146..a6ca160 100644
Binary files a/shifter_8b/db/shifter_8b.pre_map.cdb and b/shifter_8b/db/shifter_8b.pre_map.cdb differ
diff --git a/shifter_8b/db/shifter_8b.pre_map.hdb b/shifter_8b/db/shifter_8b.pre_map.hdb
index 4f97e1a..0fb61fc 100644
Binary files a/shifter_8b/db/shifter_8b.pre_map.hdb and b/shifter_8b/db/shifter_8b.pre_map.hdb differ
diff --git a/shifter_8b/db/shifter_8b.rtlv.hdb b/shifter_8b/db/shifter_8b.rtlv.hdb
index b6e6e83..04527c5 100644
Binary files a/shifter_8b/db/shifter_8b.rtlv.hdb and b/shifter_8b/db/shifter_8b.rtlv.hdb differ
diff --git a/shifter_8b/db/shifter_8b.rtlv_sg.cdb b/shifter_8b/db/shifter_8b.rtlv_sg.cdb
index 5c2cfec..81669c0 100644
Binary files a/shifter_8b/db/shifter_8b.rtlv_sg.cdb and b/shifter_8b/db/shifter_8b.rtlv_sg.cdb differ
diff --git a/shifter_8b/db/shifter_8b.rtlv_sg_swap.cdb b/shifter_8b/db/shifter_8b.rtlv_sg_swap.cdb
index c2c2f88..dd7f3f2 100644
Binary files a/shifter_8b/db/shifter_8b.rtlv_sg_swap.cdb and b/shifter_8b/db/shifter_8b.rtlv_sg_swap.cdb differ
diff --git a/shifter_8b/db/shifter_8b.sgdiff.cdb b/shifter_8b/db/shifter_8b.sgdiff.cdb
index 5c552ae..036f736 100644
Binary files a/shifter_8b/db/shifter_8b.sgdiff.cdb and b/shifter_8b/db/shifter_8b.sgdiff.cdb differ
diff --git a/shifter_8b/db/shifter_8b.sgdiff.hdb b/shifter_8b/db/shifter_8b.sgdiff.hdb
index 71eb3dd..11d56e9 100644
Binary files a/shifter_8b/db/shifter_8b.sgdiff.hdb and b/shifter_8b/db/shifter_8b.sgdiff.hdb differ
diff --git a/shifter_8b/db/shifter_8b.sld_design_entry.sci b/shifter_8b/db/shifter_8b.sld_design_entry.sci
index a8e7d42..904d003 100644
Binary files a/shifter_8b/db/shifter_8b.sld_design_entry.sci and b/shifter_8b/db/shifter_8b.sld_design_entry.sci differ
diff --git a/shifter_8b/db/shifter_8b.tan.qmsg b/shifter_8b/db/shifter_8b.tan.qmsg
index 70add04..ec16759 100644
--- a/shifter_8b/db/shifter_8b.tan.qmsg
+++ b/shifter_8b/db/shifter_8b.tan.qmsg
@@ -1,6 +1,6 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:15:57 2022 " "Info: Processing started: Mon Mar 07 11:15:57 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:17:19 2022 " "Info: Processing started: Tue Mar 08 15:17:19 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 6 " "Info: Parallel compilation is enabled and will use 4 of the 6 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
-{ "Info" "ITDB_FULL_TPD_RESULT" "A6 Y7 13.413 ns Longest " "Info: Longest tpd from source pin \"A6\" to destination pin \"Y7\" is 13.413 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns A6 1 PIN PIN_67 3 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 3; PIN Node = 'A6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A6 } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 120 40 208 136 "A6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.895 ns) + CELL(0.624 ns) 8.513 ns triple_selector_8b:inst\|inst31 2 COMB LCCOMB_X1_Y5_N10 1 " "Info: 2: + IC(6.895 ns) + CELL(0.624 ns) = 8.513 ns; Loc. = LCCOMB_X1_Y5_N10; Fanout = 1; COMB Node = 'triple_selector_8b:inst\|inst31'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.519 ns" { A6 triple_selector_8b:inst|inst31 } "NODE_NAME" } } { "triple_selector_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/triple_selector_8b.bdf" { { 64 488 552 112 "inst31" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.604 ns) + CELL(3.296 ns) 13.413 ns Y7 3 PIN PIN_60 0 " "Info: 3: + IC(1.604 ns) + CELL(3.296 ns) = 13.413 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'Y7'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.900 ns" { triple_selector_8b:inst|inst31 Y7 } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 56 688 864 72 "Y7" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.914 ns ( 36.64 % ) " "Info: Total cell delay = 4.914 ns ( 36.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.499 ns ( 63.36 % ) " "Info: Total interconnect delay = 8.499 ns ( 63.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "13.413 ns" { A6 triple_selector_8b:inst|inst31 Y7 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "13.413 ns" { A6 {} A6~combout {} triple_selector_8b:inst|inst31 {} Y7 {} } { 0.000ns 0.000ns 6.895ns 1.604ns } { 0.000ns 0.994ns 0.624ns 3.296ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "191 " "Info: Peak virtual memory: 191 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:15:58 2022 " "Info: Processing ended: Mon Mar 07 11:15:58 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TPD_RESULT" "LM Y5 15.661 ns Longest " "Info: Longest tpd from source pin \"LM\" to destination pin \"Y5\" is 15.661 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns LM 1 PIN PIN_69 7 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_69; Fanout = 7; PIN Node = 'LM'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LM } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { { 456 40 208 472 "LM" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.879 ns) + CELL(0.650 ns) 8.523 ns triple_selector_8b:inst\|inst23~0 2 COMB LCCOMB_X26_Y1_N18 1 " "Info: 2: + IC(6.879 ns) + CELL(0.650 ns) = 8.523 ns; Loc. = LCCOMB_X26_Y1_N18; Fanout = 1; COMB Node = 'triple_selector_8b:inst\|inst23~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.529 ns" { LM triple_selector_8b:inst|inst23~0 } "NODE_NAME" } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/triple_selector_8b.bdf" { { 352 488 552 400 "inst23" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.370 ns) + CELL(0.624 ns) 9.517 ns triple_selector_8b:inst\|inst23 3 COMB LCCOMB_X26_Y1_N20 1 " "Info: 3: + IC(0.370 ns) + CELL(0.624 ns) = 9.517 ns; Loc. = LCCOMB_X26_Y1_N20; Fanout = 1; COMB Node = 'triple_selector_8b:inst\|inst23'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.994 ns" { triple_selector_8b:inst|inst23~0 triple_selector_8b:inst|inst23 } "NODE_NAME" } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/triple_selector_8b.bdf" { { 352 488 552 400 "inst23" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.028 ns) + CELL(3.116 ns) 15.661 ns Y5 4 PIN PIN_147 0 " "Info: 4: + IC(3.028 ns) + CELL(3.116 ns) = 15.661 ns; Loc. = PIN_147; Fanout = 0; PIN Node = 'Y5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.144 ns" { triple_selector_8b:inst|inst23 Y5 } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { { 88 688 864 104 "Y5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.384 ns ( 34.38 % ) " "Info: Total cell delay = 5.384 ns ( 34.38 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "10.277 ns ( 65.62 % ) " "Info: Total interconnect delay = 10.277 ns ( 65.62 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "15.661 ns" { LM triple_selector_8b:inst|inst23~0 triple_selector_8b:inst|inst23 Y5 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "15.661 ns" { LM {} LM~combout {} triple_selector_8b:inst|inst23~0 {} triple_selector_8b:inst|inst23 {} Y5 {} } { 0.000ns 0.000ns 6.879ns 0.370ns 3.028ns } { 0.000ns 0.994ns 0.650ns 0.624ns 3.116ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:17:19 2022 " "Info: Processing ended: Tue Mar 08 15:17:19 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/shifter_8b/db/shifter_8b.tis_db_list.ddb b/shifter_8b/db/shifter_8b.tis_db_list.ddb
index 62fc03a..2a9a6ed 100644
Binary files a/shifter_8b/db/shifter_8b.tis_db_list.ddb and b/shifter_8b/db/shifter_8b.tis_db_list.ddb differ
diff --git a/shifter_8b/db/shifter_8b.tmw_info b/shifter_8b/db/shifter_8b.tmw_info
new file mode 100644
index 0000000..6516e48
--- /dev/null
+++ b/shifter_8b/db/shifter_8b.tmw_info
@@ -0,0 +1,6 @@
+start_full_compilation:s:00:00:05
+start_analysis_synthesis:s:00:00:02-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:01-start_full_compilation
+start_assembler:s:00:00:02-start_full_compilation
+start_timing_analyzer:s:00:00:00-start_full_compilation
diff --git a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.atm b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.atm
index a96c2a3..9caa3ef 100644
Binary files a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.atm and b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.atm differ
diff --git a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.hdbx b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.hdbx
index bd628c2..ef0a47a 100644
Binary files a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.hdbx and b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.hdbx differ
diff --git a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.rcf b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.rcf
index 39cb3c6..b22c47a 100644
Binary files a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.rcf and b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.rcf differ
diff --git a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.atm b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.atm
index 402825d..ce1faa9 100644
Binary files a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.atm and b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.atm differ
diff --git a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.dpi b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.dpi
index af53fad..21cb83e 100644
Binary files a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.dpi and b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.dpi differ
diff --git a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.hdbx b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.hdbx
index 0a258d7..dec6d46 100644
Binary files a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.hdbx and b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.hdbx differ
diff --git a/shifter_8b/shifter_8b.asm.rpt b/shifter_8b/shifter_8b.asm.rpt
index ab487c3..354db37 100644
--- a/shifter_8b/shifter_8b.asm.rpt
+++ b/shifter_8b/shifter_8b.asm.rpt
@@ -1,5 +1,5 @@
Assembler report for shifter_8b
-Mon Mar 07 11:15:57 2022
+Tue Mar 08 15:17:18 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@@ -10,8 +10,8 @@ Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
- 5. Assembler Device Options: D:/dev/quartus/shifter_8b/shifter_8b.sof
- 6. Assembler Device Options: D:/dev/quartus/shifter_8b/shifter_8b.pof
+ 5. Assembler Device Options: D:/projects/quartus/shifter_8b/shifter_8b.sof
+ 6. Assembler Device Options: D:/projects/quartus/shifter_8b/shifter_8b.pof
7. Assembler Messages
@@ -38,7 +38,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Mon Mar 07 11:15:57 2022 ;
+; Assembler Status ; Successful - Tue Mar 08 15:17:18 2022 ;
; Revision Name ; shifter_8b ;
; Top-level Entity Name ; shifter_8b ;
; Family ; Cyclone II ;
@@ -76,37 +76,37 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+----------+---------------+
-+------------------------------------------+
-; Assembler Generated Files ;
-+------------------------------------------+
-; File Name ;
-+------------------------------------------+
-; D:/dev/quartus/shifter_8b/shifter_8b.sof ;
-; D:/dev/quartus/shifter_8b/shifter_8b.pof ;
-+------------------------------------------+
++-----------------------------------------------+
+; Assembler Generated Files ;
++-----------------------------------------------+
+; File Name ;
++-----------------------------------------------+
+; D:/projects/quartus/shifter_8b/shifter_8b.sof ;
+; D:/projects/quartus/shifter_8b/shifter_8b.pof ;
++-----------------------------------------------+
-+--------------------------------------------------------------------+
-; Assembler Device Options: D:/dev/quartus/shifter_8b/shifter_8b.sof ;
-+----------------+---------------------------------------------------+
-; Option ; Setting ;
-+----------------+---------------------------------------------------+
-; Device ; EP2C8Q208C8 ;
-; JTAG usercode ; 0xFFFFFFFF ;
-; Checksum ; 0x000C73F5 ;
-+----------------+---------------------------------------------------+
++-------------------------------------------------------------------------+
+; Assembler Device Options: D:/projects/quartus/shifter_8b/shifter_8b.sof ;
++----------------+--------------------------------------------------------+
+; Option ; Setting ;
++----------------+--------------------------------------------------------+
+; Device ; EP2C8Q208C8 ;
+; JTAG usercode ; 0xFFFFFFFF ;
+; Checksum ; 0x000C22C5 ;
++----------------+--------------------------------------------------------+
-+--------------------------------------------------------------------+
-; Assembler Device Options: D:/dev/quartus/shifter_8b/shifter_8b.pof ;
-+--------------------+-----------------------------------------------+
-; Option ; Setting ;
-+--------------------+-----------------------------------------------+
-; Device ; EPCS4 ;
-; JTAG usercode ; 0x00000000 ;
-; Checksum ; 0x06F0A9BA ;
-; Compression Ratio ; 3 ;
-+--------------------+-----------------------------------------------+
++-------------------------------------------------------------------------+
+; Assembler Device Options: D:/projects/quartus/shifter_8b/shifter_8b.pof ;
++--------------------+----------------------------------------------------+
+; Option ; Setting ;
++--------------------+----------------------------------------------------+
+; Device ; EPCS4 ;
+; JTAG usercode ; 0x00000000 ;
+; Checksum ; 0x06F00042 ;
+; Compression Ratio ; 3 ;
++--------------------+----------------------------------------------------+
+--------------------+
@@ -115,15 +115,15 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
- Info: Processing started: Mon Mar 07 11:15:56 2022
+ Info: Processing started: Tue Mar 08 15:17:18 2022
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b
Info: Writing out detailed assembly data for power analysis
Info: Assembler is generating device programming files
Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
- Info: Peak virtual memory: 221 megabytes
- Info: Processing ended: Mon Mar 07 11:15:57 2022
- Info: Elapsed time: 00:00:01
+ Info: Peak virtual memory: 241 megabytes
+ Info: Processing ended: Tue Mar 08 15:17:18 2022
+ Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00
diff --git a/shifter_8b/shifter_8b.done b/shifter_8b/shifter_8b.done
index c251748..028fc07 100644
--- a/shifter_8b/shifter_8b.done
+++ b/shifter_8b/shifter_8b.done
@@ -1 +1 @@
-Mon Mar 07 11:17:08 2022
+Tue Mar 08 15:17:19 2022
diff --git a/shifter_8b/shifter_8b.fit.rpt b/shifter_8b/shifter_8b.fit.rpt
index c9cea6f..8ed0afd 100644
--- a/shifter_8b/shifter_8b.fit.rpt
+++ b/shifter_8b/shifter_8b.fit.rpt
@@ -1,5 +1,5 @@
Fitter report for shifter_8b
-Mon Mar 07 11:15:55 2022
+Tue Mar 08 15:17:17 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@@ -63,7 +63,7 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+----------------------------------------------+
-; Fitter Status ; Successful - Mon Mar 07 11:15:55 2022 ;
+; Fitter Status ; Successful - Tue Mar 08 15:17:17 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; shifter_8b ;
; Top-level Entity Name ; shifter_8b ;
@@ -91,6 +91,7 @@ applicable agreement for further details.
; Minimum Core Junction Temperature ; 0 ; ;
; Maximum Core Junction Temperature ; 85 ; ;
; Fit Attempts to Skip ; 0 ; 0.0 ;
+; Device I/O Standard ; 3.3-V LVTTL ; ;
; Use smart compilation ; Off ; Off ;
; Use TimeQuest Timing Analyzer ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
@@ -137,7 +138,7 @@ applicable agreement for further details.
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
-; Number detected on machine ; 6 ;
+; Number detected on machine ; 4 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
@@ -146,7 +147,6 @@ applicable agreement for further details.
; Usage by Processor ; % Time Used ;
; 1 processor ; 100.0% ;
; 2-4 processors ; < 0.1% ;
-; 5-6 processors ; 0.0% ;
+----------------------------+-------------+
@@ -186,7 +186,7 @@ applicable agreement for further details.
+--------------+
; Pin-Out File ;
+--------------+
-The pin-out file can be found in D:/dev/quartus/shifter_8b/shifter_8b.pin.
+The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin.
+--------------------------------------------------------------------+
@@ -217,7 +217,7 @@ The pin-out file can be found in D:/dev/quartus/shifter_8b/shifter_8b.pin.
; User inserted logic elements ; 0 ;
; Virtual pins ; 0 ;
; I/O pins ; 19 / 138 ( 14 % ) ;
-; -- Clock pins ; 2 / 4 ( 50 % ) ;
+; -- Clock pins ; 0 / 4 ( 0 % ) ;
; Global signals ; 0 ;
; M4Ks ; 0 / 36 ( 0 % ) ;
; Total block memory bits ; 0 / 165,888 ( 0 % ) ;
@@ -246,17 +246,17 @@ The pin-out file can be found in D:/dev/quartus/shifter_8b/shifter_8b.pin.
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
-; A0 ; 15 ; 1 ; 0 ; 14 ; 3 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; A1 ; 63 ; 4 ; 3 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; A2 ; 23 ; 1 ; 0 ; 9 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; A3 ; 24 ; 1 ; 0 ; 9 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; A4 ; 27 ; 1 ; 0 ; 9 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; A5 ; 28 ; 1 ; 0 ; 9 ; 3 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; A6 ; 67 ; 4 ; 9 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; A7 ; 13 ; 1 ; 0 ; 16 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; DM ; 205 ; 2 ; 1 ; 19 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; LM ; 30 ; 1 ; 0 ; 8 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; RM ; 35 ; 1 ; 0 ; 7 ; 1 ; 7 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; A0 ; 77 ; 4 ; 18 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; A1 ; 80 ; 4 ; 23 ; 0 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; A2 ; 81 ; 4 ; 23 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; A3 ; 82 ; 4 ; 23 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; A4 ; 84 ; 4 ; 25 ; 0 ; 3 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; A5 ; 86 ; 4 ; 25 ; 0 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; A6 ; 87 ; 4 ; 25 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; A7 ; 88 ; 4 ; 25 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; DM ; 68 ; 4 ; 12 ; 0 ; 1 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; LM ; 69 ; 4 ; 12 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; RM ; 67 ; 4 ; 9 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
@@ -265,14 +265,14 @@ The pin-out file can be found in D:/dev/quartus/shifter_8b/shifter_8b.pin.
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
-; Y0 ; 48 ; 1 ; 0 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; Y1 ; 40 ; 1 ; 0 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; Y2 ; 33 ; 1 ; 0 ; 8 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; Y3 ; 208 ; 2 ; 1 ; 19 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; Y4 ; 34 ; 1 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; Y5 ; 31 ; 1 ; 0 ; 8 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; Y6 ; 39 ; 1 ; 0 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; Y7 ; 60 ; 4 ; 3 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; Y0 ; 142 ; 3 ; 34 ; 12 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; Y1 ; 143 ; 3 ; 34 ; 13 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; Y2 ; 144 ; 3 ; 34 ; 13 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; Y3 ; 145 ; 3 ; 34 ; 14 ; 4 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; Y4 ; 146 ; 3 ; 34 ; 15 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; Y5 ; 147 ; 3 ; 34 ; 15 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; Y6 ; 149 ; 3 ; 34 ; 16 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; Y7 ; 150 ; 3 ; 34 ; 16 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
@@ -281,10 +281,10 @@ The pin-out file can be found in D:/dev/quartus/shifter_8b/shifter_8b.pin.
+----------+------------------+---------------+--------------+
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
+----------+------------------+---------------+--------------+
-; 1 ; 16 / 32 ( 50 % ) ; 3.3V ; -- ;
-; 2 ; 2 / 35 ( 6 % ) ; 3.3V ; -- ;
-; 3 ; 1 / 35 ( 3 % ) ; 3.3V ; -- ;
-; 4 ; 3 / 36 ( 8 % ) ; 3.3V ; -- ;
+; 1 ; 2 / 32 ( 6 % ) ; 3.3V ; -- ;
+; 2 ; 0 / 35 ( 0 % ) ; 3.3V ; -- ;
+; 3 ; 9 / 35 ( 26 % ) ; 3.3V ; -- ;
+; 4 ; 11 / 36 ( 31 % ) ; 3.3V ; -- ;
+----------+------------------+---------------+--------------+
@@ -295,19 +295,19 @@ The pin-out file can be found in D:/dev/quartus/shifter_8b/shifter_8b.pin.
+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; 1 ; 0 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
; 2 ; 1 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
-; 3 ; 2 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 4 ; 3 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 5 ; 4 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 6 ; 5 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 3 ; 2 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 4 ; 3 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 5 ; 4 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 6 ; 5 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 8 ; 6 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 8 ; 6 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 10 ; 7 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 11 ; 8 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 12 ; 9 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 13 ; 10 ; 1 ; A7 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 14 ; 18 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 15 ; 19 ; 1 ; A0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 10 ; 7 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 11 ; 8 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 12 ; 9 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 13 ; 10 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 14 ; 18 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 15 ; 19 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
; 18 ; 22 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
@@ -315,32 +315,32 @@ The pin-out file can be found in D:/dev/quartus/shifter_8b/shifter_8b.pin.
; 20 ; 24 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ;
; 21 ; 25 ; 1 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ;
; 22 ; 26 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
-; 23 ; 27 ; 1 ; A2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 24 ; 28 ; 1 ; A3 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 23 ; 27 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; 24 ; 28 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 26 ; 29 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
-; 27 ; 30 ; 1 ; A4 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 28 ; 31 ; 1 ; A5 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 27 ; 30 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; 28 ; 31 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 30 ; 32 ; 1 ; LM ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 31 ; 33 ; 1 ; Y5 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 30 ; 32 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 31 ; 33 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 33 ; 35 ; 1 ; Y2 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 34 ; 36 ; 1 ; Y4 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 35 ; 37 ; 1 ; RM ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 33 ; 35 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 34 ; 36 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 35 ; 37 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 37 ; 39 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 37 ; 39 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 39 ; 43 ; 1 ; Y6 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 40 ; 44 ; 1 ; Y1 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 41 ; 45 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 39 ; 43 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 40 ; 44 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 41 ; 45 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 42 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 43 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 44 ; 49 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 45 ; 50 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 46 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 47 ; 52 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 48 ; 53 ; 1 ; Y0 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 43 ; 48 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 44 ; 49 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 45 ; 50 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 46 ; 51 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 47 ; 52 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 48 ; 53 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 49 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 50 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
; 51 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
@@ -348,69 +348,69 @@ The pin-out file can be found in D:/dev/quartus/shifter_8b/shifter_8b.pin.
; 53 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 54 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
; 55 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 56 ; 54 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 57 ; 55 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 58 ; 56 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 59 ; 57 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 60 ; 58 ; 4 ; Y7 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
-; 61 ; 59 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 56 ; 54 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 57 ; 55 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 58 ; 56 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 59 ; 57 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 60 ; 58 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 61 ; 59 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 63 ; 60 ; 4 ; A1 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
-; 64 ; 61 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 63 ; 60 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 64 ; 61 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 67 ; 69 ; 4 ; A6 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
-; 68 ; 70 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 69 ; 71 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 70 ; 74 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 67 ; 69 ; 4 ; RM ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 68 ; 70 ; 4 ; DM ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 69 ; 71 ; 4 ; LM ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 70 ; 74 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 71 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 72 ; 75 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 72 ; 75 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 74 ; 76 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 75 ; 77 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 76 ; 78 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 77 ; 79 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 74 ; 76 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 75 ; 77 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 76 ; 78 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 77 ; 79 ; 4 ; A0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 80 ; 82 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 81 ; 83 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 82 ; 84 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 80 ; 82 ; 4 ; A1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 81 ; 83 ; 4 ; A2 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 82 ; 84 ; 4 ; A3 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 83 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 84 ; 85 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 84 ; 85 ; 4 ; A4 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 85 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 86 ; 86 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 87 ; 87 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 88 ; 88 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 89 ; 89 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 90 ; 90 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 86 ; 86 ; 4 ; A5 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 87 ; 87 ; 4 ; A6 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 88 ; 88 ; 4 ; A7 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 89 ; 89 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 90 ; 90 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 91 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 92 ; 91 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 92 ; 91 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 94 ; 92 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 95 ; 93 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 96 ; 94 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 97 ; 95 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 94 ; 92 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 95 ; 93 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 96 ; 94 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 97 ; 95 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 98 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 99 ; 96 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 99 ; 96 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 100 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 101 ; 97 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 102 ; 98 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 103 ; 99 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 104 ; 100 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 105 ; 101 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 106 ; 102 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 107 ; 105 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 101 ; 97 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 102 ; 98 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 103 ; 99 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 104 ; 100 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 105 ; 101 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 106 ; 102 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 107 ; 105 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 108 ; 106 ; 3 ; ~LVDS54p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 109 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 110 ; 107 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 110 ; 107 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 111 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 112 ; 108 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 113 ; 109 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 114 ; 110 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 115 ; 112 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 116 ; 113 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 117 ; 114 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 118 ; 117 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 112 ; 108 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 113 ; 109 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 114 ; 110 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 115 ; 112 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 116 ; 113 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 117 ; 114 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 118 ; 117 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 119 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 120 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 121 ; 121 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
@@ -419,32 +419,32 @@ The pin-out file can be found in D:/dev/quartus/shifter_8b/shifter_8b.pin.
; 124 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 125 ; 123 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
; 126 ; 124 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
-; 127 ; 125 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 128 ; 126 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 127 ; 125 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 128 ; 126 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 129 ; 127 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 130 ; 128 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 131 ; 129 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 132 ; 130 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; 133 ; 131 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 134 ; 132 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 135 ; 133 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 133 ; 131 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 134 ; 132 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 135 ; 133 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 136 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 137 ; 134 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 138 ; 135 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 139 ; 136 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 137 ; 134 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 138 ; 135 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 139 ; 136 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 141 ; 137 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 142 ; 138 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 143 ; 141 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 144 ; 142 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 145 ; 143 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 146 ; 149 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 147 ; 150 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 141 ; 137 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 142 ; 138 ; 3 ; Y0 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 143 ; 141 ; 3 ; Y1 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 144 ; 142 ; 3 ; Y2 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 145 ; 143 ; 3 ; Y3 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 146 ; 149 ; 3 ; Y4 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 147 ; 150 ; 3 ; Y5 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 148 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 149 ; 151 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 150 ; 152 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 151 ; 153 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 152 ; 154 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 149 ; 151 ; 3 ; Y6 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 150 ; 152 ; 3 ; Y7 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 151 ; 153 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 152 ; 154 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 153 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 154 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
; 155 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
@@ -452,55 +452,55 @@ The pin-out file can be found in D:/dev/quartus/shifter_8b/shifter_8b.pin.
; 157 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 158 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
; 159 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 160 ; 155 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 161 ; 156 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 162 ; 157 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 163 ; 158 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 164 ; 159 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 165 ; 160 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 160 ; 155 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 161 ; 156 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 162 ; 157 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 163 ; 158 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 164 ; 159 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 165 ; 160 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 166 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 167 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 168 ; 161 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 169 ; 162 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 170 ; 163 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 171 ; 164 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 168 ; 161 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 169 ; 162 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 170 ; 163 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 171 ; 164 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 172 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 173 ; 165 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 173 ; 165 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 174 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 175 ; 168 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 176 ; 169 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 175 ; 168 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 176 ; 169 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 177 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 178 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 179 ; 173 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 180 ; 174 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 181 ; 175 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 182 ; 176 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 179 ; 173 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 180 ; 174 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 181 ; 175 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 182 ; 176 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 183 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 184 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 185 ; 180 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 185 ; 180 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 186 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 187 ; 181 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 188 ; 182 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 189 ; 183 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 187 ; 181 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 188 ; 182 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 189 ; 183 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 190 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 191 ; 184 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 192 ; 185 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 193 ; 186 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 191 ; 184 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 192 ; 185 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 193 ; 186 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 194 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 195 ; 187 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 195 ; 187 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 196 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 197 ; 191 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 198 ; 192 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 199 ; 195 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 200 ; 196 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 201 ; 197 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 197 ; 191 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 198 ; 192 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 199 ; 195 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 200 ; 196 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 201 ; 197 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 202 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 203 ; 198 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 203 ; 198 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 204 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 205 ; 199 ; 2 ; DM ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
-; 206 ; 200 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 207 ; 201 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 208 ; 202 ; 2 ; Y3 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 205 ; 199 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 206 ; 200 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 207 ; 201 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 208 ; 202 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
@@ -571,10 +571,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; RM ; Input ; 6 ; 6 ; -- ; -- ;
; DM ; Input ; 6 ; 6 ; -- ; -- ;
; LM ; Input ; 6 ; 6 ; -- ; -- ;
-; A2 ; Input ; 0 ; 0 ; -- ; -- ;
-; A3 ; Input ; 0 ; 0 ; -- ; -- ;
-; A4 ; Input ; 0 ; 0 ; -- ; -- ;
-; A5 ; Input ; 0 ; 0 ; -- ; -- ;
+; A2 ; Input ; 6 ; 6 ; -- ; -- ;
+; A3 ; Input ; 6 ; 6 ; -- ; -- ;
+; A4 ; Input ; 6 ; 6 ; -- ; -- ;
+; A5 ; Input ; 6 ; 6 ; -- ; -- ;
; A6 ; Input ; 6 ; 6 ; -- ; -- ;
; A7 ; Input ; 6 ; 6 ; -- ; -- ;
+------+----------+---------------+---------------+-----------------------+-----+
@@ -586,8 +586,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
+-----------------------------------------+-------------------+---------+
; A0 ; ; ;
-; - triple_selector_8b:inst|inst3 ; 1 ; 6 ;
-; - triple_selector_8b:inst|inst7~0 ; 1 ; 6 ;
+; - triple_selector_8b:inst|inst3 ; 0 ; 6 ;
+; - triple_selector_8b:inst|inst7~0 ; 0 ; 6 ;
; A1 ; ; ;
; - triple_selector_8b:inst|inst3 ; 0 ; 6 ;
; - triple_selector_8b:inst|inst7~0 ; 0 ; 6 ;
@@ -610,17 +610,29 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; - triple_selector_8b:inst|inst27~0 ; 0 ; 6 ;
; - triple_selector_8b:inst|inst31 ; 0 ; 6 ;
; LM ; ; ;
-; - triple_selector_8b:inst|inst7~0 ; 0 ; 6 ;
+; - triple_selector_8b:inst|inst7~0 ; 1 ; 6 ;
+; - triple_selector_8b:inst|inst11~0 ; 1 ; 6 ;
+; - triple_selector_8b:inst|inst15~0 ; 1 ; 6 ;
+; - triple_selector_8b:inst|inst19~0 ; 1 ; 6 ;
+; - triple_selector_8b:inst|inst23~0 ; 1 ; 6 ;
+; - triple_selector_8b:inst|inst27~0 ; 1 ; 6 ;
+; - triple_selector_8b:inst|inst31 ; 1 ; 6 ;
+; A2 ; ; ;
+; - triple_selector_8b:inst|inst7 ; 0 ; 6 ;
; - triple_selector_8b:inst|inst11~0 ; 0 ; 6 ;
; - triple_selector_8b:inst|inst15~0 ; 0 ; 6 ;
+; A3 ; ; ;
+; - triple_selector_8b:inst|inst11 ; 0 ; 6 ;
+; - triple_selector_8b:inst|inst15~0 ; 0 ; 6 ;
+; - triple_selector_8b:inst|inst19~0 ; 0 ; 6 ;
+; A4 ; ; ;
+; - triple_selector_8b:inst|inst15 ; 0 ; 6 ;
; - triple_selector_8b:inst|inst19~0 ; 0 ; 6 ;
; - triple_selector_8b:inst|inst23~0 ; 0 ; 6 ;
-; - triple_selector_8b:inst|inst27~0 ; 0 ; 6 ;
-; - triple_selector_8b:inst|inst31 ; 0 ; 6 ;
-; A2 ; ; ;
-; A3 ; ; ;
-; A4 ; ; ;
; A5 ; ; ;
+; - triple_selector_8b:inst|inst19 ; 0 ; 6 ;
+; - triple_selector_8b:inst|inst23~0 ; 0 ; 6 ;
+; - triple_selector_8b:inst|inst27~0 ; 0 ; 6 ;
; A6 ; ; ;
; - triple_selector_8b:inst|inst23 ; 0 ; 6 ;
; - triple_selector_8b:inst|inst27~0 ; 0 ; 6 ;
@@ -669,14 +681,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------+-----------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+-----------------------+
-; Block interconnects ; 19 / 26,052 ( < 1 % ) ;
-; C16 interconnects ; 2 / 1,156 ( < 1 % ) ;
-; C4 interconnects ; 24 / 17,952 ( < 1 % ) ;
-; Direct links ; 2 / 26,052 ( < 1 % ) ;
+; Block interconnects ; 20 / 26,052 ( < 1 % ) ;
+; C16 interconnects ; 3 / 1,156 ( < 1 % ) ;
+; C4 interconnects ; 38 / 17,952 ( < 1 % ) ;
+; Direct links ; 0 / 26,052 ( 0 % ) ;
; Global clocks ; 0 / 8 ( 0 % ) ;
; Local interconnects ; 6 / 8,256 ( < 1 % ) ;
-; R24 interconnects ; 0 / 1,020 ( 0 % ) ;
-; R4 interconnects ; 4 / 22,440 ( < 1 % ) ;
+; R24 interconnects ; 3 / 1,020 ( < 1 % ) ;
+; R4 interconnects ; 23 / 22,440 ( < 1 % ) ;
+----------------------------+-----------------------+
@@ -777,7 +789,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Error detection CRC ; Off ;
; nCEO ; As output driving ground ;
; ASDO,nCSO ; As input tri-stated ;
-; Reserve all unused pins ; As output driving ground ;
+; Reserve all unused pins ; As input tri-stated ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+--------------------------+
@@ -852,6 +864,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Name ; Value ;
+------------------------------------+------------+
; Auto Fit Point 2 - Fit Attempt 1 ; ff ;
+; Early Wire Use - Fit Attempt 1 ; 0 ;
+; Early Slack - Fit Attempt 1 ; 2147483639 ;
; Auto Fit Point 5 - Fit Attempt 1 ; ff ;
; Mid Wire Use - Fit Attempt 1 ; 0 ;
; Mid Slack - Fit Attempt 1 ; 2147483639 ;
@@ -878,10 +892,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Name ; Value ;
+------------------------------------+-------------+
; Early Slack - Fit Attempt 1 ; 2147483639 ;
+; Early Wire Use - Fit Attempt 1 ; 0 ;
+; Peak Regional Wire - Fit Attempt 1 ; 1 ;
; Mid Slack - Fit Attempt 1 ; 2147483639 ;
; Late Slack - Fit Attempt 1 ; -2147483648 ;
-; Early Wire Use - Fit Attempt 1 ; 0 ;
-; Peak Regional Wire - Fit Attempt 1 ; 0 ;
; Late Wire Use - Fit Attempt 1 ; 0 ;
; Time - Fit Attempt 1 ; 0 ;
+------------------------------------+-------------+
@@ -893,9 +907,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
- Info: Processing started: Mon Mar 07 11:15:54 2022
+ Info: Processing started: Tue Mar 08 15:17:16 2022
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b
-Info: Parallel compilation is enabled and will use 4 of the 6 processors detected
+Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Info: Selected device EP2C8Q208C8 for design "shifter_8b"
Info: Low junction temperature is 0 degrees C
Info: High junction temperature is 85 degrees C
@@ -908,40 +922,11 @@ Info: Fitter converted 3 user pins into dedicated programming pins
Info: Pin ~ASDO~ is reserved at location 1
Info: Pin ~nCSO~ is reserved at location 2
Info: Pin ~LVDS54p/nCEO~ is reserved at location 108
-Warning: No exact pin location assignment(s) for 19 pins of 19 total pins
- Info: Pin Y0 not assigned to an exact location on the device
- Info: Pin Y1 not assigned to an exact location on the device
- Info: Pin Y2 not assigned to an exact location on the device
- Info: Pin Y3 not assigned to an exact location on the device
- Info: Pin Y4 not assigned to an exact location on the device
- Info: Pin Y5 not assigned to an exact location on the device
- Info: Pin Y6 not assigned to an exact location on the device
- Info: Pin Y7 not assigned to an exact location on the device
- Info: Pin A0 not assigned to an exact location on the device
- Info: Pin A1 not assigned to an exact location on the device
- Info: Pin RM not assigned to an exact location on the device
- Info: Pin DM not assigned to an exact location on the device
- Info: Pin LM not assigned to an exact location on the device
- Info: Pin A2 not assigned to an exact location on the device
- Info: Pin A3 not assigned to an exact location on the device
- Info: Pin A4 not assigned to an exact location on the device
- Info: Pin A5 not assigned to an exact location on the device
- Info: Pin A6 not assigned to an exact location on the device
- Info: Pin A7 not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Starting register packing
Info: Finished register packing
Extra Info: No registers were packed into other blocks
-Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
- Info: Number of I/O pins in group: 19 (unused VREF, 3.3V VCCIO, 11 input, 8 output, 0 bidirectional)
- Info: I/O standards used: 3.3-V LVTTL.
-Info: I/O bank details before I/O pin placement
- Info: Statistics of I/O banks
- Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available
- Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available
- Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available
- Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available
Info: Fitter preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
@@ -950,7 +935,7 @@ Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources
- Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9
+ Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X34_Y9
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
@@ -966,11 +951,10 @@ Warning: Found 8 output pins without output pin load capacitance assignment
Info: Pin "Y6" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "Y7" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
-Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
-Info: Generated suppressed messages file D:/dev/quartus/shifter_8b/shifter_8b.fit.smsg
-Info: Quartus II Fitter was successful. 0 errors, 3 warnings
- Info: Peak virtual memory: 286 megabytes
- Info: Processing ended: Mon Mar 07 11:15:55 2022
+Info: Generated suppressed messages file D:/projects/quartus/shifter_8b/shifter_8b.fit.smsg
+Info: Quartus II Fitter was successful. 0 errors, 1 warning
+ Info: Peak virtual memory: 306 megabytes
+ Info: Processing ended: Tue Mar 08 15:17:17 2022
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
@@ -978,6 +962,6 @@ Info: Quartus II Fitter was successful. 0 errors, 3 warnings
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
-The suppressed messages can be found in D:/dev/quartus/shifter_8b/shifter_8b.fit.smsg.
+The suppressed messages can be found in D:/projects/quartus/shifter_8b/shifter_8b.fit.smsg.
diff --git a/shifter_8b/shifter_8b.fit.summary b/shifter_8b/shifter_8b.fit.summary
index 066e8ec..875a683 100644
--- a/shifter_8b/shifter_8b.fit.summary
+++ b/shifter_8b/shifter_8b.fit.summary
@@ -1,4 +1,4 @@
-Fitter Status : Successful - Mon Mar 07 11:15:55 2022
+Fitter Status : Successful - Tue Mar 08 15:17:17 2022
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : shifter_8b
Top-level Entity Name : shifter_8b
diff --git a/shifter_8b/shifter_8b.flow.rpt b/shifter_8b/shifter_8b.flow.rpt
index d09b958..a5831e7 100644
--- a/shifter_8b/shifter_8b.flow.rpt
+++ b/shifter_8b/shifter_8b.flow.rpt
@@ -1,5 +1,5 @@
Flow report for shifter_8b
-Mon Mar 07 11:17:07 2022
+Tue Mar 08 15:17:19 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@@ -38,23 +38,23 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+----------------------------------------------+
-; Flow Status ; Successful - Mon Mar 07 11:17:07 2022 ;
+; Flow Status ; Successful - Tue Mar 08 15:17:19 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; shifter_8b ;
; Top-level Entity Name ; shifter_8b ;
; Family ; Cyclone II ;
; Device ; EP2C8Q208C8 ;
; Timing Models ; Final ;
-; Met timing requirements ; N/A ;
-; Total logic elements ; 14 ;
-; Total combinational functions ; 14 ;
-; Dedicated logic registers ; 0 ;
+; Met timing requirements ; Yes ;
+; Total logic elements ; 14 / 8,256 ( < 1 % ) ;
+; Total combinational functions ; 14 / 8,256 ( < 1 % ) ;
+; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ;
; Total registers ; 0 ;
-; Total pins ; 19 ;
+; Total pins ; 19 / 138 ( 14 % ) ;
; Total virtual pins ; 0 ;
-; Total memory bits ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; Total PLLs ; 0 ;
+; Total memory bits ; 0 / 165,888 ( 0 % ) ;
+; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
+; Total PLLs ; 0 / 2 ( 0 % ) ;
+------------------------------------+----------------------------------------------+
@@ -63,50 +63,60 @@ applicable agreement for further details.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
-; Start date & time ; 03/07/2022 11:17:07 ;
+; Start date & time ; 03/08/2022 15:17:15 ;
; Main task ; Compilation ;
; Revision Name ; shifter_8b ;
+-------------------+---------------------+
-+------------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+------------------------------------+------------------------------------------+---------------+-------------+----------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+------------------------------------+------------------------------------------+---------------+-------------+----------------+
-; COMPILER_SIGNATURE_ID ; 136411542855513.164662302732708 ; -- ; -- ; -- ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
-; MISC_FILE ; D:/dev/quartus/shifter_8b/shifter_8b.dpf ; -- ; -- ; -- ;
-; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
-; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
-; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
-+------------------------------------+------------------------------------------+---------------+-------------+----------------+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings ;
++------------------------------------+-----------------------------------------------+---------------+-------------+----------------+
+; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
++------------------------------------+-----------------------------------------------+---------------+-------------+----------------+
+; COMPILER_SIGNATURE_ID ; 220283517943889.164672383512820 ; -- ; -- ; -- ;
+; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
+; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
+; MISC_FILE ; D:/dev/quartus/shifter_8b/shifter_8b.dpf ; -- ; -- ; -- ;
+; MISC_FILE ; D:/projects/quartus/shifter_8b/shifter_8b.dpf ; -- ; -- ; -- ;
+; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
+; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
+; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
++------------------------------------+-----------------------------------------------+---------------+-------------+----------------+
-+--------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 226 MB ; 00:00:00 ;
-; Total ; 00:00:00 ; -- ; -- ; 00:00:00 ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
++-----------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time ;
++-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 246 MB ; 00:00:00 ;
+; Fitter ; 00:00:01 ; 1.0 ; 306 MB ; 00:00:01 ;
+; Assembler ; 00:00:00 ; 1.0 ; 241 MB ; 00:00:00 ;
+; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 198 MB ; 00:00:00 ;
+; Total ; 00:00:01 ; -- ; -- ; 00:00:01 ;
++-------------------------+--------------+-------------------------+---------------------+------------------------------------+
-+---------------------------------------------------------------------------------------+
-; Flow OS Summary ;
-+----------------------+------------------+---------------+------------+----------------+
-; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
-+----------------------+------------------+---------------+------------+----------------+
-; Analysis & Synthesis ; DESKTOP-G0CBSMT ; Windows Vista ; 6.2 ; x86_64 ;
-+----------------------+------------------+---------------+------------+----------------+
++------------------------------------------------------------------------------------------+
+; Flow OS Summary ;
++-------------------------+------------------+---------------+------------+----------------+
+; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
++-------------------------+------------------+---------------+------------+----------------+
+; Analysis & Synthesis ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
+; Fitter ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
+; Assembler ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
+; Classic Timing Analyzer ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
++-------------------------+------------------+---------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b
+quartus_fit --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b
+quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b
+quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only
diff --git a/shifter_8b/shifter_8b.map.rpt b/shifter_8b/shifter_8b.map.rpt
index b68366d..529797a 100644
--- a/shifter_8b/shifter_8b.map.rpt
+++ b/shifter_8b/shifter_8b.map.rpt
@@ -1,5 +1,5 @@
Analysis & Synthesis report for shifter_8b
-Mon Mar 07 11:17:07 2022
+Tue Mar 08 15:17:15 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@@ -39,7 +39,7 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+----------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Mon Mar 07 11:17:07 2022 ;
+; Analysis & Synthesis Status ; Successful - Tue Mar 08 15:17:15 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; shifter_8b ;
; Top-level Entity Name ; shifter_8b ;
@@ -131,14 +131,14 @@ applicable agreement for further details.
+--------------------------------------------------------------+--------------------+--------------------+
-+--------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+------------------------------------------+--------------------------------------------------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
-+----------------------------------+-----------------+------------------------------------------+--------------------------------------------------+
-; shifter_8b.bdf ; yes ; User Block Diagram/Schematic File ; D:/dev/quartus/shifter_8b/shifter_8b.bdf ;
-; triple_selector_8b.bdf ; yes ; Auto-Found Block Diagram/Schematic File ; D:/dev/quartus/shifter_8b/triple_selector_8b.bdf ;
-+----------------------------------+-----------------+------------------------------------------+--------------------------------------------------+
++-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++----------------------------------+-----------------+------------------------------------------+-------------------------------------------------------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
++----------------------------------+-----------------+------------------------------------------+-------------------------------------------------------+
+; shifter_8b.bdf ; yes ; User Block Diagram/Schematic File ; D:/projects/quartus/shifter_8b/shifter_8b.bdf ;
+; triple_selector_8b.bdf ; yes ; Auto-Found Block Diagram/Schematic File ; D:/projects/quartus/shifter_8b/triple_selector_8b.bdf ;
++----------------------------------+-----------------+------------------------------------------+-------------------------------------------------------+
+-----------------------------------------------------+
@@ -202,7 +202,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
- Info: Processing started: Mon Mar 07 11:17:07 2022
+ Info: Processing started: Tue Mar 08 15:17:15 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b
Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf
Info: Found entity 1: shifter_8b
@@ -215,8 +215,8 @@ Info: Implemented 33 device resources after synthesis - the final resource count
Info: Implemented 8 output pins
Info: Implemented 14 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 229 megabytes
- Info: Processing ended: Mon Mar 07 11:17:07 2022
+ Info: Peak virtual memory: 250 megabytes
+ Info: Processing ended: Tue Mar 08 15:17:15 2022
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00
diff --git a/shifter_8b/shifter_8b.map.summary b/shifter_8b/shifter_8b.map.summary
index 81855af..0d1f33e 100644
--- a/shifter_8b/shifter_8b.map.summary
+++ b/shifter_8b/shifter_8b.map.summary
@@ -1,4 +1,4 @@
-Analysis & Synthesis Status : Successful - Mon Mar 07 11:17:07 2022
+Analysis & Synthesis Status : Successful - Tue Mar 08 15:17:15 2022
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : shifter_8b
Top-level Entity Name : shifter_8b
diff --git a/shifter_8b/shifter_8b.pin b/shifter_8b/shifter_8b.pin
index afef75c..bf29e52 100644
--- a/shifter_8b/shifter_8b.pin
+++ b/shifter_8b/shifter_8b.pin
@@ -70,19 +70,19 @@ Pin Name/Usage : Location : Dir. : I/O Standard : Voltage
-------------------------------------------------------------------------------------------------------------
~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVTTL : : 1 : N
~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVTTL : : 1 : N
-GND* : 3 : : : : 1 :
-GND* : 4 : : : : 1 :
-GND* : 5 : : : : 1 :
-GND* : 6 : : : : 1 :
+RESERVED_INPUT : 3 : : : : 1 :
+RESERVED_INPUT : 4 : : : : 1 :
+RESERVED_INPUT : 5 : : : : 1 :
+RESERVED_INPUT : 6 : : : : 1 :
VCCIO1 : 7 : power : : 3.3V : 1 :
-GND* : 8 : : : : 1 :
+RESERVED_INPUT : 8 : : : : 1 :
GND : 9 : gnd : : : :
-GND* : 10 : : : : 1 :
-GND* : 11 : : : : 1 :
-GND* : 12 : : : : 1 :
-A7 : 13 : input : 3.3-V LVTTL : : 1 : N
-GND* : 14 : : : : 1 :
-A0 : 15 : input : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 10 : : : : 1 :
+RESERVED_INPUT : 11 : : : : 1 :
+RESERVED_INPUT : 12 : : : : 1 :
+RESERVED_INPUT : 13 : : : : 1 :
+RESERVED_INPUT : 14 : : : : 1 :
+RESERVED_INPUT : 15 : : : : 1 :
TDO : 16 : output : : : 1 :
TMS : 17 : input : : : 1 :
TCK : 18 : input : : : 1 :
@@ -90,32 +90,32 @@ TDI : 19 : input : :
DATA0 : 20 : input : : : 1 :
DCLK : 21 : : : : 1 :
nCE : 22 : : : : 1 :
-A2 : 23 : input : 3.3-V LVTTL : : 1 : N
-A3 : 24 : input : 3.3-V LVTTL : : 1 : N
+GND+ : 23 : : : : 1 :
+GND+ : 24 : : : : 1 :
GND : 25 : gnd : : : :
nCONFIG : 26 : : : : 1 :
-A4 : 27 : input : 3.3-V LVTTL : : 1 : N
-A5 : 28 : input : 3.3-V LVTTL : : 1 : N
+GND+ : 27 : : : : 1 :
+GND+ : 28 : : : : 1 :
VCCIO1 : 29 : power : : 3.3V : 1 :
-LM : 30 : input : 3.3-V LVTTL : : 1 : N
-Y5 : 31 : output : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 30 : : : : 1 :
+RESERVED_INPUT : 31 : : : : 1 :
VCCINT : 32 : power : : 1.2V : :
-Y2 : 33 : output : 3.3-V LVTTL : : 1 : N
-Y4 : 34 : output : 3.3-V LVTTL : : 1 : N
-RM : 35 : input : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 33 : : : : 1 :
+RESERVED_INPUT : 34 : : : : 1 :
+RESERVED_INPUT : 35 : : : : 1 :
GND : 36 : gnd : : : :
-GND* : 37 : : : : 1 :
+RESERVED_INPUT : 37 : : : : 1 :
GND : 38 : gnd : : : :
-Y6 : 39 : output : 3.3-V LVTTL : : 1 : N
-Y1 : 40 : output : 3.3-V LVTTL : : 1 : N
-GND* : 41 : : : : 1 :
+RESERVED_INPUT : 39 : : : : 1 :
+RESERVED_INPUT : 40 : : : : 1 :
+RESERVED_INPUT : 41 : : : : 1 :
VCCIO1 : 42 : power : : 3.3V : 1 :
-GND* : 43 : : : : 1 :
-GND* : 44 : : : : 1 :
-GND* : 45 : : : : 1 :
-GND* : 46 : : : : 1 :
-GND* : 47 : : : : 1 :
-Y0 : 48 : output : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 43 : : : : 1 :
+RESERVED_INPUT : 44 : : : : 1 :
+RESERVED_INPUT : 45 : : : : 1 :
+RESERVED_INPUT : 46 : : : : 1 :
+RESERVED_INPUT : 47 : : : : 1 :
+RESERVED_INPUT : 48 : : : : 1 :
GND : 49 : gnd : : : :
GND_PLL1 : 50 : gnd : : : :
VCCD_PLL1 : 51 : power : : 1.2V : :
@@ -123,69 +123,69 @@ GND_PLL1 : 52 : gnd : :
VCCA_PLL1 : 53 : power : : 1.2V : :
GNDA_PLL1 : 54 : gnd : : : :
GND : 55 : gnd : : : :
-GND* : 56 : : : : 4 :
-GND* : 57 : : : : 4 :
-GND* : 58 : : : : 4 :
-GND* : 59 : : : : 4 :
-Y7 : 60 : output : 3.3-V LVTTL : : 4 : N
-GND* : 61 : : : : 4 :
+RESERVED_INPUT : 56 : : : : 4 :
+RESERVED_INPUT : 57 : : : : 4 :
+RESERVED_INPUT : 58 : : : : 4 :
+RESERVED_INPUT : 59 : : : : 4 :
+RESERVED_INPUT : 60 : : : : 4 :
+RESERVED_INPUT : 61 : : : : 4 :
VCCIO4 : 62 : power : : 3.3V : 4 :
-A1 : 63 : input : 3.3-V LVTTL : : 4 : N
-GND* : 64 : : : : 4 :
+RESERVED_INPUT : 63 : : : : 4 :
+RESERVED_INPUT : 64 : : : : 4 :
GND : 65 : gnd : : : :
VCCINT : 66 : power : : 1.2V : :
-A6 : 67 : input : 3.3-V LVTTL : : 4 : N
-GND* : 68 : : : : 4 :
-GND* : 69 : : : : 4 :
-GND* : 70 : : : : 4 :
+RM : 67 : input : 3.3-V LVTTL : : 4 : Y
+DM : 68 : input : 3.3-V LVTTL : : 4 : Y
+LM : 69 : input : 3.3-V LVTTL : : 4 : Y
+RESERVED_INPUT : 70 : : : : 4 :
VCCIO4 : 71 : power : : 3.3V : 4 :
-GND* : 72 : : : : 4 :
+RESERVED_INPUT : 72 : : : : 4 :
GND : 73 : gnd : : : :
-GND* : 74 : : : : 4 :
-GND* : 75 : : : : 4 :
-GND* : 76 : : : : 4 :
-GND* : 77 : : : : 4 :
+RESERVED_INPUT : 74 : : : : 4 :
+RESERVED_INPUT : 75 : : : : 4 :
+RESERVED_INPUT : 76 : : : : 4 :
+A0 : 77 : input : 3.3-V LVTTL : : 4 : Y
GND : 78 : gnd : : : :
VCCINT : 79 : power : : 1.2V : :
-GND* : 80 : : : : 4 :
-GND* : 81 : : : : 4 :
-GND* : 82 : : : : 4 :
+A1 : 80 : input : 3.3-V LVTTL : : 4 : Y
+A2 : 81 : input : 3.3-V LVTTL : : 4 : Y
+A3 : 82 : input : 3.3-V LVTTL : : 4 : Y
VCCIO4 : 83 : power : : 3.3V : 4 :
-GND* : 84 : : : : 4 :
+A4 : 84 : input : 3.3-V LVTTL : : 4 : Y
GND : 85 : gnd : : : :
-GND* : 86 : : : : 4 :
-GND* : 87 : : : : 4 :
-GND* : 88 : : : : 4 :
-GND* : 89 : : : : 4 :
-GND* : 90 : : : : 4 :
+A5 : 86 : input : 3.3-V LVTTL : : 4 : Y
+A6 : 87 : input : 3.3-V LVTTL : : 4 : Y
+A7 : 88 : input : 3.3-V LVTTL : : 4 : Y
+RESERVED_INPUT : 89 : : : : 4 :
+RESERVED_INPUT : 90 : : : : 4 :
VCCIO4 : 91 : power : : 3.3V : 4 :
-GND* : 92 : : : : 4 :
+RESERVED_INPUT : 92 : : : : 4 :
GND : 93 : gnd : : : :
-GND* : 94 : : : : 4 :
-GND* : 95 : : : : 4 :
-GND* : 96 : : : : 4 :
-GND* : 97 : : : : 4 :
+RESERVED_INPUT : 94 : : : : 4 :
+RESERVED_INPUT : 95 : : : : 4 :
+RESERVED_INPUT : 96 : : : : 4 :
+RESERVED_INPUT : 97 : : : : 4 :
VCCIO4 : 98 : power : : 3.3V : 4 :
-GND* : 99 : : : : 4 :
+RESERVED_INPUT : 99 : : : : 4 :
GND : 100 : gnd : : : :
-GND* : 101 : : : : 4 :
-GND* : 102 : : : : 4 :
-GND* : 103 : : : : 4 :
-GND* : 104 : : : : 4 :
-GND* : 105 : : : : 3 :
-GND* : 106 : : : : 3 :
-GND* : 107 : : : : 3 :
+RESERVED_INPUT : 101 : : : : 4 :
+RESERVED_INPUT : 102 : : : : 4 :
+RESERVED_INPUT : 103 : : : : 4 :
+RESERVED_INPUT : 104 : : : : 4 :
+RESERVED_INPUT : 105 : : : : 3 :
+RESERVED_INPUT : 106 : : : : 3 :
+RESERVED_INPUT : 107 : : : : 3 :
~LVDS54p/nCEO~ : 108 : output : 3.3-V LVTTL : : 3 : N
VCCIO3 : 109 : power : : 3.3V : 3 :
-GND* : 110 : : : : 3 :
+RESERVED_INPUT : 110 : : : : 3 :
GND : 111 : gnd : : : :
-GND* : 112 : : : : 3 :
-GND* : 113 : : : : 3 :
-GND* : 114 : : : : 3 :
-GND* : 115 : : : : 3 :
-GND* : 116 : : : : 3 :
-GND* : 117 : : : : 3 :
-GND* : 118 : : : : 3 :
+RESERVED_INPUT : 112 : : : : 3 :
+RESERVED_INPUT : 113 : : : : 3 :
+RESERVED_INPUT : 114 : : : : 3 :
+RESERVED_INPUT : 115 : : : : 3 :
+RESERVED_INPUT : 116 : : : : 3 :
+RESERVED_INPUT : 117 : : : : 3 :
+RESERVED_INPUT : 118 : : : : 3 :
GND : 119 : gnd : : : :
VCCINT : 120 : power : : 1.2V : :
nSTATUS : 121 : : : : 3 :
@@ -194,32 +194,32 @@ CONF_DONE : 123 : : :
GND : 124 : gnd : : : :
MSEL1 : 125 : : : : 3 :
MSEL0 : 126 : : : : 3 :
-GND* : 127 : : : : 3 :
-GND* : 128 : : : : 3 :
+RESERVED_INPUT : 127 : : : : 3 :
+RESERVED_INPUT : 128 : : : : 3 :
GND+ : 129 : : : : 3 :
GND+ : 130 : : : : 3 :
GND+ : 131 : : : : 3 :
GND+ : 132 : : : : 3 :
-GND* : 133 : : : : 3 :
-GND* : 134 : : : : 3 :
-GND* : 135 : : : : 3 :
+RESERVED_INPUT : 133 : : : : 3 :
+RESERVED_INPUT : 134 : : : : 3 :
+RESERVED_INPUT : 135 : : : : 3 :
VCCIO3 : 136 : power : : 3.3V : 3 :
-GND* : 137 : : : : 3 :
-GND* : 138 : : : : 3 :
-GND* : 139 : : : : 3 :
+RESERVED_INPUT : 137 : : : : 3 :
+RESERVED_INPUT : 138 : : : : 3 :
+RESERVED_INPUT : 139 : : : : 3 :
GND : 140 : gnd : : : :
-GND* : 141 : : : : 3 :
-GND* : 142 : : : : 3 :
-GND* : 143 : : : : 3 :
-GND* : 144 : : : : 3 :
-GND* : 145 : : : : 3 :
-GND* : 146 : : : : 3 :
-GND* : 147 : : : : 3 :
+RESERVED_INPUT : 141 : : : : 3 :
+Y0 : 142 : output : 3.3-V LVTTL : : 3 : Y
+Y1 : 143 : output : 3.3-V LVTTL : : 3 : Y
+Y2 : 144 : output : 3.3-V LVTTL : : 3 : Y
+Y3 : 145 : output : 3.3-V LVTTL : : 3 : Y
+Y4 : 146 : output : 3.3-V LVTTL : : 3 : Y
+Y5 : 147 : output : 3.3-V LVTTL : : 3 : Y
VCCIO3 : 148 : power : : 3.3V : 3 :
-GND* : 149 : : : : 3 :
-GND* : 150 : : : : 3 :
-GND* : 151 : : : : 3 :
-GND* : 152 : : : : 3 :
+Y6 : 149 : output : 3.3-V LVTTL : : 3 : Y
+Y7 : 150 : output : 3.3-V LVTTL : : 3 : Y
+RESERVED_INPUT : 151 : : : : 3 :
+RESERVED_INPUT : 152 : : : : 3 :
GND : 153 : gnd : : : :
GND_PLL2 : 154 : gnd : : : :
VCCD_PLL2 : 155 : power : : 1.2V : :
@@ -227,52 +227,52 @@ GND_PLL2 : 156 : gnd : :
VCCA_PLL2 : 157 : power : : 1.2V : :
GNDA_PLL2 : 158 : gnd : : : :
GND : 159 : gnd : : : :
-GND* : 160 : : : : 2 :
-GND* : 161 : : : : 2 :
-GND* : 162 : : : : 2 :
-GND* : 163 : : : : 2 :
-GND* : 164 : : : : 2 :
-GND* : 165 : : : : 2 :
+RESERVED_INPUT : 160 : : : : 2 :
+RESERVED_INPUT : 161 : : : : 2 :
+RESERVED_INPUT : 162 : : : : 2 :
+RESERVED_INPUT : 163 : : : : 2 :
+RESERVED_INPUT : 164 : : : : 2 :
+RESERVED_INPUT : 165 : : : : 2 :
VCCIO2 : 166 : power : : 3.3V : 2 :
GND : 167 : gnd : : : :
-GND* : 168 : : : : 2 :
-GND* : 169 : : : : 2 :
-GND* : 170 : : : : 2 :
-GND* : 171 : : : : 2 :
+RESERVED_INPUT : 168 : : : : 2 :
+RESERVED_INPUT : 169 : : : : 2 :
+RESERVED_INPUT : 170 : : : : 2 :
+RESERVED_INPUT : 171 : : : : 2 :
VCCIO2 : 172 : power : : 3.3V : 2 :
-GND* : 173 : : : : 2 :
+RESERVED_INPUT : 173 : : : : 2 :
GND : 174 : gnd : : : :
-GND* : 175 : : : : 2 :
-GND* : 176 : : : : 2 :
+RESERVED_INPUT : 175 : : : : 2 :
+RESERVED_INPUT : 176 : : : : 2 :
GND : 177 : gnd : : : :
VCCINT : 178 : power : : 1.2V : :
-GND* : 179 : : : : 2 :
-GND* : 180 : : : : 2 :
-GND* : 181 : : : : 2 :
-GND* : 182 : : : : 2 :
+RESERVED_INPUT : 179 : : : : 2 :
+RESERVED_INPUT : 180 : : : : 2 :
+RESERVED_INPUT : 181 : : : : 2 :
+RESERVED_INPUT : 182 : : : : 2 :
VCCIO2 : 183 : power : : 3.3V : 2 :
GND : 184 : gnd : : : :
-GND* : 185 : : : : 2 :
+RESERVED_INPUT : 185 : : : : 2 :
GND : 186 : gnd : : : :
-GND* : 187 : : : : 2 :
-GND* : 188 : : : : 2 :
-GND* : 189 : : : : 2 :
+RESERVED_INPUT : 187 : : : : 2 :
+RESERVED_INPUT : 188 : : : : 2 :
+RESERVED_INPUT : 189 : : : : 2 :
VCCINT : 190 : power : : 1.2V : :
-GND* : 191 : : : : 2 :
-GND* : 192 : : : : 2 :
-GND* : 193 : : : : 2 :
+RESERVED_INPUT : 191 : : : : 2 :
+RESERVED_INPUT : 192 : : : : 2 :
+RESERVED_INPUT : 193 : : : : 2 :
VCCIO2 : 194 : power : : 3.3V : 2 :
-GND* : 195 : : : : 2 :
+RESERVED_INPUT : 195 : : : : 2 :
GND : 196 : gnd : : : :
-GND* : 197 : : : : 2 :
-GND* : 198 : : : : 2 :
-GND* : 199 : : : : 2 :
-GND* : 200 : : : : 2 :
-GND* : 201 : : : : 2 :
+RESERVED_INPUT : 197 : : : : 2 :
+RESERVED_INPUT : 198 : : : : 2 :
+RESERVED_INPUT : 199 : : : : 2 :
+RESERVED_INPUT : 200 : : : : 2 :
+RESERVED_INPUT : 201 : : : : 2 :
VCCIO2 : 202 : power : : 3.3V : 2 :
-GND* : 203 : : : : 2 :
+RESERVED_INPUT : 203 : : : : 2 :
GND : 204 : gnd : : : :
-DM : 205 : input : 3.3-V LVTTL : : 2 : N
-GND* : 206 : : : : 2 :
-GND* : 207 : : : : 2 :
-Y3 : 208 : output : 3.3-V LVTTL : : 2 : N
+RESERVED_INPUT : 205 : : : : 2 :
+RESERVED_INPUT : 206 : : : : 2 :
+RESERVED_INPUT : 207 : : : : 2 :
+RESERVED_INPUT : 208 : : : : 2 :
diff --git a/shifter_8b/shifter_8b.pof b/shifter_8b/shifter_8b.pof
index eccf019..a8fc6b6 100644
Binary files a/shifter_8b/shifter_8b.pof and b/shifter_8b/shifter_8b.pof differ
diff --git a/shifter_8b/shifter_8b.qsf b/shifter_8b/shifter_8b.qsf
index 5550511..5d8c71a 100644
--- a/shifter_8b/shifter_8b.qsf
+++ b/shifter_8b/shifter_8b.qsf
@@ -51,4 +51,27 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-set_global_assignment -name MISC_FILE "D:/dev/quartus/shifter_8b/shifter_8b.dpf"
\ No newline at end of file
+set_global_assignment -name MISC_FILE "D:/dev/quartus/shifter_8b/shifter_8b.dpf"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_location_assignment PIN_77 -to A0
+set_location_assignment PIN_80 -to A1
+set_location_assignment PIN_81 -to A2
+set_location_assignment PIN_82 -to A3
+set_location_assignment PIN_84 -to A4
+set_location_assignment PIN_86 -to A5
+set_location_assignment PIN_87 -to A6
+set_location_assignment PIN_88 -to A7
+set_location_assignment PIN_68 -to DM
+set_location_assignment PIN_69 -to LM
+set_location_assignment PIN_67 -to RM
+set_location_assignment PIN_142 -to Y0
+set_location_assignment PIN_143 -to Y1
+set_location_assignment PIN_144 -to Y2
+set_location_assignment PIN_145 -to Y3
+set_location_assignment PIN_146 -to Y4
+set_location_assignment PIN_147 -to Y5
+set_location_assignment PIN_149 -to Y6
+set_location_assignment PIN_150 -to Y7
+set_global_assignment -name MISC_FILE "D:/projects/quartus/shifter_8b/shifter_8b.dpf"
\ No newline at end of file
diff --git a/shifter_8b/shifter_8b.qws b/shifter_8b/shifter_8b.qws
index fc216dc..9571b85 100644
--- a/shifter_8b/shifter_8b.qws
+++ b/shifter_8b/shifter_8b.qws
@@ -2,3 +2,13 @@
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
+[ProjectWorkspace.Frames.ChildFrames]
+ptn_Child1=Document-0
+[ProjectWorkspace.Frames.ChildFrames.Document-0]
+ptn_Child1=ViewFrame-0
+[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
+DocPathName=shifter_8b.bdf
+DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde}
+IsChildFrameDetached=False
+IsActiveChildFrame=True
+ptn_Child1=StateMap
diff --git a/shifter_8b/shifter_8b.sof b/shifter_8b/shifter_8b.sof
index a8c45e5..d28ea9d 100644
Binary files a/shifter_8b/shifter_8b.sof and b/shifter_8b/shifter_8b.sof differ
diff --git a/shifter_8b/shifter_8b.tan.rpt b/shifter_8b/shifter_8b.tan.rpt
index 0be7927..e94c46b 100644
--- a/shifter_8b/shifter_8b.tan.rpt
+++ b/shifter_8b/shifter_8b.tan.rpt
@@ -1,5 +1,5 @@
Classic Timing Analyzer report for shifter_8b
-Mon Mar 07 11:15:57 2022
+Tue Mar 08 15:17:19 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@@ -39,7 +39,7 @@ applicable agreement for further details.
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
-; Worst-case tpd ; N/A ; None ; 13.413 ns ; A6 ; Y7 ; -- ; -- ; 0 ;
+; Worst-case tpd ; N/A ; None ; 15.661 ns ; LM ; Y5 ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
@@ -81,7 +81,7 @@ applicable agreement for further details.
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
-; Number detected on machine ; 6 ;
+; Number detected on machine ; 4 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
@@ -89,7 +89,7 @@ applicable agreement for further details.
; ; ;
; Usage by Processor ; % Time Used ;
; 1 processor ; 100.0% ;
-; 2-6 processors ; 0.0% ;
+; 2-4 processors ; 0.0% ;
+----------------------------+-------------+
@@ -98,50 +98,50 @@ applicable agreement for further details.
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
-; N/A ; None ; 13.413 ns ; A6 ; Y7 ;
-; N/A ; None ; 13.008 ns ; A7 ; Y7 ;
-; N/A ; None ; 12.993 ns ; DM ; Y3 ;
-; N/A ; None ; 12.852 ns ; A1 ; Y2 ;
-; N/A ; None ; 12.792 ns ; A6 ; Y6 ;
-; N/A ; None ; 12.781 ns ; DM ; Y4 ;
-; N/A ; None ; 12.737 ns ; DM ; Y5 ;
-; N/A ; None ; 12.544 ns ; LM ; Y3 ;
-; N/A ; None ; 12.476 ns ; DM ; Y7 ;
-; N/A ; None ; 12.455 ns ; A1 ; Y0 ;
-; N/A ; None ; 12.428 ns ; A1 ; Y1 ;
-; N/A ; None ; 12.419 ns ; A0 ; Y0 ;
-; N/A ; None ; 12.394 ns ; A0 ; Y1 ;
-; N/A ; None ; 12.311 ns ; DM ; Y2 ;
-; N/A ; None ; 12.292 ns ; LM ; Y5 ;
-; N/A ; None ; 12.248 ns ; A6 ; Y5 ;
-; N/A ; None ; 12.029 ns ; LM ; Y7 ;
-; N/A ; None ; 11.943 ns ; RM ; Y3 ;
-; N/A ; None ; 11.911 ns ; DM ; Y0 ;
-; N/A ; None ; 11.884 ns ; DM ; Y1 ;
-; N/A ; None ; 11.864 ns ; LM ; Y2 ;
-; N/A ; None ; 11.859 ns ; LM ; Y4 ;
-; N/A ; None ; 11.855 ns ; DM ; Y6 ;
-; N/A ; None ; 11.827 ns ; A7 ; Y6 ;
-; N/A ; None ; 11.433 ns ; LM ; Y1 ;
-; N/A ; None ; 11.432 ns ; RM ; Y0 ;
-; N/A ; None ; 11.404 ns ; LM ; Y6 ;
-; N/A ; None ; 11.258 ns ; RM ; Y2 ;
-; N/A ; None ; 11.254 ns ; RM ; Y5 ;
-; N/A ; None ; 11.249 ns ; RM ; Y4 ;
-; N/A ; None ; 10.823 ns ; RM ; Y1 ;
-; N/A ; None ; 10.804 ns ; RM ; Y6 ;
-; N/A ; None ; 8.265 ns ; A2 ; Y3 ;
-; N/A ; None ; 8.237 ns ; A3 ; Y3 ;
-; N/A ; None ; 8.014 ns ; A5 ; Y5 ;
-; N/A ; None ; 7.942 ns ; A4 ; Y5 ;
-; N/A ; None ; 7.635 ns ; A4 ; Y3 ;
-; N/A ; None ; 7.583 ns ; A2 ; Y2 ;
-; N/A ; None ; 7.551 ns ; A3 ; Y4 ;
-; N/A ; None ; 7.136 ns ; A5 ; Y6 ;
-; N/A ; None ; 7.085 ns ; A4 ; Y4 ;
-; N/A ; None ; 7.014 ns ; A5 ; Y4 ;
-; N/A ; None ; 6.993 ns ; A3 ; Y2 ;
-; N/A ; None ; 6.585 ns ; A2 ; Y1 ;
+; N/A ; None ; 15.661 ns ; LM ; Y5 ;
+; N/A ; None ; 15.651 ns ; DM ; Y5 ;
+; N/A ; None ; 15.610 ns ; LM ; Y3 ;
+; N/A ; None ; 15.606 ns ; DM ; Y3 ;
+; N/A ; None ; 15.297 ns ; DM ; Y1 ;
+; N/A ; None ; 15.251 ns ; DM ; Y6 ;
+; N/A ; None ; 15.189 ns ; LM ; Y4 ;
+; N/A ; None ; 15.186 ns ; DM ; Y4 ;
+; N/A ; None ; 14.807 ns ; LM ; Y1 ;
+; N/A ; None ; 14.796 ns ; DM ; Y2 ;
+; N/A ; None ; 14.768 ns ; LM ; Y6 ;
+; N/A ; None ; 14.737 ns ; RM ; Y6 ;
+; N/A ; None ; 14.714 ns ; RM ; Y5 ;
+; N/A ; None ; 14.662 ns ; RM ; Y3 ;
+; N/A ; None ; 14.654 ns ; RM ; Y4 ;
+; N/A ; None ; 14.633 ns ; DM ; Y7 ;
+; N/A ; None ; 14.630 ns ; LM ; Y7 ;
+; N/A ; None ; 14.582 ns ; A0 ; Y1 ;
+; N/A ; None ; 14.517 ns ; A3 ; Y3 ;
+; N/A ; None ; 14.509 ns ; A1 ; Y1 ;
+; N/A ; None ; 14.410 ns ; A2 ; Y3 ;
+; N/A ; None ; 14.345 ns ; RM ; Y1 ;
+; N/A ; None ; 14.328 ns ; LM ; Y2 ;
+; N/A ; None ; 14.284 ns ; RM ; Y2 ;
+; N/A ; None ; 14.272 ns ; RM ; Y0 ;
+; N/A ; None ; 14.232 ns ; A5 ; Y5 ;
+; N/A ; None ; 14.231 ns ; DM ; Y0 ;
+; N/A ; None ; 14.156 ns ; A6 ; Y6 ;
+; N/A ; None ; 14.096 ns ; A3 ; Y4 ;
+; N/A ; None ; 14.080 ns ; A2 ; Y2 ;
+; N/A ; None ; 14.078 ns ; A4 ; Y5 ;
+; N/A ; None ; 13.824 ns ; A5 ; Y6 ;
+; N/A ; None ; 13.706 ns ; A1 ; Y2 ;
+; N/A ; None ; 13.606 ns ; A4 ; Y4 ;
+; N/A ; None ; 13.309 ns ; A0 ; Y0 ;
+; N/A ; None ; 13.231 ns ; A7 ; Y6 ;
+; N/A ; None ; 13.196 ns ; A5 ; Y4 ;
+; N/A ; None ; 13.181 ns ; A7 ; Y7 ;
+; N/A ; None ; 13.141 ns ; A1 ; Y0 ;
+; N/A ; None ; 13.137 ns ; A3 ; Y2 ;
+; N/A ; None ; 13.099 ns ; A2 ; Y1 ;
+; N/A ; None ; 13.098 ns ; A6 ; Y5 ;
+; N/A ; None ; 13.064 ns ; A6 ; Y7 ;
+; N/A ; None ; 13.036 ns ; A4 ; Y3 ;
+-------+-------------------+-----------------+------+----+
@@ -151,19 +151,20 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
- Info: Processing started: Mon Mar 07 11:15:57 2022
+ Info: Processing started: Tue Mar 08 15:17:19 2022
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only
-Info: Parallel compilation is enabled and will use 4 of the 6 processors detected
-Info: Longest tpd from source pin "A6" to destination pin "Y7" is 13.413 ns
- Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 3; PIN Node = 'A6'
- Info: 2: + IC(6.895 ns) + CELL(0.624 ns) = 8.513 ns; Loc. = LCCOMB_X1_Y5_N10; Fanout = 1; COMB Node = 'triple_selector_8b:inst|inst31'
- Info: 3: + IC(1.604 ns) + CELL(3.296 ns) = 13.413 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'Y7'
- Info: Total cell delay = 4.914 ns ( 36.64 % )
- Info: Total interconnect delay = 8.499 ns ( 63.36 % )
+Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info: Longest tpd from source pin "LM" to destination pin "Y5" is 15.661 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_69; Fanout = 7; PIN Node = 'LM'
+ Info: 2: + IC(6.879 ns) + CELL(0.650 ns) = 8.523 ns; Loc. = LCCOMB_X26_Y1_N18; Fanout = 1; COMB Node = 'triple_selector_8b:inst|inst23~0'
+ Info: 3: + IC(0.370 ns) + CELL(0.624 ns) = 9.517 ns; Loc. = LCCOMB_X26_Y1_N20; Fanout = 1; COMB Node = 'triple_selector_8b:inst|inst23'
+ Info: 4: + IC(3.028 ns) + CELL(3.116 ns) = 15.661 ns; Loc. = PIN_147; Fanout = 0; PIN Node = 'Y5'
+ Info: Total cell delay = 5.384 ns ( 34.38 % )
+ Info: Total interconnect delay = 10.277 ns ( 65.62 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
- Info: Peak virtual memory: 191 megabytes
- Info: Processing ended: Mon Mar 07 11:15:58 2022
- Info: Elapsed time: 00:00:01
+ Info: Peak virtual memory: 212 megabytes
+ Info: Processing ended: Tue Mar 08 15:17:19 2022
+ Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00
diff --git a/shifter_8b/shifter_8b.tan.summary b/shifter_8b/shifter_8b.tan.summary
index e1cbc56..3eb3609 100644
--- a/shifter_8b/shifter_8b.tan.summary
+++ b/shifter_8b/shifter_8b.tan.summary
@@ -5,9 +5,9 @@ Timing Analyzer Summary
Type : Worst-case tpd
Slack : N/A
Required Time : None
-Actual Time : 13.413 ns
-From : A6
-To : Y7
+Actual Time : 15.661 ns
+From : LM
+To : Y5
From Clock : --
To Clock : --
Failed Paths : 0