diff --git a/README.md b/README.md index 462bc05..a531c07 100644 --- a/README.md +++ b/README.md @@ -58,4 +58,13 @@ LR0~LR7: Y0~Y7 ### shifter_8b -8位数据移位器。 \ No newline at end of file +8位数据移位器。 + +``` +K0~K7: A0~A7 +K8: RM +K9: DM +K10: LM +LR0~LR7: Y0~Y7 +``` + diff --git a/shifter_8b/db/prev_cmp_shifter_8b.map.qmsg b/shifter_8b/db/prev_cmp_shifter_8b.map.qmsg index 9687781..52c24e3 100644 --- a/shifter_8b/db/prev_cmp_shifter_8b.map.qmsg +++ b/shifter_8b/db/prev_cmp_shifter_8b.map.qmsg @@ -1,9 +1,9 @@ { "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:15:53 2022 " "Info: Processing started: Mon Mar 07 11:15:53 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:17:07 2022 " "Info: Processing started: Mon Mar 07 11:17:07 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 shifter_8b " "Info: Found entity 1: shifter_8b" { } { { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} { "Info" "ISGN_START_ELABORATION_TOP" "shifter_8b " "Info: Elaborating entity \"shifter_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} { "Warning" "WSGN_SEARCH_FILE" "triple_selector_8b.bdf 1 1 " "Warning: Using design file triple_selector_8b.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 triple_selector_8b " "Info: Found entity 1: triple_selector_8b" { } { { "triple_selector_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/triple_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "triple_selector_8b triple_selector_8b:inst " "Info: Elaborating entity \"triple_selector_8b\" for hierarchy \"triple_selector_8b:inst\"" { } { { "shifter_8b.bdf" "inst" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 32 488 584 512 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_SUMMARY" "33 " "Info: Implemented 33 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Info: Implemented 11 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "14 " "Info: Implemented 14 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "229 " "Info: Peak virtual memory: 229 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:15:53 2022 " "Info: Processing ended: Mon Mar 07 11:15:53 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "229 " "Info: Peak virtual memory: 229 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:17:07 2022 " "Info: Processing ended: Mon Mar 07 11:17:07 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/shifter_8b/db/shifter_8b.(0).cnf.hdb b/shifter_8b/db/shifter_8b.(0).cnf.hdb index 07be9fe..3174167 100644 Binary files a/shifter_8b/db/shifter_8b.(0).cnf.hdb and b/shifter_8b/db/shifter_8b.(0).cnf.hdb differ diff --git a/shifter_8b/db/shifter_8b.asm.qmsg b/shifter_8b/db/shifter_8b.asm.qmsg index 4449273..e680608 100644 --- a/shifter_8b/db/shifter_8b.asm.qmsg +++ b/shifter_8b/db/shifter_8b.asm.qmsg @@ -1,7 +1,7 @@ { "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:15:56 2022 " "Info: Processing started: Mon Mar 07 11:15:56 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:17:18 2022 " "Info: Processing started: Tue Mar 08 15:17:18 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} { "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1} { "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1} { "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "221 " "Info: Peak virtual memory: 221 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:15:57 2022 " "Info: Processing ended: Mon Mar 07 11:15:57 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:17:18 2022 " "Info: Processing ended: Tue Mar 08 15:17:18 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/shifter_8b/db/shifter_8b.asm_labs.ddb b/shifter_8b/db/shifter_8b.asm_labs.ddb new file mode 100644 index 0000000..8cd0a91 Binary files /dev/null and b/shifter_8b/db/shifter_8b.asm_labs.ddb differ diff --git a/shifter_8b/db/shifter_8b.cmp.bpm b/shifter_8b/db/shifter_8b.cmp.bpm new file mode 100644 index 0000000..d6e0bd5 Binary files /dev/null and b/shifter_8b/db/shifter_8b.cmp.bpm differ diff --git a/shifter_8b/db/shifter_8b.cmp.cdb b/shifter_8b/db/shifter_8b.cmp.cdb new file mode 100644 index 0000000..dada380 Binary files /dev/null and b/shifter_8b/db/shifter_8b.cmp.cdb differ diff --git a/shifter_8b/db/shifter_8b.cmp.hdb b/shifter_8b/db/shifter_8b.cmp.hdb new file mode 100644 index 0000000..e6663dd Binary files /dev/null and b/shifter_8b/db/shifter_8b.cmp.hdb differ diff --git a/shifter_8b/db/shifter_8b.cmp.logdb b/shifter_8b/db/shifter_8b.cmp.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/shifter_8b/db/shifter_8b.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/shifter_8b/db/shifter_8b.cmp.rdb b/shifter_8b/db/shifter_8b.cmp.rdb index 5bfebce..fe318f8 100644 Binary files a/shifter_8b/db/shifter_8b.cmp.rdb and b/shifter_8b/db/shifter_8b.cmp.rdb differ diff --git a/shifter_8b/db/shifter_8b.cmp.tdb b/shifter_8b/db/shifter_8b.cmp.tdb new file mode 100644 index 0000000..7805610 Binary files /dev/null and b/shifter_8b/db/shifter_8b.cmp.tdb differ diff --git a/shifter_8b/db/shifter_8b.cmp0.ddb b/shifter_8b/db/shifter_8b.cmp0.ddb index 76611d0..37dd3bd 100644 Binary files a/shifter_8b/db/shifter_8b.cmp0.ddb and b/shifter_8b/db/shifter_8b.cmp0.ddb differ diff --git a/shifter_8b/db/shifter_8b.cmp2.ddb b/shifter_8b/db/shifter_8b.cmp2.ddb index d1cbd3a..d56bdc0 100644 Binary files a/shifter_8b/db/shifter_8b.cmp2.ddb and b/shifter_8b/db/shifter_8b.cmp2.ddb differ diff --git a/shifter_8b/db/shifter_8b.eco.cdb b/shifter_8b/db/shifter_8b.eco.cdb index eb283d9..6612017 100644 Binary files a/shifter_8b/db/shifter_8b.eco.cdb and b/shifter_8b/db/shifter_8b.eco.cdb differ diff --git a/shifter_8b/db/shifter_8b.fit.qmsg b/shifter_8b/db/shifter_8b.fit.qmsg index 26deb53..10af5de 100644 --- a/shifter_8b/db/shifter_8b.fit.qmsg +++ b/shifter_8b/db/shifter_8b.fit.qmsg @@ -1,14 +1,13 @@ { "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:15:54 2022 " "Info: Processing started: Mon Mar 07 11:15:54 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:17:16 2022 " "Info: Processing started: Tue Mar 08 15:17:16 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 6 " "Info: Parallel compilation is enabled and will use 4 of the 6 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} { "Info" "IMPP_MPP_USER_DEVICE" "shifter_8b EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"shifter_8b\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} { "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1} -{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "19 19 " "Warning: No exact pin location assignment(s) for 19 pins of 19 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y0 " "Info: Pin Y0 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y0 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 168 688 864 184 "Y0" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y1 " "Info: Pin Y1 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y1 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 152 688 864 168 "Y1" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y2 " "Info: Pin Y2 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y2 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 136 688 864 152 "Y2" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y3 " "Info: Pin Y3 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y3 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 120 688 864 136 "Y3" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y4 " "Info: Pin Y4 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y4 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 104 688 864 120 "Y4" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y5 " "Info: Pin Y5 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y5 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 88 688 864 104 "Y5" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y6 " "Info: Pin Y6 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y6 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 72 688 864 88 "Y6" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y7 " "Info: Pin Y7 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y7 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 56 688 864 72 "Y7" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A0 " "Info: Pin A0 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { A0 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 408 40 208 424 "A0" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A1 " "Info: Pin A1 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { A1 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 360 40 208 376 "A1" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RM " "Info: Pin RM not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { RM } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 552 40 208 568 "RM" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RM } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DM " "Info: Pin DM not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DM } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 504 40 208 520 "DM" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DM } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LM " "Info: Pin LM not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { LM } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 456 40 208 472 "LM" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LM } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A2 " "Info: Pin A2 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { A2 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 312 40 208 328 "A2" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A3 " "Info: Pin A3 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { A3 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 264 40 208 280 "A3" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A4 " "Info: Pin A4 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { A4 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 216 40 208 232 "A4" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A5 " "Info: Pin A5 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { A5 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 168 40 208 184 "A5" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A6 " "Info: Pin A6 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { A6 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 120 40 208 136 "A6" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A7 " "Info: Pin A7 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { A7 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 72 40 208 88 "A7" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1} { "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1} { "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1} @@ -19,8 +18,6 @@ { "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1} { "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1} { "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "19 unused 3.3V 11 8 0 " "Info: Number of I/O pins in group: 19 (unused VREF, 3.3V VCCIO, 11 input, 8 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 2 30 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 35 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 34 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 36 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1} { "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} @@ -28,12 +25,11 @@ { "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X10_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y0 X34_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X34_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1} { "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y0 0 " "Info: Pin \"Y0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y1 0 " "Info: Pin \"Y1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y2 0 " "Info: Pin \"Y2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y3 0 " "Info: Pin \"Y3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y4 0 " "Info: Pin \"Y4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y5 0 " "Info: Pin \"Y5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y6 0 " "Info: Pin \"Y6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y7 0 " "Info: Pin \"Y7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1} { "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/dev/quartus/shifter_8b/shifter_8b.fit.smsg " "Info: Generated suppressed messages file D:/dev/quartus/shifter_8b/shifter_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "286 " "Info: Peak virtual memory: 286 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:15:55 2022 " "Info: Processing ended: Mon Mar 07 11:15:55 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/shifter_8b/shifter_8b.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/shifter_8b/shifter_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "306 " "Info: Peak virtual memory: 306 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:17:17 2022 " "Info: Processing ended: Tue Mar 08 15:17:17 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/shifter_8b/db/shifter_8b.hif b/shifter_8b/db/shifter_8b.hif index 2ef093c..67e4fda 100644 --- a/shifter_8b/db/shifter_8b.hif +++ b/shifter_8b/db/shifter_8b.hif @@ -19,26 +19,6 @@ VHSM_ON -- Start VHDL Libraries -- -- End VHDL Libraries -- # entity -shifter_8b -# storage -db|shifter_8b.(0).cnf -db|shifter_8b.(0).cnf -# case_insensitive -# source_file -shifter_8b.bdf -d6db26b9c5f411a913f215ffd97edb7d -26 -# internal_option { -BLOCK_DESIGN_NAMING -AUTO -} -# hierarchies { -| -} -# macro_sequence - -# end -# entity triple_selector_8b # storage db|shifter_8b.(1).cnf @@ -57,6 +37,26 @@ triple_selector_8b:inst } # macro_sequence +# end +# entity +shifter_8b +# storage +db|shifter_8b.(0).cnf +db|shifter_8b.(0).cnf +# case_insensitive +# source_file +shifter_8b.bdf +48c3dd91b772b04158a51fc34d535c +26 +# internal_option { +BLOCK_DESIGN_NAMING +AUTO +} +# hierarchies { +| +} +# macro_sequence + # end # complete \ No newline at end of file diff --git a/shifter_8b/db/shifter_8b.map.bpm b/shifter_8b/db/shifter_8b.map.bpm index 4872f20..4e215f2 100644 Binary files a/shifter_8b/db/shifter_8b.map.bpm and b/shifter_8b/db/shifter_8b.map.bpm differ diff --git a/shifter_8b/db/shifter_8b.map.cdb b/shifter_8b/db/shifter_8b.map.cdb index 8671bce..a0b4dd5 100644 Binary files a/shifter_8b/db/shifter_8b.map.cdb and b/shifter_8b/db/shifter_8b.map.cdb differ diff --git a/shifter_8b/db/shifter_8b.map.hdb b/shifter_8b/db/shifter_8b.map.hdb index 366960c..97e63cb 100644 Binary files a/shifter_8b/db/shifter_8b.map.hdb and b/shifter_8b/db/shifter_8b.map.hdb differ diff --git a/shifter_8b/db/shifter_8b.map.qmsg b/shifter_8b/db/shifter_8b.map.qmsg index 52c24e3..4893583 100644 --- a/shifter_8b/db/shifter_8b.map.qmsg +++ b/shifter_8b/db/shifter_8b.map.qmsg @@ -1,9 +1,9 @@ { "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:17:07 2022 " "Info: Processing started: Mon Mar 07 11:17:07 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:17:15 2022 " "Info: Processing started: Tue Mar 08 15:17:15 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 shifter_8b " "Info: Found entity 1: shifter_8b" { } { { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 shifter_8b " "Info: Found entity 1: shifter_8b" { } { { "shifter_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} { "Info" "ISGN_START_ELABORATION_TOP" "shifter_8b " "Info: Elaborating entity \"shifter_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} -{ "Warning" "WSGN_SEARCH_FILE" "triple_selector_8b.bdf 1 1 " "Warning: Using design file triple_selector_8b.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 triple_selector_8b " "Info: Found entity 1: triple_selector_8b" { } { { "triple_selector_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/triple_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "triple_selector_8b triple_selector_8b:inst " "Info: Elaborating entity \"triple_selector_8b\" for hierarchy \"triple_selector_8b:inst\"" { } { { "shifter_8b.bdf" "inst" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 32 488 584 512 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} +{ "Warning" "WSGN_SEARCH_FILE" "triple_selector_8b.bdf 1 1 " "Warning: Using design file triple_selector_8b.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 triple_selector_8b " "Info: Found entity 1: triple_selector_8b" { } { { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/triple_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "triple_selector_8b triple_selector_8b:inst " "Info: Elaborating entity \"triple_selector_8b\" for hierarchy \"triple_selector_8b:inst\"" { } { { "shifter_8b.bdf" "inst" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { { 32 488 584 512 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_SUMMARY" "33 " "Info: Implemented 33 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Info: Implemented 11 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "14 " "Info: Implemented 14 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "229 " "Info: Peak virtual memory: 229 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:17:07 2022 " "Info: Processing ended: Mon Mar 07 11:17:07 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:17:15 2022 " "Info: Processing ended: Tue Mar 08 15:17:15 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/shifter_8b/db/shifter_8b.map_bb.cdb b/shifter_8b/db/shifter_8b.map_bb.cdb index 9abbc6a..55dd818 100644 Binary files a/shifter_8b/db/shifter_8b.map_bb.cdb and b/shifter_8b/db/shifter_8b.map_bb.cdb differ diff --git a/shifter_8b/db/shifter_8b.map_bb.hdb b/shifter_8b/db/shifter_8b.map_bb.hdb index edecfc4..28183aa 100644 Binary files a/shifter_8b/db/shifter_8b.map_bb.hdb and b/shifter_8b/db/shifter_8b.map_bb.hdb differ diff --git a/shifter_8b/db/shifter_8b.pre_map.cdb b/shifter_8b/db/shifter_8b.pre_map.cdb index e038146..a6ca160 100644 Binary files a/shifter_8b/db/shifter_8b.pre_map.cdb and b/shifter_8b/db/shifter_8b.pre_map.cdb differ diff --git a/shifter_8b/db/shifter_8b.pre_map.hdb b/shifter_8b/db/shifter_8b.pre_map.hdb index 4f97e1a..0fb61fc 100644 Binary files a/shifter_8b/db/shifter_8b.pre_map.hdb and b/shifter_8b/db/shifter_8b.pre_map.hdb differ diff --git a/shifter_8b/db/shifter_8b.rtlv.hdb b/shifter_8b/db/shifter_8b.rtlv.hdb index b6e6e83..04527c5 100644 Binary files a/shifter_8b/db/shifter_8b.rtlv.hdb and b/shifter_8b/db/shifter_8b.rtlv.hdb differ diff --git a/shifter_8b/db/shifter_8b.rtlv_sg.cdb b/shifter_8b/db/shifter_8b.rtlv_sg.cdb index 5c2cfec..81669c0 100644 Binary files a/shifter_8b/db/shifter_8b.rtlv_sg.cdb and b/shifter_8b/db/shifter_8b.rtlv_sg.cdb differ diff --git a/shifter_8b/db/shifter_8b.rtlv_sg_swap.cdb b/shifter_8b/db/shifter_8b.rtlv_sg_swap.cdb index c2c2f88..dd7f3f2 100644 Binary files a/shifter_8b/db/shifter_8b.rtlv_sg_swap.cdb and b/shifter_8b/db/shifter_8b.rtlv_sg_swap.cdb differ diff --git a/shifter_8b/db/shifter_8b.sgdiff.cdb b/shifter_8b/db/shifter_8b.sgdiff.cdb index 5c552ae..036f736 100644 Binary files a/shifter_8b/db/shifter_8b.sgdiff.cdb and b/shifter_8b/db/shifter_8b.sgdiff.cdb differ diff --git a/shifter_8b/db/shifter_8b.sgdiff.hdb b/shifter_8b/db/shifter_8b.sgdiff.hdb index 71eb3dd..11d56e9 100644 Binary files a/shifter_8b/db/shifter_8b.sgdiff.hdb and b/shifter_8b/db/shifter_8b.sgdiff.hdb differ diff --git a/shifter_8b/db/shifter_8b.sld_design_entry.sci b/shifter_8b/db/shifter_8b.sld_design_entry.sci index a8e7d42..904d003 100644 Binary files a/shifter_8b/db/shifter_8b.sld_design_entry.sci and b/shifter_8b/db/shifter_8b.sld_design_entry.sci differ diff --git a/shifter_8b/db/shifter_8b.tan.qmsg b/shifter_8b/db/shifter_8b.tan.qmsg index 70add04..ec16759 100644 --- a/shifter_8b/db/shifter_8b.tan.qmsg +++ b/shifter_8b/db/shifter_8b.tan.qmsg @@ -1,6 +1,6 @@ { "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:15:57 2022 " "Info: Processing started: Mon Mar 07 11:15:57 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:17:19 2022 " "Info: Processing started: Tue Mar 08 15:17:19 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 6 " "Info: Parallel compilation is enabled and will use 4 of the 6 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "ITDB_FULL_TPD_RESULT" "A6 Y7 13.413 ns Longest " "Info: Longest tpd from source pin \"A6\" to destination pin \"Y7\" is 13.413 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns A6 1 PIN PIN_67 3 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 3; PIN Node = 'A6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A6 } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 120 40 208 136 "A6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.895 ns) + CELL(0.624 ns) 8.513 ns triple_selector_8b:inst\|inst31 2 COMB LCCOMB_X1_Y5_N10 1 " "Info: 2: + IC(6.895 ns) + CELL(0.624 ns) = 8.513 ns; Loc. = LCCOMB_X1_Y5_N10; Fanout = 1; COMB Node = 'triple_selector_8b:inst\|inst31'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.519 ns" { A6 triple_selector_8b:inst|inst31 } "NODE_NAME" } } { "triple_selector_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/triple_selector_8b.bdf" { { 64 488 552 112 "inst31" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.604 ns) + CELL(3.296 ns) 13.413 ns Y7 3 PIN PIN_60 0 " "Info: 3: + IC(1.604 ns) + CELL(3.296 ns) = 13.413 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'Y7'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.900 ns" { triple_selector_8b:inst|inst31 Y7 } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 56 688 864 72 "Y7" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.914 ns ( 36.64 % ) " "Info: Total cell delay = 4.914 ns ( 36.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.499 ns ( 63.36 % ) " "Info: Total interconnect delay = 8.499 ns ( 63.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "13.413 ns" { A6 triple_selector_8b:inst|inst31 Y7 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "13.413 ns" { A6 {} A6~combout {} triple_selector_8b:inst|inst31 {} Y7 {} } { 0.000ns 0.000ns 6.895ns 1.604ns } { 0.000ns 0.994ns 0.624ns 3.296ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "191 " "Info: Peak virtual memory: 191 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:15:58 2022 " "Info: Processing ended: Mon Mar 07 11:15:58 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_TPD_RESULT" "LM Y5 15.661 ns Longest " "Info: Longest tpd from source pin \"LM\" to destination pin \"Y5\" is 15.661 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns LM 1 PIN PIN_69 7 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_69; Fanout = 7; PIN Node = 'LM'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LM } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { { 456 40 208 472 "LM" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.879 ns) + CELL(0.650 ns) 8.523 ns triple_selector_8b:inst\|inst23~0 2 COMB LCCOMB_X26_Y1_N18 1 " "Info: 2: + IC(6.879 ns) + CELL(0.650 ns) = 8.523 ns; Loc. = LCCOMB_X26_Y1_N18; Fanout = 1; COMB Node = 'triple_selector_8b:inst\|inst23~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.529 ns" { LM triple_selector_8b:inst|inst23~0 } "NODE_NAME" } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/triple_selector_8b.bdf" { { 352 488 552 400 "inst23" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.370 ns) + CELL(0.624 ns) 9.517 ns triple_selector_8b:inst\|inst23 3 COMB LCCOMB_X26_Y1_N20 1 " "Info: 3: + IC(0.370 ns) + CELL(0.624 ns) = 9.517 ns; Loc. = LCCOMB_X26_Y1_N20; Fanout = 1; COMB Node = 'triple_selector_8b:inst\|inst23'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.994 ns" { triple_selector_8b:inst|inst23~0 triple_selector_8b:inst|inst23 } "NODE_NAME" } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/triple_selector_8b.bdf" { { 352 488 552 400 "inst23" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.028 ns) + CELL(3.116 ns) 15.661 ns Y5 4 PIN PIN_147 0 " "Info: 4: + IC(3.028 ns) + CELL(3.116 ns) = 15.661 ns; Loc. = PIN_147; Fanout = 0; PIN Node = 'Y5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.144 ns" { triple_selector_8b:inst|inst23 Y5 } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { { 88 688 864 104 "Y5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.384 ns ( 34.38 % ) " "Info: Total cell delay = 5.384 ns ( 34.38 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "10.277 ns ( 65.62 % ) " "Info: Total interconnect delay = 10.277 ns ( 65.62 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "15.661 ns" { LM triple_selector_8b:inst|inst23~0 triple_selector_8b:inst|inst23 Y5 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "15.661 ns" { LM {} LM~combout {} triple_selector_8b:inst|inst23~0 {} triple_selector_8b:inst|inst23 {} Y5 {} } { 0.000ns 0.000ns 6.879ns 0.370ns 3.028ns } { 0.000ns 0.994ns 0.650ns 0.624ns 3.116ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:17:19 2022 " "Info: Processing ended: Tue Mar 08 15:17:19 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/shifter_8b/db/shifter_8b.tis_db_list.ddb b/shifter_8b/db/shifter_8b.tis_db_list.ddb index 62fc03a..2a9a6ed 100644 Binary files a/shifter_8b/db/shifter_8b.tis_db_list.ddb and b/shifter_8b/db/shifter_8b.tis_db_list.ddb differ diff --git a/shifter_8b/db/shifter_8b.tmw_info b/shifter_8b/db/shifter_8b.tmw_info new file mode 100644 index 0000000..6516e48 --- /dev/null +++ b/shifter_8b/db/shifter_8b.tmw_info @@ -0,0 +1,6 @@ +start_full_compilation:s:00:00:05 +start_analysis_synthesis:s:00:00:02-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:01-start_full_compilation +start_assembler:s:00:00:02-start_full_compilation +start_timing_analyzer:s:00:00:00-start_full_compilation diff --git a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.atm b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.atm index a96c2a3..9caa3ef 100644 Binary files a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.atm and b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.atm differ diff --git a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.hdbx b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.hdbx index bd628c2..ef0a47a 100644 Binary files a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.hdbx and b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.hdbx differ diff --git a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.rcf b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.rcf index 39cb3c6..b22c47a 100644 Binary files a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.rcf and b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.rcf differ diff --git a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.atm b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.atm index 402825d..ce1faa9 100644 Binary files a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.atm and b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.atm differ diff --git a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.dpi b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.dpi index af53fad..21cb83e 100644 Binary files a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.dpi and b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.dpi differ diff --git a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.hdbx b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.hdbx index 0a258d7..dec6d46 100644 Binary files a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.hdbx and b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.hdbx differ diff --git a/shifter_8b/shifter_8b.asm.rpt b/shifter_8b/shifter_8b.asm.rpt index ab487c3..354db37 100644 --- a/shifter_8b/shifter_8b.asm.rpt +++ b/shifter_8b/shifter_8b.asm.rpt @@ -1,5 +1,5 @@ Assembler report for shifter_8b -Mon Mar 07 11:15:57 2022 +Tue Mar 08 15:17:18 2022 Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition @@ -10,8 +10,8 @@ Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition 2. Assembler Summary 3. Assembler Settings 4. Assembler Generated Files - 5. Assembler Device Options: D:/dev/quartus/shifter_8b/shifter_8b.sof - 6. Assembler Device Options: D:/dev/quartus/shifter_8b/shifter_8b.pof + 5. Assembler Device Options: D:/projects/quartus/shifter_8b/shifter_8b.sof + 6. Assembler Device Options: D:/projects/quartus/shifter_8b/shifter_8b.pof 7. Assembler Messages @@ -38,7 +38,7 @@ applicable agreement for further details. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Mon Mar 07 11:15:57 2022 ; +; Assembler Status ; Successful - Tue Mar 08 15:17:18 2022 ; ; Revision Name ; shifter_8b ; ; Top-level Entity Name ; shifter_8b ; ; Family ; Cyclone II ; @@ -76,37 +76,37 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+----------+---------------+ -+------------------------------------------+ -; Assembler Generated Files ; -+------------------------------------------+ -; File Name ; -+------------------------------------------+ -; D:/dev/quartus/shifter_8b/shifter_8b.sof ; -; D:/dev/quartus/shifter_8b/shifter_8b.pof ; -+------------------------------------------+ ++-----------------------------------------------+ +; Assembler Generated Files ; ++-----------------------------------------------+ +; File Name ; ++-----------------------------------------------+ +; D:/projects/quartus/shifter_8b/shifter_8b.sof ; +; D:/projects/quartus/shifter_8b/shifter_8b.pof ; ++-----------------------------------------------+ -+--------------------------------------------------------------------+ -; Assembler Device Options: D:/dev/quartus/shifter_8b/shifter_8b.sof ; -+----------------+---------------------------------------------------+ -; Option ; Setting ; -+----------------+---------------------------------------------------+ -; Device ; EP2C8Q208C8 ; -; JTAG usercode ; 0xFFFFFFFF ; -; Checksum ; 0x000C73F5 ; -+----------------+---------------------------------------------------+ ++-------------------------------------------------------------------------+ +; Assembler Device Options: D:/projects/quartus/shifter_8b/shifter_8b.sof ; ++----------------+--------------------------------------------------------+ +; Option ; Setting ; ++----------------+--------------------------------------------------------+ +; Device ; EP2C8Q208C8 ; +; JTAG usercode ; 0xFFFFFFFF ; +; Checksum ; 0x000C22C5 ; ++----------------+--------------------------------------------------------+ -+--------------------------------------------------------------------+ -; Assembler Device Options: D:/dev/quartus/shifter_8b/shifter_8b.pof ; -+--------------------+-----------------------------------------------+ -; Option ; Setting ; -+--------------------+-----------------------------------------------+ -; Device ; EPCS4 ; -; JTAG usercode ; 0x00000000 ; -; Checksum ; 0x06F0A9BA ; -; Compression Ratio ; 3 ; -+--------------------+-----------------------------------------------+ ++-------------------------------------------------------------------------+ +; Assembler Device Options: D:/projects/quartus/shifter_8b/shifter_8b.pof ; ++--------------------+----------------------------------------------------+ +; Option ; Setting ; ++--------------------+----------------------------------------------------+ +; Device ; EPCS4 ; +; JTAG usercode ; 0x00000000 ; +; Checksum ; 0x06F00042 ; +; Compression Ratio ; 3 ; ++--------------------+----------------------------------------------------+ +--------------------+ @@ -115,15 +115,15 @@ applicable agreement for further details. Info: ******************************************************************* Info: Running Quartus II Assembler Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Mon Mar 07 11:15:56 2022 + Info: Processing started: Tue Mar 08 15:17:18 2022 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b Info: Writing out detailed assembly data for power analysis Info: Assembler is generating device programming files Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled Info: Quartus II Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 221 megabytes - Info: Processing ended: Mon Mar 07 11:15:57 2022 - Info: Elapsed time: 00:00:01 + Info: Peak virtual memory: 241 megabytes + Info: Processing ended: Tue Mar 08 15:17:18 2022 + Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:00 diff --git a/shifter_8b/shifter_8b.done b/shifter_8b/shifter_8b.done index c251748..028fc07 100644 --- a/shifter_8b/shifter_8b.done +++ b/shifter_8b/shifter_8b.done @@ -1 +1 @@ -Mon Mar 07 11:17:08 2022 +Tue Mar 08 15:17:19 2022 diff --git a/shifter_8b/shifter_8b.fit.rpt b/shifter_8b/shifter_8b.fit.rpt index c9cea6f..8ed0afd 100644 --- a/shifter_8b/shifter_8b.fit.rpt +++ b/shifter_8b/shifter_8b.fit.rpt @@ -1,5 +1,5 @@ Fitter report for shifter_8b -Mon Mar 07 11:15:55 2022 +Tue Mar 08 15:17:17 2022 Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition @@ -63,7 +63,7 @@ applicable agreement for further details. +-----------------------------------------------------------------------------------+ ; Fitter Summary ; +------------------------------------+----------------------------------------------+ -; Fitter Status ; Successful - Mon Mar 07 11:15:55 2022 ; +; Fitter Status ; Successful - Tue Mar 08 15:17:17 2022 ; ; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; ; Revision Name ; shifter_8b ; ; Top-level Entity Name ; shifter_8b ; @@ -91,6 +91,7 @@ applicable agreement for further details. ; Minimum Core Junction Temperature ; 0 ; ; ; Maximum Core Junction Temperature ; 85 ; ; ; Fit Attempts to Skip ; 0 ; 0.0 ; +; Device I/O Standard ; 3.3-V LVTTL ; ; ; Use smart compilation ; Off ; Off ; ; Use TimeQuest Timing Analyzer ; Off ; Off ; ; Router Timing Optimization Level ; Normal ; Normal ; @@ -137,7 +138,7 @@ applicable agreement for further details. +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ -; Number detected on machine ; 6 ; +; Number detected on machine ; 4 ; ; Maximum allowed ; 4 ; ; ; ; ; Average used ; 1.00 ; @@ -146,7 +147,6 @@ applicable agreement for further details. ; Usage by Processor ; % Time Used ; ; 1 processor ; 100.0% ; ; 2-4 processors ; < 0.1% ; -; 5-6 processors ; 0.0% ; +----------------------------+-------------+ @@ -186,7 +186,7 @@ applicable agreement for further details. +--------------+ ; Pin-Out File ; +--------------+ -The pin-out file can be found in D:/dev/quartus/shifter_8b/shifter_8b.pin. +The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin. +--------------------------------------------------------------------+ @@ -217,7 +217,7 @@ The pin-out file can be found in D:/dev/quartus/shifter_8b/shifter_8b.pin. ; User inserted logic elements ; 0 ; ; Virtual pins ; 0 ; ; I/O pins ; 19 / 138 ( 14 % ) ; -; -- Clock pins ; 2 / 4 ( 50 % ) ; +; -- Clock pins ; 0 / 4 ( 0 % ) ; ; Global signals ; 0 ; ; M4Ks ; 0 / 36 ( 0 % ) ; ; Total block memory bits ; 0 / 165,888 ( 0 % ) ; @@ -246,17 +246,17 @@ The pin-out file can be found in D:/dev/quartus/shifter_8b/shifter_8b.pin. +------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ; +------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ -; A0 ; 15 ; 1 ; 0 ; 14 ; 3 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; A1 ; 63 ; 4 ; 3 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; A2 ; 23 ; 1 ; 0 ; 9 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; A3 ; 24 ; 1 ; 0 ; 9 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; A4 ; 27 ; 1 ; 0 ; 9 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; A5 ; 28 ; 1 ; 0 ; 9 ; 3 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; A6 ; 67 ; 4 ; 9 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; A7 ; 13 ; 1 ; 0 ; 16 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; DM ; 205 ; 2 ; 1 ; 19 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; LM ; 30 ; 1 ; 0 ; 8 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; RM ; 35 ; 1 ; 0 ; 7 ; 1 ; 7 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; A0 ; 77 ; 4 ; 18 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; A1 ; 80 ; 4 ; 23 ; 0 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; A2 ; 81 ; 4 ; 23 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; A3 ; 82 ; 4 ; 23 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; A4 ; 84 ; 4 ; 25 ; 0 ; 3 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; A5 ; 86 ; 4 ; 25 ; 0 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; A6 ; 87 ; 4 ; 25 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; A7 ; 88 ; 4 ; 25 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; DM ; 68 ; 4 ; 12 ; 0 ; 1 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; LM ; 69 ; 4 ; 12 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; RM ; 67 ; 4 ; 9 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ @@ -265,14 +265,14 @@ The pin-out file can be found in D:/dev/quartus/shifter_8b/shifter_8b.pin. +------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; +------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ -; Y0 ; 48 ; 1 ; 0 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; -; Y1 ; 40 ; 1 ; 0 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; -; Y2 ; 33 ; 1 ; 0 ; 8 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; -; Y3 ; 208 ; 2 ; 1 ; 19 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; -; Y4 ; 34 ; 1 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; -; Y5 ; 31 ; 1 ; 0 ; 8 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; -; Y6 ; 39 ; 1 ; 0 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; -; Y7 ; 60 ; 4 ; 3 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; +; Y0 ; 142 ; 3 ; 34 ; 12 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; +; Y1 ; 143 ; 3 ; 34 ; 13 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; +; Y2 ; 144 ; 3 ; 34 ; 13 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; +; Y3 ; 145 ; 3 ; 34 ; 14 ; 4 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; +; Y4 ; 146 ; 3 ; 34 ; 15 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; +; Y5 ; 147 ; 3 ; 34 ; 15 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; +; Y6 ; 149 ; 3 ; 34 ; 16 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; +; Y7 ; 150 ; 3 ; 34 ; 16 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; +------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ @@ -281,10 +281,10 @@ The pin-out file can be found in D:/dev/quartus/shifter_8b/shifter_8b.pin. +----------+------------------+---------------+--------------+ ; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; +----------+------------------+---------------+--------------+ -; 1 ; 16 / 32 ( 50 % ) ; 3.3V ; -- ; -; 2 ; 2 / 35 ( 6 % ) ; 3.3V ; -- ; -; 3 ; 1 / 35 ( 3 % ) ; 3.3V ; -- ; -; 4 ; 3 / 36 ( 8 % ) ; 3.3V ; -- ; +; 1 ; 2 / 32 ( 6 % ) ; 3.3V ; -- ; +; 2 ; 0 / 35 ( 0 % ) ; 3.3V ; -- ; +; 3 ; 9 / 35 ( 26 % ) ; 3.3V ; -- ; +; 4 ; 11 / 36 ( 31 % ) ; 3.3V ; -- ; +----------+------------------+---------------+--------------+ @@ -295,19 +295,19 @@ The pin-out file can be found in D:/dev/quartus/shifter_8b/shifter_8b.pin. +----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ ; 1 ; 0 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; ; 2 ; 1 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; -; 3 ; 2 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 4 ; 3 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 5 ; 4 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 6 ; 5 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 3 ; 2 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 4 ; 3 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 5 ; 4 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 6 ; 5 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 8 ; 6 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 8 ; 6 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 10 ; 7 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 11 ; 8 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 12 ; 9 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 13 ; 10 ; 1 ; A7 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 14 ; 18 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 15 ; 19 ; 1 ; A0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 10 ; 7 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 11 ; 8 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 12 ; 9 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 13 ; 10 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 14 ; 18 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 15 ; 19 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; ; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; ; 18 ; 22 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; @@ -315,32 +315,32 @@ The pin-out file can be found in D:/dev/quartus/shifter_8b/shifter_8b.pin. ; 20 ; 24 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ; ; 21 ; 25 ; 1 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ; ; 22 ; 26 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; -; 23 ; 27 ; 1 ; A2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 24 ; 28 ; 1 ; A3 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 23 ; 27 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 24 ; 28 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; ; 25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; 26 ; 29 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; -; 27 ; 30 ; 1 ; A4 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 28 ; 31 ; 1 ; A5 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 27 ; 30 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 28 ; 31 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; ; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 30 ; 32 ; 1 ; LM ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 31 ; 33 ; 1 ; Y5 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 30 ; 32 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 31 ; 33 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 33 ; 35 ; 1 ; Y2 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 34 ; 36 ; 1 ; Y4 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 35 ; 37 ; 1 ; RM ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 33 ; 35 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 34 ; 36 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 35 ; 37 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 37 ; 39 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 37 ; 39 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 39 ; 43 ; 1 ; Y6 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 40 ; 44 ; 1 ; Y1 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 41 ; 45 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 39 ; 43 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 40 ; 44 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 41 ; 45 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 42 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 43 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 44 ; 49 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 45 ; 50 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 46 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 47 ; 52 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 48 ; 53 ; 1 ; Y0 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 43 ; 48 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 44 ; 49 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 45 ; 50 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 46 ; 51 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 47 ; 52 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 48 ; 53 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 49 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; 50 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; ; 51 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; @@ -348,69 +348,69 @@ The pin-out file can be found in D:/dev/quartus/shifter_8b/shifter_8b.pin. ; 53 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; 54 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; ; 55 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 56 ; 54 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 57 ; 55 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 58 ; 56 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 59 ; 57 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 60 ; 58 ; 4 ; Y7 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 61 ; 59 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 56 ; 54 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 57 ; 55 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 58 ; 56 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 59 ; 57 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 60 ; 58 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 61 ; 59 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 63 ; 60 ; 4 ; A1 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 64 ; 61 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 63 ; 60 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 64 ; 61 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 67 ; 69 ; 4 ; A6 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 68 ; 70 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 69 ; 71 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 70 ; 74 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 67 ; 69 ; 4 ; RM ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 68 ; 70 ; 4 ; DM ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 69 ; 71 ; 4 ; LM ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 70 ; 74 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 71 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 72 ; 75 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 72 ; 75 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 74 ; 76 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 75 ; 77 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 76 ; 78 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 77 ; 79 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 74 ; 76 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 75 ; 77 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 76 ; 78 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 77 ; 79 ; 4 ; A0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; ; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 80 ; 82 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 81 ; 83 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 82 ; 84 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 80 ; 82 ; 4 ; A1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 81 ; 83 ; 4 ; A2 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 82 ; 84 ; 4 ; A3 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; ; 83 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 84 ; 85 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 84 ; 85 ; 4 ; A4 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; ; 85 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 86 ; 86 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 87 ; 87 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 88 ; 88 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 89 ; 89 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 90 ; 90 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 86 ; 86 ; 4 ; A5 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 87 ; 87 ; 4 ; A6 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 88 ; 88 ; 4 ; A7 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 89 ; 89 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 90 ; 90 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 91 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 92 ; 91 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 92 ; 91 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 94 ; 92 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 95 ; 93 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 96 ; 94 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 97 ; 95 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 94 ; 92 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 95 ; 93 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 96 ; 94 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 97 ; 95 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 98 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 99 ; 96 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 99 ; 96 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 100 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 101 ; 97 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 102 ; 98 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 103 ; 99 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 104 ; 100 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 105 ; 101 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 106 ; 102 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 107 ; 105 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 101 ; 97 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 102 ; 98 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 103 ; 99 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 104 ; 100 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 105 ; 101 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 106 ; 102 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 107 ; 105 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 108 ; 106 ; 3 ; ~LVDS54p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; ; 109 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 110 ; 107 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 110 ; 107 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 111 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 112 ; 108 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 113 ; 109 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 114 ; 110 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 115 ; 112 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 116 ; 113 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 117 ; 114 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 118 ; 117 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 112 ; 108 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 113 ; 109 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 114 ; 110 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 115 ; 112 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 116 ; 113 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 117 ; 114 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 118 ; 117 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 119 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; 120 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; 121 ; 121 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; @@ -419,32 +419,32 @@ The pin-out file can be found in D:/dev/quartus/shifter_8b/shifter_8b.pin. ; 124 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; 125 ; 123 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; ; 126 ; 124 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; -; 127 ; 125 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 128 ; 126 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 127 ; 125 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 128 ; 126 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 129 ; 127 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; ; 130 ; 128 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; ; 131 ; 129 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; ; 132 ; 130 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 133 ; 131 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 134 ; 132 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 135 ; 133 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 133 ; 131 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 134 ; 132 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 135 ; 133 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 136 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 137 ; 134 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 138 ; 135 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 139 ; 136 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 137 ; 134 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 138 ; 135 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 139 ; 136 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 141 ; 137 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 142 ; 138 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 143 ; 141 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 144 ; 142 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 145 ; 143 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 146 ; 149 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 147 ; 150 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 141 ; 137 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 142 ; 138 ; 3 ; Y0 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 143 ; 141 ; 3 ; Y1 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 144 ; 142 ; 3 ; Y2 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 145 ; 143 ; 3 ; Y3 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 146 ; 149 ; 3 ; Y4 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 147 ; 150 ; 3 ; Y5 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; 148 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 149 ; 151 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 150 ; 152 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 151 ; 153 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 152 ; 154 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 149 ; 151 ; 3 ; Y6 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 150 ; 152 ; 3 ; Y7 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; 151 ; 153 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 152 ; 154 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; 153 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; 154 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; ; 155 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; @@ -452,55 +452,55 @@ The pin-out file can be found in D:/dev/quartus/shifter_8b/shifter_8b.pin. ; 157 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; ; 158 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; ; 159 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 160 ; 155 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 161 ; 156 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 162 ; 157 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 163 ; 158 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 164 ; 159 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 165 ; 160 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 160 ; 155 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 161 ; 156 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 162 ; 157 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 163 ; 158 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 164 ; 159 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 165 ; 160 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 166 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; 167 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 168 ; 161 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 169 ; 162 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 170 ; 163 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 171 ; 164 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 168 ; 161 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 169 ; 162 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 170 ; 163 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 171 ; 164 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 172 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 173 ; 165 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 173 ; 165 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 174 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 175 ; 168 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 176 ; 169 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 175 ; 168 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 176 ; 169 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 177 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ; 178 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 179 ; 173 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 180 ; 174 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 181 ; 175 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 182 ; 176 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 179 ; 173 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 180 ; 174 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 181 ; 175 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 182 ; 176 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 183 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; 184 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 185 ; 180 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 185 ; 180 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 186 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 187 ; 181 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 188 ; 182 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 189 ; 183 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 187 ; 181 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 188 ; 182 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 189 ; 183 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 190 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 191 ; 184 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 192 ; 185 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 193 ; 186 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 191 ; 184 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 192 ; 185 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 193 ; 186 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 194 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 195 ; 187 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 195 ; 187 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 196 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 197 ; 191 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 198 ; 192 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 199 ; 195 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 200 ; 196 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 201 ; 197 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 197 ; 191 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 198 ; 192 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 199 ; 195 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 200 ; 196 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 201 ; 197 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 202 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 203 ; 198 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 203 ; 198 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; 204 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 205 ; 199 ; 2 ; DM ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 206 ; 200 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 207 ; 201 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 208 ; 202 ; 2 ; Y3 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 205 ; 199 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 206 ; 200 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 207 ; 201 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 208 ; 202 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ Note: Pin directions (input, output or bidir) are based on device operating in user mode. @@ -571,10 +571,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; RM ; Input ; 6 ; 6 ; -- ; -- ; ; DM ; Input ; 6 ; 6 ; -- ; -- ; ; LM ; Input ; 6 ; 6 ; -- ; -- ; -; A2 ; Input ; 0 ; 0 ; -- ; -- ; -; A3 ; Input ; 0 ; 0 ; -- ; -- ; -; A4 ; Input ; 0 ; 0 ; -- ; -- ; -; A5 ; Input ; 0 ; 0 ; -- ; -- ; +; A2 ; Input ; 6 ; 6 ; -- ; -- ; +; A3 ; Input ; 6 ; 6 ; -- ; -- ; +; A4 ; Input ; 6 ; 6 ; -- ; -- ; +; A5 ; Input ; 6 ; 6 ; -- ; -- ; ; A6 ; Input ; 6 ; 6 ; -- ; -- ; ; A7 ; Input ; 6 ; 6 ; -- ; -- ; +------+----------+---------------+---------------+-----------------------+-----+ @@ -586,8 +586,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Source Pin / Fanout ; Pad To Core Index ; Setting ; +-----------------------------------------+-------------------+---------+ ; A0 ; ; ; -; - triple_selector_8b:inst|inst3 ; 1 ; 6 ; -; - triple_selector_8b:inst|inst7~0 ; 1 ; 6 ; +; - triple_selector_8b:inst|inst3 ; 0 ; 6 ; +; - triple_selector_8b:inst|inst7~0 ; 0 ; 6 ; ; A1 ; ; ; ; - triple_selector_8b:inst|inst3 ; 0 ; 6 ; ; - triple_selector_8b:inst|inst7~0 ; 0 ; 6 ; @@ -610,17 +610,29 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; - triple_selector_8b:inst|inst27~0 ; 0 ; 6 ; ; - triple_selector_8b:inst|inst31 ; 0 ; 6 ; ; LM ; ; ; -; - triple_selector_8b:inst|inst7~0 ; 0 ; 6 ; +; - triple_selector_8b:inst|inst7~0 ; 1 ; 6 ; +; - triple_selector_8b:inst|inst11~0 ; 1 ; 6 ; +; - triple_selector_8b:inst|inst15~0 ; 1 ; 6 ; +; - triple_selector_8b:inst|inst19~0 ; 1 ; 6 ; +; - triple_selector_8b:inst|inst23~0 ; 1 ; 6 ; +; - triple_selector_8b:inst|inst27~0 ; 1 ; 6 ; +; - triple_selector_8b:inst|inst31 ; 1 ; 6 ; +; A2 ; ; ; +; - triple_selector_8b:inst|inst7 ; 0 ; 6 ; ; - triple_selector_8b:inst|inst11~0 ; 0 ; 6 ; ; - triple_selector_8b:inst|inst15~0 ; 0 ; 6 ; +; A3 ; ; ; +; - triple_selector_8b:inst|inst11 ; 0 ; 6 ; +; - triple_selector_8b:inst|inst15~0 ; 0 ; 6 ; +; - triple_selector_8b:inst|inst19~0 ; 0 ; 6 ; +; A4 ; ; ; +; - triple_selector_8b:inst|inst15 ; 0 ; 6 ; ; - triple_selector_8b:inst|inst19~0 ; 0 ; 6 ; ; - triple_selector_8b:inst|inst23~0 ; 0 ; 6 ; -; - triple_selector_8b:inst|inst27~0 ; 0 ; 6 ; -; - triple_selector_8b:inst|inst31 ; 0 ; 6 ; -; A2 ; ; ; -; A3 ; ; ; -; A4 ; ; ; ; A5 ; ; ; +; - triple_selector_8b:inst|inst19 ; 0 ; 6 ; +; - triple_selector_8b:inst|inst23~0 ; 0 ; 6 ; +; - triple_selector_8b:inst|inst27~0 ; 0 ; 6 ; ; A6 ; ; ; ; - triple_selector_8b:inst|inst23 ; 0 ; 6 ; ; - triple_selector_8b:inst|inst27~0 ; 0 ; 6 ; @@ -669,14 +681,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------------------+-----------------------+ ; Interconnect Resource Type ; Usage ; +----------------------------+-----------------------+ -; Block interconnects ; 19 / 26,052 ( < 1 % ) ; -; C16 interconnects ; 2 / 1,156 ( < 1 % ) ; -; C4 interconnects ; 24 / 17,952 ( < 1 % ) ; -; Direct links ; 2 / 26,052 ( < 1 % ) ; +; Block interconnects ; 20 / 26,052 ( < 1 % ) ; +; C16 interconnects ; 3 / 1,156 ( < 1 % ) ; +; C4 interconnects ; 38 / 17,952 ( < 1 % ) ; +; Direct links ; 0 / 26,052 ( 0 % ) ; ; Global clocks ; 0 / 8 ( 0 % ) ; ; Local interconnects ; 6 / 8,256 ( < 1 % ) ; -; R24 interconnects ; 0 / 1,020 ( 0 % ) ; -; R4 interconnects ; 4 / 22,440 ( < 1 % ) ; +; R24 interconnects ; 3 / 1,020 ( < 1 % ) ; +; R4 interconnects ; 23 / 22,440 ( < 1 % ) ; +----------------------------+-----------------------+ @@ -777,7 +789,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Error detection CRC ; Off ; ; nCEO ; As output driving ground ; ; ASDO,nCSO ; As input tri-stated ; -; Reserve all unused pins ; As output driving ground ; +; Reserve all unused pins ; As input tri-stated ; ; Base pin-out file on sameframe device ; Off ; +----------------------------------------------+--------------------------+ @@ -852,6 +864,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Name ; Value ; +------------------------------------+------------+ ; Auto Fit Point 2 - Fit Attempt 1 ; ff ; +; Early Wire Use - Fit Attempt 1 ; 0 ; +; Early Slack - Fit Attempt 1 ; 2147483639 ; ; Auto Fit Point 5 - Fit Attempt 1 ; ff ; ; Mid Wire Use - Fit Attempt 1 ; 0 ; ; Mid Slack - Fit Attempt 1 ; 2147483639 ; @@ -878,10 +892,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Name ; Value ; +------------------------------------+-------------+ ; Early Slack - Fit Attempt 1 ; 2147483639 ; +; Early Wire Use - Fit Attempt 1 ; 0 ; +; Peak Regional Wire - Fit Attempt 1 ; 1 ; ; Mid Slack - Fit Attempt 1 ; 2147483639 ; ; Late Slack - Fit Attempt 1 ; -2147483648 ; -; Early Wire Use - Fit Attempt 1 ; 0 ; -; Peak Regional Wire - Fit Attempt 1 ; 0 ; ; Late Wire Use - Fit Attempt 1 ; 0 ; ; Time - Fit Attempt 1 ; 0 ; +------------------------------------+-------------+ @@ -893,9 +907,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi Info: ******************************************************************* Info: Running Quartus II Fitter Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Mon Mar 07 11:15:54 2022 + Info: Processing started: Tue Mar 08 15:17:16 2022 Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b -Info: Parallel compilation is enabled and will use 4 of the 6 processors detected +Info: Parallel compilation is enabled and will use 4 of the 4 processors detected Info: Selected device EP2C8Q208C8 for design "shifter_8b" Info: Low junction temperature is 0 degrees C Info: High junction temperature is 85 degrees C @@ -908,40 +922,11 @@ Info: Fitter converted 3 user pins into dedicated programming pins Info: Pin ~ASDO~ is reserved at location 1 Info: Pin ~nCSO~ is reserved at location 2 Info: Pin ~LVDS54p/nCEO~ is reserved at location 108 -Warning: No exact pin location assignment(s) for 19 pins of 19 total pins - Info: Pin Y0 not assigned to an exact location on the device - Info: Pin Y1 not assigned to an exact location on the device - Info: Pin Y2 not assigned to an exact location on the device - Info: Pin Y3 not assigned to an exact location on the device - Info: Pin Y4 not assigned to an exact location on the device - Info: Pin Y5 not assigned to an exact location on the device - Info: Pin Y6 not assigned to an exact location on the device - Info: Pin Y7 not assigned to an exact location on the device - Info: Pin A0 not assigned to an exact location on the device - Info: Pin A1 not assigned to an exact location on the device - Info: Pin RM not assigned to an exact location on the device - Info: Pin DM not assigned to an exact location on the device - Info: Pin LM not assigned to an exact location on the device - Info: Pin A2 not assigned to an exact location on the device - Info: Pin A3 not assigned to an exact location on the device - Info: Pin A4 not assigned to an exact location on the device - Info: Pin A5 not assigned to an exact location on the device - Info: Pin A6 not assigned to an exact location on the device - Info: Pin A7 not assigned to an exact location on the device Info: Fitter is using the Classic Timing Analyzer Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time. Info: Starting register packing Info: Finished register packing Extra Info: No registers were packed into other blocks -Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement - Info: Number of I/O pins in group: 19 (unused VREF, 3.3V VCCIO, 11 input, 8 output, 0 bidirectional) - Info: I/O standards used: 3.3-V LVTTL. -Info: I/O bank details before I/O pin placement - Info: Statistics of I/O banks - Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available - Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available - Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available - Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available Info: Fitter preparation operations ending: elapsed time is 00:00:00 Info: Fitter placement preparation operations beginning Info: Fitter placement preparation operations ending: elapsed time is 00:00:00 @@ -950,7 +935,7 @@ Info: Fitter placement was successful Info: Fitter placement operations ending: elapsed time is 00:00:00 Info: Fitter routing operations beginning Info: Average interconnect usage is 0% of the available device resources - Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9 + Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X34_Y9 Info: Fitter routing operations ending: elapsed time is 00:00:00 Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info: Optimizations that may affect the design's routability were skipped @@ -966,11 +951,10 @@ Warning: Found 8 output pins without output pin load capacitance assignment Info: Pin "Y6" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Y7" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Delay annotation completed successfully -Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. -Info: Generated suppressed messages file D:/dev/quartus/shifter_8b/shifter_8b.fit.smsg -Info: Quartus II Fitter was successful. 0 errors, 3 warnings - Info: Peak virtual memory: 286 megabytes - Info: Processing ended: Mon Mar 07 11:15:55 2022 +Info: Generated suppressed messages file D:/projects/quartus/shifter_8b/shifter_8b.fit.smsg +Info: Quartus II Fitter was successful. 0 errors, 1 warning + Info: Peak virtual memory: 306 megabytes + Info: Processing ended: Tue Mar 08 15:17:17 2022 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 @@ -978,6 +962,6 @@ Info: Quartus II Fitter was successful. 0 errors, 3 warnings +----------------------------+ ; Fitter Suppressed Messages ; +----------------------------+ -The suppressed messages can be found in D:/dev/quartus/shifter_8b/shifter_8b.fit.smsg. +The suppressed messages can be found in D:/projects/quartus/shifter_8b/shifter_8b.fit.smsg. diff --git a/shifter_8b/shifter_8b.fit.summary b/shifter_8b/shifter_8b.fit.summary index 066e8ec..875a683 100644 --- a/shifter_8b/shifter_8b.fit.summary +++ b/shifter_8b/shifter_8b.fit.summary @@ -1,4 +1,4 @@ -Fitter Status : Successful - Mon Mar 07 11:15:55 2022 +Fitter Status : Successful - Tue Mar 08 15:17:17 2022 Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition Revision Name : shifter_8b Top-level Entity Name : shifter_8b diff --git a/shifter_8b/shifter_8b.flow.rpt b/shifter_8b/shifter_8b.flow.rpt index d09b958..a5831e7 100644 --- a/shifter_8b/shifter_8b.flow.rpt +++ b/shifter_8b/shifter_8b.flow.rpt @@ -1,5 +1,5 @@ Flow report for shifter_8b -Mon Mar 07 11:17:07 2022 +Tue Mar 08 15:17:19 2022 Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition @@ -38,23 +38,23 @@ applicable agreement for further details. +-----------------------------------------------------------------------------------+ ; Flow Summary ; +------------------------------------+----------------------------------------------+ -; Flow Status ; Successful - Mon Mar 07 11:17:07 2022 ; +; Flow Status ; Successful - Tue Mar 08 15:17:19 2022 ; ; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; ; Revision Name ; shifter_8b ; ; Top-level Entity Name ; shifter_8b ; ; Family ; Cyclone II ; ; Device ; EP2C8Q208C8 ; ; Timing Models ; Final ; -; Met timing requirements ; N/A ; -; Total logic elements ; 14 ; -; Total combinational functions ; 14 ; -; Dedicated logic registers ; 0 ; +; Met timing requirements ; Yes ; +; Total logic elements ; 14 / 8,256 ( < 1 % ) ; +; Total combinational functions ; 14 / 8,256 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ; ; Total registers ; 0 ; -; Total pins ; 19 ; +; Total pins ; 19 / 138 ( 14 % ) ; ; Total virtual pins ; 0 ; -; Total memory bits ; 0 ; -; Embedded Multiplier 9-bit elements ; 0 ; -; Total PLLs ; 0 ; +; Total memory bits ; 0 / 165,888 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; +; Total PLLs ; 0 / 2 ( 0 % ) ; +------------------------------------+----------------------------------------------+ @@ -63,50 +63,60 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 03/07/2022 11:17:07 ; +; Start date & time ; 03/08/2022 15:17:15 ; ; Main task ; Compilation ; ; Revision Name ; shifter_8b ; +-------------------+---------------------+ -+------------------------------------------------------------------------------------------------------------------------------+ -; Flow Non-Default Global Settings ; -+------------------------------------+------------------------------------------+---------------+-------------+----------------+ -; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; -+------------------------------------+------------------------------------------+---------------+-------------+----------------+ -; COMPILER_SIGNATURE_ID ; 136411542855513.164662302732708 ; -- ; -- ; -- ; -; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; -; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; -; MISC_FILE ; D:/dev/quartus/shifter_8b/shifter_8b.dpf ; -- ; -- ; -- ; -; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; -; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; -; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ; -+------------------------------------+------------------------------------------+---------------+-------------+----------------+ ++-----------------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++------------------------------------+-----------------------------------------------+---------------+-------------+----------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++------------------------------------+-----------------------------------------------+---------------+-------------+----------------+ +; COMPILER_SIGNATURE_ID ; 220283517943889.164672383512820 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; MISC_FILE ; D:/dev/quartus/shifter_8b/shifter_8b.dpf ; -- ; -- ; -- ; +; MISC_FILE ; D:/projects/quartus/shifter_8b/shifter_8b.dpf ; -- ; -- ; -- ; +; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; +; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ; ++------------------------------------+-----------------------------------------------+---------------+-------------+----------------+ -+--------------------------------------------------------------------------------------------------------------------------+ -; Flow Elapsed Time ; -+----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; -+----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 226 MB ; 00:00:00 ; -; Total ; 00:00:00 ; -- ; -- ; 00:00:00 ; -+----------------------+--------------+-------------------------+---------------------+------------------------------------+ ++-----------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 246 MB ; 00:00:00 ; +; Fitter ; 00:00:01 ; 1.0 ; 306 MB ; 00:00:01 ; +; Assembler ; 00:00:00 ; 1.0 ; 241 MB ; 00:00:00 ; +; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 198 MB ; 00:00:00 ; +; Total ; 00:00:01 ; -- ; -- ; 00:00:01 ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ -+---------------------------------------------------------------------------------------+ -; Flow OS Summary ; -+----------------------+------------------+---------------+------------+----------------+ -; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; -+----------------------+------------------+---------------+------------+----------------+ -; Analysis & Synthesis ; DESKTOP-G0CBSMT ; Windows Vista ; 6.2 ; x86_64 ; -+----------------------+------------------+---------------+------------+----------------+ ++------------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++-------------------------+------------------+---------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++-------------------------+------------------+---------------+------------+----------------+ +; Analysis & Synthesis ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; +; Fitter ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; +; Assembler ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; +; Classic Timing Analyzer ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; ++-------------------------+------------------+---------------+------------+----------------+ ------------ ; Flow Log ; ------------ quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b +quartus_fit --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b +quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b +quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only diff --git a/shifter_8b/shifter_8b.map.rpt b/shifter_8b/shifter_8b.map.rpt index b68366d..529797a 100644 --- a/shifter_8b/shifter_8b.map.rpt +++ b/shifter_8b/shifter_8b.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for shifter_8b -Mon Mar 07 11:17:07 2022 +Tue Mar 08 15:17:15 2022 Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition @@ -39,7 +39,7 @@ applicable agreement for further details. +-----------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +------------------------------------+----------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Mon Mar 07 11:17:07 2022 ; +; Analysis & Synthesis Status ; Successful - Tue Mar 08 15:17:15 2022 ; ; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; ; Revision Name ; shifter_8b ; ; Top-level Entity Name ; shifter_8b ; @@ -131,14 +131,14 @@ applicable agreement for further details. +--------------------------------------------------------------+--------------------+--------------------+ -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+----------------------------------+-----------------+------------------------------------------+--------------------------------------------------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; -+----------------------------------+-----------------+------------------------------------------+--------------------------------------------------+ -; shifter_8b.bdf ; yes ; User Block Diagram/Schematic File ; D:/dev/quartus/shifter_8b/shifter_8b.bdf ; -; triple_selector_8b.bdf ; yes ; Auto-Found Block Diagram/Schematic File ; D:/dev/quartus/shifter_8b/triple_selector_8b.bdf ; -+----------------------------------+-----------------+------------------------------------------+--------------------------------------------------+ ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------------+-------------------------------------------------------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; ++----------------------------------+-----------------+------------------------------------------+-------------------------------------------------------+ +; shifter_8b.bdf ; yes ; User Block Diagram/Schematic File ; D:/projects/quartus/shifter_8b/shifter_8b.bdf ; +; triple_selector_8b.bdf ; yes ; Auto-Found Block Diagram/Schematic File ; D:/projects/quartus/shifter_8b/triple_selector_8b.bdf ; ++----------------------------------+-----------------+------------------------------------------+-------------------------------------------------------+ +-----------------------------------------------------+ @@ -202,7 +202,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi Info: ******************************************************************* Info: Running Quartus II Analysis & Synthesis Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Mon Mar 07 11:17:07 2022 + Info: Processing started: Tue Mar 08 15:17:15 2022 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf Info: Found entity 1: shifter_8b @@ -215,8 +215,8 @@ Info: Implemented 33 device resources after synthesis - the final resource count Info: Implemented 8 output pins Info: Implemented 14 logic cells Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning - Info: Peak virtual memory: 229 megabytes - Info: Processing ended: Mon Mar 07 11:17:07 2022 + Info: Peak virtual memory: 250 megabytes + Info: Processing ended: Tue Mar 08 15:17:15 2022 Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:00 diff --git a/shifter_8b/shifter_8b.map.summary b/shifter_8b/shifter_8b.map.summary index 81855af..0d1f33e 100644 --- a/shifter_8b/shifter_8b.map.summary +++ b/shifter_8b/shifter_8b.map.summary @@ -1,4 +1,4 @@ -Analysis & Synthesis Status : Successful - Mon Mar 07 11:17:07 2022 +Analysis & Synthesis Status : Successful - Tue Mar 08 15:17:15 2022 Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition Revision Name : shifter_8b Top-level Entity Name : shifter_8b diff --git a/shifter_8b/shifter_8b.pin b/shifter_8b/shifter_8b.pin index afef75c..bf29e52 100644 --- a/shifter_8b/shifter_8b.pin +++ b/shifter_8b/shifter_8b.pin @@ -70,19 +70,19 @@ Pin Name/Usage : Location : Dir. : I/O Standard : Voltage ------------------------------------------------------------------------------------------------------------- ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVTTL : : 1 : N ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVTTL : : 1 : N -GND* : 3 : : : : 1 : -GND* : 4 : : : : 1 : -GND* : 5 : : : : 1 : -GND* : 6 : : : : 1 : +RESERVED_INPUT : 3 : : : : 1 : +RESERVED_INPUT : 4 : : : : 1 : +RESERVED_INPUT : 5 : : : : 1 : +RESERVED_INPUT : 6 : : : : 1 : VCCIO1 : 7 : power : : 3.3V : 1 : -GND* : 8 : : : : 1 : +RESERVED_INPUT : 8 : : : : 1 : GND : 9 : gnd : : : : -GND* : 10 : : : : 1 : -GND* : 11 : : : : 1 : -GND* : 12 : : : : 1 : -A7 : 13 : input : 3.3-V LVTTL : : 1 : N -GND* : 14 : : : : 1 : -A0 : 15 : input : 3.3-V LVTTL : : 1 : N +RESERVED_INPUT : 10 : : : : 1 : +RESERVED_INPUT : 11 : : : : 1 : +RESERVED_INPUT : 12 : : : : 1 : +RESERVED_INPUT : 13 : : : : 1 : +RESERVED_INPUT : 14 : : : : 1 : +RESERVED_INPUT : 15 : : : : 1 : TDO : 16 : output : : : 1 : TMS : 17 : input : : : 1 : TCK : 18 : input : : : 1 : @@ -90,32 +90,32 @@ TDI : 19 : input : : DATA0 : 20 : input : : : 1 : DCLK : 21 : : : : 1 : nCE : 22 : : : : 1 : -A2 : 23 : input : 3.3-V LVTTL : : 1 : N -A3 : 24 : input : 3.3-V LVTTL : : 1 : N +GND+ : 23 : : : : 1 : +GND+ : 24 : : : : 1 : GND : 25 : gnd : : : : nCONFIG : 26 : : : : 1 : -A4 : 27 : input : 3.3-V LVTTL : : 1 : N -A5 : 28 : input : 3.3-V LVTTL : : 1 : N +GND+ : 27 : : : : 1 : +GND+ : 28 : : : : 1 : VCCIO1 : 29 : power : : 3.3V : 1 : -LM : 30 : input : 3.3-V LVTTL : : 1 : N -Y5 : 31 : output : 3.3-V LVTTL : : 1 : N +RESERVED_INPUT : 30 : : : : 1 : +RESERVED_INPUT : 31 : : : : 1 : VCCINT : 32 : power : : 1.2V : : -Y2 : 33 : output : 3.3-V LVTTL : : 1 : N -Y4 : 34 : output : 3.3-V LVTTL : : 1 : N -RM : 35 : input : 3.3-V LVTTL : : 1 : N +RESERVED_INPUT : 33 : : : : 1 : +RESERVED_INPUT : 34 : : : : 1 : +RESERVED_INPUT : 35 : : : : 1 : GND : 36 : gnd : : : : -GND* : 37 : : : : 1 : +RESERVED_INPUT : 37 : : : : 1 : GND : 38 : gnd : : : : -Y6 : 39 : output : 3.3-V LVTTL : : 1 : N -Y1 : 40 : output : 3.3-V LVTTL : : 1 : N -GND* : 41 : : : : 1 : +RESERVED_INPUT : 39 : : : : 1 : +RESERVED_INPUT : 40 : : : : 1 : +RESERVED_INPUT : 41 : : : : 1 : VCCIO1 : 42 : power : : 3.3V : 1 : -GND* : 43 : : : : 1 : -GND* : 44 : : : : 1 : -GND* : 45 : : : : 1 : -GND* : 46 : : : : 1 : -GND* : 47 : : : : 1 : -Y0 : 48 : output : 3.3-V LVTTL : : 1 : N +RESERVED_INPUT : 43 : : : : 1 : +RESERVED_INPUT : 44 : : : : 1 : +RESERVED_INPUT : 45 : : : : 1 : +RESERVED_INPUT : 46 : : : : 1 : +RESERVED_INPUT : 47 : : : : 1 : +RESERVED_INPUT : 48 : : : : 1 : GND : 49 : gnd : : : : GND_PLL1 : 50 : gnd : : : : VCCD_PLL1 : 51 : power : : 1.2V : : @@ -123,69 +123,69 @@ GND_PLL1 : 52 : gnd : : VCCA_PLL1 : 53 : power : : 1.2V : : GNDA_PLL1 : 54 : gnd : : : : GND : 55 : gnd : : : : -GND* : 56 : : : : 4 : -GND* : 57 : : : : 4 : -GND* : 58 : : : : 4 : -GND* : 59 : : : : 4 : -Y7 : 60 : output : 3.3-V LVTTL : : 4 : N -GND* : 61 : : : : 4 : +RESERVED_INPUT : 56 : : : : 4 : +RESERVED_INPUT : 57 : : : : 4 : +RESERVED_INPUT : 58 : : : : 4 : +RESERVED_INPUT : 59 : : : : 4 : +RESERVED_INPUT : 60 : : : : 4 : +RESERVED_INPUT : 61 : : : : 4 : VCCIO4 : 62 : power : : 3.3V : 4 : -A1 : 63 : input : 3.3-V LVTTL : : 4 : N -GND* : 64 : : : : 4 : +RESERVED_INPUT : 63 : : : : 4 : +RESERVED_INPUT : 64 : : : : 4 : GND : 65 : gnd : : : : VCCINT : 66 : power : : 1.2V : : -A6 : 67 : input : 3.3-V LVTTL : : 4 : N -GND* : 68 : : : : 4 : -GND* : 69 : : : : 4 : -GND* : 70 : : : : 4 : +RM : 67 : input : 3.3-V LVTTL : : 4 : Y +DM : 68 : input : 3.3-V LVTTL : : 4 : Y +LM : 69 : input : 3.3-V LVTTL : : 4 : Y +RESERVED_INPUT : 70 : : : : 4 : VCCIO4 : 71 : power : : 3.3V : 4 : -GND* : 72 : : : : 4 : +RESERVED_INPUT : 72 : : : : 4 : GND : 73 : gnd : : : : -GND* : 74 : : : : 4 : -GND* : 75 : : : : 4 : -GND* : 76 : : : : 4 : -GND* : 77 : : : : 4 : +RESERVED_INPUT : 74 : : : : 4 : +RESERVED_INPUT : 75 : : : : 4 : +RESERVED_INPUT : 76 : : : : 4 : +A0 : 77 : input : 3.3-V LVTTL : : 4 : Y GND : 78 : gnd : : : : VCCINT : 79 : power : : 1.2V : : -GND* : 80 : : : : 4 : -GND* : 81 : : : : 4 : -GND* : 82 : : : : 4 : +A1 : 80 : input : 3.3-V LVTTL : : 4 : Y +A2 : 81 : input : 3.3-V LVTTL : : 4 : Y +A3 : 82 : input : 3.3-V LVTTL : : 4 : Y VCCIO4 : 83 : power : : 3.3V : 4 : -GND* : 84 : : : : 4 : +A4 : 84 : input : 3.3-V LVTTL : : 4 : Y GND : 85 : gnd : : : : -GND* : 86 : : : : 4 : -GND* : 87 : : : : 4 : -GND* : 88 : : : : 4 : -GND* : 89 : : : : 4 : -GND* : 90 : : : : 4 : +A5 : 86 : input : 3.3-V LVTTL : : 4 : Y +A6 : 87 : input : 3.3-V LVTTL : : 4 : Y +A7 : 88 : input : 3.3-V LVTTL : : 4 : Y +RESERVED_INPUT : 89 : : : : 4 : +RESERVED_INPUT : 90 : : : : 4 : VCCIO4 : 91 : power : : 3.3V : 4 : -GND* : 92 : : : : 4 : +RESERVED_INPUT : 92 : : : : 4 : GND : 93 : gnd : : : : -GND* : 94 : : : : 4 : -GND* : 95 : : : : 4 : -GND* : 96 : : : : 4 : -GND* : 97 : : : : 4 : +RESERVED_INPUT : 94 : : : : 4 : +RESERVED_INPUT : 95 : : : : 4 : +RESERVED_INPUT : 96 : : : : 4 : +RESERVED_INPUT : 97 : : : : 4 : VCCIO4 : 98 : power : : 3.3V : 4 : -GND* : 99 : : : : 4 : +RESERVED_INPUT : 99 : : : : 4 : GND : 100 : gnd : : : : -GND* : 101 : : : : 4 : -GND* : 102 : : : : 4 : -GND* : 103 : : : : 4 : -GND* : 104 : : : : 4 : -GND* : 105 : : : : 3 : -GND* : 106 : : : : 3 : -GND* : 107 : : : : 3 : +RESERVED_INPUT : 101 : : : : 4 : +RESERVED_INPUT : 102 : : : : 4 : +RESERVED_INPUT : 103 : : : : 4 : +RESERVED_INPUT : 104 : : : : 4 : +RESERVED_INPUT : 105 : : : : 3 : +RESERVED_INPUT : 106 : : : : 3 : +RESERVED_INPUT : 107 : : : : 3 : ~LVDS54p/nCEO~ : 108 : output : 3.3-V LVTTL : : 3 : N VCCIO3 : 109 : power : : 3.3V : 3 : -GND* : 110 : : : : 3 : +RESERVED_INPUT : 110 : : : : 3 : GND : 111 : gnd : : : : -GND* : 112 : : : : 3 : -GND* : 113 : : : : 3 : -GND* : 114 : : : : 3 : -GND* : 115 : : : : 3 : -GND* : 116 : : : : 3 : -GND* : 117 : : : : 3 : -GND* : 118 : : : : 3 : +RESERVED_INPUT : 112 : : : : 3 : +RESERVED_INPUT : 113 : : : : 3 : +RESERVED_INPUT : 114 : : : : 3 : +RESERVED_INPUT : 115 : : : : 3 : +RESERVED_INPUT : 116 : : : : 3 : +RESERVED_INPUT : 117 : : : : 3 : +RESERVED_INPUT : 118 : : : : 3 : GND : 119 : gnd : : : : VCCINT : 120 : power : : 1.2V : : nSTATUS : 121 : : : : 3 : @@ -194,32 +194,32 @@ CONF_DONE : 123 : : : GND : 124 : gnd : : : : MSEL1 : 125 : : : : 3 : MSEL0 : 126 : : : : 3 : -GND* : 127 : : : : 3 : -GND* : 128 : : : : 3 : +RESERVED_INPUT : 127 : : : : 3 : +RESERVED_INPUT : 128 : : : : 3 : GND+ : 129 : : : : 3 : GND+ : 130 : : : : 3 : GND+ : 131 : : : : 3 : GND+ : 132 : : : : 3 : -GND* : 133 : : : : 3 : -GND* : 134 : : : : 3 : -GND* : 135 : : : : 3 : +RESERVED_INPUT : 133 : : : : 3 : +RESERVED_INPUT : 134 : : : : 3 : +RESERVED_INPUT : 135 : : : : 3 : VCCIO3 : 136 : power : : 3.3V : 3 : -GND* : 137 : : : : 3 : -GND* : 138 : : : : 3 : -GND* : 139 : : : : 3 : +RESERVED_INPUT : 137 : : : : 3 : +RESERVED_INPUT : 138 : : : : 3 : +RESERVED_INPUT : 139 : : : : 3 : GND : 140 : gnd : : : : -GND* : 141 : : : : 3 : -GND* : 142 : : : : 3 : -GND* : 143 : : : : 3 : -GND* : 144 : : : : 3 : -GND* : 145 : : : : 3 : -GND* : 146 : : : : 3 : -GND* : 147 : : : : 3 : +RESERVED_INPUT : 141 : : : : 3 : +Y0 : 142 : output : 3.3-V LVTTL : : 3 : Y +Y1 : 143 : output : 3.3-V LVTTL : : 3 : Y +Y2 : 144 : output : 3.3-V LVTTL : : 3 : Y +Y3 : 145 : output : 3.3-V LVTTL : : 3 : Y +Y4 : 146 : output : 3.3-V LVTTL : : 3 : Y +Y5 : 147 : output : 3.3-V LVTTL : : 3 : Y VCCIO3 : 148 : power : : 3.3V : 3 : -GND* : 149 : : : : 3 : -GND* : 150 : : : : 3 : -GND* : 151 : : : : 3 : -GND* : 152 : : : : 3 : +Y6 : 149 : output : 3.3-V LVTTL : : 3 : Y +Y7 : 150 : output : 3.3-V LVTTL : : 3 : Y +RESERVED_INPUT : 151 : : : : 3 : +RESERVED_INPUT : 152 : : : : 3 : GND : 153 : gnd : : : : GND_PLL2 : 154 : gnd : : : : VCCD_PLL2 : 155 : power : : 1.2V : : @@ -227,52 +227,52 @@ GND_PLL2 : 156 : gnd : : VCCA_PLL2 : 157 : power : : 1.2V : : GNDA_PLL2 : 158 : gnd : : : : GND : 159 : gnd : : : : -GND* : 160 : : : : 2 : -GND* : 161 : : : : 2 : -GND* : 162 : : : : 2 : -GND* : 163 : : : : 2 : -GND* : 164 : : : : 2 : -GND* : 165 : : : : 2 : +RESERVED_INPUT : 160 : : : : 2 : +RESERVED_INPUT : 161 : : : : 2 : +RESERVED_INPUT : 162 : : : : 2 : +RESERVED_INPUT : 163 : : : : 2 : +RESERVED_INPUT : 164 : : : : 2 : +RESERVED_INPUT : 165 : : : : 2 : VCCIO2 : 166 : power : : 3.3V : 2 : GND : 167 : gnd : : : : -GND* : 168 : : : : 2 : -GND* : 169 : : : : 2 : -GND* : 170 : : : : 2 : -GND* : 171 : : : : 2 : +RESERVED_INPUT : 168 : : : : 2 : +RESERVED_INPUT : 169 : : : : 2 : +RESERVED_INPUT : 170 : : : : 2 : +RESERVED_INPUT : 171 : : : : 2 : VCCIO2 : 172 : power : : 3.3V : 2 : -GND* : 173 : : : : 2 : +RESERVED_INPUT : 173 : : : : 2 : GND : 174 : gnd : : : : -GND* : 175 : : : : 2 : -GND* : 176 : : : : 2 : +RESERVED_INPUT : 175 : : : : 2 : +RESERVED_INPUT : 176 : : : : 2 : GND : 177 : gnd : : : : VCCINT : 178 : power : : 1.2V : : -GND* : 179 : : : : 2 : -GND* : 180 : : : : 2 : -GND* : 181 : : : : 2 : -GND* : 182 : : : : 2 : +RESERVED_INPUT : 179 : : : : 2 : +RESERVED_INPUT : 180 : : : : 2 : +RESERVED_INPUT : 181 : : : : 2 : +RESERVED_INPUT : 182 : : : : 2 : VCCIO2 : 183 : power : : 3.3V : 2 : GND : 184 : gnd : : : : -GND* : 185 : : : : 2 : +RESERVED_INPUT : 185 : : : : 2 : GND : 186 : gnd : : : : -GND* : 187 : : : : 2 : -GND* : 188 : : : : 2 : -GND* : 189 : : : : 2 : +RESERVED_INPUT : 187 : : : : 2 : +RESERVED_INPUT : 188 : : : : 2 : +RESERVED_INPUT : 189 : : : : 2 : VCCINT : 190 : power : : 1.2V : : -GND* : 191 : : : : 2 : -GND* : 192 : : : : 2 : -GND* : 193 : : : : 2 : +RESERVED_INPUT : 191 : : : : 2 : +RESERVED_INPUT : 192 : : : : 2 : +RESERVED_INPUT : 193 : : : : 2 : VCCIO2 : 194 : power : : 3.3V : 2 : -GND* : 195 : : : : 2 : +RESERVED_INPUT : 195 : : : : 2 : GND : 196 : gnd : : : : -GND* : 197 : : : : 2 : -GND* : 198 : : : : 2 : -GND* : 199 : : : : 2 : -GND* : 200 : : : : 2 : -GND* : 201 : : : : 2 : +RESERVED_INPUT : 197 : : : : 2 : +RESERVED_INPUT : 198 : : : : 2 : +RESERVED_INPUT : 199 : : : : 2 : +RESERVED_INPUT : 200 : : : : 2 : +RESERVED_INPUT : 201 : : : : 2 : VCCIO2 : 202 : power : : 3.3V : 2 : -GND* : 203 : : : : 2 : +RESERVED_INPUT : 203 : : : : 2 : GND : 204 : gnd : : : : -DM : 205 : input : 3.3-V LVTTL : : 2 : N -GND* : 206 : : : : 2 : -GND* : 207 : : : : 2 : -Y3 : 208 : output : 3.3-V LVTTL : : 2 : N +RESERVED_INPUT : 205 : : : : 2 : +RESERVED_INPUT : 206 : : : : 2 : +RESERVED_INPUT : 207 : : : : 2 : +RESERVED_INPUT : 208 : : : : 2 : diff --git a/shifter_8b/shifter_8b.pof b/shifter_8b/shifter_8b.pof index eccf019..a8fc6b6 100644 Binary files a/shifter_8b/shifter_8b.pof and b/shifter_8b/shifter_8b.pof differ diff --git a/shifter_8b/shifter_8b.qsf b/shifter_8b/shifter_8b.qsf index 5550511..5d8c71a 100644 --- a/shifter_8b/shifter_8b.qsf +++ b/shifter_8b/shifter_8b.qsf @@ -51,4 +51,27 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" -set_global_assignment -name MISC_FILE "D:/dev/quartus/shifter_8b/shifter_8b.dpf" \ No newline at end of file +set_global_assignment -name MISC_FILE "D:/dev/quartus/shifter_8b/shifter_8b.dpf" +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_location_assignment PIN_77 -to A0 +set_location_assignment PIN_80 -to A1 +set_location_assignment PIN_81 -to A2 +set_location_assignment PIN_82 -to A3 +set_location_assignment PIN_84 -to A4 +set_location_assignment PIN_86 -to A5 +set_location_assignment PIN_87 -to A6 +set_location_assignment PIN_88 -to A7 +set_location_assignment PIN_68 -to DM +set_location_assignment PIN_69 -to LM +set_location_assignment PIN_67 -to RM +set_location_assignment PIN_142 -to Y0 +set_location_assignment PIN_143 -to Y1 +set_location_assignment PIN_144 -to Y2 +set_location_assignment PIN_145 -to Y3 +set_location_assignment PIN_146 -to Y4 +set_location_assignment PIN_147 -to Y5 +set_location_assignment PIN_149 -to Y6 +set_location_assignment PIN_150 -to Y7 +set_global_assignment -name MISC_FILE "D:/projects/quartus/shifter_8b/shifter_8b.dpf" \ No newline at end of file diff --git a/shifter_8b/shifter_8b.qws b/shifter_8b/shifter_8b.qws index fc216dc..9571b85 100644 --- a/shifter_8b/shifter_8b.qws +++ b/shifter_8b/shifter_8b.qws @@ -2,3 +2,13 @@ ptn_Child1=Frames [ProjectWorkspace.Frames] ptn_Child1=ChildFrames +[ProjectWorkspace.Frames.ChildFrames] +ptn_Child1=Document-0 +[ProjectWorkspace.Frames.ChildFrames.Document-0] +ptn_Child1=ViewFrame-0 +[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0] +DocPathName=shifter_8b.bdf +DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde} +IsChildFrameDetached=False +IsActiveChildFrame=True +ptn_Child1=StateMap diff --git a/shifter_8b/shifter_8b.sof b/shifter_8b/shifter_8b.sof index a8c45e5..d28ea9d 100644 Binary files a/shifter_8b/shifter_8b.sof and b/shifter_8b/shifter_8b.sof differ diff --git a/shifter_8b/shifter_8b.tan.rpt b/shifter_8b/shifter_8b.tan.rpt index 0be7927..e94c46b 100644 --- a/shifter_8b/shifter_8b.tan.rpt +++ b/shifter_8b/shifter_8b.tan.rpt @@ -1,5 +1,5 @@ Classic Timing Analyzer report for shifter_8b -Mon Mar 07 11:15:57 2022 +Tue Mar 08 15:17:19 2022 Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition @@ -39,7 +39,7 @@ applicable agreement for further details. +------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ ; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; +------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ -; Worst-case tpd ; N/A ; None ; 13.413 ns ; A6 ; Y7 ; -- ; -- ; 0 ; +; Worst-case tpd ; N/A ; None ; 15.661 ns ; LM ; Y5 ; -- ; -- ; 0 ; ; Total number of failed paths ; ; ; ; ; ; ; ; 0 ; +------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ @@ -81,7 +81,7 @@ applicable agreement for further details. +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ -; Number detected on machine ; 6 ; +; Number detected on machine ; 4 ; ; Maximum allowed ; 4 ; ; ; ; ; Average used ; 1.00 ; @@ -89,7 +89,7 @@ applicable agreement for further details. ; ; ; ; Usage by Processor ; % Time Used ; ; 1 processor ; 100.0% ; -; 2-6 processors ; 0.0% ; +; 2-4 processors ; 0.0% ; +----------------------------+-------------+ @@ -98,50 +98,50 @@ applicable agreement for further details. +-------+-------------------+-----------------+------+----+ ; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ; +-------+-------------------+-----------------+------+----+ -; N/A ; None ; 13.413 ns ; A6 ; Y7 ; -; N/A ; None ; 13.008 ns ; A7 ; Y7 ; -; N/A ; None ; 12.993 ns ; DM ; Y3 ; -; N/A ; None ; 12.852 ns ; A1 ; Y2 ; -; N/A ; None ; 12.792 ns ; A6 ; Y6 ; -; N/A ; None ; 12.781 ns ; DM ; Y4 ; -; N/A ; None ; 12.737 ns ; DM ; Y5 ; -; N/A ; None ; 12.544 ns ; LM ; Y3 ; -; N/A ; None ; 12.476 ns ; DM ; Y7 ; -; N/A ; None ; 12.455 ns ; A1 ; Y0 ; -; N/A ; None ; 12.428 ns ; A1 ; Y1 ; -; N/A ; None ; 12.419 ns ; A0 ; Y0 ; -; N/A ; None ; 12.394 ns ; A0 ; Y1 ; -; N/A ; None ; 12.311 ns ; DM ; Y2 ; -; N/A ; None ; 12.292 ns ; LM ; Y5 ; -; N/A ; None ; 12.248 ns ; A6 ; Y5 ; -; N/A ; None ; 12.029 ns ; LM ; Y7 ; -; N/A ; None ; 11.943 ns ; RM ; Y3 ; -; N/A ; None ; 11.911 ns ; DM ; Y0 ; -; N/A ; None ; 11.884 ns ; DM ; Y1 ; -; N/A ; None ; 11.864 ns ; LM ; Y2 ; -; N/A ; None ; 11.859 ns ; LM ; Y4 ; -; N/A ; None ; 11.855 ns ; DM ; Y6 ; -; N/A ; None ; 11.827 ns ; A7 ; Y6 ; -; N/A ; None ; 11.433 ns ; LM ; Y1 ; -; N/A ; None ; 11.432 ns ; RM ; Y0 ; -; N/A ; None ; 11.404 ns ; LM ; Y6 ; -; N/A ; None ; 11.258 ns ; RM ; Y2 ; -; N/A ; None ; 11.254 ns ; RM ; Y5 ; -; N/A ; None ; 11.249 ns ; RM ; Y4 ; -; N/A ; None ; 10.823 ns ; RM ; Y1 ; -; N/A ; None ; 10.804 ns ; RM ; Y6 ; -; N/A ; None ; 8.265 ns ; A2 ; Y3 ; -; N/A ; None ; 8.237 ns ; A3 ; Y3 ; -; N/A ; None ; 8.014 ns ; A5 ; Y5 ; -; N/A ; None ; 7.942 ns ; A4 ; Y5 ; -; N/A ; None ; 7.635 ns ; A4 ; Y3 ; -; N/A ; None ; 7.583 ns ; A2 ; Y2 ; -; N/A ; None ; 7.551 ns ; A3 ; Y4 ; -; N/A ; None ; 7.136 ns ; A5 ; Y6 ; -; N/A ; None ; 7.085 ns ; A4 ; Y4 ; -; N/A ; None ; 7.014 ns ; A5 ; Y4 ; -; N/A ; None ; 6.993 ns ; A3 ; Y2 ; -; N/A ; None ; 6.585 ns ; A2 ; Y1 ; +; N/A ; None ; 15.661 ns ; LM ; Y5 ; +; N/A ; None ; 15.651 ns ; DM ; Y5 ; +; N/A ; None ; 15.610 ns ; LM ; Y3 ; +; N/A ; None ; 15.606 ns ; DM ; Y3 ; +; N/A ; None ; 15.297 ns ; DM ; Y1 ; +; N/A ; None ; 15.251 ns ; DM ; Y6 ; +; N/A ; None ; 15.189 ns ; LM ; Y4 ; +; N/A ; None ; 15.186 ns ; DM ; Y4 ; +; N/A ; None ; 14.807 ns ; LM ; Y1 ; +; N/A ; None ; 14.796 ns ; DM ; Y2 ; +; N/A ; None ; 14.768 ns ; LM ; Y6 ; +; N/A ; None ; 14.737 ns ; RM ; Y6 ; +; N/A ; None ; 14.714 ns ; RM ; Y5 ; +; N/A ; None ; 14.662 ns ; RM ; Y3 ; +; N/A ; None ; 14.654 ns ; RM ; Y4 ; +; N/A ; None ; 14.633 ns ; DM ; Y7 ; +; N/A ; None ; 14.630 ns ; LM ; Y7 ; +; N/A ; None ; 14.582 ns ; A0 ; Y1 ; +; N/A ; None ; 14.517 ns ; A3 ; Y3 ; +; N/A ; None ; 14.509 ns ; A1 ; Y1 ; +; N/A ; None ; 14.410 ns ; A2 ; Y3 ; +; N/A ; None ; 14.345 ns ; RM ; Y1 ; +; N/A ; None ; 14.328 ns ; LM ; Y2 ; +; N/A ; None ; 14.284 ns ; RM ; Y2 ; +; N/A ; None ; 14.272 ns ; RM ; Y0 ; +; N/A ; None ; 14.232 ns ; A5 ; Y5 ; +; N/A ; None ; 14.231 ns ; DM ; Y0 ; +; N/A ; None ; 14.156 ns ; A6 ; Y6 ; +; N/A ; None ; 14.096 ns ; A3 ; Y4 ; +; N/A ; None ; 14.080 ns ; A2 ; Y2 ; +; N/A ; None ; 14.078 ns ; A4 ; Y5 ; +; N/A ; None ; 13.824 ns ; A5 ; Y6 ; +; N/A ; None ; 13.706 ns ; A1 ; Y2 ; +; N/A ; None ; 13.606 ns ; A4 ; Y4 ; +; N/A ; None ; 13.309 ns ; A0 ; Y0 ; +; N/A ; None ; 13.231 ns ; A7 ; Y6 ; +; N/A ; None ; 13.196 ns ; A5 ; Y4 ; +; N/A ; None ; 13.181 ns ; A7 ; Y7 ; +; N/A ; None ; 13.141 ns ; A1 ; Y0 ; +; N/A ; None ; 13.137 ns ; A3 ; Y2 ; +; N/A ; None ; 13.099 ns ; A2 ; Y1 ; +; N/A ; None ; 13.098 ns ; A6 ; Y5 ; +; N/A ; None ; 13.064 ns ; A6 ; Y7 ; +; N/A ; None ; 13.036 ns ; A4 ; Y3 ; +-------+-------------------+-----------------+------+----+ @@ -151,19 +151,20 @@ applicable agreement for further details. Info: ******************************************************************* Info: Running Quartus II Classic Timing Analyzer Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Mon Mar 07 11:15:57 2022 + Info: Processing started: Tue Mar 08 15:17:19 2022 Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only -Info: Parallel compilation is enabled and will use 4 of the 6 processors detected -Info: Longest tpd from source pin "A6" to destination pin "Y7" is 13.413 ns - Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 3; PIN Node = 'A6' - Info: 2: + IC(6.895 ns) + CELL(0.624 ns) = 8.513 ns; Loc. = LCCOMB_X1_Y5_N10; Fanout = 1; COMB Node = 'triple_selector_8b:inst|inst31' - Info: 3: + IC(1.604 ns) + CELL(3.296 ns) = 13.413 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'Y7' - Info: Total cell delay = 4.914 ns ( 36.64 % ) - Info: Total interconnect delay = 8.499 ns ( 63.36 % ) +Info: Parallel compilation is enabled and will use 4 of the 4 processors detected +Info: Longest tpd from source pin "LM" to destination pin "Y5" is 15.661 ns + Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_69; Fanout = 7; PIN Node = 'LM' + Info: 2: + IC(6.879 ns) + CELL(0.650 ns) = 8.523 ns; Loc. = LCCOMB_X26_Y1_N18; Fanout = 1; COMB Node = 'triple_selector_8b:inst|inst23~0' + Info: 3: + IC(0.370 ns) + CELL(0.624 ns) = 9.517 ns; Loc. = LCCOMB_X26_Y1_N20; Fanout = 1; COMB Node = 'triple_selector_8b:inst|inst23' + Info: 4: + IC(3.028 ns) + CELL(3.116 ns) = 15.661 ns; Loc. = PIN_147; Fanout = 0; PIN Node = 'Y5' + Info: Total cell delay = 5.384 ns ( 34.38 % ) + Info: Total interconnect delay = 10.277 ns ( 65.62 % ) Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 191 megabytes - Info: Processing ended: Mon Mar 07 11:15:58 2022 - Info: Elapsed time: 00:00:01 + Info: Peak virtual memory: 212 megabytes + Info: Processing ended: Tue Mar 08 15:17:19 2022 + Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:00 diff --git a/shifter_8b/shifter_8b.tan.summary b/shifter_8b/shifter_8b.tan.summary index e1cbc56..3eb3609 100644 --- a/shifter_8b/shifter_8b.tan.summary +++ b/shifter_8b/shifter_8b.tan.summary @@ -5,9 +5,9 @@ Timing Analyzer Summary Type : Worst-case tpd Slack : N/A Required Time : None -Actual Time : 13.413 ns -From : A6 -To : Y7 +Actual Time : 15.661 ns +From : LM +To : Y5 From Clock : -- To Clock : -- Failed Paths : 0