commit a1e1b8764a45ded178f7c8bdb8fd8916c9aeff4f
Author: juzeon <812312770@qq.com>
Date: Sat Mar 5 20:52:27 2022 +0800
add data_selector 未设定 pins
diff --git a/data_selector/data_selector.asm.rpt b/data_selector/data_selector.asm.rpt
new file mode 100644
index 0000000..546d846
--- /dev/null
+++ b/data_selector/data_selector.asm.rpt
@@ -0,0 +1,129 @@
+Assembler report for data_selector
+Sat Mar 05 20:41:36 2022
+Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Assembler Summary
+ 3. Assembler Settings
+ 4. Assembler Generated Files
+ 5. Assembler Device Options: D:/projects/quartus/data_selector/data_selector.sof
+ 6. Assembler Device Options: D:/projects/quartus/data_selector/data_selector.pof
+ 7. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary ;
++-----------------------+---------------------------------------+
+; Assembler Status ; Successful - Sat Mar 05 20:41:36 2022 ;
+; Revision Name ; data_selector ;
+; Top-level Entity Name ; data_selector ;
+; Family ; Cyclone II ;
+; Device ; EP2C8Q208C8 ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option ; Setting ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation ; Off ; Off ;
+; Generate compressed bitstreams ; On ; On ;
+; Compression mode ; Off ; Off ;
+; Clock source for configuration device ; Internal ; Internal ;
+; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
+; Divide clock frequency by ; 1 ; 1 ;
+; Auto user code ; Off ; Off ;
+; Use configuration device ; On ; On ;
+; Configuration device ; Auto ; Auto ;
+; Configuration device auto user code ; Off ; Off ;
+; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
+; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
+; Hexadecimal Output File start address ; 0 ; 0 ;
+; Hexadecimal Output File count direction ; Up ; Up ;
+; Release clears before tri-states ; Off ; Off ;
+; Auto-restart configuration after error ; On ; On ;
+; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ;
+; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++-----------------------------------------------------+
+; Assembler Generated Files ;
++-----------------------------------------------------+
+; File Name ;
++-----------------------------------------------------+
+; D:/projects/quartus/data_selector/data_selector.sof ;
+; D:/projects/quartus/data_selector/data_selector.pof ;
++-----------------------------------------------------+
+
+
++-------------------------------------------------------------------------------+
+; Assembler Device Options: D:/projects/quartus/data_selector/data_selector.sof ;
++----------------+--------------------------------------------------------------+
+; Option ; Setting ;
++----------------+--------------------------------------------------------------+
+; Device ; EP2C8Q208C8 ;
+; JTAG usercode ; 0xFFFFFFFF ;
+; Checksum ; 0x000C1D58 ;
++----------------+--------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------+
+; Assembler Device Options: D:/projects/quartus/data_selector/data_selector.pof ;
++--------------------+----------------------------------------------------------+
+; Option ; Setting ;
++--------------------+----------------------------------------------------------+
+; Device ; EPCS4 ;
+; JTAG usercode ; 0x00000000 ;
+; Checksum ; 0x06EFE46F ;
+; Compression Ratio ; 3 ;
++--------------------+----------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II Assembler
+ Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+ Info: Processing started: Sat Mar 05 20:41:35 2022
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off data_selector -c data_selector
+Info: Writing out detailed assembly data for power analysis
+Info: Assembler is generating device programming files
+Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled
+Info: Quartus II Assembler was successful. 0 errors, 0 warnings
+ Info: Peak virtual memory: 241 megabytes
+ Info: Processing ended: Sat Mar 05 20:41:36 2022
+ Info: Elapsed time: 00:00:01
+ Info: Total CPU time (on all processors): 00:00:00
+
+
diff --git a/data_selector/data_selector.bdf b/data_selector/data_selector.bdf
new file mode 100644
index 0000000..93f0c83
--- /dev/null
+++ b/data_selector/data_selector.bdf
@@ -0,0 +1,1819 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+*/
+//#pragma file_not_in_maxplusii_format
+(header "graphic" (version "1.3"))
+(pin
+ (input)
+ (rect 176 64 344 80)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "a0" (rect 5 0 16 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 176 88 344 104)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "a1" (rect 5 0 16 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 176 112 344 128)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "a2" (rect 5 0 16 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 176 136 344 152)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "a3" (rect 5 0 16 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
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+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 176 160 344 176)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "a4" (rect 5 0 16 12)(font "Arial" ))
+ (pt 168 8)
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+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 176 184 344 200)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "a5" (rect 5 0 16 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
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+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
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+(pin
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+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
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+ )
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+)
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+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "a7" (rect 5 0 16 12)(font "Arial" ))
+ (pt 168 8)
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+ )
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+)
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+)
+(pin
+ (input)
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+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
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+ )
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+)
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+ )
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+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
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diff --git a/data_selector/data_selector.bsf b/data_selector/data_selector.bsf
new file mode 100644
index 0000000..25cf9a0
--- /dev/null
+++ b/data_selector/data_selector.bsf
@@ -0,0 +1,211 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
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+ )
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+ )
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+ )
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+ )
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+ (pt 0 224)
+ (input)
+ (text "b4" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+ (text "b4" (rect 21 219 35 233)(font "Arial" (font_size 8)))
+ (line (pt 0 224)(pt 16 224)(line_width 1))
+ )
+ (port
+ (pt 0 240)
+ (input)
+ (text "b5" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+ (text "b5" (rect 21 235 35 249)(font "Arial" (font_size 8)))
+ (line (pt 0 240)(pt 16 240)(line_width 1))
+ )
+ (port
+ (pt 0 256)
+ (input)
+ (text "b6" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+ (text "b6" (rect 21 251 35 265)(font "Arial" (font_size 8)))
+ (line (pt 0 256)(pt 16 256)(line_width 1))
+ )
+ (port
+ (pt 0 272)
+ (input)
+ (text "b7" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+ (text "b7" (rect 21 267 35 281)(font "Arial" (font_size 8)))
+ (line (pt 0 272)(pt 16 272)(line_width 1))
+ )
+ (port
+ (pt 0 288)
+ (input)
+ (text "AY" (rect 0 0 18 14)(font "Arial" (font_size 8)))
+ (text "AY" (rect 21 283 39 297)(font "Arial" (font_size 8)))
+ (line (pt 0 288)(pt 16 288)(line_width 1))
+ )
+ (port
+ (pt 0 304)
+ (input)
+ (text "BY" (rect 0 0 17 14)(font "Arial" (font_size 8)))
+ (text "BY" (rect 21 299 38 313)(font "Arial" (font_size 8)))
+ (line (pt 0 304)(pt 16 304)(line_width 1))
+ )
+ (port
+ (pt 96 32)
+ (output)
+ (text "Y0" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+ (text "Y0" (rect 59 27 75 41)(font "Arial" (font_size 8)))
+ (line (pt 96 32)(pt 80 32)(line_width 1))
+ )
+ (port
+ (pt 96 48)
+ (output)
+ (text "Y1" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+ (text "Y1" (rect 59 43 75 57)(font "Arial" (font_size 8)))
+ (line (pt 96 48)(pt 80 48)(line_width 1))
+ )
+ (port
+ (pt 96 64)
+ (output)
+ (text "Y2" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+ (text "Y2" (rect 59 59 75 73)(font "Arial" (font_size 8)))
+ (line (pt 96 64)(pt 80 64)(line_width 1))
+ )
+ (port
+ (pt 96 80)
+ (output)
+ (text "Y3" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+ (text "Y3" (rect 59 75 75 89)(font "Arial" (font_size 8)))
+ (line (pt 96 80)(pt 80 80)(line_width 1))
+ )
+ (port
+ (pt 96 96)
+ (output)
+ (text "Y4" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+ (text "Y4" (rect 59 91 75 105)(font "Arial" (font_size 8)))
+ (line (pt 96 96)(pt 80 96)(line_width 1))
+ )
+ (port
+ (pt 96 112)
+ (output)
+ (text "Y5" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+ (text "Y5" (rect 59 107 75 121)(font "Arial" (font_size 8)))
+ (line (pt 96 112)(pt 80 112)(line_width 1))
+ )
+ (port
+ (pt 96 128)
+ (output)
+ (text "Y6" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+ (text "Y6" (rect 59 123 75 137)(font "Arial" (font_size 8)))
+ (line (pt 96 128)(pt 80 128)(line_width 1))
+ )
+ (port
+ (pt 96 144)
+ (output)
+ (text "Y7" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+ (text "Y7" (rect 59 139 75 153)(font "Arial" (font_size 8)))
+ (line (pt 96 144)(pt 80 144)(line_width 1))
+ )
+ (drawing
+ (rectangle (rect 16 16 80 336)(line_width 1))
+ )
+)
diff --git a/data_selector/data_selector.done b/data_selector/data_selector.done
new file mode 100644
index 0000000..64e702a
--- /dev/null
+++ b/data_selector/data_selector.done
@@ -0,0 +1 @@
+Sat Mar 05 20:41:37 2022
diff --git a/data_selector/data_selector.dpf b/data_selector/data_selector.dpf
new file mode 100644
index 0000000..abe19d9
--- /dev/null
+++ b/data_selector/data_selector.dpf
@@ -0,0 +1,12 @@
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/data_selector/data_selector.fit.rpt b/data_selector/data_selector.fit.rpt
new file mode 100644
index 0000000..d3b0058
--- /dev/null
+++ b/data_selector/data_selector.fit.rpt
@@ -0,0 +1,1006 @@
+Fitter report for data_selector
+Sat Mar 05 20:41:34 2022
+Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Fitter Summary
+ 3. Fitter Settings
+ 4. Parallel Compilation
+ 5. Incremental Compilation Preservation Summary
+ 6. Incremental Compilation Partition Settings
+ 7. Incremental Compilation Placement Preservation
+ 8. Pin-Out File
+ 9. Fitter Resource Usage Summary
+ 10. Input Pins
+ 11. Output Pins
+ 12. I/O Bank Usage
+ 13. All Package Pins
+ 14. Output Pin Default Load For Reported TCO
+ 15. Fitter Resource Utilization by Entity
+ 16. Delay Chain Summary
+ 17. Pad To Core Delay Chain Fanout
+ 18. Non-Global High Fan-Out Signals
+ 19. Interconnect Usage Summary
+ 20. LAB Logic Elements
+ 21. LAB Signals Sourced
+ 22. LAB Signals Sourced Out
+ 23. LAB Distinct Inputs
+ 24. Fitter Device Options
+ 25. Operating Settings and Conditions
+ 26. Estimated Delay Added for Hold Timing
+ 27. Advanced Data - General
+ 28. Advanced Data - Placement Preparation
+ 29. Advanced Data - Placement
+ 30. Advanced Data - Routing
+ 31. Fitter Messages
+ 32. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Fitter Summary ;
++------------------------------------+----------------------------------------------+
+; Fitter Status ; Successful - Sat Mar 05 20:41:34 2022 ;
+; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
+; Revision Name ; data_selector ;
+; Top-level Entity Name ; data_selector ;
+; Family ; Cyclone II ;
+; Device ; EP2C8Q208C8 ;
+; Timing Models ; Final ;
+; Total logic elements ; 8 / 8,256 ( < 1 % ) ;
+; Total combinational functions ; 8 / 8,256 ( < 1 % ) ;
+; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ;
+; Total registers ; 0 ;
+; Total pins ; 26 / 138 ( 19 % ) ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 0 / 165,888 ( 0 % ) ;
+; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
+; Total PLLs ; 0 / 2 ( 0 % ) ;
++------------------------------------+----------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+; Option ; Setting ; Default Value ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+; Device ; EP2C8Q208C8 ; ;
+; Minimum Core Junction Temperature ; 0 ; ;
+; Maximum Core Junction Temperature ; 85 ; ;
+; Fit Attempts to Skip ; 0 ; 0.0 ;
+; Use smart compilation ; Off ; Off ;
+; Use TimeQuest Timing Analyzer ; Off ; Off ;
+; Router Timing Optimization Level ; Normal ; Normal ;
+; Placement Effort Multiplier ; 1.0 ; 1.0 ;
+; Router Effort Multiplier ; 1.0 ; 1.0 ;
+; Always Enable Input Buffers ; Off ; Off ;
+; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
+; Optimize Multi-Corner Timing ; Off ; Off ;
+; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
+; Optimize Timing ; Normal compilation ; Normal compilation ;
+; Optimize Timing for ECOs ; Off ; Off ;
+; Regenerate full fit report during ECO compiles ; Off ; Off ;
+; Optimize IOC Register Placement for Timing ; On ; On ;
+; Limit to One Fitting Attempt ; Off ; Off ;
+; Final Placement Optimizations ; Automatically ; Automatically ;
+; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
+; Fitter Initial Placement Seed ; 1 ; 1 ;
+; PCI I/O ; Off ; Off ;
+; Weak Pull-Up Resistor ; Off ; Off ;
+; Enable Bus-Hold Circuitry ; Off ; Off ;
+; Auto Global Memory Control Signals ; Off ; Off ;
+; Auto Packed Registers ; Auto ; Auto ;
+; Auto Delay Chains ; On ; On ;
+; Auto Merge PLLs ; On ; On ;
+; Ignore PLL Mode When Merging PLLs ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
+; Perform Register Duplication for Performance ; Off ; Off ;
+; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
+; Perform Register Retiming for Performance ; Off ; Off ;
+; Perform Asynchronous Signal Pipelining ; Off ; Off ;
+; Fitter Effort ; Auto Fit ; Auto Fit ;
+; Physical Synthesis Effort Level ; Normal ; Normal ;
+; Auto Global Clock ; On ; On ;
+; Auto Global Register Control Signals ; On ; On ;
+; Stop After Congestion Map Generation ; Off ; Off ;
+; Save Intermediate Fitting Results ; Off ; Off ;
+; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 4 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.00 ;
+; Maximum used ; 4 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; 1 processor ; 100.0% ;
+; 2-4 processors ; < 0.1% ;
++----------------------------+-------------+
+
+
++----------------------------------------------+
+; Incremental Compilation Preservation Summary ;
++-------------------------+--------------------+
+; Type ; Value ;
++-------------------------+--------------------+
+; Placement ; ;
+; -- Requested ; 0 / 34 ( 0.00 % ) ;
+; -- Achieved ; 0 / 34 ( 0.00 % ) ;
+; ; ;
+; Routing (by Connection) ; ;
+; -- Requested ; 0 / 0 ( 0.00 % ) ;
+; -- Achieved ; 0 / 0 ( 0.00 % ) ;
++-------------------------+--------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings ;
++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
+; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
+; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
+
+
++--------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation ;
++----------------+---------+-------------------+-------------------------+-------------------+
+; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
++----------------+---------+-------------------+-------------------------+-------------------+
+; Top ; 34 ; 0 ; N/A ; Source File ;
++----------------+---------+-------------------+-------------------------+-------------------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in D:/projects/quartus/data_selector/data_selector.pin.
+
+
++-------------------------------------------------------------------+
+; Fitter Resource Usage Summary ;
++---------------------------------------------+---------------------+
+; Resource ; Usage ;
++---------------------------------------------+---------------------+
+; Total logic elements ; 8 / 8,256 ( < 1 % ) ;
+; -- Combinational with no register ; 8 ;
+; -- Register only ; 0 ;
+; -- Combinational with a register ; 0 ;
+; ; ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 8 ;
+; -- 3 input functions ; 0 ;
+; -- <=2 input functions ; 0 ;
+; -- Register only ; 0 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 8 ;
+; -- arithmetic mode ; 0 ;
+; ; ;
+; Total registers* ; 0 / 8,646 ( 0 % ) ;
+; -- Dedicated logic registers ; 0 / 8,256 ( 0 % ) ;
+; -- I/O registers ; 0 / 390 ( 0 % ) ;
+; ; ;
+; Total LABs: partially or completely used ; 1 / 516 ( < 1 % ) ;
+; User inserted logic elements ; 0 ;
+; Virtual pins ; 0 ;
+; I/O pins ; 26 / 138 ( 19 % ) ;
+; -- Clock pins ; 2 / 4 ( 50 % ) ;
+; Global signals ; 0 ;
+; M4Ks ; 0 / 36 ( 0 % ) ;
+; Total block memory bits ; 0 / 165,888 ( 0 % ) ;
+; Total block memory implementation bits ; 0 / 165,888 ( 0 % ) ;
+; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
+; PLLs ; 0 / 2 ( 0 % ) ;
+; Global clocks ; 0 / 8 ( 0 % ) ;
+; JTAGs ; 0 / 1 ( 0 % ) ;
+; ASMI blocks ; 0 / 1 ( 0 % ) ;
+; CRC blocks ; 0 / 1 ( 0 % ) ;
+; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ;
+; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ;
+; Maximum fan-out node ; AY ;
+; Maximum fan-out ; 8 ;
+; Highest non-global fan-out signal ; AY ;
+; Highest non-global fan-out ; 8 ;
+; Total fan-out ; 40 ;
+; Average fan-out ; 1.08 ;
++---------------------------------------------+---------------------+
+* Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins ;
++------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
++------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+; AY ; 56 ; 4 ; 1 ; 0 ; 3 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; BY ; 44 ; 1 ; 0 ; 3 ; 1 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; a0 ; 39 ; 1 ; 0 ; 5 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; a1 ; 37 ; 1 ; 0 ; 6 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; a2 ; 24 ; 1 ; 0 ; 9 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; a3 ; 28 ; 1 ; 0 ; 9 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; a4 ; 12 ; 1 ; 0 ; 16 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; a5 ; 31 ; 1 ; 0 ; 8 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; a6 ; 34 ; 1 ; 0 ; 7 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; a7 ; 3 ; 1 ; 0 ; 18 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; b0 ; 40 ; 1 ; 0 ; 5 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; b1 ; 23 ; 1 ; 0 ; 9 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; b2 ; 27 ; 1 ; 0 ; 9 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; b3 ; 59 ; 4 ; 1 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; b4 ; 41 ; 1 ; 0 ; 4 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; b5 ; 45 ; 1 ; 0 ; 3 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; b6 ; 57 ; 4 ; 1 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; b7 ; 33 ; 1 ; 0 ; 8 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
++------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins ;
++------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
++------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
+; Y0 ; 58 ; 4 ; 1 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; Y1 ; 35 ; 1 ; 0 ; 7 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; Y2 ; 14 ; 1 ; 0 ; 14 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; Y3 ; 15 ; 1 ; 0 ; 14 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; Y4 ; 10 ; 1 ; 0 ; 17 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; Y5 ; 208 ; 2 ; 1 ; 19 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; Y6 ; 30 ; 1 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; Y7 ; 48 ; 1 ; 0 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
++------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
+
+
++------------------------------------------------------------+
+; I/O Bank Usage ;
++----------+------------------+---------------+--------------+
+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
++----------+------------------+---------------+--------------+
+; 1 ; 23 / 32 ( 72 % ) ; 3.3V ; -- ;
+; 2 ; 1 / 35 ( 3 % ) ; 3.3V ; -- ;
+; 3 ; 1 / 35 ( 3 % ) ; 3.3V ; -- ;
+; 4 ; 4 / 36 ( 11 % ) ; 3.3V ; -- ;
++----------+------------------+---------------+--------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins ;
++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; 1 ; 0 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
+; 2 ; 1 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
+; 3 ; 2 ; 1 ; a7 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 4 ; 3 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 5 ; 4 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 6 ; 5 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 8 ; 6 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 10 ; 7 ; 1 ; Y4 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 11 ; 8 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 12 ; 9 ; 1 ; a4 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 13 ; 10 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 14 ; 18 ; 1 ; Y2 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 15 ; 19 ; 1 ; Y3 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
+; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
+; 18 ; 22 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
+; 19 ; 23 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
+; 20 ; 24 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ;
+; 21 ; 25 ; 1 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ;
+; 22 ; 26 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
+; 23 ; 27 ; 1 ; b1 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 24 ; 28 ; 1 ; a2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 26 ; 29 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
+; 27 ; 30 ; 1 ; b2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 28 ; 31 ; 1 ; a3 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 30 ; 32 ; 1 ; Y6 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 31 ; 33 ; 1 ; a5 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 33 ; 35 ; 1 ; b7 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 34 ; 36 ; 1 ; a6 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 35 ; 37 ; 1 ; Y1 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 37 ; 39 ; 1 ; a1 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 39 ; 43 ; 1 ; a0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 40 ; 44 ; 1 ; b0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 41 ; 45 ; 1 ; b4 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 42 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 43 ; 48 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 44 ; 49 ; 1 ; BY ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 45 ; 50 ; 1 ; b5 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 46 ; 51 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 47 ; 52 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 48 ; 53 ; 1 ; Y7 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 49 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 50 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
+; 51 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 52 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
+; 53 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 54 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
+; 55 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 56 ; 54 ; 4 ; AY ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 57 ; 55 ; 4 ; b6 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 58 ; 56 ; 4 ; Y0 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 59 ; 57 ; 4 ; b3 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 60 ; 58 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 61 ; 59 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 63 ; 60 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 64 ; 61 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 67 ; 69 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 68 ; 70 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 69 ; 71 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 70 ; 74 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 71 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 72 ; 75 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 74 ; 76 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 75 ; 77 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 76 ; 78 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 77 ; 79 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 80 ; 82 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 81 ; 83 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 82 ; 84 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 83 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 84 ; 85 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 85 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 86 ; 86 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 87 ; 87 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 88 ; 88 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 89 ; 89 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 90 ; 90 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 91 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 92 ; 91 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 94 ; 92 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 95 ; 93 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 96 ; 94 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 97 ; 95 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 98 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 99 ; 96 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 100 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 101 ; 97 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 102 ; 98 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 103 ; 99 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 104 ; 100 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 105 ; 101 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 106 ; 102 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 107 ; 105 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 108 ; 106 ; 3 ; ~LVDS54p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 109 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 110 ; 107 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 111 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 112 ; 108 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 113 ; 109 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 114 ; 110 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 115 ; 112 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 116 ; 113 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 117 ; 114 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 118 ; 117 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 119 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 120 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 121 ; 121 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
+; 122 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 123 ; 122 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
+; 124 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 125 ; 123 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
+; 126 ; 124 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
+; 127 ; 125 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 128 ; 126 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 129 ; 127 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; 130 ; 128 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; 131 ; 129 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; 132 ; 130 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; 133 ; 131 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 134 ; 132 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 135 ; 133 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 136 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 137 ; 134 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 138 ; 135 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 139 ; 136 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 141 ; 137 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 142 ; 138 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 143 ; 141 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 144 ; 142 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 145 ; 143 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 146 ; 149 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 147 ; 150 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 148 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 149 ; 151 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 150 ; 152 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 151 ; 153 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 152 ; 154 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 153 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 154 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
+; 155 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 156 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
+; 157 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 158 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
+; 159 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 160 ; 155 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 161 ; 156 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 162 ; 157 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 163 ; 158 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 164 ; 159 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 165 ; 160 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 166 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 167 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 168 ; 161 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 169 ; 162 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 170 ; 163 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 171 ; 164 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 172 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 173 ; 165 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 174 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 175 ; 168 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 176 ; 169 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 177 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 178 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 179 ; 173 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 180 ; 174 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 181 ; 175 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 182 ; 176 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 183 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 184 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 185 ; 180 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 186 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 187 ; 181 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 188 ; 182 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 189 ; 183 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 190 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 191 ; 184 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 192 ; 185 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 193 ; 186 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 194 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 195 ; 187 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 196 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 197 ; 191 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 198 ; 192 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 199 ; 195 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 200 ; 196 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 201 ; 197 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 202 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 203 ; 198 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 204 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 205 ; 199 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 206 ; 200 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 207 ; 201 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 208 ; 202 ; 2 ; Y5 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-------------------------------------------------------------------------------+
+; Output Pin Default Load For Reported TCO ;
++----------------------------------+-------+------------------------------------+
+; I/O Standard ; Load ; Termination Resistance ;
++----------------------------------+-------+------------------------------------+
+; 3.3-V LVTTL ; 0 pF ; Not Available ;
+; 3.3-V LVCMOS ; 0 pF ; Not Available ;
+; 2.5 V ; 0 pF ; Not Available ;
+; 1.8 V ; 0 pF ; Not Available ;
+; 1.5 V ; 0 pF ; Not Available ;
+; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ;
+; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ;
+; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
+; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;
+; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;
+; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;
+; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;
+; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ;
+; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ;
+; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ;
+; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ;
+; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ;
+; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ;
+; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ;
+; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ;
+; LVDS ; 0 pF ; 100 Ohm (Differential) ;
+; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ;
+; RSDS ; 0 pF ; 100 Ohm (Differential) ;
+; Simple RSDS ; 0 pF ; Not Available ;
+; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ;
++----------------------------------+-------+------------------------------------+
+Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
+; |data_selector ; 8 (8) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 26 ; 0 ; 8 (8) ; 0 (0) ; 0 (0) ; |data_selector ; work ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-------------------------------------------------------------------------------+
+; Delay Chain Summary ;
++------+----------+---------------+---------------+-----------------------+-----+
+; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
++------+----------+---------------+---------------+-----------------------+-----+
+; Y0 ; Output ; -- ; -- ; -- ; -- ;
+; Y1 ; Output ; -- ; -- ; -- ; -- ;
+; Y2 ; Output ; -- ; -- ; -- ; -- ;
+; Y3 ; Output ; -- ; -- ; -- ; -- ;
+; Y4 ; Output ; -- ; -- ; -- ; -- ;
+; Y5 ; Output ; -- ; -- ; -- ; -- ;
+; Y6 ; Output ; -- ; -- ; -- ; -- ;
+; Y7 ; Output ; -- ; -- ; -- ; -- ;
+; b0 ; Input ; 6 ; 6 ; -- ; -- ;
+; a0 ; Input ; 6 ; 6 ; -- ; -- ;
+; AY ; Input ; 6 ; 6 ; -- ; -- ;
+; BY ; Input ; 6 ; 6 ; -- ; -- ;
+; a1 ; Input ; 6 ; 6 ; -- ; -- ;
+; b1 ; Input ; 0 ; 0 ; -- ; -- ;
+; a2 ; Input ; 0 ; 0 ; -- ; -- ;
+; b2 ; Input ; 0 ; 0 ; -- ; -- ;
+; a3 ; Input ; 0 ; 0 ; -- ; -- ;
+; b3 ; Input ; 6 ; 6 ; -- ; -- ;
+; a4 ; Input ; 6 ; 6 ; -- ; -- ;
+; b4 ; Input ; 6 ; 6 ; -- ; -- ;
+; a5 ; Input ; 6 ; 6 ; -- ; -- ;
+; b5 ; Input ; 6 ; 6 ; -- ; -- ;
+; a6 ; Input ; 6 ; 6 ; -- ; -- ;
+; b6 ; Input ; 6 ; 6 ; -- ; -- ;
+; a7 ; Input ; 6 ; 6 ; -- ; -- ;
+; b7 ; Input ; 6 ; 6 ; -- ; -- ;
++------+----------+---------------+---------------+-----------------------+-----+
+
+
++---------------------------------------------------+
+; Pad To Core Delay Chain Fanout ;
++---------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++---------------------+-------------------+---------+
+; b0 ; ; ;
+; - inst1 ; 1 ; 6 ;
+; a0 ; ; ;
+; - inst1 ; 0 ; 6 ;
+; AY ; ; ;
+; - inst1 ; 0 ; 6 ;
+; - inst2 ; 0 ; 6 ;
+; - inst3 ; 0 ; 6 ;
+; - inst4 ; 0 ; 6 ;
+; - inst5 ; 0 ; 6 ;
+; - inst6 ; 0 ; 6 ;
+; - inst7 ; 0 ; 6 ;
+; - inst8 ; 0 ; 6 ;
+; BY ; ; ;
+; - inst1 ; 1 ; 6 ;
+; - inst2 ; 1 ; 6 ;
+; - inst3 ; 1 ; 6 ;
+; - inst4 ; 1 ; 6 ;
+; - inst5 ; 1 ; 6 ;
+; - inst6 ; 1 ; 6 ;
+; - inst7 ; 1 ; 6 ;
+; - inst8 ; 1 ; 6 ;
+; a1 ; ; ;
+; - inst2 ; 0 ; 6 ;
+; b1 ; ; ;
+; a2 ; ; ;
+; b2 ; ; ;
+; a3 ; ; ;
+; b3 ; ; ;
+; - inst4 ; 0 ; 6 ;
+; a4 ; ; ;
+; - inst5 ; 0 ; 6 ;
+; b4 ; ; ;
+; - inst5 ; 1 ; 6 ;
+; a5 ; ; ;
+; - inst6 ; 0 ; 6 ;
+; b5 ; ; ;
+; - inst6 ; 1 ; 6 ;
+; a6 ; ; ;
+; - inst7 ; 0 ; 6 ;
+; b6 ; ; ;
+; - inst7 ; 1 ; 6 ;
+; a7 ; ; ;
+; - inst8 ; 0 ; 6 ;
+; b7 ; ; ;
+; - inst8 ; 0 ; 6 ;
++---------------------+-------------------+---------+
+
+
++---------------------------------+
+; Non-Global High Fan-Out Signals ;
++-------+-------------------------+
+; Name ; Fan-Out ;
++-------+-------------------------+
+; BY ; 8 ;
+; AY ; 8 ;
+; b7 ; 1 ;
+; a7 ; 1 ;
+; b6 ; 1 ;
+; a6 ; 1 ;
+; b5 ; 1 ;
+; a5 ; 1 ;
+; b4 ; 1 ;
+; a4 ; 1 ;
+; b3 ; 1 ;
+; a3 ; 1 ;
+; b2 ; 1 ;
+; a2 ; 1 ;
+; b1 ; 1 ;
+; a1 ; 1 ;
+; a0 ; 1 ;
+; b0 ; 1 ;
+; inst8 ; 1 ;
+; inst7 ; 1 ;
+; inst6 ; 1 ;
+; inst5 ; 1 ;
+; inst4 ; 1 ;
+; inst3 ; 1 ;
+; inst2 ; 1 ;
+; inst1 ; 1 ;
++-------+-------------------------+
+
+
++----------------------------------------------------+
+; Interconnect Usage Summary ;
++----------------------------+-----------------------+
+; Interconnect Resource Type ; Usage ;
++----------------------------+-----------------------+
+; Block interconnects ; 26 / 26,052 ( < 1 % ) ;
+; C16 interconnects ; 3 / 1,156 ( < 1 % ) ;
+; C4 interconnects ; 35 / 17,952 ( < 1 % ) ;
+; Direct links ; 0 / 26,052 ( 0 % ) ;
+; Global clocks ; 0 / 8 ( 0 % ) ;
+; Local interconnects ; 0 / 8,256 ( 0 % ) ;
+; R24 interconnects ; 0 / 1,020 ( 0 % ) ;
+; R4 interconnects ; 3 / 22,440 ( < 1 % ) ;
++----------------------------+-----------------------+
+
+
++--------------------------------------------------------------------------+
+; LAB Logic Elements ;
++--------------------------------------------+-----------------------------+
+; Number of Logic Elements (Average = 8.00) ; Number of LABs (Total = 1) ;
++--------------------------------------------+-----------------------------+
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 0 ;
+; 4 ; 0 ;
+; 5 ; 0 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 1 ;
+; 9 ; 0 ;
+; 10 ; 0 ;
+; 11 ; 0 ;
+; 12 ; 0 ;
+; 13 ; 0 ;
+; 14 ; 0 ;
+; 15 ; 0 ;
+; 16 ; 0 ;
++--------------------------------------------+-----------------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Signals Sourced ;
++---------------------------------------------+-----------------------------+
+; Number of Signals Sourced (Average = 8.00) ; Number of LABs (Total = 1) ;
++---------------------------------------------+-----------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 0 ;
+; 4 ; 0 ;
+; 5 ; 0 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 1 ;
++---------------------------------------------+-----------------------------+
+
+
++-------------------------------------------------------------------------------+
+; LAB Signals Sourced Out ;
++-------------------------------------------------+-----------------------------+
+; Number of Signals Sourced Out (Average = 8.00) ; Number of LABs (Total = 1) ;
++-------------------------------------------------+-----------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 0 ;
+; 4 ; 0 ;
+; 5 ; 0 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 1 ;
++-------------------------------------------------+-----------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Distinct Inputs ;
++----------------------------------------------+-----------------------------+
+; Number of Distinct Inputs (Average = 18.00) ; Number of LABs (Total = 1) ;
++----------------------------------------------+-----------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 0 ;
+; 4 ; 0 ;
+; 5 ; 0 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 0 ;
+; 9 ; 0 ;
+; 10 ; 0 ;
+; 11 ; 0 ;
+; 12 ; 0 ;
+; 13 ; 0 ;
+; 14 ; 0 ;
+; 15 ; 0 ;
+; 16 ; 0 ;
+; 17 ; 0 ;
+; 18 ; 1 ;
++----------------------------------------------+-----------------------------+
+
+
++-------------------------------------------------------------------------+
+; Fitter Device Options ;
++----------------------------------------------+--------------------------+
+; Option ; Setting ;
++----------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR) ; Off ;
+; Enable device-wide reset (DEV_CLRn) ; Off ;
+; Enable device-wide output enable (DEV_OE) ; Off ;
+; Enable INIT_DONE output ; Off ;
+; Configuration scheme ; Active Serial ;
+; Error detection CRC ; Off ;
+; nCEO ; As output driving ground ;
+; ASDO,nCSO ; As input tri-stated ;
+; Reserve all unused pins ; As input tri-stated ;
+; Base pin-out file on sameframe device ; Off ;
++----------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions ;
++---------------------------+--------+
+; Setting ; Value ;
++---------------------------+--------+
+; Nominal Core Voltage ; 1.20 V ;
+; Low Junction Temperature ; 0 °C ;
+; High Junction Temperature ; 85 °C ;
++---------------------------+--------+
+
+
++------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing ;
++-----------------+----------------------+-------------------+
+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
++-----------------+----------------------+-------------------+
+
+
++----------------------------+
+; Advanced Data - General ;
++--------------------+-------+
+; Name ; Value ;
++--------------------+-------+
+; Status Code ; 0 ;
+; Desired User Slack ; 0 ;
+; Fit Attempts ; 1 ;
++--------------------+-------+
+
+
++-------------------------------------------------------------------------------+
+; Advanced Data - Placement Preparation ;
++------------------------------------------------------------------+------------+
+; Name ; Value ;
++------------------------------------------------------------------+------------+
+; Auto Fit Point 1 - Fit Attempt 1 ; ff ;
+; Mid Wire Use - Fit Attempt 1 ; 0 ;
+; Mid Slack - Fit Attempt 1 ; 2147483639 ;
+; Internal Atom Count - Fit Attempt 1 ; 9 ;
+; LE/ALM Count - Fit Attempt 1 ; 9 ;
+; LAB Count - Fit Attempt 1 ; 2 ;
+; Outputs per Lab - Fit Attempt 1 ; 4.000 ;
+; Inputs per LAB - Fit Attempt 1 ; 9.000 ;
+; Global Inputs per LAB - Fit Attempt 1 ; 0.000 ;
+; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:1 ;
+; LEs in Chains - Fit Attempt 1 ; 0 ;
+; LEs in Long Chains - Fit Attempt 1 ; 0 ;
+; LABs with Chains - Fit Attempt 1 ; 0 ;
+; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;
+; Time - Fit Attempt 1 ; 0 ;
++------------------------------------------------------------------+------------+
+
+
++-------------------------------------------------+
+; Advanced Data - Placement ;
++------------------------------------+------------+
+; Name ; Value ;
++------------------------------------+------------+
+; Auto Fit Point 2 - Fit Attempt 1 ; ff ;
+; Auto Fit Point 5 - Fit Attempt 1 ; ff ;
+; Mid Wire Use - Fit Attempt 1 ; 0 ;
+; Mid Slack - Fit Attempt 1 ; 2147483639 ;
+; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
+; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
+; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
+; Auto Fit Point 5 - Fit Attempt 1 ; ff ;
+; Mid Wire Use - Fit Attempt 1 ; 0 ;
+; Mid Slack - Fit Attempt 1 ; 2147483639 ;
+; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
+; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
+; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
+; Late Wire Use - Fit Attempt 1 ; 0 ;
+; Late Slack - Fit Attempt 1 ; 2147483639 ;
+; Peak Regional Wire - Fit Attempt 1 ; 0.000 ;
+; Auto Fit Point 7 - Fit Attempt 1 ; ff ;
+; Time - Fit Attempt 1 ; 0 ;
++------------------------------------+------------+
+
+
++--------------------------------------------------+
+; Advanced Data - Routing ;
++------------------------------------+-------------+
+; Name ; Value ;
++------------------------------------+-------------+
+; Early Slack - Fit Attempt 1 ; 2147483639 ;
+; Early Wire Use - Fit Attempt 1 ; 0 ;
+; Peak Regional Wire - Fit Attempt 1 ; 0 ;
+; Mid Slack - Fit Attempt 1 ; 2147483639 ;
+; Late Slack - Fit Attempt 1 ; -2147483648 ;
+; Late Wire Use - Fit Attempt 1 ; 0 ;
+; Time - Fit Attempt 1 ; 0 ;
++------------------------------------+-------------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info: *******************************************************************
+Info: Running Quartus II Fitter
+ Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+ Info: Processing started: Sat Mar 05 20:41:33 2022
+Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off data_selector -c data_selector
+Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info: Selected device EP2C8Q208C8 for design "data_selector"
+Info: Low junction temperature is 0 degrees C
+Info: High junction temperature is 85 degrees C
+Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+ Info: Device EP2C5Q208C8 is compatible
+ Info: Device EP2C5Q208I8 is compatible
+ Info: Device EP2C8Q208I8 is compatible
+Info: Fitter converted 3 user pins into dedicated programming pins
+ Info: Pin ~ASDO~ is reserved at location 1
+ Info: Pin ~nCSO~ is reserved at location 2
+ Info: Pin ~LVDS54p/nCEO~ is reserved at location 108
+Warning: No exact pin location assignment(s) for 26 pins of 26 total pins
+ Info: Pin Y0 not assigned to an exact location on the device
+ Info: Pin Y1 not assigned to an exact location on the device
+ Info: Pin Y2 not assigned to an exact location on the device
+ Info: Pin Y3 not assigned to an exact location on the device
+ Info: Pin Y4 not assigned to an exact location on the device
+ Info: Pin Y5 not assigned to an exact location on the device
+ Info: Pin Y6 not assigned to an exact location on the device
+ Info: Pin Y7 not assigned to an exact location on the device
+ Info: Pin b0 not assigned to an exact location on the device
+ Info: Pin a0 not assigned to an exact location on the device
+ Info: Pin AY not assigned to an exact location on the device
+ Info: Pin BY not assigned to an exact location on the device
+ Info: Pin a1 not assigned to an exact location on the device
+ Info: Pin b1 not assigned to an exact location on the device
+ Info: Pin a2 not assigned to an exact location on the device
+ Info: Pin b2 not assigned to an exact location on the device
+ Info: Pin a3 not assigned to an exact location on the device
+ Info: Pin b3 not assigned to an exact location on the device
+ Info: Pin a4 not assigned to an exact location on the device
+ Info: Pin b4 not assigned to an exact location on the device
+ Info: Pin a5 not assigned to an exact location on the device
+ Info: Pin b5 not assigned to an exact location on the device
+ Info: Pin a6 not assigned to an exact location on the device
+ Info: Pin b6 not assigned to an exact location on the device
+ Info: Pin a7 not assigned to an exact location on the device
+ Info: Pin b7 not assigned to an exact location on the device
+Info: Fitter is using the Classic Timing Analyzer
+Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
+Info: Starting register packing
+Info: Finished register packing
+ Extra Info: No registers were packed into other blocks
+Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+ Info: Number of I/O pins in group: 26 (unused VREF, 3.3V VCCIO, 18 input, 8 output, 0 bidirectional)
+ Info: I/O standards used: 3.3-V LVTTL.
+Info: I/O bank details before I/O pin placement
+ Info: Statistics of I/O banks
+ Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available
+ Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available
+ Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available
+ Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available
+Info: Fitter preparation operations ending: elapsed time is 00:00:01
+Info: Fitter placement preparation operations beginning
+Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info: Fitter placement operations beginning
+Info: Fitter placement was successful
+Info: Fitter placement operations ending: elapsed time is 00:00:00
+Info: Fitter routing operations beginning
+Info: Average interconnect usage is 0% of the available device resources
+ Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9
+Info: Fitter routing operations ending: elapsed time is 00:00:00
+Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
+ Info: Optimizations that may affect the design's routability were skipped
+ Info: Optimizations that may affect the design's timing were skipped
+Info: Started post-fitting delay annotation
+Warning: Found 8 output pins without output pin load capacitance assignment
+ Info: Pin "Y0" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "Y1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "Y2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "Y3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "Y4" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "Y5" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "Y6" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "Y7" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+Info: Delay annotation completed successfully
+Info: Generated suppressed messages file D:/projects/quartus/data_selector/data_selector.fit.smsg
+Info: Quartus II Fitter was successful. 0 errors, 2 warnings
+ Info: Peak virtual memory: 306 megabytes
+ Info: Processing ended: Sat Mar 05 20:41:34 2022
+ Info: Elapsed time: 00:00:01
+ Info: Total CPU time (on all processors): 00:00:01
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in D:/projects/quartus/data_selector/data_selector.fit.smsg.
+
+
diff --git a/data_selector/data_selector.fit.smsg b/data_selector/data_selector.fit.smsg
new file mode 100644
index 0000000..14764e7
--- /dev/null
+++ b/data_selector/data_selector.fit.smsg
@@ -0,0 +1,6 @@
+Extra Info: Performing register packing on registers with non-logic cell location assignments
+Extra Info: Completed register packing on registers with non-logic cell location assignments
+Extra Info: Started Fast Input/Output/OE register processing
+Extra Info: Finished Fast Input/Output/OE register processing
+Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/data_selector/data_selector.fit.summary b/data_selector/data_selector.fit.summary
new file mode 100644
index 0000000..38c08c6
--- /dev/null
+++ b/data_selector/data_selector.fit.summary
@@ -0,0 +1,16 @@
+Fitter Status : Successful - Sat Mar 05 20:41:34 2022
+Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
+Revision Name : data_selector
+Top-level Entity Name : data_selector
+Family : Cyclone II
+Device : EP2C8Q208C8
+Timing Models : Final
+Total logic elements : 8 / 8,256 ( < 1 % )
+ Total combinational functions : 8 / 8,256 ( < 1 % )
+ Dedicated logic registers : 0 / 8,256 ( 0 % )
+Total registers : 0
+Total pins : 26 / 138 ( 19 % )
+Total virtual pins : 0
+Total memory bits : 0 / 165,888 ( 0 % )
+Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % )
+Total PLLs : 0 / 2 ( 0 % )
diff --git a/data_selector/data_selector.flow.rpt b/data_selector/data_selector.flow.rpt
new file mode 100644
index 0000000..174039c
--- /dev/null
+++ b/data_selector/data_selector.flow.rpt
@@ -0,0 +1,120 @@
+Flow report for data_selector
+Sat Mar 05 20:41:36 2022
+Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Flow Summary
+ 3. Flow Settings
+ 4. Flow Non-Default Global Settings
+ 5. Flow Elapsed Time
+ 6. Flow OS Summary
+ 7. Flow Log
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Flow Summary ;
++------------------------------------+----------------------------------------------+
+; Flow Status ; Successful - Sat Mar 05 20:41:36 2022 ;
+; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
+; Revision Name ; data_selector ;
+; Top-level Entity Name ; data_selector ;
+; Family ; Cyclone II ;
+; Device ; EP2C8Q208C8 ;
+; Timing Models ; Final ;
+; Met timing requirements ; Yes ;
+; Total logic elements ; 8 / 8,256 ( < 1 % ) ;
+; Total combinational functions ; 8 / 8,256 ( < 1 % ) ;
+; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ;
+; Total registers ; 0 ;
+; Total pins ; 26 / 138 ( 19 % ) ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 0 / 165,888 ( 0 % ) ;
+; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
+; Total PLLs ; 0 / 2 ( 0 % ) ;
++------------------------------------+----------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings ;
++-------------------+---------------------+
+; Option ; Setting ;
++-------------------+---------------------+
+; Start date & time ; 03/05/2022 20:41:32 ;
+; Main task ; Compilation ;
+; Revision Name ; data_selector ;
++-------------------+---------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings ;
++------------------------------------+---------------------------------+---------------+-------------+----------------+
+; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
++------------------------------------+---------------------------------+---------------+-------------+----------------+
+; COMPILER_SIGNATURE_ID ; 220283517943889.164648409201276 ; -- ; -- ; -- ;
+; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
+; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
+; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
+; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
+; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
++------------------------------------+---------------------------------+---------------+-------------+----------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time ;
++-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 245 MB ; 00:00:00 ;
+; Fitter ; 00:00:01 ; 1.0 ; 306 MB ; 00:00:01 ;
+; Assembler ; 00:00:01 ; 1.0 ; 241 MB ; 00:00:00 ;
+; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 198 MB ; 00:00:00 ;
+; Total ; 00:00:02 ; -- ; -- ; 00:00:01 ;
++-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++------------------------------------------------------------------------------------------+
+; Flow OS Summary ;
++-------------------------+------------------+---------------+------------+----------------+
+; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
++-------------------------+------------------+---------------+------------+----------------+
+; Analysis & Synthesis ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
+; Fitter ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
+; Assembler ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
+; Classic Timing Analyzer ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
++-------------------------+------------------+---------------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off data_selector -c data_selector
+quartus_fit --read_settings_files=off --write_settings_files=off data_selector -c data_selector
+quartus_asm --read_settings_files=off --write_settings_files=off data_selector -c data_selector
+quartus_tan --read_settings_files=off --write_settings_files=off data_selector -c data_selector --timing_analysis_only
+
+
+
diff --git a/data_selector/data_selector.map.rpt b/data_selector/data_selector.map.rpt
new file mode 100644
index 0000000..d8583a4
--- /dev/null
+++ b/data_selector/data_selector.map.rpt
@@ -0,0 +1,218 @@
+Analysis & Synthesis report for data_selector
+Sat Mar 05 20:41:32 2022
+Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Analysis & Synthesis Summary
+ 3. Analysis & Synthesis Settings
+ 4. Analysis & Synthesis Source Files Read
+ 5. Analysis & Synthesis Resource Usage Summary
+ 6. Analysis & Synthesis Resource Utilization by Entity
+ 7. General Register Statistics
+ 8. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary ;
++------------------------------------+----------------------------------------------+
+; Analysis & Synthesis Status ; Successful - Sat Mar 05 20:41:32 2022 ;
+; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
+; Revision Name ; data_selector ;
+; Top-level Entity Name ; data_selector ;
+; Family ; Cyclone II ;
+; Total logic elements ; 8 ;
+; Total combinational functions ; 8 ;
+; Dedicated logic registers ; 0 ;
+; Total registers ; 0 ;
+; Total pins ; 26 ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 0 ;
+; Embedded Multiplier 9-bit elements ; 0 ;
+; Total PLLs ; 0 ;
++------------------------------------+----------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings ;
++--------------------------------------------------------------+--------------------+--------------------+
+; Option ; Setting ; Default Value ;
++--------------------------------------------------------------+--------------------+--------------------+
+; Device ; EP2C8Q208C8 ; ;
+; Top-level entity name ; data_selector ; data_selector ;
+; Family name ; Cyclone II ; Stratix II ;
+; Use Generated Physical Constraints File ; Off ; ;
+; Use smart compilation ; Off ; Off ;
+; Restructure Multiplexers ; Auto ; Auto ;
+; Create Debugging Nodes for IP Cores ; Off ; Off ;
+; Preserve fewer node names ; On ; On ;
+; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
+; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
+; VHDL Version ; VHDL93 ; VHDL93 ;
+; State Machine Processing ; Auto ; Auto ;
+; Safe State Machine ; Off ; Off ;
+; Extract Verilog State Machines ; On ; On ;
+; Extract VHDL State Machines ; On ; On ;
+; Ignore Verilog initial constructs ; Off ; Off ;
+; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
+; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
+; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
+; Parallel Synthesis ; Off ; Off ;
+; DSP Block Balancing ; Auto ; Auto ;
+; NOT Gate Push-Back ; On ; On ;
+; Power-Up Don't Care ; On ; On ;
+; Remove Redundant Logic Cells ; Off ; Off ;
+; Remove Duplicate Registers ; On ; On ;
+; Ignore CARRY Buffers ; Off ; Off ;
+; Ignore CASCADE Buffers ; Off ; Off ;
+; Ignore GLOBAL Buffers ; Off ; Off ;
+; Ignore ROW GLOBAL Buffers ; Off ; Off ;
+; Ignore LCELL Buffers ; Off ; Off ;
+; Ignore SOFT Buffers ; On ; On ;
+; Limit AHDL Integers to 32 Bits ; Off ; Off ;
+; Optimization Technique ; Balanced ; Balanced ;
+; Carry Chain Length ; 70 ; 70 ;
+; Auto Carry Chains ; On ; On ;
+; Auto Open-Drain Pins ; On ; On ;
+; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
+; Auto ROM Replacement ; On ; On ;
+; Auto RAM Replacement ; On ; On ;
+; Auto Shift Register Replacement ; Auto ; Auto ;
+; Auto Clock Enable Replacement ; On ; On ;
+; Strict RAM Replacement ; Off ; Off ;
+; Allow Synchronous Control Signals ; On ; On ;
+; Force Use of Synchronous Clear Signals ; Off ; Off ;
+; Auto RAM to Logic Cell Conversion ; Off ; Off ;
+; Auto Resource Sharing ; Off ; Off ;
+; Allow Any RAM Size For Recognition ; Off ; Off ;
+; Allow Any ROM Size For Recognition ; Off ; Off ;
+; Allow Any Shift Register Size For Recognition ; Off ; Off ;
+; Use LogicLock Constraints during Resource Balancing ; On ; On ;
+; Ignore translate_off and synthesis_off directives ; Off ; Off ;
+; Timing-Driven Synthesis ; Off ; Off ;
+; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
+; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
+; Synchronization Register Chain Length ; 2 ; 2 ;
+; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
+; HDL message level ; Level2 ; Level2 ;
+; Suppress Register Optimization Related Messages ; Off ; Off ;
+; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Clock MUX Protection ; On ; On ;
+; Auto Gated Clock Conversion ; Off ; Off ;
+; Block Design Naming ; Auto ; Auto ;
+; SDC constraint protection ; Off ; Off ;
+; Synthesis Effort ; Auto ; Auto ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
+; Analysis & Synthesis Message Level ; Medium ; Medium ;
++--------------------------------------------------------------+--------------------+--------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------+
+; data_selector.bdf ; yes ; User Block Diagram/Schematic File ; D:/projects/quartus/data_selector/data_selector.bdf ;
++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------+
+
+
++-----------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary ;
++---------------------------------------------+-------+
+; Resource ; Usage ;
++---------------------------------------------+-------+
+; Estimated Total logic elements ; 8 ;
+; ; ;
+; Total combinational functions ; 8 ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 8 ;
+; -- 3 input functions ; 0 ;
+; -- <=2 input functions ; 0 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 8 ;
+; -- arithmetic mode ; 0 ;
+; ; ;
+; Total registers ; 0 ;
+; -- Dedicated logic registers ; 0 ;
+; -- I/O registers ; 0 ;
+; ; ;
+; I/O pins ; 26 ;
+; Maximum fan-out node ; AY ;
+; Maximum fan-out ; 8 ;
+; Total fan-out ; 40 ;
+; Average fan-out ; 1.18 ;
++---------------------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
+; |data_selector ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 26 ; 0 ; |data_selector ; work ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics ;
++----------------------------------------------+-------+
+; Statistic ; Value ;
++----------------------------------------------+-------+
+; Total registers ; 0 ;
+; Number of registers using Synchronous Clear ; 0 ;
+; Number of registers using Synchronous Load ; 0 ;
+; Number of registers using Asynchronous Clear ; 0 ;
+; Number of registers using Asynchronous Load ; 0 ;
+; Number of registers using Clock Enable ; 0 ;
+; Number of registers using Preset ; 0 ;
++----------------------------------------------+-------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II Analysis & Synthesis
+ Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+ Info: Processing started: Sat Mar 05 20:41:32 2022
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off data_selector -c data_selector
+Info: Found 1 design units, including 1 entities, in source file data_selector.bdf
+ Info: Found entity 1: data_selector
+Info: Elaborating entity "data_selector" for the top level hierarchy
+Info: Implemented 34 device resources after synthesis - the final resource count might be different
+ Info: Implemented 18 input pins
+ Info: Implemented 8 output pins
+ Info: Implemented 8 logic cells
+Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
+ Info: Peak virtual memory: 248 megabytes
+ Info: Processing ended: Sat Mar 05 20:41:32 2022
+ Info: Elapsed time: 00:00:00
+ Info: Total CPU time (on all processors): 00:00:00
+
+
diff --git a/data_selector/data_selector.map.summary b/data_selector/data_selector.map.summary
new file mode 100644
index 0000000..d0a286d
--- /dev/null
+++ b/data_selector/data_selector.map.summary
@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Sat Mar 05 20:41:32 2022
+Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
+Revision Name : data_selector
+Top-level Entity Name : data_selector
+Family : Cyclone II
+Total logic elements : 8
+ Total combinational functions : 8
+ Dedicated logic registers : 0
+Total registers : 0
+Total pins : 26
+Total virtual pins : 0
+Total memory bits : 0
+Embedded Multiplier 9-bit elements : 0
+Total PLLs : 0
diff --git a/data_selector/data_selector.pin b/data_selector/data_selector.pin
new file mode 100644
index 0000000..a5a89bd
--- /dev/null
+++ b/data_selector/data_selector.pin
@@ -0,0 +1,278 @@
+ -- Copyright (C) 1991-2009 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions
+ -- and other software and tools, and its AMPP partner logic
+ -- functions, and any output files from any of the foregoing
+ -- (including device programming or simulation files), and any
+ -- associated documentation or information are expressly subject
+ -- to the terms and conditions of the Altera Program License
+ -- Subscription Agreement, Altera MegaCore Function License
+ -- Agreement, or other applicable license agreement, including,
+ -- without limitation, that your use is for the sole purpose of
+ -- programming logic devices manufactured by Altera and sold by
+ -- Altera or its authorized distributors. Please refer to the
+ -- applicable agreement for further details.
+ --
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC : No Connect. This pin has no internal connection to the device.
+ -- DNU : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
+ -- VCCIO : Dedicated power pin, which MUST be connected to VCC
+ -- of its bank.
+ -- Bank 1: 3.3V
+ -- Bank 2: 3.3V
+ -- Bank 3: 3.3V
+ -- Bank 4: 3.3V
+ -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ -- It can also be used to report unused dedicated pins. The connection
+ -- on the board for unused dedicated pins depends on whether this will
+ -- be used in a future design. One example is device migration. When
+ -- using device migration, refer to the device pin-tables. If it is a
+ -- GND pin in the pin table or if it will not be used in a future design
+ -- for another purpose the it MUST be connected to GND. If it is an unused
+ -- dedicated pin, then it can be connected to a valid signal on the board
+ -- (low, high, or toggling) if that signal is required for a different
+ -- revision of the design.
+ -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
+ -- This pin should be connected to GND. It may also be connected to a
+ -- valid signal on the board (low, high, or toggling) if that signal
+ -- is required for a different revision of the design.
+ -- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17),
+ -- connect each pin marked GND* either individually through a 10k Ohm resistor
+ -- to GND or tie all pins together and connect through a single 10k Ohm resistor
+ -- to GND.
+ -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND
+ -- or leave it unconnected.
+ -- RESERVED : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+CHIP "data_selector" ASSIGNED TO AN: EP2C8Q208C8
+
+Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
+-------------------------------------------------------------------------------------------------------------
+~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVTTL : : 1 : N
+~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVTTL : : 1 : N
+a7 : 3 : input : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 4 : : : : 1 :
+RESERVED_INPUT : 5 : : : : 1 :
+RESERVED_INPUT : 6 : : : : 1 :
+VCCIO1 : 7 : power : : 3.3V : 1 :
+RESERVED_INPUT : 8 : : : : 1 :
+GND : 9 : gnd : : : :
+Y4 : 10 : output : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 11 : : : : 1 :
+a4 : 12 : input : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 13 : : : : 1 :
+Y2 : 14 : output : 3.3-V LVTTL : : 1 : N
+Y3 : 15 : output : 3.3-V LVTTL : : 1 : N
+TDO : 16 : output : : : 1 :
+TMS : 17 : input : : : 1 :
+TCK : 18 : input : : : 1 :
+TDI : 19 : input : : : 1 :
+DATA0 : 20 : input : : : 1 :
+DCLK : 21 : : : : 1 :
+nCE : 22 : : : : 1 :
+b1 : 23 : input : 3.3-V LVTTL : : 1 : N
+a2 : 24 : input : 3.3-V LVTTL : : 1 : N
+GND : 25 : gnd : : : :
+nCONFIG : 26 : : : : 1 :
+b2 : 27 : input : 3.3-V LVTTL : : 1 : N
+a3 : 28 : input : 3.3-V LVTTL : : 1 : N
+VCCIO1 : 29 : power : : 3.3V : 1 :
+Y6 : 30 : output : 3.3-V LVTTL : : 1 : N
+a5 : 31 : input : 3.3-V LVTTL : : 1 : N
+VCCINT : 32 : power : : 1.2V : :
+b7 : 33 : input : 3.3-V LVTTL : : 1 : N
+a6 : 34 : input : 3.3-V LVTTL : : 1 : N
+Y1 : 35 : output : 3.3-V LVTTL : : 1 : N
+GND : 36 : gnd : : : :
+a1 : 37 : input : 3.3-V LVTTL : : 1 : N
+GND : 38 : gnd : : : :
+a0 : 39 : input : 3.3-V LVTTL : : 1 : N
+b0 : 40 : input : 3.3-V LVTTL : : 1 : N
+b4 : 41 : input : 3.3-V LVTTL : : 1 : N
+VCCIO1 : 42 : power : : 3.3V : 1 :
+RESERVED_INPUT : 43 : : : : 1 :
+BY : 44 : input : 3.3-V LVTTL : : 1 : N
+b5 : 45 : input : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 46 : : : : 1 :
+RESERVED_INPUT : 47 : : : : 1 :
+Y7 : 48 : output : 3.3-V LVTTL : : 1 : N
+GND : 49 : gnd : : : :
+GND_PLL1 : 50 : gnd : : : :
+VCCD_PLL1 : 51 : power : : 1.2V : :
+GND_PLL1 : 52 : gnd : : : :
+VCCA_PLL1 : 53 : power : : 1.2V : :
+GNDA_PLL1 : 54 : gnd : : : :
+GND : 55 : gnd : : : :
+AY : 56 : input : 3.3-V LVTTL : : 4 : N
+b6 : 57 : input : 3.3-V LVTTL : : 4 : N
+Y0 : 58 : output : 3.3-V LVTTL : : 4 : N
+b3 : 59 : input : 3.3-V LVTTL : : 4 : N
+RESERVED_INPUT : 60 : : : : 4 :
+RESERVED_INPUT : 61 : : : : 4 :
+VCCIO4 : 62 : power : : 3.3V : 4 :
+RESERVED_INPUT : 63 : : : : 4 :
+RESERVED_INPUT : 64 : : : : 4 :
+GND : 65 : gnd : : : :
+VCCINT : 66 : power : : 1.2V : :
+RESERVED_INPUT : 67 : : : : 4 :
+RESERVED_INPUT : 68 : : : : 4 :
+RESERVED_INPUT : 69 : : : : 4 :
+RESERVED_INPUT : 70 : : : : 4 :
+VCCIO4 : 71 : power : : 3.3V : 4 :
+RESERVED_INPUT : 72 : : : : 4 :
+GND : 73 : gnd : : : :
+RESERVED_INPUT : 74 : : : : 4 :
+RESERVED_INPUT : 75 : : : : 4 :
+RESERVED_INPUT : 76 : : : : 4 :
+RESERVED_INPUT : 77 : : : : 4 :
+GND : 78 : gnd : : : :
+VCCINT : 79 : power : : 1.2V : :
+RESERVED_INPUT : 80 : : : : 4 :
+RESERVED_INPUT : 81 : : : : 4 :
+RESERVED_INPUT : 82 : : : : 4 :
+VCCIO4 : 83 : power : : 3.3V : 4 :
+RESERVED_INPUT : 84 : : : : 4 :
+GND : 85 : gnd : : : :
+RESERVED_INPUT : 86 : : : : 4 :
+RESERVED_INPUT : 87 : : : : 4 :
+RESERVED_INPUT : 88 : : : : 4 :
+RESERVED_INPUT : 89 : : : : 4 :
+RESERVED_INPUT : 90 : : : : 4 :
+VCCIO4 : 91 : power : : 3.3V : 4 :
+RESERVED_INPUT : 92 : : : : 4 :
+GND : 93 : gnd : : : :
+RESERVED_INPUT : 94 : : : : 4 :
+RESERVED_INPUT : 95 : : : : 4 :
+RESERVED_INPUT : 96 : : : : 4 :
+RESERVED_INPUT : 97 : : : : 4 :
+VCCIO4 : 98 : power : : 3.3V : 4 :
+RESERVED_INPUT : 99 : : : : 4 :
+GND : 100 : gnd : : : :
+RESERVED_INPUT : 101 : : : : 4 :
+RESERVED_INPUT : 102 : : : : 4 :
+RESERVED_INPUT : 103 : : : : 4 :
+RESERVED_INPUT : 104 : : : : 4 :
+RESERVED_INPUT : 105 : : : : 3 :
+RESERVED_INPUT : 106 : : : : 3 :
+RESERVED_INPUT : 107 : : : : 3 :
+~LVDS54p/nCEO~ : 108 : output : 3.3-V LVTTL : : 3 : N
+VCCIO3 : 109 : power : : 3.3V : 3 :
+RESERVED_INPUT : 110 : : : : 3 :
+GND : 111 : gnd : : : :
+RESERVED_INPUT : 112 : : : : 3 :
+RESERVED_INPUT : 113 : : : : 3 :
+RESERVED_INPUT : 114 : : : : 3 :
+RESERVED_INPUT : 115 : : : : 3 :
+RESERVED_INPUT : 116 : : : : 3 :
+RESERVED_INPUT : 117 : : : : 3 :
+RESERVED_INPUT : 118 : : : : 3 :
+GND : 119 : gnd : : : :
+VCCINT : 120 : power : : 1.2V : :
+nSTATUS : 121 : : : : 3 :
+VCCIO3 : 122 : power : : 3.3V : 3 :
+CONF_DONE : 123 : : : : 3 :
+GND : 124 : gnd : : : :
+MSEL1 : 125 : : : : 3 :
+MSEL0 : 126 : : : : 3 :
+RESERVED_INPUT : 127 : : : : 3 :
+RESERVED_INPUT : 128 : : : : 3 :
+GND+ : 129 : : : : 3 :
+GND+ : 130 : : : : 3 :
+GND+ : 131 : : : : 3 :
+GND+ : 132 : : : : 3 :
+RESERVED_INPUT : 133 : : : : 3 :
+RESERVED_INPUT : 134 : : : : 3 :
+RESERVED_INPUT : 135 : : : : 3 :
+VCCIO3 : 136 : power : : 3.3V : 3 :
+RESERVED_INPUT : 137 : : : : 3 :
+RESERVED_INPUT : 138 : : : : 3 :
+RESERVED_INPUT : 139 : : : : 3 :
+GND : 140 : gnd : : : :
+RESERVED_INPUT : 141 : : : : 3 :
+RESERVED_INPUT : 142 : : : : 3 :
+RESERVED_INPUT : 143 : : : : 3 :
+RESERVED_INPUT : 144 : : : : 3 :
+RESERVED_INPUT : 145 : : : : 3 :
+RESERVED_INPUT : 146 : : : : 3 :
+RESERVED_INPUT : 147 : : : : 3 :
+VCCIO3 : 148 : power : : 3.3V : 3 :
+RESERVED_INPUT : 149 : : : : 3 :
+RESERVED_INPUT : 150 : : : : 3 :
+RESERVED_INPUT : 151 : : : : 3 :
+RESERVED_INPUT : 152 : : : : 3 :
+GND : 153 : gnd : : : :
+GND_PLL2 : 154 : gnd : : : :
+VCCD_PLL2 : 155 : power : : 1.2V : :
+GND_PLL2 : 156 : gnd : : : :
+VCCA_PLL2 : 157 : power : : 1.2V : :
+GNDA_PLL2 : 158 : gnd : : : :
+GND : 159 : gnd : : : :
+RESERVED_INPUT : 160 : : : : 2 :
+RESERVED_INPUT : 161 : : : : 2 :
+RESERVED_INPUT : 162 : : : : 2 :
+RESERVED_INPUT : 163 : : : : 2 :
+RESERVED_INPUT : 164 : : : : 2 :
+RESERVED_INPUT : 165 : : : : 2 :
+VCCIO2 : 166 : power : : 3.3V : 2 :
+GND : 167 : gnd : : : :
+RESERVED_INPUT : 168 : : : : 2 :
+RESERVED_INPUT : 169 : : : : 2 :
+RESERVED_INPUT : 170 : : : : 2 :
+RESERVED_INPUT : 171 : : : : 2 :
+VCCIO2 : 172 : power : : 3.3V : 2 :
+RESERVED_INPUT : 173 : : : : 2 :
+GND : 174 : gnd : : : :
+RESERVED_INPUT : 175 : : : : 2 :
+RESERVED_INPUT : 176 : : : : 2 :
+GND : 177 : gnd : : : :
+VCCINT : 178 : power : : 1.2V : :
+RESERVED_INPUT : 179 : : : : 2 :
+RESERVED_INPUT : 180 : : : : 2 :
+RESERVED_INPUT : 181 : : : : 2 :
+RESERVED_INPUT : 182 : : : : 2 :
+VCCIO2 : 183 : power : : 3.3V : 2 :
+GND : 184 : gnd : : : :
+RESERVED_INPUT : 185 : : : : 2 :
+GND : 186 : gnd : : : :
+RESERVED_INPUT : 187 : : : : 2 :
+RESERVED_INPUT : 188 : : : : 2 :
+RESERVED_INPUT : 189 : : : : 2 :
+VCCINT : 190 : power : : 1.2V : :
+RESERVED_INPUT : 191 : : : : 2 :
+RESERVED_INPUT : 192 : : : : 2 :
+RESERVED_INPUT : 193 : : : : 2 :
+VCCIO2 : 194 : power : : 3.3V : 2 :
+RESERVED_INPUT : 195 : : : : 2 :
+GND : 196 : gnd : : : :
+RESERVED_INPUT : 197 : : : : 2 :
+RESERVED_INPUT : 198 : : : : 2 :
+RESERVED_INPUT : 199 : : : : 2 :
+RESERVED_INPUT : 200 : : : : 2 :
+RESERVED_INPUT : 201 : : : : 2 :
+VCCIO2 : 202 : power : : 3.3V : 2 :
+RESERVED_INPUT : 203 : : : : 2 :
+GND : 204 : gnd : : : :
+RESERVED_INPUT : 205 : : : : 2 :
+RESERVED_INPUT : 206 : : : : 2 :
+RESERVED_INPUT : 207 : : : : 2 :
+Y5 : 208 : output : 3.3-V LVTTL : : 2 : N
diff --git a/data_selector/data_selector.pof b/data_selector/data_selector.pof
new file mode 100644
index 0000000..044a1d0
Binary files /dev/null and b/data_selector/data_selector.pof differ
diff --git a/data_selector/data_selector.qpf b/data_selector/data_selector.qpf
new file mode 100644
index 0000000..32e9aef
--- /dev/null
+++ b/data_selector/data_selector.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+# Date created = 19:48:38 March 05, 2022
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "9.0"
+DATE = "19:48:38 March 05, 2022"
+
+# Revisions
+
+PROJECT_REVISION = "data_selector"
diff --git a/data_selector/data_selector.qsf b/data_selector/data_selector.qsf
new file mode 100644
index 0000000..acc75cb
--- /dev/null
+++ b/data_selector/data_selector.qsf
@@ -0,0 +1,56 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+# Date created = 19:48:38 March 05, 2022
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# data_selector_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone II"
+set_global_assignment -name DEVICE EP2C8Q208C8
+set_global_assignment -name TOP_LEVEL_ENTITY data_selector
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:48:38 MARCH 05, 2022"
+set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2"
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name BDF_FILE data_selector.bdf
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name MISC_FILE "D:/projects/quartus/data_selector/data_selector.dpf"
\ No newline at end of file
diff --git a/data_selector/data_selector.qws b/data_selector/data_selector.qws
new file mode 100644
index 0000000..fc216dc
--- /dev/null
+++ b/data_selector/data_selector.qws
@@ -0,0 +1,4 @@
+[ProjectWorkspace]
+ptn_Child1=Frames
+[ProjectWorkspace.Frames]
+ptn_Child1=ChildFrames
diff --git a/data_selector/data_selector.sof b/data_selector/data_selector.sof
new file mode 100644
index 0000000..4cb434c
Binary files /dev/null and b/data_selector/data_selector.sof differ
diff --git a/data_selector/data_selector.tan.rpt b/data_selector/data_selector.tan.rpt
new file mode 100644
index 0000000..43b0ebd
--- /dev/null
+++ b/data_selector/data_selector.tan.rpt
@@ -0,0 +1,157 @@
+Classic Timing Analyzer report for data_selector
+Sat Mar 05 20:41:36 2022
+Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Timing Analyzer Summary
+ 3. Timing Analyzer Settings
+ 4. Parallel Compilation
+ 5. tpd
+ 6. Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------------------------------------------+
+; Timing Analyzer Summary ;
++------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
+; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
++------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
+; Worst-case tpd ; N/A ; None ; 12.694 ns ; b5 ; Y5 ; -- ; -- ; 0 ;
+; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
++------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
+
+
++--------------------------------------------------------------------------------------------------------------------+
+; Timing Analyzer Settings ;
++---------------------------------------------------------------------+--------------------+------+----+-------------+
+; Option ; Setting ; From ; To ; Entity Name ;
++---------------------------------------------------------------------+--------------------+------+----+-------------+
+; Device Name ; EP2C8Q208C8 ; ; ; ;
+; Timing Models ; Final ; ; ; ;
+; Default hold multicycle ; Same as Multicycle ; ; ; ;
+; Cut paths between unrelated clock domains ; On ; ; ; ;
+; Cut off read during write signal paths ; On ; ; ; ;
+; Cut off feedback from I/O pins ; On ; ; ; ;
+; Report Combined Fast/Slow Timing ; Off ; ; ; ;
+; Ignore Clock Settings ; Off ; ; ; ;
+; Analyze latches as synchronous elements ; On ; ; ; ;
+; Enable Recovery/Removal analysis ; Off ; ; ; ;
+; Enable Clock Latency ; Off ; ; ; ;
+; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+; Minimum Core Junction Temperature ; 0 ; ; ; ;
+; Maximum Core Junction Temperature ; 85 ; ; ; ;
+; Number of source nodes to report per destination node ; 10 ; ; ; ;
+; Number of destination nodes to report ; 10 ; ; ; ;
+; Number of paths to report ; 200 ; ; ; ;
+; Report Minimum Timing Checks ; Off ; ; ; ;
+; Use Fast Timing Models ; Off ; ; ; ;
+; Report IO Paths Separately ; Off ; ; ; ;
+; Perform Multicorner Analysis ; On ; ; ; ;
+; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
+; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
+; Output I/O Timing Endpoint ; Near End ; ; ; ;
++---------------------------------------------------------------------+--------------------+------+----+-------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 4 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.00 ;
+; Maximum used ; 1 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; 1 processor ; 100.0% ;
+; 2-4 processors ; 0.0% ;
++----------------------------+-------------+
+
+
++---------------------------------------------------------+
+; tpd ;
++-------+-------------------+-----------------+------+----+
+; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
++-------+-------------------+-----------------+------+----+
+; N/A ; None ; 12.694 ns ; b5 ; Y5 ;
+; N/A ; None ; 12.565 ns ; BY ; Y7 ;
+; N/A ; None ; 12.553 ns ; BY ; Y0 ;
+; N/A ; None ; 12.543 ns ; a7 ; Y7 ;
+; N/A ; None ; 12.522 ns ; AY ; Y0 ;
+; N/A ; None ; 12.477 ns ; BY ; Y5 ;
+; N/A ; None ; 12.469 ns ; a4 ; Y4 ;
+; N/A ; None ; 12.451 ns ; AY ; Y5 ;
+; N/A ; None ; 12.396 ns ; b3 ; Y3 ;
+; N/A ; None ; 12.360 ns ; a0 ; Y0 ;
+; N/A ; None ; 12.298 ns ; b0 ; Y0 ;
+; N/A ; None ; 12.293 ns ; AY ; Y7 ;
+; N/A ; None ; 12.239 ns ; a5 ; Y5 ;
+; N/A ; None ; 12.214 ns ; b4 ; Y4 ;
+; N/A ; None ; 12.099 ns ; AY ; Y1 ;
+; N/A ; None ; 12.083 ns ; b7 ; Y7 ;
+; N/A ; None ; 12.036 ns ; BY ; Y2 ;
+; N/A ; None ; 12.035 ns ; BY ; Y4 ;
+; N/A ; None ; 12.030 ns ; BY ; Y3 ;
+; N/A ; None ; 12.014 ns ; AY ; Y4 ;
+; N/A ; None ; 12.010 ns ; AY ; Y2 ;
+; N/A ; None ; 11.998 ns ; AY ; Y3 ;
+; N/A ; None ; 11.941 ns ; b6 ; Y6 ;
+; N/A ; None ; 11.823 ns ; a1 ; Y1 ;
+; N/A ; None ; 11.701 ns ; BY ; Y1 ;
+; N/A ; None ; 11.697 ns ; BY ; Y6 ;
+; N/A ; None ; 11.670 ns ; AY ; Y6 ;
+; N/A ; None ; 11.480 ns ; a6 ; Y6 ;
+; N/A ; None ; 6.818 ns ; a3 ; Y3 ;
+; N/A ; None ; 6.817 ns ; b2 ; Y2 ;
+; N/A ; None ; 6.775 ns ; a2 ; Y2 ;
+; N/A ; None ; 6.079 ns ; b1 ; Y1 ;
++-------+-------------------+-----------------+------+----+
+
+
++--------------------------+
+; Timing Analyzer Messages ;
++--------------------------+
+Info: *******************************************************************
+Info: Running Quartus II Classic Timing Analyzer
+ Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+ Info: Processing started: Sat Mar 05 20:41:36 2022
+Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off data_selector -c data_selector --timing_analysis_only
+Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info: Longest tpd from source pin "b5" to destination pin "Y5" is 12.694 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_45; Fanout = 1; PIN Node = 'b5'
+ Info: 2: + IC(6.147 ns) + CELL(0.624 ns) = 7.766 ns; Loc. = LCCOMB_X1_Y9_N26; Fanout = 1; COMB Node = 'inst6'
+ Info: 3: + IC(1.642 ns) + CELL(3.286 ns) = 12.694 ns; Loc. = PIN_208; Fanout = 0; PIN Node = 'Y5'
+ Info: Total cell delay = 4.905 ns ( 38.64 % )
+ Info: Total interconnect delay = 7.789 ns ( 61.36 % )
+Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
+ Info: Peak virtual memory: 212 megabytes
+ Info: Processing ended: Sat Mar 05 20:41:36 2022
+ Info: Elapsed time: 00:00:00
+ Info: Total CPU time (on all processors): 00:00:00
+
+
diff --git a/data_selector/data_selector.tan.summary b/data_selector/data_selector.tan.summary
new file mode 100644
index 0000000..957d2f4
--- /dev/null
+++ b/data_selector/data_selector.tan.summary
@@ -0,0 +1,26 @@
+--------------------------------------------------------------------------------------
+Timing Analyzer Summary
+--------------------------------------------------------------------------------------
+
+Type : Worst-case tpd
+Slack : N/A
+Required Time : None
+Actual Time : 12.694 ns
+From : b5
+To : Y5
+From Clock : --
+To Clock : --
+Failed Paths : 0
+
+Type : Total number of failed paths
+Slack :
+Required Time :
+Actual Time :
+From :
+To :
+From Clock :
+To Clock :
+Failed Paths : 0
+
+--------------------------------------------------------------------------------------
+
diff --git a/data_selector/db/data_selector.(0).cnf.cdb b/data_selector/db/data_selector.(0).cnf.cdb
new file mode 100644
index 0000000..5ce4906
Binary files /dev/null and b/data_selector/db/data_selector.(0).cnf.cdb differ
diff --git a/data_selector/db/data_selector.(0).cnf.hdb b/data_selector/db/data_selector.(0).cnf.hdb
new file mode 100644
index 0000000..141b3cf
Binary files /dev/null and b/data_selector/db/data_selector.(0).cnf.hdb differ
diff --git a/data_selector/db/data_selector.asm.qmsg b/data_selector/db/data_selector.asm.qmsg
new file mode 100644
index 0000000..6a3f1f6
--- /dev/null
+++ b/data_selector/db/data_selector.asm.qmsg
@@ -0,0 +1,7 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sat Mar 05 20:41:35 2022 " "Info: Processing started: Sat Mar 05 20:41:35 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off data_selector -c data_selector " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off data_selector -c data_selector" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
+{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sat Mar 05 20:41:36 2022 " "Info: Processing ended: Sat Mar 05 20:41:36 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/data_selector/db/data_selector.asm_labs.ddb b/data_selector/db/data_selector.asm_labs.ddb
new file mode 100644
index 0000000..d733dcb
Binary files /dev/null and b/data_selector/db/data_selector.asm_labs.ddb differ
diff --git a/data_selector/db/data_selector.cbx.xml b/data_selector/db/data_selector.cbx.xml
new file mode 100644
index 0000000..042417b
--- /dev/null
+++ b/data_selector/db/data_selector.cbx.xml
@@ -0,0 +1,5 @@
+
+
+
+
+
diff --git a/data_selector/db/data_selector.cmp.bpm b/data_selector/db/data_selector.cmp.bpm
new file mode 100644
index 0000000..588123f
Binary files /dev/null and b/data_selector/db/data_selector.cmp.bpm differ
diff --git a/data_selector/db/data_selector.cmp.cdb b/data_selector/db/data_selector.cmp.cdb
new file mode 100644
index 0000000..a89e904
Binary files /dev/null and b/data_selector/db/data_selector.cmp.cdb differ
diff --git a/data_selector/db/data_selector.cmp.ecobp b/data_selector/db/data_selector.cmp.ecobp
new file mode 100644
index 0000000..e05efff
Binary files /dev/null and b/data_selector/db/data_selector.cmp.ecobp differ
diff --git a/data_selector/db/data_selector.cmp.hdb b/data_selector/db/data_selector.cmp.hdb
new file mode 100644
index 0000000..99199ba
Binary files /dev/null and b/data_selector/db/data_selector.cmp.hdb differ
diff --git a/data_selector/db/data_selector.cmp.kpt b/data_selector/db/data_selector.cmp.kpt
new file mode 100644
index 0000000..94e542d
--- /dev/null
+++ b/data_selector/db/data_selector.cmp.kpt
@@ -0,0 +1,10 @@
+
+
+
+
+
+
+
+
+
+
diff --git a/data_selector/db/data_selector.cmp.logdb b/data_selector/db/data_selector.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/data_selector/db/data_selector.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/data_selector/db/data_selector.cmp.rdb b/data_selector/db/data_selector.cmp.rdb
new file mode 100644
index 0000000..5b5c1b5
Binary files /dev/null and b/data_selector/db/data_selector.cmp.rdb differ
diff --git a/data_selector/db/data_selector.cmp.tdb b/data_selector/db/data_selector.cmp.tdb
new file mode 100644
index 0000000..c9c92e7
Binary files /dev/null and b/data_selector/db/data_selector.cmp.tdb differ
diff --git a/data_selector/db/data_selector.cmp0.ddb b/data_selector/db/data_selector.cmp0.ddb
new file mode 100644
index 0000000..04e5967
Binary files /dev/null and b/data_selector/db/data_selector.cmp0.ddb differ
diff --git a/data_selector/db/data_selector.cmp2.ddb b/data_selector/db/data_selector.cmp2.ddb
new file mode 100644
index 0000000..79a1b01
Binary files /dev/null and b/data_selector/db/data_selector.cmp2.ddb differ
diff --git a/data_selector/db/data_selector.cmp_merge.kpt b/data_selector/db/data_selector.cmp_merge.kpt
new file mode 100644
index 0000000..70cf43e
--- /dev/null
+++ b/data_selector/db/data_selector.cmp_merge.kpt
@@ -0,0 +1,10 @@
+
+
+
+
+
+
+
+
+
+
diff --git a/data_selector/db/data_selector.db_info b/data_selector/db/data_selector.db_info
new file mode 100644
index 0000000..7581217
--- /dev/null
+++ b/data_selector/db/data_selector.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+Version_Index = 167832322
+Creation_Time = Sat Mar 05 19:48:38 2022
diff --git a/data_selector/db/data_selector.eco.cdb b/data_selector/db/data_selector.eco.cdb
new file mode 100644
index 0000000..6612017
Binary files /dev/null and b/data_selector/db/data_selector.eco.cdb differ
diff --git a/data_selector/db/data_selector.fit.qmsg b/data_selector/db/data_selector.fit.qmsg
new file mode 100644
index 0000000..bc98ca5
--- /dev/null
+++ b/data_selector/db/data_selector.fit.qmsg
@@ -0,0 +1,38 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sat Mar 05 20:41:33 2022 " "Info: Processing started: Sat Mar 05 20:41:33 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off data_selector -c data_selector " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off data_selector -c data_selector" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "IMPP_MPP_USER_DEVICE" "data_selector EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"data_selector\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "26 26 " "Warning: No exact pin location assignment(s) for 26 pins of 26 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y0 " "Info: Pin Y0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y0 } } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { -136 928 1104 -120 "Y0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y1 " "Info: Pin Y1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y1 } } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { -80 928 1104 -64 "Y1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y2 " "Info: Pin Y2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y2 } } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { -24 928 1104 -8 "Y2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y3 " "Info: Pin Y3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y3 } } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 32 928 1104 48 "Y3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y4 " "Info: Pin Y4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y4 } } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 88 928 1104 104 "Y4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y5 " "Info: Pin Y5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y5 } } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 144 928 1104 160 "Y5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y6 " "Info: Pin Y6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y6 } } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 200 928 1104 216 "Y6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y7 " "Info: Pin Y7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y7 } } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 240 928 1104 256 "Y7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b0 " "Info: Pin b0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { b0 } } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 312 176 344 328 "b0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a0 " "Info: Pin a0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { a0 } } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 64 176 344 80 "a0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "AY " "Info: Pin AY not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { AY } } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 576 176 344 592 "AY" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AY } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "BY " "Info: Pin BY not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { BY } } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 600 176 344 616 "BY" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { BY } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a1 " "Info: Pin a1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { a1 } } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 88 176 344 104 "a1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b1 " "Info: Pin b1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { b1 } } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 336 176 344 352 "b1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a2 " "Info: Pin a2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { a2 } } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 112 176 344 128 "a2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b2 " "Info: Pin b2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { b2 } } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 360 176 344 376 "b2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a3 " "Info: Pin a3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { a3 } } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 136 176 344 152 "a3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b3 " "Info: Pin b3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { b3 } } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 384 176 344 400 "b3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a4 " "Info: Pin a4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { a4 } } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 160 176 344 176 "a4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b4 " "Info: Pin b4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { b4 } } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 408 176 344 424 "b4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a5 " "Info: Pin a5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { a5 } } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 184 176 344 200 "a5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b5 " "Info: Pin b5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { b5 } } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 432 176 344 448 "b5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a6 " "Info: Pin a6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { a6 } } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 208 176 344 224 "a6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b6 " "Info: Pin b6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { b6 } } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 456 176 344 472 "b6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a7 " "Info: Pin a7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { a7 } } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 232 176 344 248 "a7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b7 " "Info: Pin b7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { b7 } } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 480 176 344 496 "b7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
+{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
+{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "26 unused 3.3V 18 8 0 " "Info: Number of I/O pins in group: 26 (unused VREF, 3.3V VCCIO, 18 input, 8 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 2 30 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 35 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 34 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 36 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Info: Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X10_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
+{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y0 0 " "Info: Pin \"Y0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y1 0 " "Info: Pin \"Y1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y2 0 " "Info: Pin \"Y2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y3 0 " "Info: Pin \"Y3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y4 0 " "Info: Pin \"Y4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y5 0 " "Info: Pin \"Y5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y6 0 " "Info: Pin \"Y6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y7 0 " "Info: Pin \"Y7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/data_selector/data_selector.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/data_selector/data_selector.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "306 " "Info: Peak virtual memory: 306 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sat Mar 05 20:41:34 2022 " "Info: Processing ended: Sat Mar 05 20:41:34 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/data_selector/db/data_selector.hier_info b/data_selector/db/data_selector.hier_info
new file mode 100644
index 0000000..fa4b6e8
--- /dev/null
+++ b/data_selector/db/data_selector.hier_info
@@ -0,0 +1,43 @@
+|data_selector
+Y0 <= inst1.DB_MAX_OUTPUT_PORT_TYPE
+b0 => inst25.IN0
+BY => inst25.IN1
+BY => inst26.IN1
+BY => inst27.IN1
+BY => inst28.IN1
+BY => inst29.IN1
+BY => inst30.IN1
+BY => inst31.IN1
+BY => inst32.IN1
+a0 => inst24.IN0
+AY => inst24.IN1
+AY => inst23.IN1
+AY => inst22.IN1
+AY => inst21.IN1
+AY => inst.IN1
+AY => inst18.IN1
+AY => inst19.IN1
+AY => inst20.IN1
+Y1 <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+b1 => inst26.IN0
+a1 => inst23.IN0
+Y2 <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+b2 => inst27.IN0
+a2 => inst22.IN0
+Y3 <= inst4.DB_MAX_OUTPUT_PORT_TYPE
+b3 => inst28.IN0
+a3 => inst21.IN0
+Y4 <= inst5.DB_MAX_OUTPUT_PORT_TYPE
+b4 => inst29.IN0
+a4 => inst.IN0
+Y5 <= inst6.DB_MAX_OUTPUT_PORT_TYPE
+b5 => inst30.IN0
+a5 => inst18.IN0
+Y6 <= inst7.DB_MAX_OUTPUT_PORT_TYPE
+b6 => inst31.IN0
+a6 => inst19.IN0
+Y7 <= inst8.DB_MAX_OUTPUT_PORT_TYPE
+b7 => inst32.IN0
+a7 => inst20.IN0
+
+
diff --git a/data_selector/db/data_selector.hif b/data_selector/db/data_selector.hif
new file mode 100644
index 0000000..00b7a08
--- /dev/null
+++ b/data_selector/db/data_selector.hif
@@ -0,0 +1,42 @@
+Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+11
+936
+OFF
+OFF
+OFF
+ON
+ON
+ON
+FV_OFF
+Level2
+0
+0
+VRSM_ON
+VHSM_ON
+0
+-- Start Library Paths --
+-- End Library Paths --
+-- Start VHDL Libraries --
+-- End VHDL Libraries --
+# entity
+data_selector
+# storage
+db|data_selector.(0).cnf
+db|data_selector.(0).cnf
+# case_insensitive
+# source_file
+data_selector.bdf
+c85a509528fd3f5e5f3854c4318833a1
+26
+# internal_option {
+BLOCK_DESIGN_NAMING
+AUTO
+}
+# hierarchies {
+|
+}
+# macro_sequence
+
+# end
+# complete
+
\ No newline at end of file
diff --git a/data_selector/db/data_selector.lpc.html b/data_selector/db/data_selector.lpc.html
new file mode 100644
index 0000000..fd4875d
--- /dev/null
+++ b/data_selector/db/data_selector.lpc.html
@@ -0,0 +1,18 @@
+
+
+| Hierarchy |
+Input |
+Constant Input |
+Unused Input |
+Floating Input |
+Output |
+Constant Output |
+Unused Output |
+Floating Output |
+Bidir |
+Constant Bidir |
+Unused Bidir |
+Input only Bidir |
+Output only Bidir |
+
+
diff --git a/data_selector/db/data_selector.lpc.rdb b/data_selector/db/data_selector.lpc.rdb
new file mode 100644
index 0000000..8bd163a
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diff --git a/data_selector/db/data_selector.lpc.txt b/data_selector/db/data_selector.lpc.txt
new file mode 100644
index 0000000..a463804
--- /dev/null
+++ b/data_selector/db/data_selector.lpc.txt
@@ -0,0 +1,5 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/data_selector/db/data_selector.map.bpm b/data_selector/db/data_selector.map.bpm
new file mode 100644
index 0000000..368ecc1
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diff --git a/data_selector/db/data_selector.map.cdb b/data_selector/db/data_selector.map.cdb
new file mode 100644
index 0000000..87abcc1
Binary files /dev/null and b/data_selector/db/data_selector.map.cdb differ
diff --git a/data_selector/db/data_selector.map.ecobp b/data_selector/db/data_selector.map.ecobp
new file mode 100644
index 0000000..e05efff
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diff --git a/data_selector/db/data_selector.map.hdb b/data_selector/db/data_selector.map.hdb
new file mode 100644
index 0000000..6ef49ce
Binary files /dev/null and b/data_selector/db/data_selector.map.hdb differ
diff --git a/data_selector/db/data_selector.map.kpt b/data_selector/db/data_selector.map.kpt
new file mode 100644
index 0000000..a58ed0f
--- /dev/null
+++ b/data_selector/db/data_selector.map.kpt
@@ -0,0 +1,10 @@
+
+
+
+
+
+
+
+
+
+
diff --git a/data_selector/db/data_selector.map.logdb b/data_selector/db/data_selector.map.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/data_selector/db/data_selector.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/data_selector/db/data_selector.map.qmsg b/data_selector/db/data_selector.map.qmsg
new file mode 100644
index 0000000..54510e9
--- /dev/null
+++ b/data_selector/db/data_selector.map.qmsg
@@ -0,0 +1,7 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sat Mar 05 20:41:32 2022 " "Info: Processing started: Sat Mar 05 20:41:32 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off data_selector -c data_selector " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off data_selector -c data_selector" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_selector.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file data_selector.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 data_selector " "Info: Found entity 1: data_selector" { } { { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_TOP" "data_selector " "Info: Elaborating entity \"data_selector\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "34 " "Info: Implemented 34 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "18 " "Info: Implemented 18 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "248 " "Info: Peak virtual memory: 248 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sat Mar 05 20:41:32 2022 " "Info: Processing ended: Sat Mar 05 20:41:32 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/data_selector/db/data_selector.map_bb.cdb b/data_selector/db/data_selector.map_bb.cdb
new file mode 100644
index 0000000..3fd5295
Binary files /dev/null and b/data_selector/db/data_selector.map_bb.cdb differ
diff --git a/data_selector/db/data_selector.map_bb.hdb b/data_selector/db/data_selector.map_bb.hdb
new file mode 100644
index 0000000..fd925ed
Binary files /dev/null and b/data_selector/db/data_selector.map_bb.hdb differ
diff --git a/data_selector/db/data_selector.map_bb.logdb b/data_selector/db/data_selector.map_bb.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/data_selector/db/data_selector.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/data_selector/db/data_selector.pre_map.cdb b/data_selector/db/data_selector.pre_map.cdb
new file mode 100644
index 0000000..70eb62f
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diff --git a/data_selector/db/data_selector.pre_map.hdb b/data_selector/db/data_selector.pre_map.hdb
new file mode 100644
index 0000000..fd44e2d
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diff --git a/data_selector/db/data_selector.rtlv.hdb b/data_selector/db/data_selector.rtlv.hdb
new file mode 100644
index 0000000..beb808b
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diff --git a/data_selector/db/data_selector.rtlv_sg.cdb b/data_selector/db/data_selector.rtlv_sg.cdb
new file mode 100644
index 0000000..7aaf4e1
Binary files /dev/null and b/data_selector/db/data_selector.rtlv_sg.cdb differ
diff --git a/data_selector/db/data_selector.rtlv_sg_swap.cdb b/data_selector/db/data_selector.rtlv_sg_swap.cdb
new file mode 100644
index 0000000..bccc94e
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diff --git a/data_selector/db/data_selector.sgdiff.cdb b/data_selector/db/data_selector.sgdiff.cdb
new file mode 100644
index 0000000..c811b4f
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diff --git a/data_selector/db/data_selector.sgdiff.hdb b/data_selector/db/data_selector.sgdiff.hdb
new file mode 100644
index 0000000..5cb1d03
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diff --git a/data_selector/db/data_selector.sld_design_entry.sci b/data_selector/db/data_selector.sld_design_entry.sci
new file mode 100644
index 0000000..904d003
Binary files /dev/null and b/data_selector/db/data_selector.sld_design_entry.sci differ
diff --git a/data_selector/db/data_selector.sld_design_entry_dsc.sci b/data_selector/db/data_selector.sld_design_entry_dsc.sci
new file mode 100644
index 0000000..2000bdc
Binary files /dev/null and b/data_selector/db/data_selector.sld_design_entry_dsc.sci differ
diff --git a/data_selector/db/data_selector.syn_hier_info b/data_selector/db/data_selector.syn_hier_info
new file mode 100644
index 0000000..e69de29
diff --git a/data_selector/db/data_selector.tan.qmsg b/data_selector/db/data_selector.tan.qmsg
new file mode 100644
index 0000000..0b0f867
--- /dev/null
+++ b/data_selector/db/data_selector.tan.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sat Mar 05 20:41:36 2022 " "Info: Processing started: Sat Mar 05 20:41:36 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off data_selector -c data_selector --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off data_selector -c data_selector --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TPD_RESULT" "b5 Y5 12.694 ns Longest " "Info: Longest tpd from source pin \"b5\" to destination pin \"Y5\" is 12.694 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns b5 1 PIN PIN_45 1 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_45; Fanout = 1; PIN Node = 'b5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b5 } "NODE_NAME" } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 432 176 344 448 "b5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.147 ns) + CELL(0.624 ns) 7.766 ns inst6 2 COMB LCCOMB_X1_Y9_N26 1 " "Info: 2: + IC(6.147 ns) + CELL(0.624 ns) = 7.766 ns; Loc. = LCCOMB_X1_Y9_N26; Fanout = 1; COMB Node = 'inst6'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.771 ns" { b5 inst6 } "NODE_NAME" } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 128 776 840 176 "inst6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.642 ns) + CELL(3.286 ns) 12.694 ns Y5 3 PIN PIN_208 0 " "Info: 3: + IC(1.642 ns) + CELL(3.286 ns) = 12.694 ns; Loc. = PIN_208; Fanout = 0; PIN Node = 'Y5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.928 ns" { inst6 Y5 } "NODE_NAME" } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 144 928 1104 160 "Y5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.905 ns ( 38.64 % ) " "Info: Total cell delay = 4.905 ns ( 38.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "7.789 ns ( 61.36 % ) " "Info: Total interconnect delay = 7.789 ns ( 61.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "12.694 ns" { b5 inst6 Y5 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "12.694 ns" { b5 {} b5~combout {} inst6 {} Y5 {} } { 0.000ns 0.000ns 6.147ns 1.642ns } { 0.000ns 0.995ns 0.624ns 3.286ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sat Mar 05 20:41:36 2022 " "Info: Processing ended: Sat Mar 05 20:41:36 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/data_selector/db/data_selector.tis_db_list.ddb b/data_selector/db/data_selector.tis_db_list.ddb
new file mode 100644
index 0000000..2a9a6ed
Binary files /dev/null and b/data_selector/db/data_selector.tis_db_list.ddb differ
diff --git a/data_selector/db/data_selector.tmw_info b/data_selector/db/data_selector.tmw_info
new file mode 100644
index 0000000..15a6255
--- /dev/null
+++ b/data_selector/db/data_selector.tmw_info
@@ -0,0 +1,6 @@
+start_full_compilation:s:00:00:05
+start_analysis_synthesis:s:00:00:01-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:02-start_full_compilation
+start_assembler:s:00:00:01-start_full_compilation
+start_timing_analyzer:s:00:00:01-start_full_compilation
diff --git a/data_selector/incremental_db/README b/data_selector/incremental_db/README
new file mode 100644
index 0000000..9f62dcd
--- /dev/null
+++ b/data_selector/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used. To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.atm b/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.atm
new file mode 100644
index 0000000..db35fd5
Binary files /dev/null and b/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.atm differ
diff --git a/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.dfp b/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.dfp
new file mode 100644
index 0000000..b1c67d6
Binary files /dev/null and b/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.dfp differ
diff --git a/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.hdbx b/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.hdbx
new file mode 100644
index 0000000..1b7ce26
Binary files /dev/null and b/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.hdbx differ
diff --git a/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.kpt b/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.kpt
new file mode 100644
index 0000000..c1e72d7
--- /dev/null
+++ b/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.kpt
@@ -0,0 +1,10 @@
+
+
+
+
+
+
+
+
+
+
diff --git a/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.logdb b/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.rcf b/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.rcf
new file mode 100644
index 0000000..6fc2c16
Binary files /dev/null and b/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.rcf differ
diff --git a/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.atm b/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.atm
new file mode 100644
index 0000000..43d374b
Binary files /dev/null and b/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.atm differ
diff --git a/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.dpi b/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.dpi
new file mode 100644
index 0000000..5f0168e
Binary files /dev/null and b/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.dpi differ
diff --git a/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.hdbx b/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.hdbx
new file mode 100644
index 0000000..96d47e5
Binary files /dev/null and b/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.hdbx differ
diff --git a/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.kpt b/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.kpt
new file mode 100644
index 0000000..1372c2e
--- /dev/null
+++ b/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.kpt
@@ -0,0 +1,10 @@
+
+
+
+
+
+
+
+
+
+