From a1e1b8764a45ded178f7c8bdb8fd8916c9aeff4f Mon Sep 17 00:00:00 2001
From: juzeon <812312770@qq.com>
Date: Sat, 5 Mar 2022 20:52:27 +0800
Subject: [PATCH] =?UTF-8?q?add=20data=5Fselector=20=E6=9C=AA=E8=AE=BE?=
=?UTF-8?q?=E5=AE=9A=20pins?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
---
data_selector/data_selector.asm.rpt | 129 ++
data_selector/data_selector.bdf | 1819 +++++++++++++++++
data_selector/data_selector.bsf | 211 ++
data_selector/data_selector.done | 1 +
data_selector/data_selector.dpf | 12 +
data_selector/data_selector.fit.rpt | 1006 +++++++++
data_selector/data_selector.fit.smsg | 6 +
data_selector/data_selector.fit.summary | 16 +
data_selector/data_selector.flow.rpt | 120 ++
data_selector/data_selector.map.rpt | 218 ++
data_selector/data_selector.map.summary | 14 +
data_selector/data_selector.pin | 278 +++
data_selector/data_selector.pof | Bin 0 -> 524488 bytes
data_selector/data_selector.qpf | 30 +
data_selector/data_selector.qsf | 56 +
data_selector/data_selector.qws | 4 +
data_selector/data_selector.sof | Bin 0 -> 240789 bytes
data_selector/data_selector.tan.rpt | 157 ++
data_selector/data_selector.tan.summary | 26 +
data_selector/db/data_selector.(0).cnf.cdb | Bin 0 -> 1310 bytes
data_selector/db/data_selector.(0).cnf.hdb | Bin 0 -> 1188 bytes
data_selector/db/data_selector.asm.qmsg | 7 +
data_selector/db/data_selector.asm_labs.ddb | Bin 0 -> 3616 bytes
data_selector/db/data_selector.cbx.xml | 5 +
data_selector/db/data_selector.cmp.bpm | Bin 0 -> 630 bytes
data_selector/db/data_selector.cmp.cdb | Bin 0 -> 3926 bytes
data_selector/db/data_selector.cmp.ecobp | Bin 0 -> 28 bytes
data_selector/db/data_selector.cmp.hdb | Bin 0 -> 7054 bytes
data_selector/db/data_selector.cmp.kpt | 10 +
data_selector/db/data_selector.cmp.logdb | 1 +
data_selector/db/data_selector.cmp.rdb | Bin 0 -> 15586 bytes
data_selector/db/data_selector.cmp.tdb | Bin 0 -> 3188 bytes
data_selector/db/data_selector.cmp0.ddb | Bin 0 -> 54621 bytes
data_selector/db/data_selector.cmp2.ddb | Bin 0 -> 41873 bytes
data_selector/db/data_selector.cmp_merge.kpt | 10 +
data_selector/db/data_selector.db_info | 3 +
data_selector/db/data_selector.eco.cdb | Bin 0 -> 175 bytes
data_selector/db/data_selector.fit.qmsg | 38 +
data_selector/db/data_selector.hier_info | 43 +
data_selector/db/data_selector.hif | 42 +
data_selector/db/data_selector.lpc.html | 18 +
data_selector/db/data_selector.lpc.rdb | Bin 0 -> 399 bytes
data_selector/db/data_selector.lpc.txt | 5 +
data_selector/db/data_selector.map.bpm | Bin 0 -> 618 bytes
data_selector/db/data_selector.map.cdb | Bin 0 -> 1387 bytes
data_selector/db/data_selector.map.ecobp | Bin 0 -> 28 bytes
data_selector/db/data_selector.map.hdb | Bin 0 -> 6730 bytes
data_selector/db/data_selector.map.kpt | 10 +
data_selector/db/data_selector.map.logdb | 1 +
data_selector/db/data_selector.map.qmsg | 7 +
data_selector/db/data_selector.map_bb.cdb | Bin 0 -> 726 bytes
data_selector/db/data_selector.map_bb.hdb | Bin 0 -> 6166 bytes
data_selector/db/data_selector.map_bb.logdb | 1 +
data_selector/db/data_selector.pre_map.cdb | Bin 0 -> 1430 bytes
data_selector/db/data_selector.pre_map.hdb | Bin 0 -> 7084 bytes
data_selector/db/data_selector.rtlv.hdb | Bin 0 -> 7082 bytes
data_selector/db/data_selector.rtlv_sg.cdb | Bin 0 -> 1349 bytes
.../db/data_selector.rtlv_sg_swap.cdb | Bin 0 -> 192 bytes
data_selector/db/data_selector.sgdiff.cdb | Bin 0 -> 1226 bytes
data_selector/db/data_selector.sgdiff.hdb | Bin 0 -> 7103 bytes
.../db/data_selector.sld_design_entry.sci | Bin 0 -> 168 bytes
.../db/data_selector.sld_design_entry_dsc.sci | Bin 0 -> 168 bytes
data_selector/db/data_selector.syn_hier_info | 0
data_selector/db/data_selector.tan.qmsg | 6 +
.../db/data_selector.tis_db_list.ddb | Bin 0 -> 188 bytes
data_selector/db/data_selector.tmw_info | 6 +
data_selector/incremental_db/README | 11 +
.../data_selector.root_partition.cmp.atm | Bin 0 -> 6863 bytes
.../data_selector.root_partition.cmp.dfp | Bin 0 -> 33 bytes
.../data_selector.root_partition.cmp.hdbx | Bin 0 -> 1864 bytes
.../data_selector.root_partition.cmp.kpt | 10 +
.../data_selector.root_partition.cmp.logdb | 1 +
.../data_selector.root_partition.cmp.rcf | Bin 0 -> 1018 bytes
.../data_selector.root_partition.map.atm | Bin 0 -> 4224 bytes
.../data_selector.root_partition.map.dpi | Bin 0 -> 747 bytes
.../data_selector.root_partition.map.hdbx | Bin 0 -> 1771 bytes
.../data_selector.root_partition.map.kpt | 10 +
77 files changed, 4348 insertions(+)
create mode 100644 data_selector/data_selector.asm.rpt
create mode 100644 data_selector/data_selector.bdf
create mode 100644 data_selector/data_selector.bsf
create mode 100644 data_selector/data_selector.done
create mode 100644 data_selector/data_selector.dpf
create mode 100644 data_selector/data_selector.fit.rpt
create mode 100644 data_selector/data_selector.fit.smsg
create mode 100644 data_selector/data_selector.fit.summary
create mode 100644 data_selector/data_selector.flow.rpt
create mode 100644 data_selector/data_selector.map.rpt
create mode 100644 data_selector/data_selector.map.summary
create mode 100644 data_selector/data_selector.pin
create mode 100644 data_selector/data_selector.pof
create mode 100644 data_selector/data_selector.qpf
create mode 100644 data_selector/data_selector.qsf
create mode 100644 data_selector/data_selector.qws
create mode 100644 data_selector/data_selector.sof
create mode 100644 data_selector/data_selector.tan.rpt
create mode 100644 data_selector/data_selector.tan.summary
create mode 100644 data_selector/db/data_selector.(0).cnf.cdb
create mode 100644 data_selector/db/data_selector.(0).cnf.hdb
create mode 100644 data_selector/db/data_selector.asm.qmsg
create mode 100644 data_selector/db/data_selector.asm_labs.ddb
create mode 100644 data_selector/db/data_selector.cbx.xml
create mode 100644 data_selector/db/data_selector.cmp.bpm
create mode 100644 data_selector/db/data_selector.cmp.cdb
create mode 100644 data_selector/db/data_selector.cmp.ecobp
create mode 100644 data_selector/db/data_selector.cmp.hdb
create mode 100644 data_selector/db/data_selector.cmp.kpt
create mode 100644 data_selector/db/data_selector.cmp.logdb
create mode 100644 data_selector/db/data_selector.cmp.rdb
create mode 100644 data_selector/db/data_selector.cmp.tdb
create mode 100644 data_selector/db/data_selector.cmp0.ddb
create mode 100644 data_selector/db/data_selector.cmp2.ddb
create mode 100644 data_selector/db/data_selector.cmp_merge.kpt
create mode 100644 data_selector/db/data_selector.db_info
create mode 100644 data_selector/db/data_selector.eco.cdb
create mode 100644 data_selector/db/data_selector.fit.qmsg
create mode 100644 data_selector/db/data_selector.hier_info
create mode 100644 data_selector/db/data_selector.hif
create mode 100644 data_selector/db/data_selector.lpc.html
create mode 100644 data_selector/db/data_selector.lpc.rdb
create mode 100644 data_selector/db/data_selector.lpc.txt
create mode 100644 data_selector/db/data_selector.map.bpm
create mode 100644 data_selector/db/data_selector.map.cdb
create mode 100644 data_selector/db/data_selector.map.ecobp
create mode 100644 data_selector/db/data_selector.map.hdb
create mode 100644 data_selector/db/data_selector.map.kpt
create mode 100644 data_selector/db/data_selector.map.logdb
create mode 100644 data_selector/db/data_selector.map.qmsg
create mode 100644 data_selector/db/data_selector.map_bb.cdb
create mode 100644 data_selector/db/data_selector.map_bb.hdb
create mode 100644 data_selector/db/data_selector.map_bb.logdb
create mode 100644 data_selector/db/data_selector.pre_map.cdb
create mode 100644 data_selector/db/data_selector.pre_map.hdb
create mode 100644 data_selector/db/data_selector.rtlv.hdb
create mode 100644 data_selector/db/data_selector.rtlv_sg.cdb
create mode 100644 data_selector/db/data_selector.rtlv_sg_swap.cdb
create mode 100644 data_selector/db/data_selector.sgdiff.cdb
create mode 100644 data_selector/db/data_selector.sgdiff.hdb
create mode 100644 data_selector/db/data_selector.sld_design_entry.sci
create mode 100644 data_selector/db/data_selector.sld_design_entry_dsc.sci
create mode 100644 data_selector/db/data_selector.syn_hier_info
create mode 100644 data_selector/db/data_selector.tan.qmsg
create mode 100644 data_selector/db/data_selector.tis_db_list.ddb
create mode 100644 data_selector/db/data_selector.tmw_info
create mode 100644 data_selector/incremental_db/README
create mode 100644 data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.atm
create mode 100644 data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.dfp
create mode 100644 data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.hdbx
create mode 100644 data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.kpt
create mode 100644 data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.logdb
create mode 100644 data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.rcf
create mode 100644 data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.atm
create mode 100644 data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.dpi
create mode 100644 data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.hdbx
create mode 100644 data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.kpt
diff --git a/data_selector/data_selector.asm.rpt b/data_selector/data_selector.asm.rpt
new file mode 100644
index 0000000..546d846
--- /dev/null
+++ b/data_selector/data_selector.asm.rpt
@@ -0,0 +1,129 @@
+Assembler report for data_selector
+Sat Mar 05 20:41:36 2022
+Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Assembler Summary
+ 3. Assembler Settings
+ 4. Assembler Generated Files
+ 5. Assembler Device Options: D:/projects/quartus/data_selector/data_selector.sof
+ 6. Assembler Device Options: D:/projects/quartus/data_selector/data_selector.pof
+ 7. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary ;
++-----------------------+---------------------------------------+
+; Assembler Status ; Successful - Sat Mar 05 20:41:36 2022 ;
+; Revision Name ; data_selector ;
+; Top-level Entity Name ; data_selector ;
+; Family ; Cyclone II ;
+; Device ; EP2C8Q208C8 ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option ; Setting ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation ; Off ; Off ;
+; Generate compressed bitstreams ; On ; On ;
+; Compression mode ; Off ; Off ;
+; Clock source for configuration device ; Internal ; Internal ;
+; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
+; Divide clock frequency by ; 1 ; 1 ;
+; Auto user code ; Off ; Off ;
+; Use configuration device ; On ; On ;
+; Configuration device ; Auto ; Auto ;
+; Configuration device auto user code ; Off ; Off ;
+; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
+; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
+; Hexadecimal Output File start address ; 0 ; 0 ;
+; Hexadecimal Output File count direction ; Up ; Up ;
+; Release clears before tri-states ; Off ; Off ;
+; Auto-restart configuration after error ; On ; On ;
+; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ;
+; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++-----------------------------------------------------+
+; Assembler Generated Files ;
++-----------------------------------------------------+
+; File Name ;
++-----------------------------------------------------+
+; D:/projects/quartus/data_selector/data_selector.sof ;
+; D:/projects/quartus/data_selector/data_selector.pof ;
++-----------------------------------------------------+
+
+
++-------------------------------------------------------------------------------+
+; Assembler Device Options: D:/projects/quartus/data_selector/data_selector.sof ;
++----------------+--------------------------------------------------------------+
+; Option ; Setting ;
++----------------+--------------------------------------------------------------+
+; Device ; EP2C8Q208C8 ;
+; JTAG usercode ; 0xFFFFFFFF ;
+; Checksum ; 0x000C1D58 ;
++----------------+--------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------+
+; Assembler Device Options: D:/projects/quartus/data_selector/data_selector.pof ;
++--------------------+----------------------------------------------------------+
+; Option ; Setting ;
++--------------------+----------------------------------------------------------+
+; Device ; EPCS4 ;
+; JTAG usercode ; 0x00000000 ;
+; Checksum ; 0x06EFE46F ;
+; Compression Ratio ; 3 ;
++--------------------+----------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II Assembler
+ Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+ Info: Processing started: Sat Mar 05 20:41:35 2022
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off data_selector -c data_selector
+Info: Writing out detailed assembly data for power analysis
+Info: Assembler is generating device programming files
+Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled
+Info: Quartus II Assembler was successful. 0 errors, 0 warnings
+ Info: Peak virtual memory: 241 megabytes
+ Info: Processing ended: Sat Mar 05 20:41:36 2022
+ Info: Elapsed time: 00:00:01
+ Info: Total CPU time (on all processors): 00:00:00
+
+
diff --git a/data_selector/data_selector.bdf b/data_selector/data_selector.bdf
new file mode 100644
index 0000000..93f0c83
--- /dev/null
+++ b/data_selector/data_selector.bdf
@@ -0,0 +1,1819 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+*/
+//#pragma file_not_in_maxplusii_format
+(header "graphic" (version "1.3"))
+(pin
+ (input)
+ (rect 176 64 344 80)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "a0" (rect 5 0 16 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 176 88 344 104)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "a1" (rect 5 0 16 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 176 112 344 128)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "a2" (rect 5 0 16 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 176 136 344 152)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "a3" (rect 5 0 16 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 176 160 344 176)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "a4" (rect 5 0 16 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 176 184 344 200)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "a5" (rect 5 0 16 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 176 208 344 224)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "a6" (rect 5 0 16 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 176 232 344 248)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "a7" (rect 5 0 16 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 176 312 344 328)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "b0" (rect 5 0 16 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 176 336 344 352)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "b1" (rect 5 0 16 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 176 360 344 376)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "b2" (rect 5 0 16 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 176 384 344 400)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "b3" (rect 5 0 16 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 176 408 344 424)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "b4" (rect 5 0 16 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 176 432 344 448)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "b5" (rect 5 0 16 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 176 456 344 472)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "b6" (rect 5 0 16 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 176 480 344 496)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "b7" (rect 5 0 16 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 176 576 344 592)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "AY" (rect 5 0 20 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 176 600 344 616)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "BY" (rect 5 0 20 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (output)
+ (rect 928 -136 1104 -120)
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+ (text "Y0" (rect 90 0 104 12)(font "Arial" ))
+ (pt 0 8)
+ (drawing
+ (line (pt 0 8)(pt 52 8)(line_width 1))
+ (line (pt 52 4)(pt 78 4)(line_width 1))
+ (line (pt 52 12)(pt 78 12)(line_width 1))
+ (line (pt 52 12)(pt 52 4)(line_width 1))
+ (line (pt 78 4)(pt 82 8)(line_width 1))
+ (line (pt 82 8)(pt 78 12)(line_width 1))
+ (line (pt 78 12)(pt 82 8)(line_width 1))
+ )
+)
+(pin
+ (output)
+ (rect 928 -80 1104 -64)
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+ (text "Y1" (rect 90 0 104 12)(font "Arial" ))
+ (pt 0 8)
+ (drawing
+ (line (pt 0 8)(pt 52 8)(line_width 1))
+ (line (pt 52 4)(pt 78 4)(line_width 1))
+ (line (pt 52 12)(pt 78 12)(line_width 1))
+ (line (pt 52 12)(pt 52 4)(line_width 1))
+ (line (pt 78 4)(pt 82 8)(line_width 1))
+ (line (pt 82 8)(pt 78 12)(line_width 1))
+ (line (pt 78 12)(pt 82 8)(line_width 1))
+ )
+)
+(pin
+ (output)
+ (rect 928 -24 1104 -8)
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+ (text "Y2" (rect 90 0 104 12)(font "Arial" ))
+ (pt 0 8)
+ (drawing
+ (line (pt 0 8)(pt 52 8)(line_width 1))
+ (line (pt 52 4)(pt 78 4)(line_width 1))
+ (line (pt 52 12)(pt 78 12)(line_width 1))
+ (line (pt 52 12)(pt 52 4)(line_width 1))
+ (line (pt 78 4)(pt 82 8)(line_width 1))
+ (line (pt 82 8)(pt 78 12)(line_width 1))
+ (line (pt 78 12)(pt 82 8)(line_width 1))
+ )
+)
+(pin
+ (output)
+ (rect 928 32 1104 48)
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+ (text "Y3" (rect 90 0 104 12)(font "Arial" ))
+ (pt 0 8)
+ (drawing
+ (line (pt 0 8)(pt 52 8)(line_width 1))
+ (line (pt 52 4)(pt 78 4)(line_width 1))
+ (line (pt 52 12)(pt 78 12)(line_width 1))
+ (line (pt 52 12)(pt 52 4)(line_width 1))
+ (line (pt 78 4)(pt 82 8)(line_width 1))
+ (line (pt 82 8)(pt 78 12)(line_width 1))
+ (line (pt 78 12)(pt 82 8)(line_width 1))
+ )
+)
+(pin
+ (output)
+ (rect 928 88 1104 104)
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+ (text "Y4" (rect 90 0 104 12)(font "Arial" ))
+ (pt 0 8)
+ (drawing
+ (line (pt 0 8)(pt 52 8)(line_width 1))
+ (line (pt 52 4)(pt 78 4)(line_width 1))
+ (line (pt 52 12)(pt 78 12)(line_width 1))
+ (line (pt 52 12)(pt 52 4)(line_width 1))
+ (line (pt 78 4)(pt 82 8)(line_width 1))
+ (line (pt 82 8)(pt 78 12)(line_width 1))
+ (line (pt 78 12)(pt 82 8)(line_width 1))
+ )
+)
+(pin
+ (output)
+ (rect 928 144 1104 160)
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+ (text "Y5" (rect 90 0 104 12)(font "Arial" ))
+ (pt 0 8)
+ (drawing
+ (line (pt 0 8)(pt 52 8)(line_width 1))
+ (line (pt 52 4)(pt 78 4)(line_width 1))
+ (line (pt 52 12)(pt 78 12)(line_width 1))
+ (line (pt 52 12)(pt 52 4)(line_width 1))
+ (line (pt 78 4)(pt 82 8)(line_width 1))
+ (line (pt 82 8)(pt 78 12)(line_width 1))
+ (line (pt 78 12)(pt 82 8)(line_width 1))
+ )
+)
+(pin
+ (output)
+ (rect 928 200 1104 216)
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+ (text "Y6" (rect 90 0 104 12)(font "Arial" ))
+ (pt 0 8)
+ (drawing
+ (line (pt 0 8)(pt 52 8)(line_width 1))
+ (line (pt 52 4)(pt 78 4)(line_width 1))
+ (line (pt 52 12)(pt 78 12)(line_width 1))
+ (line (pt 52 12)(pt 52 4)(line_width 1))
+ (line (pt 78 4)(pt 82 8)(line_width 1))
+ (line (pt 82 8)(pt 78 12)(line_width 1))
+ (line (pt 78 12)(pt 82 8)(line_width 1))
+ )
+)
+(pin
+ (output)
+ (rect 928 240 1104 256)
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+ (text "Y7" (rect 90 0 104 12)(font "Arial" ))
+ (pt 0 8)
+ (drawing
+ (line (pt 0 8)(pt 52 8)(line_width 1))
+ (line (pt 52 4)(pt 78 4)(line_width 1))
+ (line (pt 52 12)(pt 78 12)(line_width 1))
+ (line (pt 52 12)(pt 52 4)(line_width 1))
+ (line (pt 78 4)(pt 82 8)(line_width 1))
+ (line (pt 82 8)(pt 78 12)(line_width 1))
+ (line (pt 78 12)(pt 82 8)(line_width 1))
+ )
+)
+(symbol
+ (rect 480 32 544 80)
+ (text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+ (text "inst" (rect 3 37 20 49)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 14 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 14 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (line (pt 42 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 14 12)(pt 30 12)(line_width 1))
+ (line (pt 14 37)(pt 31 37)(line_width 1))
+ (line (pt 14 12)(pt 14 37)(line_width 1))
+ (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)(line_width 1))
+ )
+)
+(symbol
+ (rect 480 88 544 136)
+ (text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+ (text "inst18" (rect 3 37 32 49)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 14 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 14 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (line (pt 42 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 14 12)(pt 30 12)(line_width 1))
+ (line (pt 14 37)(pt 31 37)(line_width 1))
+ (line (pt 14 12)(pt 14 37)(line_width 1))
+ (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)(line_width 1))
+ )
+)
+(symbol
+ (rect 480 144 544 192)
+ (text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+ (text "inst19" (rect 3 37 32 49)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 14 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 14 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (line (pt 42 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 14 12)(pt 30 12)(line_width 1))
+ (line (pt 14 37)(pt 31 37)(line_width 1))
+ (line (pt 14 12)(pt 14 37)(line_width 1))
+ (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)(line_width 1))
+ )
+)
+(symbol
+ (rect 480 200 544 248)
+ (text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+ (text "inst20" (rect 3 37 32 49)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 14 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 14 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (line (pt 42 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 14 12)(pt 30 12)(line_width 1))
+ (line (pt 14 37)(pt 31 37)(line_width 1))
+ (line (pt 14 12)(pt 14 37)(line_width 1))
+ (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)(line_width 1))
+ )
+)
+(symbol
+ (rect 480 -24 544 24)
+ (text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+ (text "inst21" (rect 3 37 32 49)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 14 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 14 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (line (pt 42 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 14 12)(pt 30 12)(line_width 1))
+ (line (pt 14 37)(pt 31 37)(line_width 1))
+ (line (pt 14 12)(pt 14 37)(line_width 1))
+ (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)(line_width 1))
+ )
+)
+(symbol
+ (rect 480 -80 544 -32)
+ (text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+ (text "inst22" (rect 3 37 32 49)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 14 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 14 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (line (pt 42 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 14 12)(pt 30 12)(line_width 1))
+ (line (pt 14 37)(pt 31 37)(line_width 1))
+ (line (pt 14 12)(pt 14 37)(line_width 1))
+ (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)(line_width 1))
+ )
+)
+(symbol
+ (rect 480 -136 544 -88)
+ (text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+ (text "inst23" (rect 3 37 32 49)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 14 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 14 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (line (pt 42 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 14 12)(pt 30 12)(line_width 1))
+ (line (pt 14 37)(pt 31 37)(line_width 1))
+ (line (pt 14 12)(pt 14 37)(line_width 1))
+ (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)(line_width 1))
+ )
+)
+(symbol
+ (rect 480 -192 544 -144)
+ (text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+ (text "inst24" (rect 3 37 32 49)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 14 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 14 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (line (pt 42 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 14 12)(pt 30 12)(line_width 1))
+ (line (pt 14 37)(pt 31 37)(line_width 1))
+ (line (pt 14 12)(pt 14 37)(line_width 1))
+ (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)(line_width 1))
+ )
+)
+(symbol
+ (rect 480 296 544 344)
+ (text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+ (text "inst25" (rect 3 37 32 49)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 14 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 14 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (line (pt 42 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 14 12)(pt 30 12)(line_width 1))
+ (line (pt 14 37)(pt 31 37)(line_width 1))
+ (line (pt 14 12)(pt 14 37)(line_width 1))
+ (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)(line_width 1))
+ )
+)
+(symbol
+ (rect 480 352 544 400)
+ (text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+ (text "inst26" (rect 3 37 32 49)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 14 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 14 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (line (pt 42 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 14 12)(pt 30 12)(line_width 1))
+ (line (pt 14 37)(pt 31 37)(line_width 1))
+ (line (pt 14 12)(pt 14 37)(line_width 1))
+ (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)(line_width 1))
+ )
+)
+(symbol
+ (rect 480 408 544 456)
+ (text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+ (text "inst27" (rect 3 37 32 49)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 14 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 14 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (line (pt 42 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 14 12)(pt 30 12)(line_width 1))
+ (line (pt 14 37)(pt 31 37)(line_width 1))
+ (line (pt 14 12)(pt 14 37)(line_width 1))
+ (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)(line_width 1))
+ )
+)
+(symbol
+ (rect 480 464 544 512)
+ (text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+ (text "inst28" (rect 3 37 32 49)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 14 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 14 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (line (pt 42 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 14 12)(pt 30 12)(line_width 1))
+ (line (pt 14 37)(pt 31 37)(line_width 1))
+ (line (pt 14 12)(pt 14 37)(line_width 1))
+ (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)(line_width 1))
+ )
+)
+(symbol
+ (rect 480 520 544 568)
+ (text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+ (text "inst29" (rect 3 37 32 49)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 14 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 14 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (line (pt 42 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 14 12)(pt 30 12)(line_width 1))
+ (line (pt 14 37)(pt 31 37)(line_width 1))
+ (line (pt 14 12)(pt 14 37)(line_width 1))
+ (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)(line_width 1))
+ )
+)
+(symbol
+ (rect 480 576 544 624)
+ (text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+ (text "inst30" (rect 3 37 32 49)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 14 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 14 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (line (pt 42 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 14 12)(pt 30 12)(line_width 1))
+ (line (pt 14 37)(pt 31 37)(line_width 1))
+ (line (pt 14 12)(pt 14 37)(line_width 1))
+ (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)(line_width 1))
+ )
+)
+(symbol
+ (rect 480 632 544 680)
+ (text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+ (text "inst31" (rect 3 37 32 49)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 14 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 14 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (line (pt 42 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 14 12)(pt 30 12)(line_width 1))
+ (line (pt 14 37)(pt 31 37)(line_width 1))
+ (line (pt 14 12)(pt 14 37)(line_width 1))
+ (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)(line_width 1))
+ )
+)
+(symbol
+ (rect 480 688 544 736)
+ (text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+ (text "inst32" (rect 3 37 32 49)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 14 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 14 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (line (pt 42 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 14 12)(pt 30 12)(line_width 1))
+ (line (pt 14 37)(pt 31 37)(line_width 1))
+ (line (pt 14 12)(pt 14 37)(line_width 1))
+ (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)(line_width 1))
+ )
+)
+(symbol
+ (rect 776 -152 840 -104)
+ (text "OR2" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst1" (rect 3 37 26 49)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 15 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 15 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (line (pt 48 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 14 36)(pt 25 36)(line_width 1))
+ (line (pt 14 13)(pt 25 13)(line_width 1))
+ (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)(line_width 1))
+ (arc (pt 49 24)(pt 25 13)(rect -6 13 57 76)(line_width 1))
+ (arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36)(line_width 1))
+ )
+)
+(symbol
+ (rect 776 -96 840 -48)
+ (text "OR2" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst2" (rect 3 37 26 49)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 15 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 15 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (line (pt 48 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 14 36)(pt 25 36)(line_width 1))
+ (line (pt 14 13)(pt 25 13)(line_width 1))
+ (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)(line_width 1))
+ (arc (pt 49 24)(pt 25 13)(rect -6 13 57 76)(line_width 1))
+ (arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36)(line_width 1))
+ )
+)
+(symbol
+ (rect 776 -40 840 8)
+ (text "OR2" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst3" (rect 3 37 26 49)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 15 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 15 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (line (pt 48 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 14 36)(pt 25 36)(line_width 1))
+ (line (pt 14 13)(pt 25 13)(line_width 1))
+ (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)(line_width 1))
+ (arc (pt 49 24)(pt 25 13)(rect -6 13 57 76)(line_width 1))
+ (arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36)(line_width 1))
+ )
+)
+(symbol
+ (rect 776 16 840 64)
+ (text "OR2" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst4" (rect 3 37 26 49)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 15 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 15 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (line (pt 48 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 14 36)(pt 25 36)(line_width 1))
+ (line (pt 14 13)(pt 25 13)(line_width 1))
+ (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)(line_width 1))
+ (arc (pt 49 24)(pt 25 13)(rect -6 13 57 76)(line_width 1))
+ (arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36)(line_width 1))
+ )
+)
+(symbol
+ (rect 776 72 840 120)
+ (text "OR2" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst5" (rect 3 37 26 49)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 15 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 15 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (line (pt 48 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 14 36)(pt 25 36)(line_width 1))
+ (line (pt 14 13)(pt 25 13)(line_width 1))
+ (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)(line_width 1))
+ (arc (pt 49 24)(pt 25 13)(rect -6 13 57 76)(line_width 1))
+ (arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36)(line_width 1))
+ )
+)
+(symbol
+ (rect 776 128 840 176)
+ (text "OR2" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst6" (rect 3 37 26 49)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 15 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 15 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (line (pt 48 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 14 36)(pt 25 36)(line_width 1))
+ (line (pt 14 13)(pt 25 13)(line_width 1))
+ (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)(line_width 1))
+ (arc (pt 49 24)(pt 25 13)(rect -6 13 57 76)(line_width 1))
+ (arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36)(line_width 1))
+ )
+)
+(symbol
+ (rect 776 184 840 232)
+ (text "OR2" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst7" (rect 3 37 26 49)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 15 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 15 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (line (pt 48 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 14 36)(pt 25 36)(line_width 1))
+ (line (pt 14 13)(pt 25 13)(line_width 1))
+ (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)(line_width 1))
+ (arc (pt 49 24)(pt 25 13)(rect -6 13 57 76)(line_width 1))
+ (arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36)(line_width 1))
+ )
+)
+(symbol
+ (rect 776 240 840 288)
+ (text "OR2" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst8" (rect 3 37 26 49)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 15 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 15 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+ (line (pt 48 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 14 36)(pt 25 36)(line_width 1))
+ (line (pt 14 13)(pt 25 13)(line_width 1))
+ (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)(line_width 1))
+ (arc (pt 49 24)(pt 25 13)(rect -6 13 57 76)(line_width 1))
+ (arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36)(line_width 1))
+ )
+)
+(connector
+ (pt 344 72)
+ (pt 352 72)
+)
+(connector
+ (pt 352 -176)
+ (pt 352 72)
+)
+(connector
+ (pt 352 -176)
+ (pt 480 -176)
+)
+(connector
+ (pt 344 96)
+ (pt 360 96)
+)
+(connector
+ (pt 360 96)
+ (pt 360 -120)
+)
+(connector
+ (pt 360 -120)
+ (pt 480 -120)
+)
+(connector
+ (pt 376 120)
+ (pt 344 120)
+)
+(connector
+ (pt 376 120)
+ (pt 376 -64)
+)
+(connector
+ (pt 376 -64)
+ (pt 480 -64)
+)
+(connector
+ (pt 344 144)
+ (pt 384 144)
+)
+(connector
+ (pt 384 144)
+ (pt 384 -8)
+)
+(connector
+ (pt 384 -8)
+ (pt 480 -8)
+)
+(connector
+ (pt 344 168)
+ (pt 392 168)
+)
+(connector
+ (pt 392 168)
+ (pt 392 48)
+)
+(connector
+ (pt 392 48)
+ (pt 480 48)
+)
+(connector
+ (pt 344 192)
+ (pt 400 192)
+)
+(connector
+ (pt 400 192)
+ (pt 400 104)
+)
+(connector
+ (pt 400 104)
+ (pt 480 104)
+)
+(connector
+ (pt 344 216)
+ (pt 408 216)
+)
+(connector
+ (pt 408 216)
+ (pt 408 160)
+)
+(connector
+ (pt 408 160)
+ (pt 480 160)
+)
+(connector
+ (pt 344 240)
+ (pt 416 240)
+)
+(connector
+ (pt 416 240)
+ (pt 416 216)
+)
+(connector
+ (pt 416 216)
+ (pt 480 216)
+)
+(connector
+ (pt 328 584)
+ (pt 344 584)
+)
+(connector
+ (pt 480 -160)
+ (pt 328 -160)
+)
+(connector
+ (pt 328 -160)
+ (pt 328 -192)
+)
+(connector
+ (pt 480 -104)
+ (pt 328 -104)
+)
+(connector
+ (pt 328 -104)
+ (pt 328 -160)
+)
+(connector
+ (pt 480 -48)
+ (pt 328 -48)
+)
+(connector
+ (pt 328 -48)
+ (pt 328 -104)
+)
+(connector
+ (pt 480 8)
+ (pt 328 8)
+)
+(connector
+ (pt 328 8)
+ (pt 328 -48)
+)
+(connector
+ (pt 480 64)
+ (pt 328 64)
+)
+(connector
+ (pt 328 64)
+ (pt 328 8)
+)
+(connector
+ (pt 480 120)
+ (pt 416 120)
+)
+(connector
+ (pt 416 136)
+ (pt 416 120)
+)
+(connector
+ (pt 416 136)
+ (pt 328 136)
+)
+(connector
+ (pt 328 136)
+ (pt 328 64)
+)
+(connector
+ (pt 480 176)
+ (pt 328 176)
+)
+(connector
+ (pt 328 176)
+ (pt 328 136)
+)
+(connector
+ (pt 480 232)
+ (pt 328 232)
+)
+(connector
+ (pt 328 584)
+ (pt 328 232)
+)
+(connector
+ (pt 328 232)
+ (pt 328 176)
+)
+(connector
+ (pt 344 320)
+ (pt 352 320)
+)
+(connector
+ (pt 352 320)
+ (pt 352 312)
+)
+(connector
+ (pt 352 312)
+ (pt 480 312)
+)
+(connector
+ (pt 344 344)
+ (pt 472 344)
+)
+(connector
+ (pt 472 344)
+ (pt 472 368)
+)
+(connector
+ (pt 472 368)
+ (pt 480 368)
+)
+(connector
+ (pt 344 368)
+ (pt 464 368)
+)
+(connector
+ (pt 464 368)
+ (pt 464 424)
+)
+(connector
+ (pt 464 424)
+ (pt 480 424)
+)
+(connector
+ (pt 344 392)
+ (pt 456 392)
+)
+(connector
+ (pt 456 392)
+ (pt 456 480)
+)
+(connector
+ (pt 456 480)
+ (pt 480 480)
+)
+(connector
+ (pt 344 416)
+ (pt 448 416)
+)
+(connector
+ (pt 448 536)
+ (pt 448 416)
+)
+(connector
+ (pt 448 536)
+ (pt 480 536)
+)
+(connector
+ (pt 344 440)
+ (pt 440 440)
+)
+(connector
+ (pt 440 440)
+ (pt 440 592)
+)
+(connector
+ (pt 440 592)
+ (pt 480 592)
+)
+(connector
+ (pt 344 464)
+ (pt 432 464)
+)
+(connector
+ (pt 432 648)
+ (pt 432 464)
+)
+(connector
+ (pt 432 648)
+ (pt 480 648)
+)
+(connector
+ (pt 344 488)
+ (pt 416 488)
+)
+(connector
+ (pt 416 704)
+ (pt 416 488)
+)
+(connector
+ (pt 416 704)
+ (pt 480 704)
+)
+(connector
+ (pt 480 328)
+ (pt 400 328)
+)
+(connector
+ (pt 400 288)
+ (pt 400 328)
+)
+(connector
+ (pt 480 384)
+ (pt 400 384)
+)
+(connector
+ (pt 400 328)
+ (pt 400 384)
+)
+(connector
+ (pt 480 440)
+ (pt 464 440)
+)
+(connector
+ (pt 464 440)
+ (pt 464 432)
+)
+(connector
+ (pt 464 432)
+ (pt 400 432)
+)
+(connector
+ (pt 400 384)
+ (pt 400 432)
+)
+(connector
+ (pt 480 496)
+ (pt 400 496)
+)
+(connector
+ (pt 400 432)
+ (pt 400 496)
+)
+(connector
+ (pt 480 552)
+ (pt 400 552)
+)
+(connector
+ (pt 400 496)
+ (pt 400 552)
+)
+(connector
+ (pt 400 552)
+ (pt 400 608)
+)
+(connector
+ (pt 344 608)
+ (pt 400 608)
+)
+(connector
+ (pt 400 608)
+ (pt 480 608)
+)
+(connector
+ (pt 480 664)
+ (pt 400 664)
+)
+(connector
+ (pt 400 608)
+ (pt 400 664)
+)
+(connector
+ (pt 480 720)
+ (pt 400 720)
+)
+(connector
+ (pt 400 664)
+ (pt 400 720)
+)
+(connector
+ (pt 400 720)
+ (pt 400 760)
+)
+(connector
+ (pt 544 -168)
+ (pt 560 -168)
+)
+(connector
+ (pt 560 -136)
+ (pt 560 -168)
+)
+(connector
+ (pt 560 -136)
+ (pt 776 -136)
+)
+(connector
+ (pt 544 -112)
+ (pt 560 -112)
+)
+(connector
+ (pt 560 -80)
+ (pt 560 -112)
+)
+(connector
+ (pt 560 -80)
+ (pt 776 -80)
+)
+(connector
+ (pt 544 -56)
+ (pt 560 -56)
+)
+(connector
+ (pt 560 -24)
+ (pt 560 -56)
+)
+(connector
+ (pt 560 -24)
+ (pt 776 -24)
+)
+(connector
+ (pt 544 0)
+ (pt 560 0)
+)
+(connector
+ (pt 560 0)
+ (pt 560 32)
+)
+(connector
+ (pt 560 32)
+ (pt 776 32)
+)
+(connector
+ (pt 776 32)
+ (pt 784 32)
+)
+(connector
+ (pt 544 56)
+ (pt 560 56)
+)
+(connector
+ (pt 560 88)
+ (pt 560 56)
+)
+(connector
+ (pt 560 88)
+ (pt 776 88)
+)
+(connector
+ (pt 544 112)
+ (pt 560 112)
+)
+(connector
+ (pt 560 144)
+ (pt 560 112)
+)
+(connector
+ (pt 560 144)
+ (pt 776 144)
+)
+(connector
+ (pt 544 168)
+ (pt 560 168)
+)
+(connector
+ (pt 560 168)
+ (pt 560 200)
+)
+(connector
+ (pt 560 200)
+ (pt 776 200)
+)
+(connector
+ (pt 544 224)
+ (pt 560 224)
+)
+(connector
+ (pt 560 256)
+ (pt 560 224)
+)
+(connector
+ (pt 560 256)
+ (pt 776 256)
+)
+(connector
+ (pt 544 320)
+ (pt 600 320)
+)
+(connector
+ (pt 600 320)
+ (pt 600 -120)
+)
+(connector
+ (pt 600 -120)
+ (pt 776 -120)
+)
+(connector
+ (pt 544 376)
+ (pt 616 376)
+)
+(connector
+ (pt 616 376)
+ (pt 616 -64)
+)
+(connector
+ (pt 616 -64)
+ (pt 776 -64)
+)
+(connector
+ (pt 544 432)
+ (pt 640 432)
+)
+(connector
+ (pt 640 432)
+ (pt 640 -8)
+)
+(connector
+ (pt 640 -8)
+ (pt 776 -8)
+)
+(connector
+ (pt 544 488)
+ (pt 664 488)
+)
+(connector
+ (pt 664 48)
+ (pt 776 48)
+)
+(connector
+ (pt 664 48)
+ (pt 664 488)
+)
+(connector
+ (pt 544 544)
+ (pt 688 544)
+)
+(connector
+ (pt 688 544)
+ (pt 688 104)
+)
+(connector
+ (pt 688 104)
+ (pt 776 104)
+)
+(connector
+ (pt 544 600)
+ (pt 712 600)
+)
+(connector
+ (pt 712 160)
+ (pt 776 160)
+)
+(connector
+ (pt 712 160)
+ (pt 712 600)
+)
+(connector
+ (pt 728 656)
+ (pt 544 656)
+)
+(connector
+ (pt 728 656)
+ (pt 728 216)
+)
+(connector
+ (pt 728 216)
+ (pt 776 216)
+)
+(connector
+ (pt 544 712)
+ (pt 744 712)
+)
+(connector
+ (pt 744 368)
+ (pt 744 712)
+)
+(connector
+ (pt 776 368)
+ (pt 744 368)
+)
+(connector
+ (pt 776 368)
+ (pt 776 272)
+)
+(connector
+ (pt 840 -128)
+ (pt 928 -128)
+)
+(connector
+ (pt 840 -72)
+ (pt 928 -72)
+)
+(connector
+ (pt 840 -16)
+ (pt 928 -16)
+)
+(connector
+ (pt 840 40)
+ (pt 928 40)
+)
+(connector
+ (pt 840 96)
+ (pt 928 96)
+)
+(connector
+ (pt 840 152)
+ (pt 928 152)
+)
+(connector
+ (pt 840 208)
+ (pt 928 208)
+)
+(connector
+ (pt 840 264)
+ (pt 928 264)
+)
+(connector
+ (pt 928 264)
+ (pt 928 248)
+)
+(junction (pt 328 -160))
+(junction (pt 328 -104))
+(junction (pt 328 -48))
+(junction (pt 328 8))
+(junction (pt 328 64))
+(junction (pt 328 136))
+(junction (pt 328 176))
+(junction (pt 328 232))
+(junction (pt 400 608))
+(junction (pt 400 328))
+(junction (pt 400 384))
+(junction (pt 400 432))
+(junction (pt 400 496))
+(junction (pt 400 552))
+(junction (pt 400 664))
+(junction (pt 400 720))
+(junction (pt 776 32))
diff --git a/data_selector/data_selector.bsf b/data_selector/data_selector.bsf
new file mode 100644
index 0000000..25cf9a0
--- /dev/null
+++ b/data_selector/data_selector.bsf
@@ -0,0 +1,211 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 16 16 112 368)
+ (text "data_selector" (rect 5 0 82 14)(font "Arial" (font_size 8)))
+ (text "inst" (rect 8 336 25 348)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "a0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+ (text "a0" (rect 21 27 35 41)(font "Arial" (font_size 8)))
+ (line (pt 0 32)(pt 16 32)(line_width 1))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "a1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+ (text "a1" (rect 21 43 35 57)(font "Arial" (font_size 8)))
+ (line (pt 0 48)(pt 16 48)(line_width 1))
+ )
+ (port
+ (pt 0 64)
+ (input)
+ (text "a2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+ (text "a2" (rect 21 59 35 73)(font "Arial" (font_size 8)))
+ (line (pt 0 64)(pt 16 64)(line_width 1))
+ )
+ (port
+ (pt 0 80)
+ (input)
+ (text "a3" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+ (text "a3" (rect 21 75 35 89)(font "Arial" (font_size 8)))
+ (line (pt 0 80)(pt 16 80)(line_width 1))
+ )
+ (port
+ (pt 0 96)
+ (input)
+ (text "a4" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+ (text "a4" (rect 21 91 35 105)(font "Arial" (font_size 8)))
+ (line (pt 0 96)(pt 16 96)(line_width 1))
+ )
+ (port
+ (pt 0 112)
+ (input)
+ (text "a5" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+ (text "a5" (rect 21 107 35 121)(font "Arial" (font_size 8)))
+ (line (pt 0 112)(pt 16 112)(line_width 1))
+ )
+ (port
+ (pt 0 128)
+ (input)
+ (text "a6" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+ (text "a6" (rect 21 123 35 137)(font "Arial" (font_size 8)))
+ (line (pt 0 128)(pt 16 128)(line_width 1))
+ )
+ (port
+ (pt 0 144)
+ (input)
+ (text "a7" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+ (text "a7" (rect 21 139 35 153)(font "Arial" (font_size 8)))
+ (line (pt 0 144)(pt 16 144)(line_width 1))
+ )
+ (port
+ (pt 0 160)
+ (input)
+ (text "b0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+ (text "b0" (rect 21 155 35 169)(font "Arial" (font_size 8)))
+ (line (pt 0 160)(pt 16 160)(line_width 1))
+ )
+ (port
+ (pt 0 176)
+ (input)
+ (text "b1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+ (text "b1" (rect 21 171 35 185)(font "Arial" (font_size 8)))
+ (line (pt 0 176)(pt 16 176)(line_width 1))
+ )
+ (port
+ (pt 0 192)
+ (input)
+ (text "b2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+ (text "b2" (rect 21 187 35 201)(font "Arial" (font_size 8)))
+ (line (pt 0 192)(pt 16 192)(line_width 1))
+ )
+ (port
+ (pt 0 208)
+ (input)
+ (text "b3" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+ (text "b3" (rect 21 203 35 217)(font "Arial" (font_size 8)))
+ (line (pt 0 208)(pt 16 208)(line_width 1))
+ )
+ (port
+ (pt 0 224)
+ (input)
+ (text "b4" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+ (text "b4" (rect 21 219 35 233)(font "Arial" (font_size 8)))
+ (line (pt 0 224)(pt 16 224)(line_width 1))
+ )
+ (port
+ (pt 0 240)
+ (input)
+ (text "b5" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+ (text "b5" (rect 21 235 35 249)(font "Arial" (font_size 8)))
+ (line (pt 0 240)(pt 16 240)(line_width 1))
+ )
+ (port
+ (pt 0 256)
+ (input)
+ (text "b6" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+ (text "b6" (rect 21 251 35 265)(font "Arial" (font_size 8)))
+ (line (pt 0 256)(pt 16 256)(line_width 1))
+ )
+ (port
+ (pt 0 272)
+ (input)
+ (text "b7" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+ (text "b7" (rect 21 267 35 281)(font "Arial" (font_size 8)))
+ (line (pt 0 272)(pt 16 272)(line_width 1))
+ )
+ (port
+ (pt 0 288)
+ (input)
+ (text "AY" (rect 0 0 18 14)(font "Arial" (font_size 8)))
+ (text "AY" (rect 21 283 39 297)(font "Arial" (font_size 8)))
+ (line (pt 0 288)(pt 16 288)(line_width 1))
+ )
+ (port
+ (pt 0 304)
+ (input)
+ (text "BY" (rect 0 0 17 14)(font "Arial" (font_size 8)))
+ (text "BY" (rect 21 299 38 313)(font "Arial" (font_size 8)))
+ (line (pt 0 304)(pt 16 304)(line_width 1))
+ )
+ (port
+ (pt 96 32)
+ (output)
+ (text "Y0" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+ (text "Y0" (rect 59 27 75 41)(font "Arial" (font_size 8)))
+ (line (pt 96 32)(pt 80 32)(line_width 1))
+ )
+ (port
+ (pt 96 48)
+ (output)
+ (text "Y1" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+ (text "Y1" (rect 59 43 75 57)(font "Arial" (font_size 8)))
+ (line (pt 96 48)(pt 80 48)(line_width 1))
+ )
+ (port
+ (pt 96 64)
+ (output)
+ (text "Y2" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+ (text "Y2" (rect 59 59 75 73)(font "Arial" (font_size 8)))
+ (line (pt 96 64)(pt 80 64)(line_width 1))
+ )
+ (port
+ (pt 96 80)
+ (output)
+ (text "Y3" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+ (text "Y3" (rect 59 75 75 89)(font "Arial" (font_size 8)))
+ (line (pt 96 80)(pt 80 80)(line_width 1))
+ )
+ (port
+ (pt 96 96)
+ (output)
+ (text "Y4" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+ (text "Y4" (rect 59 91 75 105)(font "Arial" (font_size 8)))
+ (line (pt 96 96)(pt 80 96)(line_width 1))
+ )
+ (port
+ (pt 96 112)
+ (output)
+ (text "Y5" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+ (text "Y5" (rect 59 107 75 121)(font "Arial" (font_size 8)))
+ (line (pt 96 112)(pt 80 112)(line_width 1))
+ )
+ (port
+ (pt 96 128)
+ (output)
+ (text "Y6" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+ (text "Y6" (rect 59 123 75 137)(font "Arial" (font_size 8)))
+ (line (pt 96 128)(pt 80 128)(line_width 1))
+ )
+ (port
+ (pt 96 144)
+ (output)
+ (text "Y7" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+ (text "Y7" (rect 59 139 75 153)(font "Arial" (font_size 8)))
+ (line (pt 96 144)(pt 80 144)(line_width 1))
+ )
+ (drawing
+ (rectangle (rect 16 16 80 336)(line_width 1))
+ )
+)
diff --git a/data_selector/data_selector.done b/data_selector/data_selector.done
new file mode 100644
index 0000000..64e702a
--- /dev/null
+++ b/data_selector/data_selector.done
@@ -0,0 +1 @@
+Sat Mar 05 20:41:37 2022
diff --git a/data_selector/data_selector.dpf b/data_selector/data_selector.dpf
new file mode 100644
index 0000000..abe19d9
--- /dev/null
+++ b/data_selector/data_selector.dpf
@@ -0,0 +1,12 @@
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/data_selector/data_selector.fit.rpt b/data_selector/data_selector.fit.rpt
new file mode 100644
index 0000000..d3b0058
--- /dev/null
+++ b/data_selector/data_selector.fit.rpt
@@ -0,0 +1,1006 @@
+Fitter report for data_selector
+Sat Mar 05 20:41:34 2022
+Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Fitter Summary
+ 3. Fitter Settings
+ 4. Parallel Compilation
+ 5. Incremental Compilation Preservation Summary
+ 6. Incremental Compilation Partition Settings
+ 7. Incremental Compilation Placement Preservation
+ 8. Pin-Out File
+ 9. Fitter Resource Usage Summary
+ 10. Input Pins
+ 11. Output Pins
+ 12. I/O Bank Usage
+ 13. All Package Pins
+ 14. Output Pin Default Load For Reported TCO
+ 15. Fitter Resource Utilization by Entity
+ 16. Delay Chain Summary
+ 17. Pad To Core Delay Chain Fanout
+ 18. Non-Global High Fan-Out Signals
+ 19. Interconnect Usage Summary
+ 20. LAB Logic Elements
+ 21. LAB Signals Sourced
+ 22. LAB Signals Sourced Out
+ 23. LAB Distinct Inputs
+ 24. Fitter Device Options
+ 25. Operating Settings and Conditions
+ 26. Estimated Delay Added for Hold Timing
+ 27. Advanced Data - General
+ 28. Advanced Data - Placement Preparation
+ 29. Advanced Data - Placement
+ 30. Advanced Data - Routing
+ 31. Fitter Messages
+ 32. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Fitter Summary ;
++------------------------------------+----------------------------------------------+
+; Fitter Status ; Successful - Sat Mar 05 20:41:34 2022 ;
+; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
+; Revision Name ; data_selector ;
+; Top-level Entity Name ; data_selector ;
+; Family ; Cyclone II ;
+; Device ; EP2C8Q208C8 ;
+; Timing Models ; Final ;
+; Total logic elements ; 8 / 8,256 ( < 1 % ) ;
+; Total combinational functions ; 8 / 8,256 ( < 1 % ) ;
+; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ;
+; Total registers ; 0 ;
+; Total pins ; 26 / 138 ( 19 % ) ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 0 / 165,888 ( 0 % ) ;
+; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
+; Total PLLs ; 0 / 2 ( 0 % ) ;
++------------------------------------+----------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+; Option ; Setting ; Default Value ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+; Device ; EP2C8Q208C8 ; ;
+; Minimum Core Junction Temperature ; 0 ; ;
+; Maximum Core Junction Temperature ; 85 ; ;
+; Fit Attempts to Skip ; 0 ; 0.0 ;
+; Use smart compilation ; Off ; Off ;
+; Use TimeQuest Timing Analyzer ; Off ; Off ;
+; Router Timing Optimization Level ; Normal ; Normal ;
+; Placement Effort Multiplier ; 1.0 ; 1.0 ;
+; Router Effort Multiplier ; 1.0 ; 1.0 ;
+; Always Enable Input Buffers ; Off ; Off ;
+; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
+; Optimize Multi-Corner Timing ; Off ; Off ;
+; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
+; Optimize Timing ; Normal compilation ; Normal compilation ;
+; Optimize Timing for ECOs ; Off ; Off ;
+; Regenerate full fit report during ECO compiles ; Off ; Off ;
+; Optimize IOC Register Placement for Timing ; On ; On ;
+; Limit to One Fitting Attempt ; Off ; Off ;
+; Final Placement Optimizations ; Automatically ; Automatically ;
+; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
+; Fitter Initial Placement Seed ; 1 ; 1 ;
+; PCI I/O ; Off ; Off ;
+; Weak Pull-Up Resistor ; Off ; Off ;
+; Enable Bus-Hold Circuitry ; Off ; Off ;
+; Auto Global Memory Control Signals ; Off ; Off ;
+; Auto Packed Registers ; Auto ; Auto ;
+; Auto Delay Chains ; On ; On ;
+; Auto Merge PLLs ; On ; On ;
+; Ignore PLL Mode When Merging PLLs ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
+; Perform Register Duplication for Performance ; Off ; Off ;
+; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
+; Perform Register Retiming for Performance ; Off ; Off ;
+; Perform Asynchronous Signal Pipelining ; Off ; Off ;
+; Fitter Effort ; Auto Fit ; Auto Fit ;
+; Physical Synthesis Effort Level ; Normal ; Normal ;
+; Auto Global Clock ; On ; On ;
+; Auto Global Register Control Signals ; On ; On ;
+; Stop After Congestion Map Generation ; Off ; Off ;
+; Save Intermediate Fitting Results ; Off ; Off ;
+; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 4 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.00 ;
+; Maximum used ; 4 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; 1 processor ; 100.0% ;
+; 2-4 processors ; < 0.1% ;
++----------------------------+-------------+
+
+
++----------------------------------------------+
+; Incremental Compilation Preservation Summary ;
++-------------------------+--------------------+
+; Type ; Value ;
++-------------------------+--------------------+
+; Placement ; ;
+; -- Requested ; 0 / 34 ( 0.00 % ) ;
+; -- Achieved ; 0 / 34 ( 0.00 % ) ;
+; ; ;
+; Routing (by Connection) ; ;
+; -- Requested ; 0 / 0 ( 0.00 % ) ;
+; -- Achieved ; 0 / 0 ( 0.00 % ) ;
++-------------------------+--------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings ;
++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
+; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
+; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
+
+
++--------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation ;
++----------------+---------+-------------------+-------------------------+-------------------+
+; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
++----------------+---------+-------------------+-------------------------+-------------------+
+; Top ; 34 ; 0 ; N/A ; Source File ;
++----------------+---------+-------------------+-------------------------+-------------------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in D:/projects/quartus/data_selector/data_selector.pin.
+
+
++-------------------------------------------------------------------+
+; Fitter Resource Usage Summary ;
++---------------------------------------------+---------------------+
+; Resource ; Usage ;
++---------------------------------------------+---------------------+
+; Total logic elements ; 8 / 8,256 ( < 1 % ) ;
+; -- Combinational with no register ; 8 ;
+; -- Register only ; 0 ;
+; -- Combinational with a register ; 0 ;
+; ; ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 8 ;
+; -- 3 input functions ; 0 ;
+; -- <=2 input functions ; 0 ;
+; -- Register only ; 0 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 8 ;
+; -- arithmetic mode ; 0 ;
+; ; ;
+; Total registers* ; 0 / 8,646 ( 0 % ) ;
+; -- Dedicated logic registers ; 0 / 8,256 ( 0 % ) ;
+; -- I/O registers ; 0 / 390 ( 0 % ) ;
+; ; ;
+; Total LABs: partially or completely used ; 1 / 516 ( < 1 % ) ;
+; User inserted logic elements ; 0 ;
+; Virtual pins ; 0 ;
+; I/O pins ; 26 / 138 ( 19 % ) ;
+; -- Clock pins ; 2 / 4 ( 50 % ) ;
+; Global signals ; 0 ;
+; M4Ks ; 0 / 36 ( 0 % ) ;
+; Total block memory bits ; 0 / 165,888 ( 0 % ) ;
+; Total block memory implementation bits ; 0 / 165,888 ( 0 % ) ;
+; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
+; PLLs ; 0 / 2 ( 0 % ) ;
+; Global clocks ; 0 / 8 ( 0 % ) ;
+; JTAGs ; 0 / 1 ( 0 % ) ;
+; ASMI blocks ; 0 / 1 ( 0 % ) ;
+; CRC blocks ; 0 / 1 ( 0 % ) ;
+; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ;
+; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ;
+; Maximum fan-out node ; AY ;
+; Maximum fan-out ; 8 ;
+; Highest non-global fan-out signal ; AY ;
+; Highest non-global fan-out ; 8 ;
+; Total fan-out ; 40 ;
+; Average fan-out ; 1.08 ;
++---------------------------------------------+---------------------+
+* Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins ;
++------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
++------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+; AY ; 56 ; 4 ; 1 ; 0 ; 3 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; BY ; 44 ; 1 ; 0 ; 3 ; 1 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; a0 ; 39 ; 1 ; 0 ; 5 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; a1 ; 37 ; 1 ; 0 ; 6 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; a2 ; 24 ; 1 ; 0 ; 9 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; a3 ; 28 ; 1 ; 0 ; 9 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; a4 ; 12 ; 1 ; 0 ; 16 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; a5 ; 31 ; 1 ; 0 ; 8 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; a6 ; 34 ; 1 ; 0 ; 7 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; a7 ; 3 ; 1 ; 0 ; 18 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; b0 ; 40 ; 1 ; 0 ; 5 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; b1 ; 23 ; 1 ; 0 ; 9 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; b2 ; 27 ; 1 ; 0 ; 9 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; b3 ; 59 ; 4 ; 1 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; b4 ; 41 ; 1 ; 0 ; 4 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; b5 ; 45 ; 1 ; 0 ; 3 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; b6 ; 57 ; 4 ; 1 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; b7 ; 33 ; 1 ; 0 ; 8 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
++------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins ;
++------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
++------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
+; Y0 ; 58 ; 4 ; 1 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; Y1 ; 35 ; 1 ; 0 ; 7 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; Y2 ; 14 ; 1 ; 0 ; 14 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; Y3 ; 15 ; 1 ; 0 ; 14 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; Y4 ; 10 ; 1 ; 0 ; 17 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; Y5 ; 208 ; 2 ; 1 ; 19 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; Y6 ; 30 ; 1 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; Y7 ; 48 ; 1 ; 0 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
++------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
+
+
++------------------------------------------------------------+
+; I/O Bank Usage ;
++----------+------------------+---------------+--------------+
+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
++----------+------------------+---------------+--------------+
+; 1 ; 23 / 32 ( 72 % ) ; 3.3V ; -- ;
+; 2 ; 1 / 35 ( 3 % ) ; 3.3V ; -- ;
+; 3 ; 1 / 35 ( 3 % ) ; 3.3V ; -- ;
+; 4 ; 4 / 36 ( 11 % ) ; 3.3V ; -- ;
++----------+------------------+---------------+--------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins ;
++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; 1 ; 0 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
+; 2 ; 1 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
+; 3 ; 2 ; 1 ; a7 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 4 ; 3 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 5 ; 4 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 6 ; 5 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 8 ; 6 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 10 ; 7 ; 1 ; Y4 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 11 ; 8 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 12 ; 9 ; 1 ; a4 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 13 ; 10 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 14 ; 18 ; 1 ; Y2 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 15 ; 19 ; 1 ; Y3 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
+; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
+; 18 ; 22 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
+; 19 ; 23 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
+; 20 ; 24 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ;
+; 21 ; 25 ; 1 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ;
+; 22 ; 26 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
+; 23 ; 27 ; 1 ; b1 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 24 ; 28 ; 1 ; a2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 26 ; 29 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
+; 27 ; 30 ; 1 ; b2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 28 ; 31 ; 1 ; a3 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 30 ; 32 ; 1 ; Y6 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 31 ; 33 ; 1 ; a5 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 33 ; 35 ; 1 ; b7 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 34 ; 36 ; 1 ; a6 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 35 ; 37 ; 1 ; Y1 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 37 ; 39 ; 1 ; a1 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 39 ; 43 ; 1 ; a0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 40 ; 44 ; 1 ; b0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 41 ; 45 ; 1 ; b4 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 42 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 43 ; 48 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 44 ; 49 ; 1 ; BY ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 45 ; 50 ; 1 ; b5 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 46 ; 51 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 47 ; 52 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 48 ; 53 ; 1 ; Y7 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 49 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 50 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
+; 51 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 52 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
+; 53 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 54 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
+; 55 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 56 ; 54 ; 4 ; AY ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 57 ; 55 ; 4 ; b6 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 58 ; 56 ; 4 ; Y0 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 59 ; 57 ; 4 ; b3 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 60 ; 58 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 61 ; 59 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 63 ; 60 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 64 ; 61 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 67 ; 69 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 68 ; 70 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 69 ; 71 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 70 ; 74 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 71 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 72 ; 75 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 74 ; 76 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 75 ; 77 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 76 ; 78 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 77 ; 79 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 80 ; 82 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 81 ; 83 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 82 ; 84 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 83 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 84 ; 85 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 85 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 86 ; 86 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 87 ; 87 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 88 ; 88 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 89 ; 89 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 90 ; 90 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 91 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 92 ; 91 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 94 ; 92 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 95 ; 93 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 96 ; 94 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 97 ; 95 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 98 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 99 ; 96 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 100 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 101 ; 97 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 102 ; 98 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 103 ; 99 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 104 ; 100 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 105 ; 101 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 106 ; 102 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 107 ; 105 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 108 ; 106 ; 3 ; ~LVDS54p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 109 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 110 ; 107 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 111 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 112 ; 108 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 113 ; 109 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 114 ; 110 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 115 ; 112 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 116 ; 113 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 117 ; 114 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 118 ; 117 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 119 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 120 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 121 ; 121 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
+; 122 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 123 ; 122 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
+; 124 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 125 ; 123 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
+; 126 ; 124 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
+; 127 ; 125 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 128 ; 126 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 129 ; 127 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; 130 ; 128 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; 131 ; 129 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; 132 ; 130 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; 133 ; 131 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 134 ; 132 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 135 ; 133 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 136 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 137 ; 134 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 138 ; 135 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 139 ; 136 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 141 ; 137 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 142 ; 138 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 143 ; 141 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 144 ; 142 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 145 ; 143 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 146 ; 149 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 147 ; 150 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 148 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 149 ; 151 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 150 ; 152 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 151 ; 153 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 152 ; 154 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 153 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 154 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
+; 155 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 156 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
+; 157 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 158 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
+; 159 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 160 ; 155 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 161 ; 156 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 162 ; 157 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 163 ; 158 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 164 ; 159 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 165 ; 160 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 166 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 167 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 168 ; 161 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 169 ; 162 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 170 ; 163 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 171 ; 164 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 172 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 173 ; 165 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 174 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 175 ; 168 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 176 ; 169 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 177 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 178 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 179 ; 173 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 180 ; 174 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 181 ; 175 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 182 ; 176 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 183 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 184 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 185 ; 180 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 186 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 187 ; 181 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 188 ; 182 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 189 ; 183 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 190 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 191 ; 184 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 192 ; 185 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 193 ; 186 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 194 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 195 ; 187 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 196 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 197 ; 191 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 198 ; 192 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 199 ; 195 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 200 ; 196 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 201 ; 197 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 202 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 203 ; 198 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 204 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 205 ; 199 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 206 ; 200 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 207 ; 201 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 208 ; 202 ; 2 ; Y5 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-------------------------------------------------------------------------------+
+; Output Pin Default Load For Reported TCO ;
++----------------------------------+-------+------------------------------------+
+; I/O Standard ; Load ; Termination Resistance ;
++----------------------------------+-------+------------------------------------+
+; 3.3-V LVTTL ; 0 pF ; Not Available ;
+; 3.3-V LVCMOS ; 0 pF ; Not Available ;
+; 2.5 V ; 0 pF ; Not Available ;
+; 1.8 V ; 0 pF ; Not Available ;
+; 1.5 V ; 0 pF ; Not Available ;
+; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ;
+; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ;
+; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
+; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;
+; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;
+; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;
+; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;
+; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ;
+; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ;
+; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ;
+; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ;
+; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ;
+; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ;
+; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ;
+; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ;
+; LVDS ; 0 pF ; 100 Ohm (Differential) ;
+; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ;
+; RSDS ; 0 pF ; 100 Ohm (Differential) ;
+; Simple RSDS ; 0 pF ; Not Available ;
+; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ;
++----------------------------------+-------+------------------------------------+
+Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
+; |data_selector ; 8 (8) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 26 ; 0 ; 8 (8) ; 0 (0) ; 0 (0) ; |data_selector ; work ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-------------------------------------------------------------------------------+
+; Delay Chain Summary ;
++------+----------+---------------+---------------+-----------------------+-----+
+; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
++------+----------+---------------+---------------+-----------------------+-----+
+; Y0 ; Output ; -- ; -- ; -- ; -- ;
+; Y1 ; Output ; -- ; -- ; -- ; -- ;
+; Y2 ; Output ; -- ; -- ; -- ; -- ;
+; Y3 ; Output ; -- ; -- ; -- ; -- ;
+; Y4 ; Output ; -- ; -- ; -- ; -- ;
+; Y5 ; Output ; -- ; -- ; -- ; -- ;
+; Y6 ; Output ; -- ; -- ; -- ; -- ;
+; Y7 ; Output ; -- ; -- ; -- ; -- ;
+; b0 ; Input ; 6 ; 6 ; -- ; -- ;
+; a0 ; Input ; 6 ; 6 ; -- ; -- ;
+; AY ; Input ; 6 ; 6 ; -- ; -- ;
+; BY ; Input ; 6 ; 6 ; -- ; -- ;
+; a1 ; Input ; 6 ; 6 ; -- ; -- ;
+; b1 ; Input ; 0 ; 0 ; -- ; -- ;
+; a2 ; Input ; 0 ; 0 ; -- ; -- ;
+; b2 ; Input ; 0 ; 0 ; -- ; -- ;
+; a3 ; Input ; 0 ; 0 ; -- ; -- ;
+; b3 ; Input ; 6 ; 6 ; -- ; -- ;
+; a4 ; Input ; 6 ; 6 ; -- ; -- ;
+; b4 ; Input ; 6 ; 6 ; -- ; -- ;
+; a5 ; Input ; 6 ; 6 ; -- ; -- ;
+; b5 ; Input ; 6 ; 6 ; -- ; -- ;
+; a6 ; Input ; 6 ; 6 ; -- ; -- ;
+; b6 ; Input ; 6 ; 6 ; -- ; -- ;
+; a7 ; Input ; 6 ; 6 ; -- ; -- ;
+; b7 ; Input ; 6 ; 6 ; -- ; -- ;
++------+----------+---------------+---------------+-----------------------+-----+
+
+
++---------------------------------------------------+
+; Pad To Core Delay Chain Fanout ;
++---------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++---------------------+-------------------+---------+
+; b0 ; ; ;
+; - inst1 ; 1 ; 6 ;
+; a0 ; ; ;
+; - inst1 ; 0 ; 6 ;
+; AY ; ; ;
+; - inst1 ; 0 ; 6 ;
+; - inst2 ; 0 ; 6 ;
+; - inst3 ; 0 ; 6 ;
+; - inst4 ; 0 ; 6 ;
+; - inst5 ; 0 ; 6 ;
+; - inst6 ; 0 ; 6 ;
+; - inst7 ; 0 ; 6 ;
+; - inst8 ; 0 ; 6 ;
+; BY ; ; ;
+; - inst1 ; 1 ; 6 ;
+; - inst2 ; 1 ; 6 ;
+; - inst3 ; 1 ; 6 ;
+; - inst4 ; 1 ; 6 ;
+; - inst5 ; 1 ; 6 ;
+; - inst6 ; 1 ; 6 ;
+; - inst7 ; 1 ; 6 ;
+; - inst8 ; 1 ; 6 ;
+; a1 ; ; ;
+; - inst2 ; 0 ; 6 ;
+; b1 ; ; ;
+; a2 ; ; ;
+; b2 ; ; ;
+; a3 ; ; ;
+; b3 ; ; ;
+; - inst4 ; 0 ; 6 ;
+; a4 ; ; ;
+; - inst5 ; 0 ; 6 ;
+; b4 ; ; ;
+; - inst5 ; 1 ; 6 ;
+; a5 ; ; ;
+; - inst6 ; 0 ; 6 ;
+; b5 ; ; ;
+; - inst6 ; 1 ; 6 ;
+; a6 ; ; ;
+; - inst7 ; 0 ; 6 ;
+; b6 ; ; ;
+; - inst7 ; 1 ; 6 ;
+; a7 ; ; ;
+; - inst8 ; 0 ; 6 ;
+; b7 ; ; ;
+; - inst8 ; 0 ; 6 ;
++---------------------+-------------------+---------+
+
+
++---------------------------------+
+; Non-Global High Fan-Out Signals ;
++-------+-------------------------+
+; Name ; Fan-Out ;
++-------+-------------------------+
+; BY ; 8 ;
+; AY ; 8 ;
+; b7 ; 1 ;
+; a7 ; 1 ;
+; b6 ; 1 ;
+; a6 ; 1 ;
+; b5 ; 1 ;
+; a5 ; 1 ;
+; b4 ; 1 ;
+; a4 ; 1 ;
+; b3 ; 1 ;
+; a3 ; 1 ;
+; b2 ; 1 ;
+; a2 ; 1 ;
+; b1 ; 1 ;
+; a1 ; 1 ;
+; a0 ; 1 ;
+; b0 ; 1 ;
+; inst8 ; 1 ;
+; inst7 ; 1 ;
+; inst6 ; 1 ;
+; inst5 ; 1 ;
+; inst4 ; 1 ;
+; inst3 ; 1 ;
+; inst2 ; 1 ;
+; inst1 ; 1 ;
++-------+-------------------------+
+
+
++----------------------------------------------------+
+; Interconnect Usage Summary ;
++----------------------------+-----------------------+
+; Interconnect Resource Type ; Usage ;
++----------------------------+-----------------------+
+; Block interconnects ; 26 / 26,052 ( < 1 % ) ;
+; C16 interconnects ; 3 / 1,156 ( < 1 % ) ;
+; C4 interconnects ; 35 / 17,952 ( < 1 % ) ;
+; Direct links ; 0 / 26,052 ( 0 % ) ;
+; Global clocks ; 0 / 8 ( 0 % ) ;
+; Local interconnects ; 0 / 8,256 ( 0 % ) ;
+; R24 interconnects ; 0 / 1,020 ( 0 % ) ;
+; R4 interconnects ; 3 / 22,440 ( < 1 % ) ;
++----------------------------+-----------------------+
+
+
++--------------------------------------------------------------------------+
+; LAB Logic Elements ;
++--------------------------------------------+-----------------------------+
+; Number of Logic Elements (Average = 8.00) ; Number of LABs (Total = 1) ;
++--------------------------------------------+-----------------------------+
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 0 ;
+; 4 ; 0 ;
+; 5 ; 0 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 1 ;
+; 9 ; 0 ;
+; 10 ; 0 ;
+; 11 ; 0 ;
+; 12 ; 0 ;
+; 13 ; 0 ;
+; 14 ; 0 ;
+; 15 ; 0 ;
+; 16 ; 0 ;
++--------------------------------------------+-----------------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Signals Sourced ;
++---------------------------------------------+-----------------------------+
+; Number of Signals Sourced (Average = 8.00) ; Number of LABs (Total = 1) ;
++---------------------------------------------+-----------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 0 ;
+; 4 ; 0 ;
+; 5 ; 0 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 1 ;
++---------------------------------------------+-----------------------------+
+
+
++-------------------------------------------------------------------------------+
+; LAB Signals Sourced Out ;
++-------------------------------------------------+-----------------------------+
+; Number of Signals Sourced Out (Average = 8.00) ; Number of LABs (Total = 1) ;
++-------------------------------------------------+-----------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 0 ;
+; 4 ; 0 ;
+; 5 ; 0 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 1 ;
++-------------------------------------------------+-----------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Distinct Inputs ;
++----------------------------------------------+-----------------------------+
+; Number of Distinct Inputs (Average = 18.00) ; Number of LABs (Total = 1) ;
++----------------------------------------------+-----------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 0 ;
+; 4 ; 0 ;
+; 5 ; 0 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 0 ;
+; 9 ; 0 ;
+; 10 ; 0 ;
+; 11 ; 0 ;
+; 12 ; 0 ;
+; 13 ; 0 ;
+; 14 ; 0 ;
+; 15 ; 0 ;
+; 16 ; 0 ;
+; 17 ; 0 ;
+; 18 ; 1 ;
++----------------------------------------------+-----------------------------+
+
+
++-------------------------------------------------------------------------+
+; Fitter Device Options ;
++----------------------------------------------+--------------------------+
+; Option ; Setting ;
++----------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR) ; Off ;
+; Enable device-wide reset (DEV_CLRn) ; Off ;
+; Enable device-wide output enable (DEV_OE) ; Off ;
+; Enable INIT_DONE output ; Off ;
+; Configuration scheme ; Active Serial ;
+; Error detection CRC ; Off ;
+; nCEO ; As output driving ground ;
+; ASDO,nCSO ; As input tri-stated ;
+; Reserve all unused pins ; As input tri-stated ;
+; Base pin-out file on sameframe device ; Off ;
++----------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions ;
++---------------------------+--------+
+; Setting ; Value ;
++---------------------------+--------+
+; Nominal Core Voltage ; 1.20 V ;
+; Low Junction Temperature ; 0 °C ;
+; High Junction Temperature ; 85 °C ;
++---------------------------+--------+
+
+
++------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing ;
++-----------------+----------------------+-------------------+
+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
++-----------------+----------------------+-------------------+
+
+
++----------------------------+
+; Advanced Data - General ;
++--------------------+-------+
+; Name ; Value ;
++--------------------+-------+
+; Status Code ; 0 ;
+; Desired User Slack ; 0 ;
+; Fit Attempts ; 1 ;
++--------------------+-------+
+
+
++-------------------------------------------------------------------------------+
+; Advanced Data - Placement Preparation ;
++------------------------------------------------------------------+------------+
+; Name ; Value ;
++------------------------------------------------------------------+------------+
+; Auto Fit Point 1 - Fit Attempt 1 ; ff ;
+; Mid Wire Use - Fit Attempt 1 ; 0 ;
+; Mid Slack - Fit Attempt 1 ; 2147483639 ;
+; Internal Atom Count - Fit Attempt 1 ; 9 ;
+; LE/ALM Count - Fit Attempt 1 ; 9 ;
+; LAB Count - Fit Attempt 1 ; 2 ;
+; Outputs per Lab - Fit Attempt 1 ; 4.000 ;
+; Inputs per LAB - Fit Attempt 1 ; 9.000 ;
+; Global Inputs per LAB - Fit Attempt 1 ; 0.000 ;
+; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:2 ;
+; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:1 ;
+; LEs in Chains - Fit Attempt 1 ; 0 ;
+; LEs in Long Chains - Fit Attempt 1 ; 0 ;
+; LABs with Chains - Fit Attempt 1 ; 0 ;
+; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;
+; Time - Fit Attempt 1 ; 0 ;
++------------------------------------------------------------------+------------+
+
+
++-------------------------------------------------+
+; Advanced Data - Placement ;
++------------------------------------+------------+
+; Name ; Value ;
++------------------------------------+------------+
+; Auto Fit Point 2 - Fit Attempt 1 ; ff ;
+; Auto Fit Point 5 - Fit Attempt 1 ; ff ;
+; Mid Wire Use - Fit Attempt 1 ; 0 ;
+; Mid Slack - Fit Attempt 1 ; 2147483639 ;
+; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
+; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
+; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
+; Auto Fit Point 5 - Fit Attempt 1 ; ff ;
+; Mid Wire Use - Fit Attempt 1 ; 0 ;
+; Mid Slack - Fit Attempt 1 ; 2147483639 ;
+; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
+; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
+; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
+; Late Wire Use - Fit Attempt 1 ; 0 ;
+; Late Slack - Fit Attempt 1 ; 2147483639 ;
+; Peak Regional Wire - Fit Attempt 1 ; 0.000 ;
+; Auto Fit Point 7 - Fit Attempt 1 ; ff ;
+; Time - Fit Attempt 1 ; 0 ;
++------------------------------------+------------+
+
+
++--------------------------------------------------+
+; Advanced Data - Routing ;
++------------------------------------+-------------+
+; Name ; Value ;
++------------------------------------+-------------+
+; Early Slack - Fit Attempt 1 ; 2147483639 ;
+; Early Wire Use - Fit Attempt 1 ; 0 ;
+; Peak Regional Wire - Fit Attempt 1 ; 0 ;
+; Mid Slack - Fit Attempt 1 ; 2147483639 ;
+; Late Slack - Fit Attempt 1 ; -2147483648 ;
+; Late Wire Use - Fit Attempt 1 ; 0 ;
+; Time - Fit Attempt 1 ; 0 ;
++------------------------------------+-------------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info: *******************************************************************
+Info: Running Quartus II Fitter
+ Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+ Info: Processing started: Sat Mar 05 20:41:33 2022
+Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off data_selector -c data_selector
+Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info: Selected device EP2C8Q208C8 for design "data_selector"
+Info: Low junction temperature is 0 degrees C
+Info: High junction temperature is 85 degrees C
+Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+ Info: Device EP2C5Q208C8 is compatible
+ Info: Device EP2C5Q208I8 is compatible
+ Info: Device EP2C8Q208I8 is compatible
+Info: Fitter converted 3 user pins into dedicated programming pins
+ Info: Pin ~ASDO~ is reserved at location 1
+ Info: Pin ~nCSO~ is reserved at location 2
+ Info: Pin ~LVDS54p/nCEO~ is reserved at location 108
+Warning: No exact pin location assignment(s) for 26 pins of 26 total pins
+ Info: Pin Y0 not assigned to an exact location on the device
+ Info: Pin Y1 not assigned to an exact location on the device
+ Info: Pin Y2 not assigned to an exact location on the device
+ Info: Pin Y3 not assigned to an exact location on the device
+ Info: Pin Y4 not assigned to an exact location on the device
+ Info: Pin Y5 not assigned to an exact location on the device
+ Info: Pin Y6 not assigned to an exact location on the device
+ Info: Pin Y7 not assigned to an exact location on the device
+ Info: Pin b0 not assigned to an exact location on the device
+ Info: Pin a0 not assigned to an exact location on the device
+ Info: Pin AY not assigned to an exact location on the device
+ Info: Pin BY not assigned to an exact location on the device
+ Info: Pin a1 not assigned to an exact location on the device
+ Info: Pin b1 not assigned to an exact location on the device
+ Info: Pin a2 not assigned to an exact location on the device
+ Info: Pin b2 not assigned to an exact location on the device
+ Info: Pin a3 not assigned to an exact location on the device
+ Info: Pin b3 not assigned to an exact location on the device
+ Info: Pin a4 not assigned to an exact location on the device
+ Info: Pin b4 not assigned to an exact location on the device
+ Info: Pin a5 not assigned to an exact location on the device
+ Info: Pin b5 not assigned to an exact location on the device
+ Info: Pin a6 not assigned to an exact location on the device
+ Info: Pin b6 not assigned to an exact location on the device
+ Info: Pin a7 not assigned to an exact location on the device
+ Info: Pin b7 not assigned to an exact location on the device
+Info: Fitter is using the Classic Timing Analyzer
+Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
+Info: Starting register packing
+Info: Finished register packing
+ Extra Info: No registers were packed into other blocks
+Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+ Info: Number of I/O pins in group: 26 (unused VREF, 3.3V VCCIO, 18 input, 8 output, 0 bidirectional)
+ Info: I/O standards used: 3.3-V LVTTL.
+Info: I/O bank details before I/O pin placement
+ Info: Statistics of I/O banks
+ Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available
+ Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available
+ Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available
+ Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available
+Info: Fitter preparation operations ending: elapsed time is 00:00:01
+Info: Fitter placement preparation operations beginning
+Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info: Fitter placement operations beginning
+Info: Fitter placement was successful
+Info: Fitter placement operations ending: elapsed time is 00:00:00
+Info: Fitter routing operations beginning
+Info: Average interconnect usage is 0% of the available device resources
+ Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9
+Info: Fitter routing operations ending: elapsed time is 00:00:00
+Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
+ Info: Optimizations that may affect the design's routability were skipped
+ Info: Optimizations that may affect the design's timing were skipped
+Info: Started post-fitting delay annotation
+Warning: Found 8 output pins without output pin load capacitance assignment
+ Info: Pin "Y0" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "Y1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "Y2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "Y3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "Y4" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "Y5" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "Y6" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "Y7" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+Info: Delay annotation completed successfully
+Info: Generated suppressed messages file D:/projects/quartus/data_selector/data_selector.fit.smsg
+Info: Quartus II Fitter was successful. 0 errors, 2 warnings
+ Info: Peak virtual memory: 306 megabytes
+ Info: Processing ended: Sat Mar 05 20:41:34 2022
+ Info: Elapsed time: 00:00:01
+ Info: Total CPU time (on all processors): 00:00:01
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in D:/projects/quartus/data_selector/data_selector.fit.smsg.
+
+
diff --git a/data_selector/data_selector.fit.smsg b/data_selector/data_selector.fit.smsg
new file mode 100644
index 0000000..14764e7
--- /dev/null
+++ b/data_selector/data_selector.fit.smsg
@@ -0,0 +1,6 @@
+Extra Info: Performing register packing on registers with non-logic cell location assignments
+Extra Info: Completed register packing on registers with non-logic cell location assignments
+Extra Info: Started Fast Input/Output/OE register processing
+Extra Info: Finished Fast Input/Output/OE register processing
+Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/data_selector/data_selector.fit.summary b/data_selector/data_selector.fit.summary
new file mode 100644
index 0000000..38c08c6
--- /dev/null
+++ b/data_selector/data_selector.fit.summary
@@ -0,0 +1,16 @@
+Fitter Status : Successful - Sat Mar 05 20:41:34 2022
+Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
+Revision Name : data_selector
+Top-level Entity Name : data_selector
+Family : Cyclone II
+Device : EP2C8Q208C8
+Timing Models : Final
+Total logic elements : 8 / 8,256 ( < 1 % )
+ Total combinational functions : 8 / 8,256 ( < 1 % )
+ Dedicated logic registers : 0 / 8,256 ( 0 % )
+Total registers : 0
+Total pins : 26 / 138 ( 19 % )
+Total virtual pins : 0
+Total memory bits : 0 / 165,888 ( 0 % )
+Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % )
+Total PLLs : 0 / 2 ( 0 % )
diff --git a/data_selector/data_selector.flow.rpt b/data_selector/data_selector.flow.rpt
new file mode 100644
index 0000000..174039c
--- /dev/null
+++ b/data_selector/data_selector.flow.rpt
@@ -0,0 +1,120 @@
+Flow report for data_selector
+Sat Mar 05 20:41:36 2022
+Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Flow Summary
+ 3. Flow Settings
+ 4. Flow Non-Default Global Settings
+ 5. Flow Elapsed Time
+ 6. Flow OS Summary
+ 7. Flow Log
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Flow Summary ;
++------------------------------------+----------------------------------------------+
+; Flow Status ; Successful - Sat Mar 05 20:41:36 2022 ;
+; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
+; Revision Name ; data_selector ;
+; Top-level Entity Name ; data_selector ;
+; Family ; Cyclone II ;
+; Device ; EP2C8Q208C8 ;
+; Timing Models ; Final ;
+; Met timing requirements ; Yes ;
+; Total logic elements ; 8 / 8,256 ( < 1 % ) ;
+; Total combinational functions ; 8 / 8,256 ( < 1 % ) ;
+; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ;
+; Total registers ; 0 ;
+; Total pins ; 26 / 138 ( 19 % ) ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 0 / 165,888 ( 0 % ) ;
+; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
+; Total PLLs ; 0 / 2 ( 0 % ) ;
++------------------------------------+----------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings ;
++-------------------+---------------------+
+; Option ; Setting ;
++-------------------+---------------------+
+; Start date & time ; 03/05/2022 20:41:32 ;
+; Main task ; Compilation ;
+; Revision Name ; data_selector ;
++-------------------+---------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings ;
++------------------------------------+---------------------------------+---------------+-------------+----------------+
+; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
++------------------------------------+---------------------------------+---------------+-------------+----------------+
+; COMPILER_SIGNATURE_ID ; 220283517943889.164648409201276 ; -- ; -- ; -- ;
+; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
+; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
+; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
+; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
+; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
++------------------------------------+---------------------------------+---------------+-------------+----------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time ;
++-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 245 MB ; 00:00:00 ;
+; Fitter ; 00:00:01 ; 1.0 ; 306 MB ; 00:00:01 ;
+; Assembler ; 00:00:01 ; 1.0 ; 241 MB ; 00:00:00 ;
+; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 198 MB ; 00:00:00 ;
+; Total ; 00:00:02 ; -- ; -- ; 00:00:01 ;
++-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++------------------------------------------------------------------------------------------+
+; Flow OS Summary ;
++-------------------------+------------------+---------------+------------+----------------+
+; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
++-------------------------+------------------+---------------+------------+----------------+
+; Analysis & Synthesis ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
+; Fitter ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
+; Assembler ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
+; Classic Timing Analyzer ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
++-------------------------+------------------+---------------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off data_selector -c data_selector
+quartus_fit --read_settings_files=off --write_settings_files=off data_selector -c data_selector
+quartus_asm --read_settings_files=off --write_settings_files=off data_selector -c data_selector
+quartus_tan --read_settings_files=off --write_settings_files=off data_selector -c data_selector --timing_analysis_only
+
+
+
diff --git a/data_selector/data_selector.map.rpt b/data_selector/data_selector.map.rpt
new file mode 100644
index 0000000..d8583a4
--- /dev/null
+++ b/data_selector/data_selector.map.rpt
@@ -0,0 +1,218 @@
+Analysis & Synthesis report for data_selector
+Sat Mar 05 20:41:32 2022
+Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Analysis & Synthesis Summary
+ 3. Analysis & Synthesis Settings
+ 4. Analysis & Synthesis Source Files Read
+ 5. Analysis & Synthesis Resource Usage Summary
+ 6. Analysis & Synthesis Resource Utilization by Entity
+ 7. General Register Statistics
+ 8. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary ;
++------------------------------------+----------------------------------------------+
+; Analysis & Synthesis Status ; Successful - Sat Mar 05 20:41:32 2022 ;
+; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
+; Revision Name ; data_selector ;
+; Top-level Entity Name ; data_selector ;
+; Family ; Cyclone II ;
+; Total logic elements ; 8 ;
+; Total combinational functions ; 8 ;
+; Dedicated logic registers ; 0 ;
+; Total registers ; 0 ;
+; Total pins ; 26 ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 0 ;
+; Embedded Multiplier 9-bit elements ; 0 ;
+; Total PLLs ; 0 ;
++------------------------------------+----------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings ;
++--------------------------------------------------------------+--------------------+--------------------+
+; Option ; Setting ; Default Value ;
++--------------------------------------------------------------+--------------------+--------------------+
+; Device ; EP2C8Q208C8 ; ;
+; Top-level entity name ; data_selector ; data_selector ;
+; Family name ; Cyclone II ; Stratix II ;
+; Use Generated Physical Constraints File ; Off ; ;
+; Use smart compilation ; Off ; Off ;
+; Restructure Multiplexers ; Auto ; Auto ;
+; Create Debugging Nodes for IP Cores ; Off ; Off ;
+; Preserve fewer node names ; On ; On ;
+; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
+; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
+; VHDL Version ; VHDL93 ; VHDL93 ;
+; State Machine Processing ; Auto ; Auto ;
+; Safe State Machine ; Off ; Off ;
+; Extract Verilog State Machines ; On ; On ;
+; Extract VHDL State Machines ; On ; On ;
+; Ignore Verilog initial constructs ; Off ; Off ;
+; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
+; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
+; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
+; Parallel Synthesis ; Off ; Off ;
+; DSP Block Balancing ; Auto ; Auto ;
+; NOT Gate Push-Back ; On ; On ;
+; Power-Up Don't Care ; On ; On ;
+; Remove Redundant Logic Cells ; Off ; Off ;
+; Remove Duplicate Registers ; On ; On ;
+; Ignore CARRY Buffers ; Off ; Off ;
+; Ignore CASCADE Buffers ; Off ; Off ;
+; Ignore GLOBAL Buffers ; Off ; Off ;
+; Ignore ROW GLOBAL Buffers ; Off ; Off ;
+; Ignore LCELL Buffers ; Off ; Off ;
+; Ignore SOFT Buffers ; On ; On ;
+; Limit AHDL Integers to 32 Bits ; Off ; Off ;
+; Optimization Technique ; Balanced ; Balanced ;
+; Carry Chain Length ; 70 ; 70 ;
+; Auto Carry Chains ; On ; On ;
+; Auto Open-Drain Pins ; On ; On ;
+; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
+; Auto ROM Replacement ; On ; On ;
+; Auto RAM Replacement ; On ; On ;
+; Auto Shift Register Replacement ; Auto ; Auto ;
+; Auto Clock Enable Replacement ; On ; On ;
+; Strict RAM Replacement ; Off ; Off ;
+; Allow Synchronous Control Signals ; On ; On ;
+; Force Use of Synchronous Clear Signals ; Off ; Off ;
+; Auto RAM to Logic Cell Conversion ; Off ; Off ;
+; Auto Resource Sharing ; Off ; Off ;
+; Allow Any RAM Size For Recognition ; Off ; Off ;
+; Allow Any ROM Size For Recognition ; Off ; Off ;
+; Allow Any Shift Register Size For Recognition ; Off ; Off ;
+; Use LogicLock Constraints during Resource Balancing ; On ; On ;
+; Ignore translate_off and synthesis_off directives ; Off ; Off ;
+; Timing-Driven Synthesis ; Off ; Off ;
+; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
+; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
+; Synchronization Register Chain Length ; 2 ; 2 ;
+; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
+; HDL message level ; Level2 ; Level2 ;
+; Suppress Register Optimization Related Messages ; Off ; Off ;
+; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Clock MUX Protection ; On ; On ;
+; Auto Gated Clock Conversion ; Off ; Off ;
+; Block Design Naming ; Auto ; Auto ;
+; SDC constraint protection ; Off ; Off ;
+; Synthesis Effort ; Auto ; Auto ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
+; Analysis & Synthesis Message Level ; Medium ; Medium ;
++--------------------------------------------------------------+--------------------+--------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------+
+; data_selector.bdf ; yes ; User Block Diagram/Schematic File ; D:/projects/quartus/data_selector/data_selector.bdf ;
++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------+
+
+
++-----------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary ;
++---------------------------------------------+-------+
+; Resource ; Usage ;
++---------------------------------------------+-------+
+; Estimated Total logic elements ; 8 ;
+; ; ;
+; Total combinational functions ; 8 ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 8 ;
+; -- 3 input functions ; 0 ;
+; -- <=2 input functions ; 0 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 8 ;
+; -- arithmetic mode ; 0 ;
+; ; ;
+; Total registers ; 0 ;
+; -- Dedicated logic registers ; 0 ;
+; -- I/O registers ; 0 ;
+; ; ;
+; I/O pins ; 26 ;
+; Maximum fan-out node ; AY ;
+; Maximum fan-out ; 8 ;
+; Total fan-out ; 40 ;
+; Average fan-out ; 1.18 ;
++---------------------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
+; |data_selector ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 26 ; 0 ; |data_selector ; work ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics ;
++----------------------------------------------+-------+
+; Statistic ; Value ;
++----------------------------------------------+-------+
+; Total registers ; 0 ;
+; Number of registers using Synchronous Clear ; 0 ;
+; Number of registers using Synchronous Load ; 0 ;
+; Number of registers using Asynchronous Clear ; 0 ;
+; Number of registers using Asynchronous Load ; 0 ;
+; Number of registers using Clock Enable ; 0 ;
+; Number of registers using Preset ; 0 ;
++----------------------------------------------+-------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II Analysis & Synthesis
+ Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+ Info: Processing started: Sat Mar 05 20:41:32 2022
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off data_selector -c data_selector
+Info: Found 1 design units, including 1 entities, in source file data_selector.bdf
+ Info: Found entity 1: data_selector
+Info: Elaborating entity "data_selector" for the top level hierarchy
+Info: Implemented 34 device resources after synthesis - the final resource count might be different
+ Info: Implemented 18 input pins
+ Info: Implemented 8 output pins
+ Info: Implemented 8 logic cells
+Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
+ Info: Peak virtual memory: 248 megabytes
+ Info: Processing ended: Sat Mar 05 20:41:32 2022
+ Info: Elapsed time: 00:00:00
+ Info: Total CPU time (on all processors): 00:00:00
+
+
diff --git a/data_selector/data_selector.map.summary b/data_selector/data_selector.map.summary
new file mode 100644
index 0000000..d0a286d
--- /dev/null
+++ b/data_selector/data_selector.map.summary
@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Sat Mar 05 20:41:32 2022
+Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
+Revision Name : data_selector
+Top-level Entity Name : data_selector
+Family : Cyclone II
+Total logic elements : 8
+ Total combinational functions : 8
+ Dedicated logic registers : 0
+Total registers : 0
+Total pins : 26
+Total virtual pins : 0
+Total memory bits : 0
+Embedded Multiplier 9-bit elements : 0
+Total PLLs : 0
diff --git a/data_selector/data_selector.pin b/data_selector/data_selector.pin
new file mode 100644
index 0000000..a5a89bd
--- /dev/null
+++ b/data_selector/data_selector.pin
@@ -0,0 +1,278 @@
+ -- Copyright (C) 1991-2009 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions
+ -- and other software and tools, and its AMPP partner logic
+ -- functions, and any output files from any of the foregoing
+ -- (including device programming or simulation files), and any
+ -- associated documentation or information are expressly subject
+ -- to the terms and conditions of the Altera Program License
+ -- Subscription Agreement, Altera MegaCore Function License
+ -- Agreement, or other applicable license agreement, including,
+ -- without limitation, that your use is for the sole purpose of
+ -- programming logic devices manufactured by Altera and sold by
+ -- Altera or its authorized distributors. Please refer to the
+ -- applicable agreement for further details.
+ --
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC : No Connect. This pin has no internal connection to the device.
+ -- DNU : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
+ -- VCCIO : Dedicated power pin, which MUST be connected to VCC
+ -- of its bank.
+ -- Bank 1: 3.3V
+ -- Bank 2: 3.3V
+ -- Bank 3: 3.3V
+ -- Bank 4: 3.3V
+ -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ -- It can also be used to report unused dedicated pins. The connection
+ -- on the board for unused dedicated pins depends on whether this will
+ -- be used in a future design. One example is device migration. When
+ -- using device migration, refer to the device pin-tables. If it is a
+ -- GND pin in the pin table or if it will not be used in a future design
+ -- for another purpose the it MUST be connected to GND. If it is an unused
+ -- dedicated pin, then it can be connected to a valid signal on the board
+ -- (low, high, or toggling) if that signal is required for a different
+ -- revision of the design.
+ -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
+ -- This pin should be connected to GND. It may also be connected to a
+ -- valid signal on the board (low, high, or toggling) if that signal
+ -- is required for a different revision of the design.
+ -- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17),
+ -- connect each pin marked GND* either individually through a 10k Ohm resistor
+ -- to GND or tie all pins together and connect through a single 10k Ohm resistor
+ -- to GND.
+ -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND
+ -- or leave it unconnected.
+ -- RESERVED : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+CHIP "data_selector" ASSIGNED TO AN: EP2C8Q208C8
+
+Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
+-------------------------------------------------------------------------------------------------------------
+~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVTTL : : 1 : N
+~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVTTL : : 1 : N
+a7 : 3 : input : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 4 : : : : 1 :
+RESERVED_INPUT : 5 : : : : 1 :
+RESERVED_INPUT : 6 : : : : 1 :
+VCCIO1 : 7 : power : : 3.3V : 1 :
+RESERVED_INPUT : 8 : : : : 1 :
+GND : 9 : gnd : : : :
+Y4 : 10 : output : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 11 : : : : 1 :
+a4 : 12 : input : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 13 : : : : 1 :
+Y2 : 14 : output : 3.3-V LVTTL : : 1 : N
+Y3 : 15 : output : 3.3-V LVTTL : : 1 : N
+TDO : 16 : output : : : 1 :
+TMS : 17 : input : : : 1 :
+TCK : 18 : input : : : 1 :
+TDI : 19 : input : : : 1 :
+DATA0 : 20 : input : : : 1 :
+DCLK : 21 : : : : 1 :
+nCE : 22 : : : : 1 :
+b1 : 23 : input : 3.3-V LVTTL : : 1 : N
+a2 : 24 : input : 3.3-V LVTTL : : 1 : N
+GND : 25 : gnd : : : :
+nCONFIG : 26 : : : : 1 :
+b2 : 27 : input : 3.3-V LVTTL : : 1 : N
+a3 : 28 : input : 3.3-V LVTTL : : 1 : N
+VCCIO1 : 29 : power : : 3.3V : 1 :
+Y6 : 30 : output : 3.3-V LVTTL : : 1 : N
+a5 : 31 : input : 3.3-V LVTTL : : 1 : N
+VCCINT : 32 : power : : 1.2V : :
+b7 : 33 : input : 3.3-V LVTTL : : 1 : N
+a6 : 34 : input : 3.3-V LVTTL : : 1 : N
+Y1 : 35 : output : 3.3-V LVTTL : : 1 : N
+GND : 36 : gnd : : : :
+a1 : 37 : input : 3.3-V LVTTL : : 1 : N
+GND : 38 : gnd : : : :
+a0 : 39 : input : 3.3-V LVTTL : : 1 : N
+b0 : 40 : input : 3.3-V LVTTL : : 1 : N
+b4 : 41 : input : 3.3-V LVTTL : : 1 : N
+VCCIO1 : 42 : power : : 3.3V : 1 :
+RESERVED_INPUT : 43 : : : : 1 :
+BY : 44 : input : 3.3-V LVTTL : : 1 : N
+b5 : 45 : input : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 46 : : : : 1 :
+RESERVED_INPUT : 47 : : : : 1 :
+Y7 : 48 : output : 3.3-V LVTTL : : 1 : N
+GND : 49 : gnd : : : :
+GND_PLL1 : 50 : gnd : : : :
+VCCD_PLL1 : 51 : power : : 1.2V : :
+GND_PLL1 : 52 : gnd : : : :
+VCCA_PLL1 : 53 : power : : 1.2V : :
+GNDA_PLL1 : 54 : gnd : : : :
+GND : 55 : gnd : : : :
+AY : 56 : input : 3.3-V LVTTL : : 4 : N
+b6 : 57 : input : 3.3-V LVTTL : : 4 : N
+Y0 : 58 : output : 3.3-V LVTTL : : 4 : N
+b3 : 59 : input : 3.3-V LVTTL : : 4 : N
+RESERVED_INPUT : 60 : : : : 4 :
+RESERVED_INPUT : 61 : : : : 4 :
+VCCIO4 : 62 : power : : 3.3V : 4 :
+RESERVED_INPUT : 63 : : : : 4 :
+RESERVED_INPUT : 64 : : : : 4 :
+GND : 65 : gnd : : : :
+VCCINT : 66 : power : : 1.2V : :
+RESERVED_INPUT : 67 : : : : 4 :
+RESERVED_INPUT : 68 : : : : 4 :
+RESERVED_INPUT : 69 : : : : 4 :
+RESERVED_INPUT : 70 : : : : 4 :
+VCCIO4 : 71 : power : : 3.3V : 4 :
+RESERVED_INPUT : 72 : : : : 4 :
+GND : 73 : gnd : : : :
+RESERVED_INPUT : 74 : : : : 4 :
+RESERVED_INPUT : 75 : : : : 4 :
+RESERVED_INPUT : 76 : : : : 4 :
+RESERVED_INPUT : 77 : : : : 4 :
+GND : 78 : gnd : : : :
+VCCINT : 79 : power : : 1.2V : :
+RESERVED_INPUT : 80 : : : : 4 :
+RESERVED_INPUT : 81 : : : : 4 :
+RESERVED_INPUT : 82 : : : : 4 :
+VCCIO4 : 83 : power : : 3.3V : 4 :
+RESERVED_INPUT : 84 : : : : 4 :
+GND : 85 : gnd : : : :
+RESERVED_INPUT : 86 : : : : 4 :
+RESERVED_INPUT : 87 : : : : 4 :
+RESERVED_INPUT : 88 : : : : 4 :
+RESERVED_INPUT : 89 : : : : 4 :
+RESERVED_INPUT : 90 : : : : 4 :
+VCCIO4 : 91 : power : : 3.3V : 4 :
+RESERVED_INPUT : 92 : : : : 4 :
+GND : 93 : gnd : : : :
+RESERVED_INPUT : 94 : : : : 4 :
+RESERVED_INPUT : 95 : : : : 4 :
+RESERVED_INPUT : 96 : : : : 4 :
+RESERVED_INPUT : 97 : : : : 4 :
+VCCIO4 : 98 : power : : 3.3V : 4 :
+RESERVED_INPUT : 99 : : : : 4 :
+GND : 100 : gnd : : : :
+RESERVED_INPUT : 101 : : : : 4 :
+RESERVED_INPUT : 102 : : : : 4 :
+RESERVED_INPUT : 103 : : : : 4 :
+RESERVED_INPUT : 104 : : : : 4 :
+RESERVED_INPUT : 105 : : : : 3 :
+RESERVED_INPUT : 106 : : : : 3 :
+RESERVED_INPUT : 107 : : : : 3 :
+~LVDS54p/nCEO~ : 108 : output : 3.3-V LVTTL : : 3 : N
+VCCIO3 : 109 : power : : 3.3V : 3 :
+RESERVED_INPUT : 110 : : : : 3 :
+GND : 111 : gnd : : : :
+RESERVED_INPUT : 112 : : : : 3 :
+RESERVED_INPUT : 113 : : : : 3 :
+RESERVED_INPUT : 114 : : : : 3 :
+RESERVED_INPUT : 115 : : : : 3 :
+RESERVED_INPUT : 116 : : : : 3 :
+RESERVED_INPUT : 117 : : : : 3 :
+RESERVED_INPUT : 118 : : : : 3 :
+GND : 119 : gnd : : : :
+VCCINT : 120 : power : : 1.2V : :
+nSTATUS : 121 : : : : 3 :
+VCCIO3 : 122 : power : : 3.3V : 3 :
+CONF_DONE : 123 : : : : 3 :
+GND : 124 : gnd : : : :
+MSEL1 : 125 : : : : 3 :
+MSEL0 : 126 : : : : 3 :
+RESERVED_INPUT : 127 : : : : 3 :
+RESERVED_INPUT : 128 : : : : 3 :
+GND+ : 129 : : : : 3 :
+GND+ : 130 : : : : 3 :
+GND+ : 131 : : : : 3 :
+GND+ : 132 : : : : 3 :
+RESERVED_INPUT : 133 : : : : 3 :
+RESERVED_INPUT : 134 : : : : 3 :
+RESERVED_INPUT : 135 : : : : 3 :
+VCCIO3 : 136 : power : : 3.3V : 3 :
+RESERVED_INPUT : 137 : : : : 3 :
+RESERVED_INPUT : 138 : : : : 3 :
+RESERVED_INPUT : 139 : : : : 3 :
+GND : 140 : gnd : : : :
+RESERVED_INPUT : 141 : : : : 3 :
+RESERVED_INPUT : 142 : : : : 3 :
+RESERVED_INPUT : 143 : : : : 3 :
+RESERVED_INPUT : 144 : : : : 3 :
+RESERVED_INPUT : 145 : : : : 3 :
+RESERVED_INPUT : 146 : : : : 3 :
+RESERVED_INPUT : 147 : : : : 3 :
+VCCIO3 : 148 : power : : 3.3V : 3 :
+RESERVED_INPUT : 149 : : : : 3 :
+RESERVED_INPUT : 150 : : : : 3 :
+RESERVED_INPUT : 151 : : : : 3 :
+RESERVED_INPUT : 152 : : : : 3 :
+GND : 153 : gnd : : : :
+GND_PLL2 : 154 : gnd : : : :
+VCCD_PLL2 : 155 : power : : 1.2V : :
+GND_PLL2 : 156 : gnd : : : :
+VCCA_PLL2 : 157 : power : : 1.2V : :
+GNDA_PLL2 : 158 : gnd : : : :
+GND : 159 : gnd : : : :
+RESERVED_INPUT : 160 : : : : 2 :
+RESERVED_INPUT : 161 : : : : 2 :
+RESERVED_INPUT : 162 : : : : 2 :
+RESERVED_INPUT : 163 : : : : 2 :
+RESERVED_INPUT : 164 : : : : 2 :
+RESERVED_INPUT : 165 : : : : 2 :
+VCCIO2 : 166 : power : : 3.3V : 2 :
+GND : 167 : gnd : : : :
+RESERVED_INPUT : 168 : : : : 2 :
+RESERVED_INPUT : 169 : : : : 2 :
+RESERVED_INPUT : 170 : : : : 2 :
+RESERVED_INPUT : 171 : : : : 2 :
+VCCIO2 : 172 : power : : 3.3V : 2 :
+RESERVED_INPUT : 173 : : : : 2 :
+GND : 174 : gnd : : : :
+RESERVED_INPUT : 175 : : : : 2 :
+RESERVED_INPUT : 176 : : : : 2 :
+GND : 177 : gnd : : : :
+VCCINT : 178 : power : : 1.2V : :
+RESERVED_INPUT : 179 : : : : 2 :
+RESERVED_INPUT : 180 : : : : 2 :
+RESERVED_INPUT : 181 : : : : 2 :
+RESERVED_INPUT : 182 : : : : 2 :
+VCCIO2 : 183 : power : : 3.3V : 2 :
+GND : 184 : gnd : : : :
+RESERVED_INPUT : 185 : : : : 2 :
+GND : 186 : gnd : : : :
+RESERVED_INPUT : 187 : : : : 2 :
+RESERVED_INPUT : 188 : : : : 2 :
+RESERVED_INPUT : 189 : : : : 2 :
+VCCINT : 190 : power : : 1.2V : :
+RESERVED_INPUT : 191 : : : : 2 :
+RESERVED_INPUT : 192 : : : : 2 :
+RESERVED_INPUT : 193 : : : : 2 :
+VCCIO2 : 194 : power : : 3.3V : 2 :
+RESERVED_INPUT : 195 : : : : 2 :
+GND : 196 : gnd : : : :
+RESERVED_INPUT : 197 : : : : 2 :
+RESERVED_INPUT : 198 : : : : 2 :
+RESERVED_INPUT : 199 : : : : 2 :
+RESERVED_INPUT : 200 : : : : 2 :
+RESERVED_INPUT : 201 : : : : 2 :
+VCCIO2 : 202 : power : : 3.3V : 2 :
+RESERVED_INPUT : 203 : : : : 2 :
+GND : 204 : gnd : : : :
+RESERVED_INPUT : 205 : : : : 2 :
+RESERVED_INPUT : 206 : : : : 2 :
+RESERVED_INPUT : 207 : : : : 2 :
+Y5 : 208 : output : 3.3-V LVTTL : : 2 : N
diff --git a/data_selector/data_selector.pof b/data_selector/data_selector.pof
new file mode 100644
index 0000000000000000000000000000000000000000..044a1d034d6f8d99d641e91da09cc82284fa9268
GIT binary patch
literal 524488
zcmeI*3zQV~o#^rEcFYdZB-1^OX+{a%MS%?r49uW{5SeZY(#^x+8O@1zl~j48vo5%K2O?pDVw!?xt87olw|p}+cgD<6>^qxp+!$(YyCgL8(w145wY1KhIXAR=
z(@i&T-modOV%>&63AKh+F9}_>X?uGBGX}HJlpQv`a_>1#hn90cQzAw8wqT;~q
zXP$ogt_RLM`|MvfJIg=)>;um|+kC!ZI3tDe!lp~-jW0QDFR|(j!x<@z_ixd7?#y$~
z{ge85Qr0(kD2A#q&xfzS{_`1AO$q;?A)q3NI+)Iy&Zww$ZO_=T*Y>>s_~UP#H~+1+
zwzhK&!(Mc1jhgD~@%b7(#x-huW$|ORbKoniXhHwd+j>6#`CDi8G&Z(*j9b+Bw~HTJ
z`=d>N5Q$E%n(a2dpDEmxcdEvAHMd&
zd|0kg<6kX)tnQC<<@+qw+j=j)_}13mi4)tr#w}|6rsBue{PBC>cYpS0KfOv0K;FK5
zCClEn?T&5lTz~zomljr|#&0fuY*i^^eyFhQnWvuWxaGswUc2>*!m?`ozZE~WepW45
zgWcKr`1?nXE}eJz#B+>gGS;!Q__5I0^}&(l^|K#-_-4ynt*tV*;VgZ_yE}JYA5mw^
zjWV`H{poycaMIMl+jin?F~Zo3)@+pYPc13mk`#Vz(*@4H&c0-I+a)SeIQu&&ni$2<
zINycSq2?YMk*SAFbuKyIGWxInvpqeZfBfMK^9Qys0V&5-iN{-)U;fjH`Q3d$jo(}R
zxL3kgbHkY(S7&zw1;H69jLX^Cx6}E=<{!?!|Ni4e5~Eqtsg^=w)i++8pw8_zYu2tE
z+n)$LclOMgpD$2{PM!C5Pav?=N!^#pSVy$@u~412vaG!*pw1;H;ky0oyYJqnmUPZI
zwJ(LC)_i>lr881YG>c2-zkl`N8*jYy%Xe@XD&yieqZMVIwUwnf1o>j@Gg@
zRhghRpgBC!=1F>!VjVEzVw=iS$%F#DqurH~AKRmK?Oww+j7axIx5?T~W#g5AHhBE%
zLzI1?{C0hEu*^n}5%S26gpI~}W1=TiZ%mqVyQMZ}$x4%T@)3+%Mj)B8z3rZ0yEkH}
z4+%%GDHZb^Sb2fBE7cU1U%OJaVI>cBULXO8bU(aUHY*#-BZb2G5UVZcx2`~qnJE=8
zU!4#~B`nX)QX$qF+}WvBw#)Vg4t+6I9XX>x!YBVj-Uajf)8m1&R~VOrQekSc(!}oH
z{oe|+R-BZa*XT?SRQy#Ys^I2_q<6wTCkH4_sQN9sU5{;5#bT{N&Z?n?_WS`g9+H6)4bFD&LDXyUE_kw%=sPs2EO9u?<@D}8fJ||@#
z@MG0c4Ti$9#e-I1RZjBQKfT@i@_!i=H2JBJX!Xxj9P9eWdkf6PDfyE}{bd#>6~E8E
zqq}3_u4meuVpDO^0pI-_kh+93{eOOGz|WE?@nhg9O24{m-de!ub3Ri9Ct3wdJ$gdOUEk?v}>
zijd5AeIh!+NYmy+zQpLeprCKt-g{dkLHH_|if1zej>u(5q8oWv8P^ncpLuk90
zs3GYId0JHvg2t7R)%OOI#W|c`3m<{}stvzdUacu)d1R69yS_JYuEFDlMbtz!+I8n!
zE>7_5;B^iDYhVz&{(54y)v8?y8o~S?shySoe*azec}A7B%TbYeRAh02tTq$u+IX_;
zo8TLkvuDkB_q$_T~XmY}yEJOjBr@_;nI=!vF3XDTn_)xnnK;xeH
z(|p~g!Um*{?>GESp3p(x0d;B|P+7UE^&jwc-}+A#7N|I>MxvE0o=s}Okh1@;r<3&&
zQ%Vw2my3mLpOhJrk!(28>LBHRkz&B4b7L3G@-;~KnhvJY!JIYGGv%NJaZanf&>Ial
zJ+bzo^YSG|RaTJ|C+np+AuCO)4=GZl&NaT^QzHj`St*0$_bTkSW!L;2<3E)(%!tfr
zgfevvQCU2l^#{Y2nvj+i9Po+EDk+)F@&#o6rf@hLN%>-F6@uX92g6Z2dC+&wCEquy
zMNqZsfy1retdhSb)!7-65Bcw;YAQ~6#y7q4-^0_QkrrQFi_hxyN6i-B;q>(A)MuhI
za)BAS#iz|FubOkC&5uTp+qI9h;GBd`d0$Ues#tiCQ~*qgHN$-I^P3O-rc%%Z}viqdDtHZniZox-|XM
zo0pz8!>^jN*3Ixc8#^XnJC8)oN29GLE|mGl9oe%t+%m3CZ7ml))H3ey_7>k!^F{xl
zP5wsaFA43>qDOLj!}Aj3`hq+AaLc%(v)}bc|0Fj(+F>SotlVPxAL}ruykq5-TFY}+
zTFs~JfBm;PUkTMa$6BRwDj{}`vV1#-wJcKDhH>`S+4_OUq<>r`BZU;AkfInr?78>+
zbpISR#zLMz_ld_PQakgMM@Biq{S(vb6o|A-x_sl@-Wn^Fg$jccJ6e8ICFI4q`oAj|
zCi{OMF!r$&O9rgZ8FgQvE?tBCojs7>04pYIHBXN-d-_)F>j9E*_Y0+46jL6P0{T
zWi=l)dz0*@KcmV?uDDk+$4Fm3wNP@#rIM*G&0X}il?!x8-YB_@jK-GdmK-bOGxuHk
zcjJ!uGrj(Gk{Ore#3v+6mHc#%)kuQA~D}NU;|5&0_hyBO2_!j
z7w<@yLRa~_y=UV+$!a-e=`y}+<~|gPL?lX-M=fXG(jstF%HCt2C|ympzgJlLs=tG=}eMjI>XEJDqnH>h^v*9BEQ=C<-yATQugU8cPLxB%7o#G
z1LMD4^~yzAIEF70xH^Z&H=lIQv$F7&PY86MK3P7s@|5B6br%(qrj!39t-4siCmB#S
zU*ii)PE+HT*leqzuIrr*pQ=*kSNkg`$DqnVyTs~0KPO+ylS}S#!zVw7oZ6kjty(Gc
z+jYk4mrSTkSU&aTc`4lz`|;?d_vEvfXt!Tg^lH`EhRD)tRTC%J$NUrQ^^pm-DfPaI
zFG|(xl>C26>TmY6gjvj6zW#TC8UEM|f8%e=vfQ`4x@P@HE_%7t)}~2qZD7rG-He>%
z+k-+|p{BS{mR_o=ij!aT56*(ucbJdbC#>H}n6I?%ymQaFg(^Ym;dJEtt5@m}CcU;{
zy!0=3y7AX79R|8jKIAeaUF#aPOV`7f(3Ho}N>kjOw3XISVcJMYUn&Hv(xlN9)O4j?
zs4z_x=qgOEIBB>9!u9Ub=)nHfa*0lF@Xi0?Lwa)>#z-h7)~do)ul9Z9%H28DD{-b`
zE3fli7n54yoB!^j*e8cqZwPe!tz3ju*Al7R^<8T%t=vh0L}g@U^*D#Pyh7FW#>p8j
z{KvRDuUv)1=w5eFFCIuXU1*-xn13Xkv>L%wvk=rqO{rmu0Hd&8_p2-3&@^lJOt_+2
zdwba`MnYk3sD{4EO@OL}&$w~H*IbsgSIn(Ze{&Ml3e~-+ZFK$dTiRLOV~x70r!jux
zL(&*W8(z&eylTyLDmEv}tM1)zyrJzc*U_ogIjO=(ND0c4r^*uuYU60C)=5*5ldzVa
zs?NbJzbw<<(>y(?SyXL!;$+*XYHgh=Jz8a0QWsz0YnL80*#n)&O^+p$YW=d@YOgc4
zZ26SCBEPYBmdKlGd*#(Pr^sHd$?lJ}FJVdn-Az<1Ts3?u-(FX<;jPwH%G#}cvn{z;
zXuTk9V9%6v4moArZ#5S#7k+)~J^74xXTImmzzeEnt!|G-pUqvU8r`h*QwH^)kp@4f
zJIjF3mN)oKu%DHlGpfaJ@{gn!&A_Xwo0s+G?8!$9eQ4g?CwI0u2TZrgPQO@aNR#Pj
zbn`{$Y6-PEW0>k6WMJAAz|mG$R(&PZMVZv#PMuMe3db7iRsYF>-70Quy;=RDGmJ8c
zi0RbOjHG4Hi3d7M+UuNFIn}u{v)%TMDe2wmEcmNg_e<_2tu!)Mdwp5+oD}>sl7SBB
z(J8ZbPuQnwcT!!GLy!r?gC(6dRr{Q3&r4-W8}w8SFZarjt>`K=YH(M>dokMUk1y->
zC+wC^$z~GLrz9bLN)k(Re<2N8d-Hut=EghBxrybud!)x@LV8>#q{n5#%I%jPmp_r#
zxA9iXuBWV)yY07g3A5#H$>TaDkIP9OmyiyS@8vr{ZkN^VIb}VXI3~*-^Y532y#3OU
zmyj$cp&Igfa}tbP+-}(=T`=PkjQG;@cYCEn%PiUWtj!(fgUe4?vgLtWKe69F^5av9
z-aT;%Lf_^Ox7@8dU?!vkX6g2&2j)LZ56qGPe2}pID)AF*!7ddFfw)^jkdUUmgf#7S
zO4DAhMB)Z%+goW5bs9ZaQgc7Gv5y3%)3Qilsazaj!xYtQ=ea
z;j%4GywUg=Wv98u9;sQ#@rEbIbJM0$?Z%3-LpXc~%jJ2~J^AKOa81yu)foru#q~QXb>z(bvMi=lnc%ioSjd19%l(r3mE=Dkckb7h_f*Y<s3f`qH4n+k#zCk#o#VaevAuj)Ze;s+ZcM92wPXxp?`K+T-uJ
z_IR;oBfTO0dENFWRaYn~wUmIAtWH9u)&tKJgP9RF_vu
z443gMX&$qjHmG>)_CS1`G(yS4OQt;G4_jg!F_$@YjHLBcJhfM~LuJ$Z{LQ|YR~i)Z
z3wF2t{YR?|x-8@xs>-7|sM3;YF7&Hs{)MdB@l>Zz+A`DWoPVNEJsUM-wpvkj*2ZGn
z1Hp0f+)cUTcgie(I4si&3oiJ!>fT^FvxTfcFsL3snoj%kGlfiN<+6fQO08R#4?C;Q
zFLLIJd742TW&Nw~K5UPDA#1PfY+C1=)SCMn|9#mh2Rp6l{;BKDMYFA$)(@?zu~YUT
zd-0m=_BFmeb@>He4Sp|mzwbvY&52{CrFQT0HziJ(2hGW=r15m2H*v_cms?9V+B@dN
z$IeRpFtNmbA$vHx^FCirHgQYaEt&Y0(aetc^S2~vL7z33dKV~c}V2ge1X*~50`
zj%<3jv*Ht-s+~-0pg695U5!hS+Eirs?k+)UovQSTBC*mw14*p3sYt9ytn?CK?jdv<
z%=EB0tvIdpVhX1fr-5;5Ddy8{>Pw$6xapeZdkM;2YL*FIxpXUZiy14eG%3MFtt`u|qK%2_#^#iJp
zazd*3#p8AIDU&=vmB;H?6W!iu`TKpmj(XlQ&)3OEShp!&Uj|%rgxpy>%W;)EkE;5k
z>${u-w|?_HSC53O83+4+bVaP)g5|EU?|?b5YYFCIC)}Dpzuij*W!#yk-FVeEHA+6ZhO*-9tg)K1?qiG=9*aQZ^G8q8Gj%=)%lv1`C-r;>p$##wPu_dBf*2t
z{1?X3iy~3qA?NGCSpBZ>s&I6P^R=+vSyx)-pWeD~Z7g{(W-Y1@1gF}oGF{;%@x8$n
z;fVS=9=785g#(i^&e!yeGh;TMa^}D2P{!Wn8Jl*##>di`rr63@Tzx$st9RCwRr9wj
zJU3Y{#gn0``T?We)8Luk_GG_R?J@FiYOJ+mNdK=RyP*=R9=z98QDh*K$Xnc8cM$%Gwt*YmTVL
zgw~v4z>mX~eaN){m)E5NEpL8qsA6<6;MA`}_5KEV4q=VAV9+{i^}oQ2)>-}5S(SXa
z>t^q=or(9KxJvemiQZ7(qpSw)woPBX%}H|@WfGcuHLBVIhNlFiDMe!t35<3Gi??>rEjTcQ=ZaZWC-d|Jb<|K4m-g5aC0L`FKH2Y8A
z%#*6uj4Q{Zmug?f8oqet^1M;+86B!|w6OpAmuqWcjD%te-6-=1i@Weld1v7WZ|9K{
z#?^V~vIuPO5EmZeqM3Gog0DxoZ5`dRUi&TFBO%ArJiscbyra;;;vI!cbMkikKTOq8
z`vET9|KqDP@f1$(;j236r5>Z~3Yp$c4O^C{+eN^TLb~=%2JWsAY70nB*JbVTczD5w
z(z{k`2y~x(NNYx!X(Yt4Pk1juSC=)o3vZ;~g{P7a>W}&KWhA5?nkgMY)qhro6aqC>
zhb{kb-%YT)?F!wJtI<4XtL_etghJpayzNnrwcfy8c-AwC4(`I^E%$ooi@{5T+}v{D
zs-UiW1codBkm|0>-nH}FuAl}P=#)Edv*}>Yn&=5j_1BEewi@cX#_##G+pbQ=+0+;#
zl=j=|)$Xx)D&q@CulsBy<%_BQ_huw&%U389hzFz6yC$9W2g8<{;w;iU_m?uRHM~5}
zRm7wQNe%Kc?HqErk|(X0Ei+Lq8v%`_!`#As!2Fg~7nOs(r0xfq72_lUK9D^y?puDZ
zB*4--_NAD*U;2Rkt$6*PdwhnmyZ*gXy2M(?*5ugq>=yv+!
zS~5GjBY3s%LSJyw`bg+tcH(_L|D+>kdX;U+tYTsgyGw&nW7krQSQY+1!
zUjObn>89{XbD9}hWY?Ju&c^J_nrvq5xZh8}H-v=^W0+
z!K?0<)ZG#1RrkE=e*KjFc5Ch@R-eSj^N=0wJ0+zv@)+HF&YZ{6y1e7d;5j=qR_f-^
zu1fx{x)bV#V7SVY?)$lp?|tQSu5QrM+{NK4188pExfaTUcJf+0Xy*_2pq(G+-maq_
z)8(qix!Y%k@J0nUw>QxBOEaaF%v3Y~a9&ugxz=IphUvNv>E?xnUFkOM=kkn%E{i;D
z$BB+SY-cn)Y={a_BeLpE
zlwG-3&M#^Y_5E0*?j7DG{B^$pkvmz)r$tLS}doFP9k&RsE+#;K-TU@_G-65Mj
z5WLR0K{mfgcTW3R0xseuRYrm_<^Bqzd_z&O2%MoU$HG9Lw#u
zkNNl8>m&PZrxEbQ#F5;oXm2jQO#a&~yDa%y*z1okO@Fty_^z(a9p;0}Pgp$(t6Bc<
z>`hp*7T3?o+4GK-`)6x;X#hS*SbvrHiM3#t3Pr+hxm!YzSoj~g#M138oku6Xn0wpG
z?d>o(OJL^4<^K&G=A+9_SntIpFmdb7FEoBu%09L_8{+Nt@(c`(*sx_iRmfuU!A(+J
zkELSXcQ(`>87-GPR0H&!wl8_xuYNk%?!6&Idjf
z3J1J1Q)+4`Sl8f>cvY~~Zw>WnXAgpw)VXE9r~5X1RySOuDjhk?fB*srAbY2cbrmg+15+=V2kt!SJ?a*q*%@oY7ma@(
z?XFiV`AiJPK>M~w9lXH!=$n565BdQHd^WI{1$^AUAjijSGK&?#sLZTnRpo2Ods&qk
z{2~~PBEMp?id{eXxBt3>+|zN>{e&L>_*Xyu#V>#Lm*z)5GC%n9KmE^N{QUD@n1BEI
zFaGk2KmRlH2mj>3eDbR=e*QD_{eSk)&BMR={eSu|fB*Xr4}V~O^7$|R%NKw0x%u>`
zfAXKq_sviKjrk9s|3~wOKl|dBWY*nwugLKqe)|0%eDufPfB5JJA9XLfcS-Z_{_K}u
z{PO3Y|E&9VcSo1M{XgAr|9-clGl-#oi0QW^?|1*|f4+c{tmKb~kSZhZM?_eb7+p8}dyx$r7r2jj|g%
zq!IA$)=@cJG9*|m$5fgh%`cG5D?GH_iPz*}PtaUjhmEdwnBEdwnBlmSyW3$=)xqJFwX
zsT+UueqsjfiT1L&k<~}F9*CE8Jka6LgK%5k(;yjqgpnypa
zjR?;p0;H<=s@~0P?^Q;$n;ph{gF3Uy(t69W_)?cf$Pe??uCE~j
zDl_u{RrvOaoHuwyP0dd{>)dp#*!WAj@~FJX%q%h;-iVwftSPP_11dA~_*D3LiG28`
z3chJVGJJJ}PQ(?ruc$zUTLJ_`u*WSTBp(J(Xo5<1N$6z@Nv
z@^TeaXn+R7;e^#`p=CnRI4ET}OH{OfpbWVi3h5PD_pp9putJRL4~4$2rNduZELl@s
zu=mJe)TAm7ed4QN3OtJ_c;pU_Yb=tox)>yNzPOLb<~NjI^DR303pyU@Hr4(^(bIdK
z2EXriztatfVE+yINSagycl^#!oea++0wl`LQeAj;@2I;NN9r5O>%E~9E+2O~{FXXL
zK)h?H@#t?yL5Q!kq_iFbm^ptRiHX1Ww-}68;8ueDOv`OWFYH6S(g+IRk()<5HDhv
zPMXw>0bx>xXAupz;f~(tnzRf|&p;2T*vCX4Iz08r)TNUqRv~&V!#(iXz!DuaWz`Jq
zs(P>QJnKMNmlW$(;T|SH$fIVZ89Dqnx$X>@D&Z|1YdxZgEbDO*yD`q0^w1RHag02a
znVETnq73&ajuFuyS=vmvxvVU?S9VoGwpG05PSHhHmoiBnscNqS9ehWR83L-pJxqX*
zhk+a;(jktT0FT2aLEwF^)S1H5+F6rLWS~csVjmO3*Wsy0mYG@fT84YzvwbhM
zt0#|hUE8?^lkjE|>NL=jY5dU|-BCmiF!3_$Kv^G)i1ZAo3hx00;z%C_EDE3sJc|f(
zif%#r;ADM4L!XV*Vdm=T8#;^5%q$2U9(!bMB4=SWMazJa0hO7#oeJ-PpGo8}nMLF<
zs3y;foM&WltDn;j(^{RGSsHYBBXX9ornrI(sLagcQ{g@E=OFTJuJT%>r;^mU>8KR!
zx!vl_%%aiZjmTNTn&JvFpfWR$PlflupM%IzkHZ5P-QWcG&{#sXba46L7<@-I4t5p~
zw{#>;ssbhZ;s|1)kl|TGfY2Yx#iM2u%J(0ra*J!Z3Mxo#Hh{4@(F!i)%|I){9ZFK8
z0g3X;bsgUW^3ulg{pUBrCKiuqpWx#j6e#4KEc^b3^VfsD3}^dXxcvl8;m;sXu+$)r
zT4A}2?@IZGz}Qv7#oY>aa0sHvFyVgdOr|7+m(`RxK~4e4VkJdZ+uBr0FuO^!>5mhGqy{Zy%Qb&
zK*)gbFo`pO+y*6w;-Qe?SwzF^O&;TiKHGK6K+Hh-
z&UJX~k&Vb%;;;rb(t-o97L1$*>REI|*
ze^s7hGmlV|;c3_;i0I%gRhla8I>T+duM&8_(5ueOnNvV@csRDr=j~
zuGYFR3mtjb$$jk5BcM3S@H8Xn0W0=V6ej8E42KL)!zMuhohiY|Oq=6ye;o3J2wm0H
z;kL;^ECJflXoJyH@J|g;nR#quJX7JRM;3;`T0|a$Y0oVKQ!?NInnvV6dOQ^2ONbl}
zdpwA|pN36>09s9aHP0J&Y?e-jFWYWs!ZMP|%sfIBo_b_q7&Id132mDC8Stp0$jq#M
z9ey?<-{vasXDpqoDFVH$=Iw2Bq%t#atO{>L&J)%&m(PGl2%95v1a0sDM#plPr32q$
zm;bJ#C5Qo{2*=7nKwuff(a|MMw1F}cLy$7u0vjW8xagjywPl-t${wh49Ug1oS#WTK
zRxoj-VM&9MH`+oQ<%KEzcu7Qz&+pSMmIm)p7Z7QmO46ilCZo5fGk34SU)qCxF3f(4
z;>{G$Y|QJ~7QrC>R?0VYnQar{{=VM(X%!B42V>h
zC7>Y92p;Idfk=`j+5pC+4EMlhbUh4O=AtQD28tQTI#AXnMH3b7VFH9a3_`C*DU&z?
zJW9${;O4MN%fQ?W^e_3imK+L@p+7(@M-c
zH!MA3Uz^C4Uy2Y@HE%{Px@gL)$^hL;R*V+CUS?MR~Ngw$L6q722^I|b*gX=JP`6QXiFyB8S(?M2;$^$@3!TX*mg~#~Ijb
zf({e2M&#G@nzUGIWI$(TR-+C-7m-^Q*CrHoZX!d|`%NU^Qb9H%zf|U1z30k+&de+d
z9eyq%5A!T6CRqfCs~sJVj!q=Y9YJ(BRu01I6zmNhUDQ}ygbH!8FZTo~!?TD?uyccT
z*=8u;d$e?}!X3as@GKZ;(F!JpG%RUQ@4)kg=;_(s(OQ`XPkT^;
z{R<;(d^vDQm*%!B!`%%9`^sSzn-T(#i-h*otS>I~t@(bxA(L!ZO8Pk!?(4&@Q{bjc
zKXuZvT`8#w?)5w4wwB}|!P(ELM0e98O`7hiUvIuY*B
z{j+^8!3LeZyf`4#aSR?O5PVmPhd0orDCxTw(SZjnva7?OPLN^HqP$7Vz@!Z19VqK#
zlD!UpAd`Ubur2jbl;z@aDZ{gfii0F~*REOyvJ6xq^16SI+++=C7cB!vGN3avGuGja
z$XUYP3WeQxE2zOJoL-1FFMgkDNo~NJnDn=)j{X
za<50pOffU@)8M;lu!g#L26Sd-;py;57NkA}C3xzQg;68E**>3B9`x7pHRta$`4
z_c5tiI{aKjE=AUKEd!+t%ph{OP~nS+9A4!?wi=P6ifQt!$az{y2Gr7d!kjuPU|sO(
z@hJDPP=4^>ab1KrB0or1yS!)y;th?;%sfIBeikCfBx|FqyfNoIttV^h+;p5A)^#}W
z2&2f%EJhvPh@2&?DXt&`Dl_x=RQOqloMLhzE=&@^=-~?VZs_Plviyn)RJes{n03M)
z%afLl+y;tFKB22JJc}q>@GRS8?s0+ksc-`n5Dq7-P75s)ipD`H!&#!D{R8EL?*YL+
z6E3?O`r85;{G}bXxzMN3H=Vqbg?oJzHnGSN1&`dpag9Y%Ru>cc)@--#BQjxoK*BZ=
z?(4lygWr$aT$F7l-0M5zwwCg)l;knmryoDb_JClYi69?$I{cRUYe2k9_7>eOX{d{Z
zZ6@5SGhN!&!r;b{LAG%vIKWFUzu$|C!mv@{J|dLQMgU80_@5nu4SN*0Rw&3fl?j&E(4}Y)mX1t
zB0Y@6J|=q8;c>E4_ov>(z_y{JWu!Uc=71+-?PTO~U~#s)+~w0f-Vz5hh#XKA?hybG
z@~DxC9O)1T*?L4?XHBEZnk16fWW@|v^3}ti*vC-7q=%*mk3@dt&-5~{bCy=>bXXSB
z`U*SWrOXQR{p1!tzid}61DDLe(kZAO^HQ29Q;}Go4v#Z}BRf}_=k(o+9
z#S1j=io{ll#Z>W{JFT)3BX8(x>IJj=B
zyax#x7Wfa9?Rv<7&de-JI=m4%OITA}K?YQ2=JBcU9{4j5xj{V+4`6hI6RcNZ3DwfU
z<%47J9oab8Sv=r-F-eoEK*_#1f>F#i
zgXa+G>Xqxd9wEIj2irtA`VD=PUW2DiCEZIq>{CgaR0a3?nm&>~gmctM8roM=K^~X+
zOuv=#NTVw40l_vAF7CF|;J4#8m-03f?$zFm+gj2-84f$tuw5w@oekSWxY%9(Lnhg-
z5`w#q`YRmvX;Fzs7cGfm1JP)6jTp?>H8X6<@Kls
zH(sKs@H8XH-@r2)(JQ;p6H!T7@9T#M^@^m<6tvErRhBlJU9ELt7CQ2N1v1ofKVC6cv6h
zA{QfT%9epb20ZkUWm6~Zp_Rl#S%jxC(gQY)$bszfkint2fcOj4xrr*x(#h~uv`%Ga
z9-#_PW27()(2Yf5qeetEWy`>#40u?vKGs7kiHEWXKO2#^Ro;Uar_N2sK_#2LRGFE#
zN`*Hf=Lu_?%V)qNgd#Ju_;mQWi2M<889ac|u^eXUz_-}Lt`eMQVhLiPDZ;UG5D-|g
zb98h`6K$Z(#1MqTGl+P>ZHiSOU>%;?%(CE6Ia@awKq;I8Zbf^2{o_o+lp
z+W10+2lA-^KY&P=*)Nl1yGl5EcbET=$syc0vVp^2V}#2aU%1!%+qA7EIpC;FW9h1g
zCR-ecpiko6n8K7Iq3W9sQC89Djcc{WW@IajWQ*Ut8
zB&?OKp9Wgcs4d0W?nxD6m3N8sFq%f>fZ`~_mk>G9fg``|MK!C5Tg}tHBfEdm&aXKG
zDl_xIRk#Np2zeN^r4^)Rjx1#^y$(=Ola_%i$-vSns2aXgOO-rT1&9qene(
zn7@H%RRD4*9Daz%uT7nM1F8g}UXj$9f>z7kn7Q3}y5bo=6JH{!kETg!?2^nIpgKIx
z2>35Wq;AZ-;(aZB_aZr9uu~NMDaJ)xq~iHV6=ptH`eK*%s4(`iD<|@E<)+p1c4R9>)l0<}#6^ipoUJT2WLyFLExXffqb-)rK^U$T#$2wNMvjKxby=Qiq?5$SsTO
zxhwkTo&dG|jmXvXw8FO_13ELa2I}y05jnno$TwIxXvGz`9j%zL{TLY>D+gh93igJM
zE@~_;#1*%Df-pGHM}*l}7>HG%M1?y73~h$}jt)mhZUaRohOQVqLx>k18G324zIID1
z#8lZUhc#macqsO+)8T0kO0a)ngpDtUKIw(I9jeRV9Cnh1_SLK}F7&PWe!n3T`L|BE
zuMfLUft&HiSJFO}v@0c5!M%QG+}4ud9CfI%7(UrHleDYk5K5i(Mu(?gQ~91FV{zjP
zciMf~83q?%`zj0{wm9HG1jSDvb$FaW@Lee$^@1)%Iljy-nl)w1z?2N6F5LqiJE_No
zBsx6J2s~`#3?R3WymGjNYPyzz*%=7$wmLI2pE^8_k@okl@Fav8{3Hg-~93P^`H
zA}{4F>ZKcm3T!c}RmUFcP3X696fMXU1v)$u
zdFNr+h@7Qwu3{;3>Ggn$nzRgDM+R(_Fw8=)9(JcNS9-rDKWRqL!)u%YcwEFPaL%NM
zCWAA`c@+LU)l9CX$`sU1u6{YN&PvSEd4B4nSsxSMY{V(3M&}zDdD1bY>7a
z+Ni=u9+roJNaXO!;80#d8aZDg>$U6jsDSmc9$HB}ltp+Waw%s`cj*kM%*=yR;oB#2
z-r$XB>fCf}r18hX^Z*o@nOW=bM&vAEO>qSoP??#>r^3%mKNN9@-*2%?M!c@K%&G(FXQRIGjP6qGe!l1~Qh-
zx}@k*g?pF)(f%GeGVwNv*=l2Y3LHn7nNgTYkE=+^9v89K<2;QK&dkvUFeV(%Aeq8t
zSM8!@K+izzqkL{5+Np346CmVa5UM~alQ;rAN`eChX^Jgnz*Gr#x6o@3JJ!d*tfKVL
z7U7Y|+fTiT$s;B1Ql^WW4xNFtGq4GY*L;S|girHaCP~E}t7RvfFY?%d{!BN{7cDS&PWU
zkhY+_zx{d(Ve%Lsz6~CqGfUt;E~5GRuA{r_r#EJmnR$3Bya#?Jk;7ynk(>Yf_kKfY
z1CvVftjKv<4#SJH>b+s`J&LP(-GxL{2h4;YM
zBl7UMdkATBdEa$khrp{n)Vb;Cx<7iiTF7-B|G4{Msz7Jv1dAs+yf%@?rIi@XmY$a^
zt!$}%*A=VF!cmzyLxu|#-UCvP$Sw7gcS00+aCiWt8=PRh3O7fV4lW-YgJUY;U}y1w
zJFTQiRiI>F96>A;GCYe2kSG=>vQ31fXR6%dq6klIHh{4@(F!i)%|I){9ZFK80g3X;
zbzP657v^A_NJNa!Z|Li88a(~@O83$Z`&5!9RWW*tXRm4XuLx)RT%y&iXWCa&K^~X+
zZ;Xb+h_L8XTv{$?pErj<$H!d~k%*-6<@JQq*|J0jD#nT4~3-kIE
z82_`y%(j?fFn{_nr*nk}{FFFmWBS<^=&r}sN;0P)@%4$^Qyn-8T{;e%0QtLjzoHoC
zzeaUt2_sP;d{yj!Q;V;+(7pezz24}w$UdNz%~-B8b3~9|Mt1dG_i6Gt8r3+fH~PP`B;5Jan<=%_xwFb@w%OHM7iOU&4?DS!9eM;5M;V@G
z1U+DTeRQ-zK_)$2;gI2J*dz#`GbK2gX>%Ozk3$;b!WsB{xcN|-nTM#tQ;#eR1N3@P
zKi};)YKN=ZMb
z5)tF``@$xceRz+$;E?Z1N!v_DZ%=3LUW3212m4%@{S?KUDWKVy*Rw5x!6VJ@`5q8#
z6XEi8*C}u}{`ktcPbKb3NmX#KpLPnI?{kR`;%}v-Z6@jWQ6ge|-ra>ACTz=y3&V%T
zr6VjH{u&B-7gmY(~RJOP!6wJ(nK5BGbzJ8
zuo+z!#yIoY6fFZW16c>kx@1IT&nnyl3WPiiLa#?DlQ;rAO3GE>=CDc2z}yV?CfBNroj8YK6NzGo{orzxLB2FkQ4HeZE%m^3066Srlh8~>uiCY#YCYLPa@
z=IHQ9DKD1+x|OUT;+^?~dQ@iS_A1;155&no^;W(QMHSCR!gAy4
zt)&Hx8S>!_Y=YwTTVJN%k>&3^Jwg#_lf?)qjxu}+ks}@DF6~iYHn5toB`YwbsSb
zd473L$s*IIpn%67Ip>EZ@V0a
zz*i>n(EWK_P17<^%)ksHhYuaTgvjBwGLfT-X;P1zchds6LR6se$14nMdPpiWb2loy
z2fi|q^N_Zo$rnGj5%b#;rOwQ(l{)-fL~dDJTTtA6w_cQeJ=e5|P}BK2e5=gN15n{T
z@QuiM)|%#`8PJ)Tg{H&LMdTqYEGAi;VL5C^hohqtSKM|4(czeOhSe$98#=nEvA7Ud
z-0lfdhG!8OI2i)eYyxWk!O}&!3MzDT1O(55K@nQP#E^z14NBfTi7dO6S
z{)US$$89aifgBM$CMhotB*^}W4#)dF5PVmPhZb}x3i}Y*0~XoUVNfT?FlbTUq-9`I
z2J#LRJEhK3L3y5G}>Z9DZ0?#5U4ifINY1YcX?OKk`?Pq+S)tQ;arNd*7Y=4iO
zC9WwhmjRubSzJ225jjg(Q(Qp?bY^A&>hMV9@D;Az+-2n(qxt}g?w
zN=SC0SDl%eQym_Ar1vmvGjf)`xr#coVR310ZfH6ll(fDSN%BZlIx}a+fa>tb!*hrn
z=}0Uc9e7kceUJdHh*8Rx7wwjtHp{bSKxbwaiVlxN-gy{K@1qKw^?G=IHnNnt^aLTN
zOdQT&R&xGVERuG2MD
zrl3x*bCuHlPwZB47@RDf=a=V{EH-@#O7PSp3!_GSv%vt92btLGSyU4g7<=mr((!D>
zZnLGs*AG2{m;0F1EFFF>B9|g-x|V@F10(IvAab}+;fshIUgbe15xD`pp41`d@U4AY
zFY3CU4cw0%rfy{`dw0Q~$D`cGLixdi$8{0ji2NX3?eZ!zpfWR$P=%j?$cKnFy2@MS
zCUVF~otqB+`fpO>5p|K7S(9{lBXX9ornrI(sLagcQ{iVL@(>p$iC}bxE38);oQP!k
z6&0v(3)3*`ggurgEgiWH6q$TNS7mq>(XilY2J^B_<{lSlp9(iX0pW1M>a@@@p=cbG
zGMptU+NU2sc}3RQHj#)JpLaL(w*_u#v5i_F!e829n+vTu-*oa$meE^0dlWXY$W;W7
z(QMAMMN(E56Z+O{x9%e{VS7NrZ=G;o?{ymde%$7gek&#IN=a34ukVc8S~#3-T#5GS
zw^G=Tmqf(g^T(YIPn$~KH5ixF+mi+(6jg9>rkk)UB|(w{`Tbs86o!oo_Yt9dHUbC}
zX)R)0xbA_E5M-oD%fOrr^Z>^W5nI#AXnMMD+tVFE<^d*sMOlPk$Uk2oUBdR)YAjB_SEG(~tCBV}f09-%11
zJ&K7+^B7?6DdRDov^VNS6`;ADM4L!XV*Vdm=T8^)T>
z%q$2U9(!bMB4=SWMazJa0hO7#oeJ-PpGo8}sZHdlW12iGa-NowfLi*uhG$e!1^Q)J
zM$(y?Rjk7sk+Xy~#T8^gWo90q3h#kG2a#`cmA9{QFE+eJb#6Ka-y41WFvYDibArVa
z9o~pM=BYhjQwCIK=7Fm49{6(*IqGqE0HYh6fFrSlYU$we!7=!bY#i(?9&YJKnp6c!
z_QeszLLtMmhyWQXP;G$9getdC$W>55YO?{1)rnScA#Vm+5$;fu8VyL4SFY=_T`6G?
z$V(f`_n+SgyHfVyX;VoDdwD0zzQ5u8HGL#qgtL7v+7?*=3zQs+hayfG
zlq!bV+h-ph+PCYL0WAaRa}L(WL@OO0JAGjo41HAaD~}o$Q7@P_RpktPUD^K`+$*#x
z)vm)Mk$Vr@>3vjz$6=Eo@Z6+jU`_^fW@esrc8jUxJ3%H$m*C8EojshU!{V6me;QnT4&}2!wH}|
zdfuj%UlXP@J{6v31j-w@=vBVYi|p$0DQbkk-qpD`AkS!C9l@(U={4G~
zUU80z2Kr>&0(bX&q*+ouvMMgc?+4<}s-7)FTVSpx8&{K{joW@EDt>WgyFd
z$Ccd2GThUJ$8!CM%TljWiFbcWuTaWtOI3TQZ!NF9wtD@!yxo}lro7U
zz@wyG1#S+Tv<%G6Ko0}4kBOdicpM|`?~#kiYsw2{piG-$Kq}nBq!GE8xTd^Z26|Mz
zHj$4z$0N0;D#Vt~n~{qyn)0eLK(~?=1owDLL}g~~P=$NofoMPVhD@9;SSwp!XhEa4
zfVI|_rFUdKLYYS7fZ`~_6K$878TOd~T84XIvw;Q0OmQ>u)8KX*tf4NSfvf|iPKsVH
ziVF8I0YV-IZD|FmnIlV?ORod3a+8*UE6KppDX1F0Q%jXX@%?@Yb5R{V>VZS~qZE%~
zNfbEaU)Y;E_Xgy-_&y+oJy%Dcj?R=iQ_yPJ8(X&ANO;VePkR+}%*hUpcH|Q_A3Rk9Rj9gpn+F)o&8&v!REJpI(k
z_h2t>e98O`7hiUvIuY*B{j+^8!3IONyf`4#aSR?O5PVmPhd0orDA~u_<%s%V?EWh?
zrb)}dWEDE(5Mg
zM0TN9otc?a9Uh6?dl<@7Z03>_9!eP=hfRV2`fQ}m{k6C>w{A}Be9(w4vP5)d&O8FD
z!()$}L*z(@eA_Gc`Yfbr7iJo4CJGBvO}3B$otaq+ba*6kjhUHCQg|rkE**zWf<#
z1UXq>kkckD1J{uOTO|y$(5r`?OhuAM9iC+4`hs*k
z8~NYcZ0Ru8Jc5_|nA9vCel8-HB5S&qfl>x$5IJ0^@I^!puks*UjmS~OG^t6>OW$gz
zMP3nwrI^l_}PdY)UrXTauYe^
zq0UXm26HTh?4c|&Gqcd)jmTNTn&JvFpfWR$Plcb0$X$pFGh8rwxWYZOp`#PY@+&G(
z;TEQ0$_#t#C9rhlHc({p30;-pSwz|HgtATM9v5hz3O7Ij;c&w0w9qo4XdIL>oFyvS
zKTtmS9uVv^;j+7-zb&A_U)o`t3w;WG)5$woxL2BBm*HtwN`i0)$2As7SzS!%TeIDU
zEhE37{APPV!Zs1^>%C5c-;di|lx-&5>pSDN7I~jc_KPjiKK=Mfwg&|JOa%G3)8T2G
z%e!Q6(cO}Ux>(p|!o51vrEM(?ZX6k88&`q@y!7(>y|^e08x`&&Liub25GLYUgu^&v
z{7bvBpx>Y@-Lkd8re0adJ>n7jm>8%IPd)O1j7xn~@LPs^ptFG`m^W3+fSQ4<1Eo%S
zB9XVhN3Q0)6`nT(J*sO&e%_?F+RmGSDnu@inlOD4TPF^(8M7VHX;WS<1ExyVSg%P<}EY^9rRF~z`60iB2`&UR1nTPDdPUS|+Fpeo#>E+FJlBgcqz
zh=XiBBF`3j5#B0NWleIG$eNQp13fOqK9=L2u6jHd;gQIX{F&Y-U*l6-S{ZY(epCDW6(BZL1)+TZmR#UVLC>cnNPkesu?$zA$O)SO{F58t7Jr4F1qQlFdJ{Hc{ZouS^I{bma0pVd4X8^ekN)E+CA;YtX
z+U)HxbM1Oc2Ff4TiPkzi_Q=AhDfUr$kjcGX467+y2Fe-8SvGc3Uoz0)k;r|ppWa6m
zcotD{kd(r0`j!F8fX>V;MLIn8$VTKWaZPc#4Cu_v;?m)f$U6_iM&vAg&qg8Mik{s1
zyM-QfW@b)xcqH=nQ*SJBixg&&)iEPl(5NlGN(KEwuR1elP65^7ONiW49XJZSABRnX
z06JG_sj7ltQL4!nGN3avYk>}rJ+jTnS>hHc`bAd9j6g+APR)R69CvC8n|;eb%RtM(
zWiwEV$j@-UR3UNrlxv%^>G$Jpc9t`Al;2yuj&Ps8y4Q<1q_2#07T^53b@&3<9ewr0
z;JZ+Tp>P1FB@4i#+}Nix*c+TfgJs811r(ylaI7l~5z)za-81^Y;q{|0j!_jwF~iIK^!i~5
zm;SUZMMR1rB2xU2v^Vyzf{%aD{WV^WAdlZ6efRL{Z*h+<{3m@X8qU)t$BTdi<#5Su
zb4?8I@R`;d4*&nZ?sxb9C%~Xgm&Z=_YZ@Jr)qx+n99{J&%`rj_^QIL6rOX`YQ$F`k
z#ws4@+la6J7LWTa%FkoiU5_tB4$VO`hs&TDS`7{KvFHgyt)3vT8Z-IikUWI{PxS`C
RUOvgK#eYy!*Zs}A{~u0mNyP+000233jqLb0B!(300011WpZ@6CZU7zt0000007V1<000000A&FH
z0000003HPZ000000C)lHnMrTeFcgK;S0({so`n!Xhy}2qeT=)nzvvQnY}mm5{WACq
zh!qkmHi&tir-t)6@vUo|bQPh`2WG^g5}
z{x($>u75}e<#&~s=lM~hTsq^b`k{w!32ja2Ylbeekz?>k$~NCumcrhn@L~$|Rr3uH
zUtwzVeR-AduIQx&?`tkw?jAKm6SdCcHZ&SKD_+|a$08@iYB@gU`f?xoz&y_BCF
zq}^a;IwuKdB>go8K6=_|rydjhv1@b@Lc>HX-&hu+v<8xDWq
z)|dPyr;1muTWX@O8LM<+^Kom#-BV|t9%?=Po?3CI!B}*;C*v_5zE8m_22F6_FT82eCMV<1{s)T`A;?8Oug?+7fP@`d6siR(l
zohtAdCa&MhKROyU*eP~h2v;2jMzEue!OjOM4R6K3d^BpXxkzbXCU>F!K}l(NHO(k4HEC!Xg`N_3S9^R)0b|(GGKR6;PpK$;62sOOh6RgbO2bDn@I*Jw
z<=Enw(xCUxgm+F8!-B=p$0ICR#qNqlwmh^)b-GnApSEr~tkUHl@5U-rz5Sa;s)_N7
z#H^d{ifk4Tq7bB(fY8i4KR{Sjt2a-6Zib-pRhYWACY&DhTAb)>{o$+5-~Wb7?SPoW
zQ5mDm?_d=#m-GgA>y>-eWAy)6Dx1r#Lj@+tnGbYK;MRSNFosEB2LebtCGFHnUV+=Z
zVC+la_HaW8+(vW=f!o0iA#mHTIs$*Vpn#xSDh03QDrtr&z1M7PKo`9G6%L7%6nC(#C}+rgVsysJ*rb;M<1LViWnao
zp6nL@00960cmWb%V*mmWAq2$1?tbxpt|302!6EUkej!1T4dH(>7(pr+9Ka+40~3%2
zDRp*niVt>o3~_~NsC=W|!VXr{gQS!nRjI#=>x9*d7jS@8ctF)z18D&ib^al)LB5;x
zceAiE7y%_ra4Pf!DYV(T$e4w}3#do|sxS&ja|5xnyJNh+lb5S=$hxG@rkr3|7N{DK
zN0@$ay~!|00030|5fXAbN~PV
literal 0
HcmV?d00001
diff --git a/data_selector/db/data_selector.(0).cnf.hdb b/data_selector/db/data_selector.(0).cnf.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..141b3cf736cd988940f0fd766ee37380eb2f4bc6
GIT binary patch
literal 1188
zcmV;V1Y7$L000233jqLb0B!(300011WpZ@6CZjTHA000000LcRY0000007?M>
z000000Hg!}000000C)l1mMc>nQ4obUZzL5JiA1I5u`k?$LLzfjxD!Z`s#HP+1ac)Z
z61ftYpRf{%j6@=lR9>6YhdsU1Rl9$HTQy71opVq3*LUV7v)OFc!KiTkL;M&nwA9kdMSU(^Sk+uq
zQeH`3yL>?TVtGY5e^V`a*X2XX7t86JnIm;2@40-7^6rZ{7rjZ5dJ^{~t_jxo;*z;C
zTao&b4_waFjV~{mD-%BrBpvC+gWWDrB<|F!KBZEo@?#_VzWw
zwDQ_A=YQcOpRUK9=Absv#0uV)JQ2IU82fd{}IXoiv}I$1TpR
z0#B|mxrS_>soPd{pirh8JTRXeGI46Y#9~uyhfMo$e~0Nic#RROHTDmH4VE*-!=FI1
z%VIC5{~%g)S>;>{JT!0<>xH$8*nR4@&oOQ+OM$ZX5L?kH)MJWu6l<-q*c3Tr8Y923
zCWwU<5-r{Fpjf%%17x(p_86?de+WDjY_I}9YJ&&W6o&GdASPB&7>cl_Ev)cbEX4|n
zl~_Y$wLvUHQ90j*720Dc!a8qbg}s=-P(EYC#0ox!BCMMhR`{-#Vgja>E-6DqhEh@c?wLnnMQOQC{d6;xfADF&eoMCI%W
zDm2GH1a;Ngt1|5QJ`CkELQJgSgUODtHW2H}3SWeI>MVVO*lbczoZ|!6S$f$zQtI&P
z7>dd%gcaIjD8jmJV}(5*A-{Y!5ECo-*sQQdh=mopGex1x&cQl-q*kbst*ht&Z-uJp
zH7NWX40~!N$p_&>(e!zZyMuh1-=7?QKKyX{_1oL#;NyP)00960cmWb%V*mmWAq2$1
z?tbw;{?3jep8i0FXK={r-d#r+K`Iy=z$60$6OfhxVvy1R*PvjaB3HkV_~4KrPe1o~
zATua3Inua^8LXTIs>vEi!_4<}4Gwm6cZDc*jbF1IWFi9t2bg4F04bFMVkgI7*NAuz
zPuC#FAZL%r_yGT)ka$l&H-B#KbqWx31)y3$28aN$Z?HSU^})^_uD*^REbH~z!OD=$
z=Z7lxbOE~8(+z0H-xf^`a7Zw~oD4D)Pyit^{v%n!UrV^YNU-TjRzHIJoxH_6jSc6|??;)hsfQ?O)OK{J4Z^Tw4Id)c
zSblx?N}laL69SXToMfDZsa~-{nAOWGn(mrW4OjY=!IRVOrnjM;;EFL>*G%u7y#{YF
zv~qMRrk^82&wz~819yJu!g~%ihhcc&U7vr
z3qSHDKVQ57pH#`aag-Dz$A%*W<}7%7@h}y$>uC%5{s17!>YbNAuOJ|`6I$1{AGg8B
z&YTD>L*BprTRrTmNK!A6%HF+vfNq@MiZOIV_<0R3kOsUa!}6b(AL@CzvBo$*^nmOK
zUTkGz)}$Bzb5CY2-M`dnf}3d`)t)&cpCjdp*YVrxuS{I%vXnM@EGQyTAKEQ=RGwt6
z3+^{NT9ZC5uwAIcE6r;6G(A|!ta3L)v21}nPH*T6oVPr8Y5L)giGxC|Nmf=?
zt7Ht`<*Ax#Ne?z?<1Q}lmxY|0o1NH%S)7V-Z2N&5W0*iMn$G)a$S^?YCHVfzhkGqQ
zW+o-p&XNgE%rV)80St^2CoQhsFCLK#u3K)Y8Gteb6~Q4vH|O||M_k0*v@Djb67SJk
zi0(kfIZVkXfdrJ&)t@3tPUZMGPsY_{Y>N5nC!hB886t*SlKbf8#*@lq2R5&VVr@ZK
zu%yWFm+~i!3j6Mz9q2JF>OA%~rTIh9lktF9@6BsH%8#4h2R$&r#m~E0h&MPR8T@nJ
z!3@4BJvG|evaix64Dyv%dunSze1??W9S#L(p@3>W+QtyPqSbGcM};k9K%E<
zTqY3>9*c6J%51}2!RVN6;L}Ob-yRm?g*7M_O_*lX;jCQr?rw@|Thr*`R?kXwS>&78
zOuIs=?LJTEBzOtREW@g>uR=(GLVH3aqx%@?BK19HW~j1)*}kW4kAN54Aw%lmz2
z89h^k)2~8qko(12$IAw_=*)qP6qY56l+TX~%!BD)RLmv!@{}0HM6o*nHT7j*#{za>
z{PT+_(*m#w@eByivVZWIJZG`;%Rt7VZ%(=C*~1bp%;vz9?#_pxH_v2uM7}{LvoH&7
zyIn}`;H6mP8A~H|RQ9WCWA%iM(gE%D-sn$^W|Z;VCPX(l2?a*k9i`-_t|YI8(!L6b
zu8#e7z?pQ>rJE(^*PYs+Hvr;_ct!3DQw@)m-ybfs$R5^QEanS@h0>*3v
zTx3Cw7Hu=FBLXK_&3t$wt10i9MfS(f<94O9A7r8La#5zs&}E*a)M!n$ZghTvFB@fg
z+Pc7;g_Y;b`Tt8!Z{(r+ki0I5I;$Dc7qy|<58b_Cci&bmOlEFW*L}vqnn4shSE}o+eWw)zw*5x@@zb=~H6Ts7sO0Bnzrt>w0(?@A;x8yJJwY
zJkTo|2Y94&jQ`XNl@4w3Cp!2~vV6Sm+*0Zol;8lomG0_(_$Sag{*uZ!_d)WSXHm%s
zf&G>NMkl?)BFbEl0|(9*0k3Htovug@t&VnEHwtkKGQ4+wSAQe!c4<{rYKLb_jwAnc
z-rZT;9*e{||Im%u+e_>~IE_3+PBr<;iP}R@&Yt-1p5rLR-fHW)7Y#U;H8yPkRnhDd
zs>y4rXsdRM8%bvT&==aB*QPHwRyQ<(D^~DFhH=(ri5E})f&V|xkGKoc(%RhImEZ)g
z{mm8W%eL2ZQ>csRzf_uiw5M#TRMeg^JRRh{+6*|fsJb>U!WEWPg}}=Bz_q@Of&KT@
z=J7`UaU9fgF~6q~U#&hNe;lGPzNoetH;5zZx)9adCs>TjzQ^0QgYm!aF8Oz$B9em<
z7D3}!;3VAw?xi%L^qW&RAtq2|X<^@^+ohVsHTGC`Az3Rzt9T#cTcRa!p+8y3-oYHP
zU+KEKZr{HM%X>&*)3qx$88A;j+^e=brcWdGP~|_`4L@Gh+P!o>v33S{t~S+xX7<)q
zU7gWtX0(Fuw8?k$MtM&o
+
+
+
+
diff --git a/data_selector/db/data_selector.cmp.bpm b/data_selector/db/data_selector.cmp.bpm
new file mode 100644
index 0000000000000000000000000000000000000000..588123f9d9d8e26b22c2da6d12045b50ae14dea3
GIT binary patch
literal 630
zcmV-+0*U<(000233jqLb0B!(300011WpZ@6CZV3qh000000Q>;}000000HXi^
z000000CoZZ000000C)lHRJ%&VKonh{s33x1Vtc7okpK4br_a&O%o_}^cJUR9IYX(ssBlo0L!`WwKnK^-h7$VrvxtaV|#(7Jj*MW)Dv2YShq
zG1zsQ;9`xgfYTZ_1ZnNPq1w>=ub|u+O;F&iS=)M=!r5?(J1DGC2L+E39y=(DCSnH#
zzxoMY(8dXre=kO(miaPW_hbmmL>{V3;Rz-V!Z(X0RR7Z0s6?w
z00hiHtPI3X0lx80{-J&@jzN*}0scWD@xG3Jj_$5O@h*-bj!urjuAcKVR2V^87!trF
z0|OI~<^y7o-T=p-5YG@#e?OOaqb!i23=Az`5~55J$Ob9%@N{u;^+UDk@6CZroh}0000005c5$000000Mr8j
z0000009FqG000000C)lHTziaNMHxSLr3-B-7O_CB=u)u}Bhn^iEv=zLt*lFnw0~6j
ztJX(J0MP_BlB!uX_>2jS2%4(N#V8WdfDcdslllkRs(}y_tCo@_NPsO!ZA+Eyc8*zXc34{~NhB?T%-
z?^J*7@PDf2`80>~B-#0wTb5sR{YO>|{-Jj1#?7ZJKYHri6_;%~w4(NPp#2w0IuwYk
zE21(}6r)I~bf1adokd(ND&zIEJTlm=mN0Qtp
zoorwMK@U^?FlFyavDodB!KH&smn~g<>7d1Z88sB(AW}Dy0B7j~fSde`WEh$nlVSOG
z0+U4PCmx?n(-D@}ou7Q3ux}!wDPcN*mO@7Ta@dr~e^LFC_nCS=i|Vfteh!1HqWUw|
znD%e++EX@w)XtBa`u!+#eLzt9S>j>lrA9=nA3|p&{mJu3l4KLsIF`%m_Ha6$o&(+9
ziO4XdTjzXzN_4yLN5^!{9l$A){i*Nj=1E95FI;KrL%O-(6Q;hKx>?qyZXOBf#`@jN
zyPE4}-S>=ad=}|$u~dh2w=1H%yKgcCx~aRX+tl3y5#7y>=x(?}-8~)A-L?vJx28?q
z{UoBhgOM?LO^3Q$ADPcqR-n5NwW+&%BD(8~_}x%R-G#>V*2tKC$5jR)G#~D$V6FII
zo4TzBbZgg&BN4y+M`W$&kNDlJ3f78C+SJYVfNtzsQH%K9v!a`jU;W1HC4%eh4Uzfo
znF@5bSaj#CM=~1X3HLefzJ@LQGGR0MKsbb5iMyuWEc=!9IM}oPS+Cyi1s@tR_5PZ>
zUiOMxWPEm02Jo$U$$eu;Uj+#y^UTPY3L@@qpO_ht5`?le3jS-d2mRuC2h1vqaB)SLfQ{OCsa%
zt}_VxJsB;JLw6Wo?53~Tv$4|8?Jl-GR
zaY%R^u7F3rWMS~<&aVlNr$^?_zeeWHyB{o`J1-X*Z>eBj;d_W88NvDp;A(GVUgEEAsR*4SIt6<*Q9nis6(ZTM>`tidy*N@9Y#+4P=c@B+?;QR7zBIDm8
zGQJep%P5iI;tFKoyj~>3?IMF+14DbtZ?|cucZ!TxRUo5X1ARMvM`U~~Vy8U;J6T`5
zq5>H%q>&JO8McWG=SJqu{gHX|iNKz7x!7rL1#=#x+4%bNdq7t-K)Hu~1khnXd7fUVYYANqD0kDKrsieP
zRe+*a0Rizee91_Z>yt^sQ-xq4$8d~a_|+Arl>sHMz+|@^@aZ}s_HFhN;&v&L@p0wzh??uEnLG(>-HhbLQ
zds#_tNF4+uP&W^NmYfp=${rp9bSZGJ&F~4m7Eqk+)khnk?Q_$p1#&|@Q&wRG3H$v8
zpce_$NI)oe#CTJxXwlq$w*rb<1q8%Cel#tq8%*GAC4t=B4_fOQpzQZPKo>V!{pIwBWO?+Jczt<}-l0
zx+(9)_^hj>QzX>QJ)m_ipgh05Ro9Xm_E5~@S-_#ab6mdBa=9sQDYsSQoNz3qOr6w|
zi)QURt;eh2ru4gAALE}M+KK!z{m1(6w0(?!($77)k6EW|R*>@b1{3;fpu#WjnzF8j
z#0hV0xsesb*eAOgmKoBNce2=m_Zkj>@Jqn>G)4*%jBOnT!0~8O(+eQ3v*{|j4N)N8
zgg_YU7+t*WV+NJmN`-ZtfslU9fT_b`u9-Kb__Jv1;0tM}VDcbWDK96~k^eXHXswWC
zOa_uyI-VZZ>R`DQ8zu=>g>)ub@&1IhAvjY2
zF(#vF`bOkNk#%i@R@y#A%!TkK*M?_90&t!35=9+(+K>YrS;p3F$VMlI4PS&PbY|Z3
zC}~5Q7}rYmq873taeTbVwIOeF(T2RtQAeIO=QE{k$PGBhAus#Xk)J|)8eTi+
zIOKh#5;o-e#W(hBl^o6K)s>{tZn+oNG+>j
ze4JXEDpMpqf%8Khk=}qQQz6T!Lyrs!dc(9D^t>>w2K{q!ey*=0wlpZF*7k{W15bcf
z4L!PGa&Fk|sKGr`KtsK)D{_(K7|Tfd}qsZ%8k6)X>A;fVVE$
zpy=V1f>#yopqLUX1-v`q`$PY2lV2vDx!=IK!QDPJ8x-7aW`RemK9t&h?b1LjqZ-b%
z^7e^T%Bz8#*jPuN3nt16SwuX{{j
z!K%St_W*wBcarp?Sa(Qxp96Vagyu7)X}-QR&F4$gHoKBp8Tp?L&&y3(|K*?>XS!D>NF23&&FhjU5KqC@(fHkMKw-s3J@D2HWF`E
zKvxdUj`(!uI+rH-Y+IkuTak^(Cxew1Qsmi~KD)tZH}nbPQYsxC8=Y`=KUw&6cHzg(
zKjDbS-9H^qPCUDFuFtFK8Cme=`3$c2Ny;g@G&v_X2IUsZ({x&q<|TQVGq_W`_}9i6xVN8SQJF3=eI1y#XPkhi0@=BOVmF)xgvX
zQcoNPPOD~WO%v*S40{WZRQ$;Uido=KA@Fk@JdGT+Gj)~15qN}m(C}hJ5khuc{uT&-
zu&%;(pcoH0*NMC`!bnPooF4c?@AJnDf6oQwFzt4uA^z0sf^rzVJzyR=Mg9!LJoA1{
zd9_K@|IqK@LOGxpG_X7?puE`FC;}Sjp~u?|OyLkQ!g?Egd)x(sQ4ap}#o{pa
z?Qs@Yh@bkf@_IOz27>L;8=Vq6zVsh-Ffk2DnvY8xj
z)@a7Q&E&9tMf;j2=IQ&@&t#l0jL7l#SL^msIi3_bI4&s%ww8)5bN|zH?7uG3_TX45
zoHyWC-!g6Wcrz`{)0bl-euIEM)S`$S^LTX_IGjhxpP}aQ2SWQr4u9TgkOTZZY6xh0
z?7xs6fRDjXS?~5qTwjg_Vh>BlroiJJo-8Z^A-BJ*q98MkSD+Mtru9;dUgU(>(Ag3E
zGji-1FoN>HmlT};XqV#^d9-~JG&%oXpvx8{o8hH
z=LpA)W@5aeSUOW)lERXrV+?pjSFlCHX=*L4)21SCeg85z&XgBGx_vUDjFoZp_Q~%D
z#~C}xC%|GCrU>gR-d&}x1DxR#Uv2RGd#c!Dt~PLd_2UJcM$hG%{aIG!`_|3C@i3F
zuG`POULQDT3Ot7M=%-a6RXBcH7)tXl_j-B&rqNMC^CL|GCB{GBpB#iWbe%=>yHD#w
kljOhO)7kCZFiW6C${;L&k^SA)sXSajH%^nmN6{sX2U2L9hnHUNDu32*=a
literal 0
HcmV?d00001
diff --git a/data_selector/db/data_selector.cmp.hdb b/data_selector/db/data_selector.cmp.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..99199ba8557947f0096b100606bb1be3d0e2a699
GIT binary patch
literal 7054
zcmZu#bx<74p2Xdf0D<5h+@0VO2o4J@?gS685MYtu4q0Gv2`uhT2=4A|aJS&@c6sl+
zS9e!+GgZ?wzp3t;KYF^R1|I(c;X-m-O+F>T5JFQF1#|93dnin$%m<|c*HJgEbo6OZ6`LW%
z2CC#V{c}BN(L&@KaWNDY9NCCWRJ#d1LWo^vPK#$$id+f~9BvWA1LT^1?Z*|V$5|EL
z%ivES--f~x6W<4TsV*G84DWYZZS#E)U;{I}j@aIwJny*Afy)fbhs|o7Qu5?-%(1zU
zBpFqe^`CQqsFnI%4#R#@jbuET62IG|I7~PEt~_H_Op3B1Z*7XUcIgx$jA^H_&fWpG
z=;e*(N+5M2D1D0>_?~4H7vsz07wI%tmbDtbdNRLrC?6GPTK5R0t(zE>
z=vTfSy0aNtrA2WZjem7JJ}NL6JAaazuQDMy^HPzS^zq)i=HKSqoZcFwEmEr{wgUOqDcsPsM46R&3o%un}6o~|D5PQ+MfR2Yk55`o-G}zl6nTlyp|FM>KC!tHbmkdT8@!q
zeJ1m+8At?wFp?Q}O1+$N
z_)#^JJy)2sfc!+cD*NRhZW@$lTRb)s)2z{y)gu8-(GuBd0JY3<02ZKt#W~nWHzN{$
z&7$K<#M%@IHSATYFlW%MjxW_41e9(4pYqjM{7~cOP3+=zDbgeQjbo#UPR)uzZZ~Vp
z*mX$-K&t^Qzmlc#Qwh|+16Dt@cmy0Cj~F<(T%;_5S8g&5Werxnm=80-sT#;;wU1)U
ztpQqCv<1JqAp_PjSF;iaMO9vKl|%ktpWzEvFlNp?rBWxJKU%QJ;@8*@3=~!x3i30P
z&UM;=LMa}riNb;g5i7_a!K7SeTSAqyVoWYM`umvt_gZPPT0VA2%C92)ESQH9ttSby
z(-5>|b652udGh7>dJ7pl2>+W#^uK8f|IoN!iwQ2IFne4()P)gT*=Jf7L4)PWkKW%i
zpCI&Jq{iIkXZG$CKv3;PYpm~sehgocCF53-lDB=S(@ca4P1Gv6s>^t@Q#Vyf=-IHR
zVyYx*nYrVIG7jVBxQ8;4b?>uv%0S%
zP19uOVKCPUd7OEA9!d(jIVbEMgK937TnRbyPQ6UD^lBO%DS%CFNvy&sxo6KjZ6_Z#
z3mC&tPe<8ofu~n1a;!GSNlUMV$4WMJL*vco$grPqE3D}x<}6K60bi4f+1XH{u~npk
z$`5AB4UJ@GWrG4wrODK(LxGT9R;_&~GbMjOfhPuW-u-__bwB@2^8L@&vF;FI0lSu1
z{vTyq_w=p}D6;`Mf6%{a;q(n!1ze7)8_cL(JxaGx$Viy{)I~1+E2H0Yl)VUTOGqz^
zF!_3Euh9?g*ajavw^>uV56&3$o+o
z_guVM4ZO7o_m38eyDbbaKCuZGeYF~K3+lO{6-PaL3I~>ky{bKUe0_%0BS^Dz-AJ>;
z&pwVAlw^W=N8Y$cVhZgT?FaWxSY4s1PB{MZdU!SA9I|V8
zwMh5ZExwAQ_ZMB@?u;JBUIW^LLJk-1HU$e_K=D!iKEEG-|8IhjeizQFrRupi+D>KJ
z$oNf^gA01d-Gt6D8V1PG$==$Bbf18@=q*r-1C$CbhEVQVJaM*_8;Gjf=b=k
zS=|!sEB!u@R159y;*#ERlJo|86SKQI@2R$9Z%JbC^jcOlH&!OH5xHJO<|{KV?)5G0
zsr^_WckwQH({${Rhc7J#p{C@3il>TKL{^?F4;
zbF#?e+8XVHj`55$T8-0$STN#xL^&J;QL?Aurl)&5FknY*ZLeU-0LzUpv}6#=;Waof
zDYL}$pt`=4^YzN=KneBTYCWYUy~~Tn85r=A9D%kO>bSz9eRSD&AE@UL;UR#S13!c{
zgpbW&ETdGP8dzbeVDfmP>%H0TZjBNCz(A0s(1A^|fkhIX=YU3Hnn|S$WfDZ;+XSXQ
zMLP&YB7eF%I4~_aQvQsCVa#|*RI5mig*D&nd#6m3I*qqFZXP64LUu{)P5hR}$f)VK
zcW@=+y5p3*VS&P69btMol^H}!N|J>?_(Vy*YYgV?HFvTV0FDs5k{-q0BK>KVvJp|@
zc{HbobINHvxzfWcWpf*4xwqgSOH86<+bJXb=w3fD{`rQS*39}OCBG66X|&p+AoWs{
zZy3ZVd`owfOAe%URDbJ^oFyeI=C;6KM_LO@uC|}y5hrMkUd~P8MkkY{;=1Y5kycy9
z9|)Vca{Dm2qHL?k9g)Ky5g;@RpM|nrc`Rt&v~^xikM;IFyCR|^a8rH2L!rq$q1xi2
zNR|HW9IY=wg0mY&d_^eog?wl?A>UBkKsgJ_%C5*Uv~@1llIVJ^(N|($%+y5R=&4vU
zmku|nB1ftR<*w`bz9(>_z(;;{1lkH8Fd*L}u@hPtheBZAQV!x1q2%mzObFF@g+GT5
zx*~w+??&9DO4Fcc5gKb=-_DZNFJ7GFbnb@-h&-Y`S#9xaZfQ{Ov|ca(2Zwpi1-@@iBqK2%9&T;{=SN5fjYkwl4i4Z~!YkZdWZ;yKN2kqx%=X^@j$cD06oOPj#FKlrWhLG=UU`P
z2L1YknRIEpdvc*pfImB3b~1z$0ix>JP7>Hek8+VuFp@08l^klyf!%3H8F+`4!ez7<
z`F&~U`x2C(h%mih7V9l|5SWq3(mX^p9}`YZOZ&oi$L-X>dPsc=?d>CJr;RV^8Bk{CiL$ab7
z_WfwcBbnzefIzVGSyy1qg<4GH=9=&mawzuWTPpzAOfzlwgd!W*;O%*&&Xe4&#J?6H
zQ16QHag5lDQdTQfXJj+^&6t$KaX~f$;)SxGxUT$=q)-QrBMGUoph%Tr^Ej`}d#4bX
z{dNta7+hk*zly3!RWC$uqW6wawd}%UX~Sn+dg+DD`V)h)KQRRZ|D^RtAqn6J2-tY~
z>;60i^yg&aq)RtYK=h6U@>8F_;#EXtAi?9A5owbV+pbMbe6!USC25mdT#@a~-@LkE
zK4Kn&(Vk%!ri6Nz$M=)>aOFIbk$OqXXC*>bkuZ;)hM3zEpkn0;iAgpAhmpN}skgbt
zxUOYYMC~nY68U7C@2Em?aca3r&J0bNoy2y*#P~nh>k@v~c4}@;F=XCd_er`FoYSZc
zKGJn!fJY3eJ6Cj2sTf{U#YZV3<vh;?`1=6`fCm+Ft|
zQLxl{*494P01jgExaLNWBtY(XY7oL_Snt-_nuhbY0^eEXDY6v;>GfrE0RnlWQs=%4
zVEQ9TA@Q}ll(9BEF{4y=P%*^>RW^O8C{SJ%0@1SC;-eOm>q%88XqNG}zq`5g|ra4dh<@Z=1SmIe;=O9Xk>ytE>%{T57kP+?V5rN8n%o{69
zhGUoTzR<{lq4)ESv2?ADNN+P_;_gZ!MB70Ysrc3
zZL8w`=JUr4_Sd`NJuHx0UdT^LdYz!}czE`*?A_GC32Co12D68ieh&`3?RDjVKn+>w
zk_Z14T$=I~@sLsq`g{q<12Msco?DRNmT5c3y@DUe
zJ`X(_xw0LvY8cvi)R2!9YQsPVD9VfD^%xfV0SD)KTw|j%ux0HA)k00tq`7tncM@fa
zNKq`VS9l7v3z#+WcamH4xu`is_v+d#gm8jLI~+OwklZvG4fdQOGAYdR8->3qvqa=;
zK)>=T!pIbLm3MDwo&9ZFAm7Avx&Lo>wTU`Kf2uvxun7|>a@yBSBEf!GURg4KPGEuo
z9jbZl`U^Rsvv2`Leq8r;|f=Q{?VP&GzR`E)d0X;g}
z=`S>q<04;dw%bp)C@1L*|%rZ!6g~`zxnEN^NU+@^IOYv+^ed~&49jkP3D|!XVnLKHVx}JdZ%h#E%|I@
zOI-flX>iZ*a1}~g_30NNr5IxXtV_-=p(LYN)|+u4yXNrm6)sj);ZJrw%9Up(_NV$5
zqhlkGlw?z3^;hpLja%Sc%5&plhrzYpMG?ctY*h~E1gJrZUdn9i4si1n923x@1jVdG45c?!X7zm*K3&nVBPDBkg;IHpRHf6?tar}Qs+RfwDTe_
zhp?jUg9Qa9{F=d;XN{xDGm)lcade0FiP^D+jI7Isc2%d@(xk@Wa_GTr(Y?EO?vT5O
zJXC>ww!d)iWdG-R>#x-xRHBZigT6<4>qn(szhw1RW+hm?9l)Oh;KxKw6^5CHg$hhJ
zd)3Ab?@e`BfFvTTsqw!ElkKVU%`gttpDQOd#}G^T#JcFE?@=BJwtWcq6Xj(&V_A0q
zntToL-M;7MVHf7f
z^7f&Fuk4@|Hh%W=tCEhV$1eHJ=ig)XuBdo@yhW~Dy&~A67}ZKt$4VDj-{LRC1C%Zn
zl=Ho)r1QPvr1HI1CG)*F|Dv-@zVK|tRK}{V?aGDeyBpTB>GuWIdb=Nm3fF-JL~X%7
z3u9mKk_PX?kgAOzM#QhXFK;`ScPB@umlQ}nTi2Z5NDTX?1PEq69(v9`S-C`;Vpt^e
zw<9Ov3q{Yyrq;BsQjwF93Ye!d3-oy?kBgH(JUwlHebMW1qeIKujc(+;b-yr-GGpoU
z%o^tYl4aL&rM~!Z(CsFRM%hgGM&SBDbKLDzjJqs$Z$}UPIyq;1JD?N3eFZ~il^^4j
z>G-ar)^%E@2i&jZAOG8AUA;irmP-V&c*hpQSx
zG5h0#JAch|#QDZP&iyEJ$F###WK7kess7;sv^RS<@04s*2K=xn+Tag5vKls-IL&ZA
zjcpWgHgWlRwdf}#wOrUx(>KKt2dw?R{#3T<_%gHLylDGDCBtLU`C_%Oh<5jP;-Z($
z8K$Kgr8{c9L}S#&oI=ad$M&k1Ip04{WnNFf(bDB(Oox63h|v6We^G6k%|eBMv(0Ci
z-OHnQj6|sytKGd5e_Y%Rc+srni3fh9TmCRM&(yczC)#YHd=+&O*ndFL%V}|RVL<`*
z2tDfCucfdO)mmNF*e4iM%|caq=3biFwTaIJ7_^L6On)j6H!I0zuGBZK^Wd7-gag5`
zJn+R-hk1>2W%2a=7K&aQEyu!Qih>1VEiXn<6)(n2xYz;14j(!Q?f7Y=`-W6(_Df%YVJ-&0!6(edbEJ
zJQ&Kfb!~37uI8{U)l_YDXc}{_ccpX-T=?qX4Z80hW-2k(I7;@MF*Wo{x`f@CKmE=U
zPI%;6TxdTWjgUnBQ#KRvDKM>pm&7tcEhWGb)npBBM
zFC62YX(afCk7t=vDFY==O@=*1R#7UH0m9Euh58}3)u!gynR<@ix<_2XlwoCI^SbRe
z{;o1s(F|E3>k904;QHfOfU$bn=6n1NCh3Bq3=E?gZqf$%>NDcHU4~c+yXJ`4v*RSd
zc*JkfgsaRbQLUji=UEkpC$*5{=9~oX;h(H|&t7Z(xH`Q{4V_j@$E$^Bar=z<<*{Ff
z?wpgKbp|NEl(YJCj|n|ee7qQ4bjuij44yx^750A2zKrUsVhmkv@4R7TbY$a(KKYHv
zG&5#<@;K5A5^?JP-TkL;nN#1$_LH;U)pVdbeoXFfl@}fTWUKV1ZtNqr8}$R!$aR+cbX}6(M+)
z8~tP4Qx=)(T)}UFQG6Sv?J_Wru|BExLt`TkfUJ7^Ql}-`MT~SV%?hQC;qnE~r}(qk
zlV{IneF)>F?pee<(>ziC
zH98_uL|mVoyYQJn^zUCo@t3|GRdJG2y@$X;$40uMAD%NLq&IL^C3Un1n7mIMUJRHq$y5uYZa^mj6H>Z#>~RaO7@a#mIb@c
z^Bs&wRn#gh)G@op7}FRElL!lGVq(Gk@6~7)?nwK>GqJeirKV0b)0{>!4EI;ZGa@(M
zJxLb_C3(FKX}$ExX$fW5{P2xayMS#JH-k`7-Y67BMgZ~Sdmu@OGSE+CK;&0n@5TXX
z_f#9c;qe{{YsoD$%43klH|*G_wyD&)&fwQ_P@4WB9ErGN_DGB4|)R3M1kGV81eFj9uG-EV34kNAIPox4NRrQHTgM8X`N`;Xj5RHBCVJO
z8(1O;kSW4TeYy3MD%-8!%nRU^VLB2PZY22nIqLv##L>DgnG5=+PKB8iyv#|~^D0-J
zq=Z`O1ix4fNBhFj4e}lkJC#SqadeGAQ*pdLK17<~P_IWwj5OOVqlNzb
zNr}ih3%gVnH3~i?4x_Wo4=8HI1|PoiWdKJDfnJEd>A1u$$q|$kz{d33;P6%A1_t($
r=t{tFfK%4<#hNB>dLZn_lX|Kx9Z-MBx5*@idr}^u;Sv2`*Xh3iO2O0=
literal 0
HcmV?d00001
diff --git a/data_selector/db/data_selector.cmp.kpt b/data_selector/db/data_selector.cmp.kpt
new file mode 100644
index 0000000..94e542d
--- /dev/null
+++ b/data_selector/db/data_selector.cmp.kpt
@@ -0,0 +1,10 @@
+
+
+
+
+
+
+
+
+
+
diff --git a/data_selector/db/data_selector.cmp.logdb b/data_selector/db/data_selector.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/data_selector/db/data_selector.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/data_selector/db/data_selector.cmp.rdb b/data_selector/db/data_selector.cmp.rdb
new file mode 100644
index 0000000000000000000000000000000000000000..5b5c1b5a7eda79415515509d95de75de28ae17cd
GIT binary patch
literal 15586
zcmch8W0NpEu;tjcZQHhO+qP}n_B>Mu)eR2-08j%B
z2w?YL;Njl``4pe28N+t`_6LAI{mwB-mt;;>unp@2#L%Hx=uz{^zdp;BvivY`(^kk0#FZ?8)1KzzffT
zg5V&iBR7cS+U0vL^fGRo=P+RBO`8v2XDpX3kKpohFoe&V
zQ{`{-p8mTxZS*pJo?p>EMus+U-9oS!o43$=u{P&L6*~%c-nVa&N
z0Zxr*qnonU7rM=T*y+%#Z?bjReiP?D=ztzV5|PkDx15$u*U6_|OYhu+$~6oa;QPn-
z!It1$IEu&f))P=qXwLhv0ul?q*lzn*aKR@Jj&radQDZo*Uht4We<;WXo?cvQqjeU-
zXBUi!>D+hVx{XWv-Lm(;ZmY3iwYSPj*ezT7b_cD4TKutiZH0uvzfh-#zq{6Kp#$T^
zRqasxp_bb>@a2fMo`cN2bo2)Pw%*8Weo*Aazp=?_f4?_p0I#QFi_*(j{(|9{aVYWn
ztMe!ac!(I``n4Mxo6qvydR7Mew$3q(aVukoU)RHLz;DM%tUf;${Q!*y;b!K+xtg@K
ztD()6?3={GPjJQa;++_L_nGy&*rtl>eDqC-ee|?H1iHb;+}li^=%0=kcso?6K9-O_
z#%uhRo;*zr2%o#-3VYH!iJTDn0ex)^4=fh&-|_4vW#>a!9v=Gv=zfdVc?rJuoBn(@
z@S}d<@tFhfAGg|jaJ-I$iM;H2_zd87{M;tux}z4l&zWDvwxv!7;5YIGZPc$ppWS6T
zE{r`z37)gfqaF=&G`j_cdF!%pm^zN{{I@^wzd!khluAALEMN{RpyL5IUcitzmOu`G
z+DDE8knemD2Jv;NzPq*qFUo5vTXw+gilcg5xWRXKpx`Xf?EV4GtRGhBNcY+-r@N~(3qzvZ6CxpWs{`D7lad&Z7<|>nVfJx{RX~kZ}VQ|3!344
zun6?JB79S*aqC(5bjOa6jbO8?57t-!1F5bROcro-$1-~%69lh^JtlY#nSIMOm#`aS{&VBe9r2vNCR=`=)oTW%AS#S~h4RRALEwc54NNf}1h<6UyRQ2&
z&8NtChH23`^L8<^wUEubkJwX6BPIX{so1qkw{KD9ctRB-44n&hd6Ic%w7&xG0AWAd
z?TmNt8Z^pN6MVvC(88!{!79mHPh`M~0!P1waXiFWLmZkK#^hU42ewLqPh7@^r@emC
zrl&W=M9VI@@J&Ozq#KWUt$F_UHzV5LQx1nam~G2;VqvCd6$Q8GblKLD$_VBJ3kBw1n1nxH_qwZPwRK&HaJN}
zTu*NQgyYp5e0)j2h&%ygj&QzvpqPF?XltGWqLl9VpMxB3$`5)XB07*jtIut>`mI|Q
zAWft|c%)){FWM^E2C{K^MRWF+(-(JBjnm=Zf(^~}u_$m{H!0gmjCt5?A8SZzY@MYG
z`i=D&B_jj5UE0?y+)>xO6%@PpJwctrfrYyJ$813-H8pq!9_e%B_
z41r<){t4743_0w?R6-t9wJ#W{IG4F^!O7A>AyS_l9z1|>mtFZoB-h<7zO*;d3lasP
z;YzyWVr>;>C5}&EdJvl8O2qXNSf44K6(?dw!r+u_t;~(Z^{Em^w|{I!7Ldw`m!*op
zA)?{)0F{*mOl3gpvjzzpl^m_l+()O56F6^QY1HrH2uNs$FaBG9N2!BB58)Skf6%DV
zq4@xI-|t|wInO+`DZ$Sj0m_kL
zEtYin$tS{QSPTaALom3X<~mStGO>{B5OSfokQ)B6kdL*2Vn+oCg$f(yXai=P9?
z0>Yb{87}6L*Ca7{xpy*?-e9xqIJ}D7enUnqbNcTzX(Og&LcN2
zpKrrJ&(|OX76(O-8d_R=MF^P!Bob@
zzTWR2pvFQ27B1nrfV~p^TAtlfV^op0XB_C#+8dUVjX?(aXaYVwU~SQcY;3;NTGu~mH8z)@kVj@{W$
z7PG~UjgF~j&YYieDaAm(tm~$=_eQkdL561C-)J>Ysv(Dsjm`n-&@(yV#ShP#Q-#XF
zWTJNTH`!l$XTZdAuG5*L+#lr7W-;KU-e#ZO*B8=IViXj~f>aXTy!Tl649eUme7vL9
zvKXV#KCf67Y|?xC)MgYfx^FAY-5*C}dVPioxHfUTWFJOW=KKz~VUZ{RK_L76&0XYt
z5DiMo%zm`(bN~_&UB@mNv`~7N@(hfbEi5|
z&LmfUv!yh(CHXTQDX0JcH~O;MM?wb7r1b$$r_jde!oN`a;?{-lLL(eefG-iWGVJNZ
zmoE7Bt|*g?g3r`GfAKtrmM1?bE8AXtio^%m=2dZ{6;&z<7#YCbwoq9_yb&u2_#U=~
zeLzKS!nj#2c6*wOpyTB{;akEb)m3^^ypiT2?t9Dix51M#WZ@yMLcX^mI!>0^Z^K!L(yIZeL8vs-b74;%Ko#7YLFjO6zR{@XiT
z{W?0&?K>8)c82r4V;Jz|d0?K80`>rSp@a8-x+#nJrvTqA=gu)cUru_7oImzr`D-u>
zuYpL8w0Cs4|9oX$NXoM@nP>3=H><}oPrVV`3MRj4ZR)E)3%vSvDt+pKzH(UdmP_0FTu^k7IcejGNxg?r5qa%92%
zKB&TZZPj$n`QF_mH91A@KZ-Z#P9=`h}si0jx`
zlJr#>)+p}I(e0VH?f)QQ`==~<<>aNZW$zvg?K8!9euVk^162d_+tAelF{?E1-uHQ3
z$5(Qaq`UvJlT0ReF${=cm`T2W<3I8jI#;xfHoKBk^X={^p^OY}K&;Wz0H6Z~?kv@v
zH4l}a-1m-rz_Y%gn8R@?%MODr&&1ZVOr-ddfFsl!W0KZEHBn9cN0dW2ajRO*Nyyt5
zm7czU-00wwJfznNmA>G8Bmvi6a8v1G
zHwni%o_Arg?6uZ&j-O52i_Kebc8G7-606$&l?QJuI+58EO}(%mR`P0RS7^#VNLZ!y
zS*E3-)RSNwxNgTr7sVty?NT&&tS)d-DDckZ%0{*a*g5
zk&&6GTEp1X5;6A
zoJV@0%7ZbM^`H!wHQ=ip#<;gu`|M0Cnx{PWT3Vs~`%@$+-k
z$kNu-*3`GOU6C$r@@>_m?`IGQB{NU(TZ-JM?eSO96@Px$w_Ux){_YNUrOge#`TFzH
z0vBBP((cZ5wI%2)(BS)ShJyVSqZ|zM<{a`Atnv&5)F@_0#!&?pVu>l_|LFM%4;D
z^_KTbR-SIXzZVx&q|s%*hxiz69X|)xO|B;uH3R)nnmzZoxFUro5vM#ug@LX5YYk*4
z%Y<%@cBH6*3xnxn{~I4e{B=e*wXk=gfR*ZR6*xRBOs4&9|G&p;@tjJN!2aEN5!2lE
z3Ljduy`;Zp)zXoo$A8_8R&ICY(GiuY#=A)NQk9caBP}kbD1~sLXOS}1`g)Y5SHUz+
zl~ALvi2RLa+F7B>*~s$>DZE&0rOgd_fU#EO+tSOS|H?~)m06}pSb{z?&Sl|FyY!B_
zBN5MX?fmBx1!I%tan@>$)2?yVqQhjRCIYVrIb~dw$P;bBcUDF3y0-=(#Hru#;;3)<
zZiIVti`RVKeg8!Q=irV5-;nmk(e5`Y9XD!6StPQ*;(%PHfCo$
z_JYOG;AYJo3(E`CjH=5GrR5LQ>q(ZcNOe$7Py9euDq|c^z2bsJC6w7?vkjuld4a#)
zQ3Vb%C5qC#WEh@o&=`6@0hP?)x(7Pg;?mN?Pi{Ye$>u7+Bv-iNerd<;-YF$gkNnzL
zL+A??_yBbxgRjxzLhvx#6!27~J%L=}};bTTxa+L7R%|4tMKIDby@DyAXzx2ZW$6qV=ibY0>O)b;Chs
ze3PbTc5pmX^r4%VU^nkqUTR2V0Isd+`vI42^K&s!0W}?cl3C7EA(lbV_a<3v14gEN
zKg3=b<5HOhlr9grXGkJ+?=+iuZL*bV(hW7ivh|xzXcRrGsS>FQ$HauiIPfZU);qOq
zL1E2^bG4CszX5q@XwwvucTk**X1H%vteVKzD}}gK^8_(v69{Ns^6%g0Z6|EUOk&-)
z(>=hW9pvrMXI0Mf<=OIVE0~_jntx+l5{iH$L+kUN8lNF^>%fIQR2UCU0??_l#yG^j
z2IC%aR{S{&AOE>!+*A)i7xyW$xJSKPcF{c@a*gy(14()1y8+7xk9)iS?mq+XO}c;g
zy9aCjyfY^2^5)lB_a}6}OU$fMUQ}j2h!DQhOy03^8!eHno$6w1FuL~9W_!Q^V{lZN
zS`nAVwFDzyDhP9atVpGhR}@sjfC0pa>ZjI=cqDPgd*-eZ^3Z)V_vap
zBfTot37jU=(C~9?HZqvI>I>rC8Murhr@{I=?C)pcc0+OV8(kOgd}kFfa>tZi3>(Oc
z)gRk`E+0TuZg7n-)nN{iG~X_ys!
ztHcj5L>KeRE08CtRYy0<=Ijt+?8B_e)uh6cI
zaV|$V9k^$FmJb7bYF^N43yiy_usMitKiXh-CobF+IUH&J+o`4)_{x1rb}waiDL_tJ*X2=|LN+#u8&Yt$re0X&k4~VT7NW%UsnXAX=-ztB9^i5=?W&;
zc7i6@WR*l$Iboa5XddNh>Z1HEg-i1znl2YL<`g-w)GQKlB;n=u6QIpGRixO7F!SElRgfROSq<9+5QPNnG6thGLVKei_}0?Z#E(K<8m0Xisop1Ua;j<3q{Rm1?9zf>Em
z98zOq=2+zATaku=XO#=;NeH&_ux10-aJ{N9BsWPHD9Gq;yXqO|puP&>-h)R5V!n6}
z3HvPsBO)+N
zBin$8=nKmM(npKtWGdpg*f^EdBG_h5RnCG);UC7B
zXKi#2lRY%LMI)wgYmFC^LXy?o05OaTv*p+fjnT+_^UOrWcMb+i3)74cIGJpR90<>E
z@jB}(V@gE)l80VT%|yu9iv-4?7*xByix54?AfB^wVegaAA^-U0_A^A?nXL`ajHA5JV1YfQj_y!msb+_HDvbT@{rUgGP%8(W$)i@i??eXck%6^NF*+{;w1EXHeM>IIIDxD%qW_
z4G&k<9gh0}OJyYn%K_HYFSM>UeR+E?YV9ksV)u2|?Z?8|-+sz22ERC*4wK}y*^_NK
zM|{bAd9v-u+PELF87%RTipm^GTMz)cbWs4a4sTE+Y{uB%?VmQr>v^w=LqS@SClX8k
zd}9tMM>6!!kb+}rYlnZEa!nxvU~&C$!Zd*eT|i<2t1ejp+P(^#{;E(I?qpc3XH3nD
zXF%88z)=`w3dA@ia411*{KYS&kaI6DFoBq7Q7~s;o3)$CydJt4;!%_g37)Gqutj=flo-uwE+1F=u+3uoIhOM^
zY)www5US*iZZKNu|sTMIDRq(X%i!lA$kWb}*mP
zEJq+7NbedL^^#eBb*MF=Xe9&|9tc<>VYG4gIF_?n9WTjF%mO>62=0bEb{DW3|0a5X3jjy$vl
zIovt!U#9yZdlrnqo}qdh8bg_J+!NT+m&GpaxAPw+%mp?PSNftta1!982RS*4
z!;MW$&$W%ttxSc*oRW)pO$8UvwWxZex(oz268@>zLc|DN*c+q_W?5tH}E(7(e~{?Xe)A0Im8w=9w9O*Lgr2?eV6MN
zjPEZ|Kq#AlI8Tb5ftDDeV0ruOIlrKJvFYhzojx7#IC{=C65@hsW*DjT2pSM>}6t5Z%
zckMi-Lb1W}giJ}!0!OcQT{o>-L@Q$Gxh#4q?R+8YI$gI*I7^LFh{eQnQ1^U#ey_LwooAE*ibtFA0uo30Fnq8wA
zDYaIj(rM*UXlO?`7Dvu86Md03LUplD0Wwm@J`aJZlrt2GNDnHbicsS|^%;09!o-!w
zqYIDEKe_xavmDmhg?nI5lmlJq4~=3oPoG#wt#jf74ws4}6eK!9ocKI1h)I}kK==c8
zE?J-O^wMbhU!P^3+c#S7=9ofYH|-MGUH
zvXrINop4he#}_v13R>+}1`2_y5-j?GP26Z#7z|5A$c<5p0nQaSF;cmV-1s0qAjO*&
zv~W~x&5{Av7&?Rky6g`LlPP9gc)%rlazXJvVQ+Dr8eAewm9Ale?(VwLi1d>$3f4>k
zDPFkGg*XzCBl{*NM=X~3p;Nllb=o3@6F=2;ha!PBfC1Tj0M$1-_jF*>Q*p5|?gko0
zk{#qwYtqv9kw*qD?&in?%B)8Tswm8X4-haE%RWKf)g%|`1b1E0ys((5N8{R7na&xQ
z8~8KV1;lfm>_z!lD3DDu3<;u{bpk3s9#c!^6uv|LHMScaH8tWb&7WW>LMCoJFwL#k
z7J;fW&JA#NU}KCkJ`DJT6d}1u^or$55wn5vs6ZUfpSNyh3{?su@AKB;HD~{@6>+Qt
z2eao)Tsm{0^jSw>h%!~PQ_&pfy!2TX+sNCx%6aLw*Kpz84rsD@q^xY=@DFjIqvYHM
zP0olDaD;=#dqi{A9^>aQL(DP;pgYTAd~qzt_;Dbe05@VDZA*LD>?EHboCEB9tK)0E
z0iBS}qPx>m)Q6s?GV5%mK+&C~_?RC;da=l{^Bo$KG*W-;kIdD=-k18HU+6kps?@6DyFcv3
zwtwc8NzaM~Nz78eS{jf1P;Opzp+f&1s?tNru6eG*>}4#L9S4X3m8f_4!ej
zV0?n4Opi=?h(vzerY%_G@)WaK9K}5
z9i1d-ujEnzMW!N5V+0w7T{!P`$>RQGkW9zlrt8Veq%!bqKgWiem}h@7q$;g9x4<)o
z3I2<)qnW5L#GYy4@8!^B<$Ot6CBQ1~K~Qu0PHJ
zm>9U$HB9hukQ8-5vTs7<4P-H^&!14Pw6E~>L~?j*2lKJ=xN}yOsn=#)kB_*Q-<8sL_FX|6T|EAXT~6om2tRhUg8p?48*w
zVC7JQc&gypS`KoC@L$L@stF@olNEc$TclT+cVTmJr7=>c`d3UPFOeQx#M?>3sS!k~
z@bLJDk(>1xPPz5L#uh76XKN+PO%mOEQ~-p`W+u6I3IYJC!y!G9dCH
z+WXDlU@wtyKoxam@Bnm#`BiHO@WA
z2?ZmK_mz6f)Y;I2f2@6B7BJVG!CvM#h>cGnO00z7ORG9E`!X-D%>rrwA+vGyrs0*e
z`%>rl8wPgcff);KJx8^s0F7>d#CG5VDS`gO6%20((5V7>2E@kIy@I?X>2U2A5gmK=
z(d*hp%(BGFm(c9iBPW7?1&
zTPjMmk~;VVvE^Z-?)bfP*Gy#Hk$hYiuIiG$Fbbi5wBMQBxQLMewfBP
zSa35fGyk|enIH}0v?Sy#