diff --git a/.gitignore b/.gitignore index dec3de3..96225e0 100644 --- a/.gitignore +++ b/.gitignore @@ -11,40 +11,39 @@ # *.sdc # ignore Quartus II generated folders -*_sim -db -greybox_tmp -incremental_db -simulation -testbench -timing +**/*_sim/ +**/db/ +**/greybox_tmp/ +**/incremental_db/ +**/simulation/ +**/testbench/ +**/timing/ # ignore Quartus II generated files -*_generation_script* -*_inst.vhd -*.bak -*.cmp -*.done -*.eqn -*.hex -*.html -*.jdi -*.jpg -*.mif -*.pin -*.pof -*.ptf.* -*.qar -*.qarlog -*.qws -*.rpt -*.smsg -*.sof -*.sopc_builder -*.summary -*.tcl -*.txt # Explicitly add any text files used -*~ -*example* -*sopc_* -PLLJ_PLLSPE_INFO.txt # The generated PLL specification file +**/*_generation_script* +**/*_inst.vhd +**/*.bak +**/*.cmp +**/*.done +**/*.eqn +**/*.hex +**/*.html +**/*.jdi +**/*.jpg +**/*.mif +**/*.pin +**/*.pof +**/*.ptf.* +**/*.qar +**/*.qarlog +**/*.qws +**/*.rpt +**/*.smsg +**/*.sof +**/*.sopc_builder +**/*.summary +**/*.tcl +**/*.txt # Explicitly add any text files used +**/*example* +**/*sopc_* +**/PLLJ_PLLSPE_INFO.txt # The generated PLL specification file diff --git a/38_decoder/38_decoder.asm.rpt b/38_decoder/38_decoder.asm.rpt deleted file mode 100644 index c616fae..0000000 --- a/38_decoder/38_decoder.asm.rpt +++ /dev/null @@ -1,129 +0,0 @@ -Assembler report for 38_decoder -Tue Mar 08 15:12:41 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Assembler Summary - 3. Assembler Settings - 4. Assembler Generated Files - 5. Assembler Device Options: D:/projects/quartus/38_decoder/38_decoder.sof - 6. Assembler Device Options: D:/projects/quartus/38_decoder/38_decoder.pof - 7. Assembler Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+---------------------------------------------------------------+ -; Assembler Summary ; -+-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Tue Mar 08 15:12:41 2022 ; -; Revision Name ; 38_decoder ; -; Top-level Entity Name ; 38_decoder ; -; Family ; Cyclone II ; -; Device ; EP2C8Q208C8 ; -+-----------------------+---------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------+ -; Assembler Settings ; -+-----------------------------------------------------------------------------+----------+---------------+ -; Option ; Setting ; Default Value ; -+-----------------------------------------------------------------------------+----------+---------------+ -; Use smart compilation ; Off ; Off ; -; Generate compressed bitstreams ; On ; On ; -; Compression mode ; Off ; Off ; -; Clock source for configuration device ; Internal ; Internal ; -; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; -; Divide clock frequency by ; 1 ; 1 ; -; Auto user code ; Off ; Off ; -; Use configuration device ; On ; On ; -; Configuration device ; Auto ; Auto ; -; Configuration device auto user code ; Off ; Off ; -; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; -; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; -; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; -; Hexadecimal Output File start address ; 0 ; 0 ; -; Hexadecimal Output File count direction ; Up ; Up ; -; Release clears before tri-states ; Off ; Off ; -; Auto-restart configuration after error ; On ; On ; -; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ; -; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; -; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; -; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; -; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; -+-----------------------------------------------------------------------------+----------+---------------+ - - -+-----------------------------------------------+ -; Assembler Generated Files ; -+-----------------------------------------------+ -; File Name ; -+-----------------------------------------------+ -; D:/projects/quartus/38_decoder/38_decoder.sof ; -; D:/projects/quartus/38_decoder/38_decoder.pof ; -+-----------------------------------------------+ - - -+-------------------------------------------------------------------------+ -; Assembler Device Options: D:/projects/quartus/38_decoder/38_decoder.sof ; -+----------------+--------------------------------------------------------+ -; Option ; Setting ; -+----------------+--------------------------------------------------------+ -; Device ; EP2C8Q208C8 ; -; JTAG usercode ; 0xFFFFFFFF ; -; Checksum ; 0x000C10D6 ; -+----------------+--------------------------------------------------------+ - - -+-------------------------------------------------------------------------+ -; Assembler Device Options: D:/projects/quartus/38_decoder/38_decoder.pof ; -+--------------------+----------------------------------------------------+ -; Option ; Setting ; -+--------------------+----------------------------------------------------+ -; Device ; EPCS4 ; -; JTAG usercode ; 0x00000000 ; -; Checksum ; 0x06F0221B ; -; Compression Ratio ; 3 ; -+--------------------+----------------------------------------------------+ - - -+--------------------+ -; Assembler Messages ; -+--------------------+ -Info: ******************************************************************* -Info: Running Quartus II Assembler - Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Tue Mar 08 15:12:41 2022 -Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder -Info: Writing out detailed assembly data for power analysis -Info: Assembler is generating device programming files -Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled -Info: Quartus II Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 241 megabytes - Info: Processing ended: Tue Mar 08 15:12:41 2022 - Info: Elapsed time: 00:00:00 - Info: Total CPU time (on all processors): 00:00:00 - - diff --git a/38_decoder/38_decoder.done b/38_decoder/38_decoder.done deleted file mode 100644 index fcc5548..0000000 --- a/38_decoder/38_decoder.done +++ /dev/null @@ -1 +0,0 @@ -Tue Mar 08 15:12:42 2022 diff --git a/38_decoder/38_decoder.fit.rpt b/38_decoder/38_decoder.fit.rpt deleted file mode 100644 index 24201f7..0000000 --- a/38_decoder/38_decoder.fit.rpt +++ /dev/null @@ -1,892 +0,0 @@ -Fitter report for 38_decoder -Tue Mar 08 15:12:40 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Fitter Summary - 3. Fitter Settings - 4. Parallel Compilation - 5. Incremental Compilation Preservation Summary - 6. Incremental Compilation Partition Settings - 7. Incremental Compilation Placement Preservation - 8. Pin-Out File - 9. Fitter Resource Usage Summary - 10. Input Pins - 11. Output Pins - 12. I/O Bank Usage - 13. All Package Pins - 14. Output Pin Default Load For Reported TCO - 15. Fitter Resource Utilization by Entity - 16. Delay Chain Summary - 17. Pad To Core Delay Chain Fanout - 18. Non-Global High Fan-Out Signals - 19. Interconnect Usage Summary - 20. LAB Logic Elements - 21. LAB Signals Sourced - 22. LAB Signals Sourced Out - 23. LAB Distinct Inputs - 24. Fitter Device Options - 25. Operating Settings and Conditions - 26. Estimated Delay Added for Hold Timing - 27. Advanced Data - General - 28. Advanced Data - Placement Preparation - 29. Advanced Data - Placement - 30. Advanced Data - Routing - 31. Fitter Messages - 32. Fitter Suppressed Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------------+ -; Fitter Summary ; -+------------------------------------+----------------------------------------------+ -; Fitter Status ; Successful - Tue Mar 08 15:12:40 2022 ; -; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; -; Revision Name ; 38_decoder ; -; Top-level Entity Name ; 38_decoder ; -; Family ; Cyclone II ; -; Device ; EP2C8Q208C8 ; -; Timing Models ; Final ; -; Total logic elements ; 8 / 8,256 ( < 1 % ) ; -; Total combinational functions ; 8 / 8,256 ( < 1 % ) ; -; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ; -; Total registers ; 0 ; -; Total pins ; 11 / 138 ( 8 % ) ; -; Total virtual pins ; 0 ; -; Total memory bits ; 0 / 165,888 ( 0 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; -; Total PLLs ; 0 / 2 ( 0 % ) ; -+------------------------------------+----------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Settings ; -+--------------------------------------------------------------------+--------------------------------+--------------------------------+ -; Option ; Setting ; Default Value ; -+--------------------------------------------------------------------+--------------------------------+--------------------------------+ -; Device ; EP2C8Q208C8 ; ; -; Minimum Core Junction Temperature ; 0 ; ; -; Maximum Core Junction Temperature ; 85 ; ; -; Fit Attempts to Skip ; 0 ; 0.0 ; -; Device I/O Standard ; 3.3-V LVTTL ; ; -; Use smart compilation ; Off ; Off ; -; Use TimeQuest Timing Analyzer ; Off ; Off ; -; Router Timing Optimization Level ; Normal ; Normal ; -; Placement Effort Multiplier ; 1.0 ; 1.0 ; -; Router Effort Multiplier ; 1.0 ; 1.0 ; -; Always Enable Input Buffers ; Off ; Off ; -; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; -; Optimize Multi-Corner Timing ; Off ; Off ; -; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; -; Optimize Timing ; Normal compilation ; Normal compilation ; -; Optimize Timing for ECOs ; Off ; Off ; -; Regenerate full fit report during ECO compiles ; Off ; Off ; -; Optimize IOC Register Placement for Timing ; On ; On ; -; Limit to One Fitting Attempt ; Off ; Off ; -; Final Placement Optimizations ; Automatically ; Automatically ; -; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; -; Fitter Initial Placement Seed ; 1 ; 1 ; -; PCI I/O ; Off ; Off ; -; Weak Pull-Up Resistor ; Off ; Off ; -; Enable Bus-Hold Circuitry ; Off ; Off ; -; Auto Global Memory Control Signals ; Off ; Off ; -; Auto Packed Registers ; Auto ; Auto ; -; Auto Delay Chains ; On ; On ; -; Auto Merge PLLs ; On ; On ; -; Ignore PLL Mode When Merging PLLs ; Off ; Off ; -; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; -; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; -; Perform Register Duplication for Performance ; Off ; Off ; -; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; -; Perform Register Retiming for Performance ; Off ; Off ; -; Perform Asynchronous Signal Pipelining ; Off ; Off ; -; Fitter Effort ; Auto Fit ; Auto Fit ; -; Physical Synthesis Effort Level ; Normal ; Normal ; -; Auto Global Clock ; On ; On ; -; Auto Global Register Control Signals ; On ; On ; -; Stop After Congestion Map Generation ; Off ; Off ; -; Save Intermediate Fitting Results ; Off ; Off ; -; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; -+--------------------------------------------------------------------+--------------------------------+--------------------------------+ - - -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 4 ; -; Maximum allowed ; 4 ; -; ; ; -; Average used ; 1.00 ; -; Maximum used ; 4 ; -; ; ; -; Usage by Processor ; % Time Used ; -; 1 processor ; 100.0% ; -; 2-4 processors ; < 0.1% ; -+----------------------------+-------------+ - - -+----------------------------------------------+ -; Incremental Compilation Preservation Summary ; -+-------------------------+--------------------+ -; Type ; Value ; -+-------------------------+--------------------+ -; Placement ; ; -; -- Requested ; 0 / 19 ( 0.00 % ) ; -; -- Achieved ; 0 / 19 ( 0.00 % ) ; -; ; ; -; Routing (by Connection) ; ; -; -- Requested ; 0 / 0 ( 0.00 % ) ; -; -- Achieved ; 0 / 0 ( 0.00 % ) ; -+-------------------------+--------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Incremental Compilation Partition Settings ; -+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ -; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; -+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ -; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; -+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ - - -+--------------------------------------------------------------------------------------------+ -; Incremental Compilation Placement Preservation ; -+----------------+---------+-------------------+-------------------------+-------------------+ -; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; -+----------------+---------+-------------------+-------------------------+-------------------+ -; Top ; 19 ; 0 ; N/A ; Source File ; -+----------------+---------+-------------------+-------------------------+-------------------+ - - -+--------------+ -; Pin-Out File ; -+--------------+ -The pin-out file can be found in D:/projects/quartus/38_decoder/38_decoder.pin. - - -+-------------------------------------------------------------------+ -; Fitter Resource Usage Summary ; -+---------------------------------------------+---------------------+ -; Resource ; Usage ; -+---------------------------------------------+---------------------+ -; Total logic elements ; 8 / 8,256 ( < 1 % ) ; -; -- Combinational with no register ; 8 ; -; -- Register only ; 0 ; -; -- Combinational with a register ; 0 ; -; ; ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 0 ; -; -- 3 input functions ; 8 ; -; -- <=2 input functions ; 0 ; -; -- Register only ; 0 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 8 ; -; -- arithmetic mode ; 0 ; -; ; ; -; Total registers* ; 0 / 8,646 ( 0 % ) ; -; -- Dedicated logic registers ; 0 / 8,256 ( 0 % ) ; -; -- I/O registers ; 0 / 390 ( 0 % ) ; -; ; ; -; Total LABs: partially or completely used ; 1 / 516 ( < 1 % ) ; -; User inserted logic elements ; 0 ; -; Virtual pins ; 0 ; -; I/O pins ; 11 / 138 ( 8 % ) ; -; -- Clock pins ; 0 / 4 ( 0 % ) ; -; Global signals ; 0 ; -; M4Ks ; 0 / 36 ( 0 % ) ; -; Total block memory bits ; 0 / 165,888 ( 0 % ) ; -; Total block memory implementation bits ; 0 / 165,888 ( 0 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; -; PLLs ; 0 / 2 ( 0 % ) ; -; Global clocks ; 0 / 8 ( 0 % ) ; -; JTAGs ; 0 / 1 ( 0 % ) ; -; ASMI blocks ; 0 / 1 ( 0 % ) ; -; CRC blocks ; 0 / 1 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; -; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ; -; Maximum fan-out node ; I2 ; -; Maximum fan-out ; 8 ; -; Highest non-global fan-out signal ; I2 ; -; Highest non-global fan-out ; 8 ; -; Total fan-out ; 32 ; -; Average fan-out ; 1.45 ; -+---------------------------------------------+---------------------+ -* Register count does not include registers inside RAM blocks or DSP blocks. - - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Input Pins ; -+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ; -+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ -; I0 ; 77 ; 4 ; 18 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; I1 ; 80 ; 4 ; 23 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; I2 ; 81 ; 4 ; 23 ; 0 ; 1 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Output Pins ; -+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; -+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ -; Y0 ; 142 ; 3 ; 34 ; 12 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; Y1 ; 143 ; 3 ; 34 ; 13 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; Y2 ; 144 ; 3 ; 34 ; 13 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; Y3 ; 145 ; 3 ; 34 ; 14 ; 4 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; Y4 ; 146 ; 3 ; 34 ; 15 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; Y5 ; 147 ; 3 ; 34 ; 15 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; Y6 ; 149 ; 3 ; 34 ; 16 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; Y7 ; 150 ; 3 ; 34 ; 16 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ - - -+-----------------------------------------------------------+ -; I/O Bank Usage ; -+----------+-----------------+---------------+--------------+ -; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; -+----------+-----------------+---------------+--------------+ -; 1 ; 2 / 32 ( 6 % ) ; 3.3V ; -- ; -; 2 ; 0 / 35 ( 0 % ) ; 3.3V ; -- ; -; 3 ; 9 / 35 ( 26 % ) ; 3.3V ; -- ; -; 4 ; 3 / 36 ( 8 % ) ; 3.3V ; -- ; -+----------+-----------------+---------------+--------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; All Package Pins ; -+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; -+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -; 1 ; 0 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; -; 2 ; 1 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; -; 3 ; 2 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 4 ; 3 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 5 ; 4 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 6 ; 5 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 8 ; 6 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 10 ; 7 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 11 ; 8 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 12 ; 9 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 13 ; 10 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 14 ; 18 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 15 ; 19 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; -; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; -; 18 ; 22 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; -; 19 ; 23 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; -; 20 ; 24 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ; -; 21 ; 25 ; 1 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ; -; 22 ; 26 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; -; 23 ; 27 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 24 ; 28 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 26 ; 29 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; -; 27 ; 30 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 28 ; 31 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 30 ; 32 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 31 ; 33 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 33 ; 35 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 34 ; 36 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 35 ; 37 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 37 ; 39 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 39 ; 43 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 40 ; 44 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 41 ; 45 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 42 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 43 ; 48 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 44 ; 49 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 45 ; 50 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 46 ; 51 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 47 ; 52 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 48 ; 53 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 49 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 50 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; -; 51 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 52 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; -; 53 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 54 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; -; 55 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 56 ; 54 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 57 ; 55 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 58 ; 56 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 59 ; 57 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 60 ; 58 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 61 ; 59 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 63 ; 60 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 64 ; 61 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 67 ; 69 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 68 ; 70 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 69 ; 71 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 70 ; 74 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 71 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 72 ; 75 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 74 ; 76 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 75 ; 77 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 76 ; 78 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 77 ; 79 ; 4 ; I0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 80 ; 82 ; 4 ; I1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 81 ; 83 ; 4 ; I2 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 82 ; 84 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 83 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 84 ; 85 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 85 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 86 ; 86 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 87 ; 87 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 88 ; 88 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 89 ; 89 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 90 ; 90 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 91 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 92 ; 91 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 94 ; 92 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 95 ; 93 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 96 ; 94 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 97 ; 95 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 98 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 99 ; 96 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 100 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 101 ; 97 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 102 ; 98 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 103 ; 99 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 104 ; 100 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 105 ; 101 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 106 ; 102 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 107 ; 105 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 108 ; 106 ; 3 ; ~LVDS54p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 109 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 110 ; 107 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 111 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 112 ; 108 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 113 ; 109 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 114 ; 110 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 115 ; 112 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 116 ; 113 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 117 ; 114 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 118 ; 117 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 119 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 120 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 121 ; 121 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; -; 122 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 123 ; 122 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; -; 124 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 125 ; 123 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; -; 126 ; 124 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; -; 127 ; 125 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 128 ; 126 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 129 ; 127 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 130 ; 128 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 131 ; 129 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 132 ; 130 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 133 ; 131 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 134 ; 132 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 135 ; 133 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 136 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 137 ; 134 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 138 ; 135 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 139 ; 136 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 141 ; 137 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 142 ; 138 ; 3 ; Y0 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 143 ; 141 ; 3 ; Y1 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 144 ; 142 ; 3 ; Y2 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 145 ; 143 ; 3 ; Y3 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 146 ; 149 ; 3 ; Y4 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 147 ; 150 ; 3 ; Y5 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 148 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 149 ; 151 ; 3 ; Y6 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 150 ; 152 ; 3 ; Y7 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 151 ; 153 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 152 ; 154 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 153 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 154 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; -; 155 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 156 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; -; 157 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 158 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; -; 159 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 160 ; 155 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 161 ; 156 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 162 ; 157 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 163 ; 158 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 164 ; 159 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 165 ; 160 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 166 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 167 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 168 ; 161 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 169 ; 162 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 170 ; 163 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 171 ; 164 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 172 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 173 ; 165 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 174 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 175 ; 168 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 176 ; 169 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 177 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 178 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 179 ; 173 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 180 ; 174 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 181 ; 175 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 182 ; 176 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 183 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 184 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 185 ; 180 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 186 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 187 ; 181 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 188 ; 182 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 189 ; 183 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 190 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 191 ; 184 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 192 ; 185 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 193 ; 186 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 194 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 195 ; 187 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 196 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 197 ; 191 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 198 ; 192 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 199 ; 195 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 200 ; 196 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 201 ; 197 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 202 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 203 ; 198 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 204 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 205 ; 199 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 206 ; 200 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 207 ; 201 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 208 ; 202 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -Note: Pin directions (input, output or bidir) are based on device operating in user mode. - - -+-------------------------------------------------------------------------------+ -; Output Pin Default Load For Reported TCO ; -+----------------------------------+-------+------------------------------------+ -; I/O Standard ; Load ; Termination Resistance ; -+----------------------------------+-------+------------------------------------+ -; 3.3-V LVTTL ; 0 pF ; Not Available ; -; 3.3-V LVCMOS ; 0 pF ; Not Available ; -; 2.5 V ; 0 pF ; Not Available ; -; 1.8 V ; 0 pF ; Not Available ; -; 1.5 V ; 0 pF ; Not Available ; -; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ; -; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ; -; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; -; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; -; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; -; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; -; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; -; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; -; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; -; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; -; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ; -; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ; -; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ; -; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ; -; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ; -; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ; -; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ; -; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ; -; LVDS ; 0 pF ; 100 Ohm (Differential) ; -; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ; -; RSDS ; 0 pF ; 100 Ohm (Differential) ; -; Simple RSDS ; 0 pF ; Not Available ; -; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ; -+----------------------------------+-------+------------------------------------+ -Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Resource Utilization by Entity ; -+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ -; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; -+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ -; |38_decoder ; 8 (8) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 11 ; 0 ; 8 (8) ; 0 (0) ; 0 (0) ; |38_decoder ; work ; -+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ -Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. - - -+-------------------------------------------------------------------------------+ -; Delay Chain Summary ; -+------+----------+---------------+---------------+-----------------------+-----+ -; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; -+------+----------+---------------+---------------+-----------------------+-----+ -; Y7 ; Output ; -- ; -- ; -- ; -- ; -; Y0 ; Output ; -- ; -- ; -- ; -- ; -; Y1 ; Output ; -- ; -- ; -- ; -- ; -; Y2 ; Output ; -- ; -- ; -- ; -- ; -; Y3 ; Output ; -- ; -- ; -- ; -- ; -; Y4 ; Output ; -- ; -- ; -- ; -- ; -; Y5 ; Output ; -- ; -- ; -- ; -- ; -; Y6 ; Output ; -- ; -- ; -- ; -- ; -; I2 ; Input ; 6 ; 6 ; -- ; -- ; -; I0 ; Input ; 6 ; 6 ; -- ; -- ; -; I1 ; Input ; 6 ; 6 ; -- ; -- ; -+------+----------+---------------+---------------+-----------------------+-----+ - - -+---------------------------------------------------+ -; Pad To Core Delay Chain Fanout ; -+---------------------+-------------------+---------+ -; Source Pin / Fanout ; Pad To Core Index ; Setting ; -+---------------------+-------------------+---------+ -; I2 ; ; ; -; - inst10~0 ; 0 ; 6 ; -; - inst10~1 ; 0 ; 6 ; -; - inst10~2 ; 0 ; 6 ; -; - inst10~3 ; 0 ; 6 ; -; - inst10~4 ; 0 ; 6 ; -; - inst10~5 ; 0 ; 6 ; -; - inst10~6 ; 0 ; 6 ; -; - inst10~7 ; 0 ; 6 ; -; I0 ; ; ; -; - inst10~0 ; 1 ; 6 ; -; - inst10~1 ; 1 ; 6 ; -; - inst10~2 ; 1 ; 6 ; -; - inst10~3 ; 1 ; 6 ; -; - inst10~4 ; 1 ; 6 ; -; - inst10~5 ; 1 ; 6 ; -; - inst10~6 ; 1 ; 6 ; -; - inst10~7 ; 1 ; 6 ; -; I1 ; ; ; -; - inst10~0 ; 1 ; 6 ; -; - inst10~1 ; 1 ; 6 ; -; - inst10~2 ; 1 ; 6 ; -; - inst10~3 ; 1 ; 6 ; -; - inst10~4 ; 1 ; 6 ; -; - inst10~5 ; 1 ; 6 ; -; - inst10~6 ; 1 ; 6 ; -; - inst10~7 ; 1 ; 6 ; -+---------------------+-------------------+---------+ - - -+---------------------------------+ -; Non-Global High Fan-Out Signals ; -+----------+----------------------+ -; Name ; Fan-Out ; -+----------+----------------------+ -; I1 ; 8 ; -; I0 ; 8 ; -; I2 ; 8 ; -; inst10~7 ; 1 ; -; inst10~6 ; 1 ; -; inst10~5 ; 1 ; -; inst10~4 ; 1 ; -; inst10~3 ; 1 ; -; inst10~2 ; 1 ; -; inst10~1 ; 1 ; -; inst10~0 ; 1 ; -+----------+----------------------+ - - -+----------------------------------------------------+ -; Interconnect Usage Summary ; -+----------------------------+-----------------------+ -; Interconnect Resource Type ; Usage ; -+----------------------------+-----------------------+ -; Block interconnects ; 11 / 26,052 ( < 1 % ) ; -; C16 interconnects ; 4 / 1,156 ( < 1 % ) ; -; C4 interconnects ; 9 / 17,952 ( < 1 % ) ; -; Direct links ; 2 / 26,052 ( < 1 % ) ; -; Global clocks ; 0 / 8 ( 0 % ) ; -; Local interconnects ; 0 / 8,256 ( 0 % ) ; -; R24 interconnects ; 3 / 1,020 ( < 1 % ) ; -; R4 interconnects ; 1 / 22,440 ( < 1 % ) ; -+----------------------------+-----------------------+ - - -+--------------------------------------------------------------------------+ -; LAB Logic Elements ; -+--------------------------------------------+-----------------------------+ -; Number of Logic Elements (Average = 8.00) ; Number of LABs (Total = 1) ; -+--------------------------------------------+-----------------------------+ -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 1 ; -; 9 ; 0 ; -; 10 ; 0 ; -; 11 ; 0 ; -; 12 ; 0 ; -; 13 ; 0 ; -; 14 ; 0 ; -; 15 ; 0 ; -; 16 ; 0 ; -+--------------------------------------------+-----------------------------+ - - -+---------------------------------------------------------------------------+ -; LAB Signals Sourced ; -+---------------------------------------------+-----------------------------+ -; Number of Signals Sourced (Average = 8.00) ; Number of LABs (Total = 1) ; -+---------------------------------------------+-----------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 1 ; -+---------------------------------------------+-----------------------------+ - - -+-------------------------------------------------------------------------------+ -; LAB Signals Sourced Out ; -+-------------------------------------------------+-----------------------------+ -; Number of Signals Sourced Out (Average = 8.00) ; Number of LABs (Total = 1) ; -+-------------------------------------------------+-----------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 1 ; -+-------------------------------------------------+-----------------------------+ - - -+---------------------------------------------------------------------------+ -; LAB Distinct Inputs ; -+---------------------------------------------+-----------------------------+ -; Number of Distinct Inputs (Average = 3.00) ; Number of LABs (Total = 1) ; -+---------------------------------------------+-----------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 1 ; -+---------------------------------------------+-----------------------------+ - - -+-------------------------------------------------------------------------+ -; Fitter Device Options ; -+----------------------------------------------+--------------------------+ -; Option ; Setting ; -+----------------------------------------------+--------------------------+ -; Enable user-supplied start-up clock (CLKUSR) ; Off ; -; Enable device-wide reset (DEV_CLRn) ; Off ; -; Enable device-wide output enable (DEV_OE) ; Off ; -; Enable INIT_DONE output ; Off ; -; Configuration scheme ; Active Serial ; -; Error detection CRC ; Off ; -; nCEO ; As output driving ground ; -; ASDO,nCSO ; As input tri-stated ; -; Reserve all unused pins ; As input tri-stated ; -; Base pin-out file on sameframe device ; Off ; -+----------------------------------------------+--------------------------+ - - -+------------------------------------+ -; Operating Settings and Conditions ; -+---------------------------+--------+ -; Setting ; Value ; -+---------------------------+--------+ -; Nominal Core Voltage ; 1.20 V ; -; Low Junction Temperature ; 0 °C ; -; High Junction Temperature ; 85 °C ; -+---------------------------+--------+ - - -+------------------------------------------------------------+ -; Estimated Delay Added for Hold Timing ; -+-----------------+----------------------+-------------------+ -; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; -+-----------------+----------------------+-------------------+ - - -+----------------------------+ -; Advanced Data - General ; -+--------------------+-------+ -; Name ; Value ; -+--------------------+-------+ -; Status Code ; 0 ; -; Desired User Slack ; 0 ; -; Fit Attempts ; 1 ; -+--------------------+-------+ - - -+-------------------------------------------------------------------------------+ -; Advanced Data - Placement Preparation ; -+------------------------------------------------------------------+------------+ -; Name ; Value ; -+------------------------------------------------------------------+------------+ -; Auto Fit Point 1 - Fit Attempt 1 ; ff ; -; Mid Wire Use - Fit Attempt 1 ; 0 ; -; Mid Slack - Fit Attempt 1 ; 2147483639 ; -; Internal Atom Count - Fit Attempt 1 ; 9 ; -; LE/ALM Count - Fit Attempt 1 ; 9 ; -; LAB Count - Fit Attempt 1 ; 2 ; -; Outputs per Lab - Fit Attempt 1 ; 4.000 ; -; Inputs per LAB - Fit Attempt 1 ; 1.500 ; -; Global Inputs per LAB - Fit Attempt 1 ; 0.000 ; -; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:1 ; -; LEs in Chains - Fit Attempt 1 ; 0 ; -; LEs in Long Chains - Fit Attempt 1 ; 0 ; -; LABs with Chains - Fit Attempt 1 ; 0 ; -; LABs with Multiple Chains - Fit Attempt 1 ; 0 ; -; Time - Fit Attempt 1 ; 0 ; -+------------------------------------------------------------------+------------+ - - -+-------------------------------------------------+ -; Advanced Data - Placement ; -+------------------------------------+------------+ -; Name ; Value ; -+------------------------------------+------------+ -; Auto Fit Point 2 - Fit Attempt 1 ; ff ; -; Auto Fit Point 5 - Fit Attempt 1 ; ff ; -; Mid Wire Use - Fit Attempt 1 ; 0 ; -; Mid Slack - Fit Attempt 1 ; 2147483639 ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 5 - Fit Attempt 1 ; ff ; -; Mid Wire Use - Fit Attempt 1 ; 0 ; -; Mid Slack - Fit Attempt 1 ; 2147483639 ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Late Wire Use - Fit Attempt 1 ; 0 ; -; Late Slack - Fit Attempt 1 ; 2147483639 ; -; Peak Regional Wire - Fit Attempt 1 ; 0.000 ; -; Auto Fit Point 7 - Fit Attempt 1 ; ff ; -; Time - Fit Attempt 1 ; 0 ; -+------------------------------------+------------+ - - -+--------------------------------------------------+ -; Advanced Data - Routing ; -+------------------------------------+-------------+ -; Name ; Value ; -+------------------------------------+-------------+ -; Early Slack - Fit Attempt 1 ; 2147483639 ; -; Mid Slack - Fit Attempt 1 ; 2147483639 ; -; Late Slack - Fit Attempt 1 ; -2147483648 ; -; Early Wire Use - Fit Attempt 1 ; 0 ; -; Peak Regional Wire - Fit Attempt 1 ; 0 ; -; Late Wire Use - Fit Attempt 1 ; 0 ; -; Time - Fit Attempt 1 ; 0 ; -+------------------------------------+-------------+ - - -+-----------------+ -; Fitter Messages ; -+-----------------+ -Info: ******************************************************************* -Info: Running Quartus II Fitter - Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Tue Mar 08 15:12:39 2022 -Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder -Info: Parallel compilation is enabled and will use 4 of the 4 processors detected -Info: Selected device EP2C8Q208C8 for design "38_decoder" -Info: Low junction temperature is 0 degrees C -Info: High junction temperature is 85 degrees C -Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time -Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices - Info: Device EP2C5Q208C8 is compatible - Info: Device EP2C5Q208I8 is compatible - Info: Device EP2C8Q208I8 is compatible -Info: Fitter converted 3 user pins into dedicated programming pins - Info: Pin ~ASDO~ is reserved at location 1 - Info: Pin ~nCSO~ is reserved at location 2 - Info: Pin ~LVDS54p/nCEO~ is reserved at location 108 -Info: Fitter is using the Classic Timing Analyzer -Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time. -Info: Starting register packing -Info: Finished register packing - Extra Info: No registers were packed into other blocks -Info: Fitter preparation operations ending: elapsed time is 00:00:00 -Info: Fitter placement preparation operations beginning -Info: Fitter placement preparation operations ending: elapsed time is 00:00:00 -Info: Fitter placement operations beginning -Info: Fitter placement was successful -Info: Fitter placement operations ending: elapsed time is 00:00:00 -Info: Fitter routing operations beginning -Info: Average interconnect usage is 0% of the available device resources - Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y10 to location X34_Y19 -Info: Fitter routing operations ending: elapsed time is 00:00:00 -Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. - Info: Optimizations that may affect the design's routability were skipped - Info: Optimizations that may affect the design's timing were skipped -Info: Started post-fitting delay annotation -Warning: Found 8 output pins without output pin load capacitance assignment - Info: Pin "Y7" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Y0" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Y1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Y2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Y3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Y4" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Y5" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Y6" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis -Info: Delay annotation completed successfully -Info: Generated suppressed messages file D:/projects/quartus/38_decoder/38_decoder.fit.smsg -Info: Quartus II Fitter was successful. 0 errors, 1 warning - Info: Peak virtual memory: 305 megabytes - Info: Processing ended: Tue Mar 08 15:12:40 2022 - Info: Elapsed time: 00:00:01 - Info: Total CPU time (on all processors): 00:00:01 - - -+----------------------------+ -; Fitter Suppressed Messages ; -+----------------------------+ -The suppressed messages can be found in D:/projects/quartus/38_decoder/38_decoder.fit.smsg. - - diff --git a/38_decoder/38_decoder.fit.smsg b/38_decoder/38_decoder.fit.smsg deleted file mode 100644 index 14764e7..0000000 --- a/38_decoder/38_decoder.fit.smsg +++ /dev/null @@ -1,6 +0,0 @@ -Extra Info: Performing register packing on registers with non-logic cell location assignments -Extra Info: Completed register packing on registers with non-logic cell location assignments -Extra Info: Started Fast Input/Output/OE register processing -Extra Info: Finished Fast Input/Output/OE register processing -Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density -Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/38_decoder/38_decoder.fit.summary b/38_decoder/38_decoder.fit.summary deleted file mode 100644 index 7cbb3c9..0000000 --- a/38_decoder/38_decoder.fit.summary +++ /dev/null @@ -1,16 +0,0 @@ -Fitter Status : Successful - Tue Mar 08 15:12:40 2022 -Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition -Revision Name : 38_decoder -Top-level Entity Name : 38_decoder -Family : Cyclone II -Device : EP2C8Q208C8 -Timing Models : Final -Total logic elements : 8 / 8,256 ( < 1 % ) - Total combinational functions : 8 / 8,256 ( < 1 % ) - Dedicated logic registers : 0 / 8,256 ( 0 % ) -Total registers : 0 -Total pins : 11 / 138 ( 8 % ) -Total virtual pins : 0 -Total memory bits : 0 / 165,888 ( 0 % ) -Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % ) -Total PLLs : 0 / 2 ( 0 % ) diff --git a/38_decoder/38_decoder.flow.rpt b/38_decoder/38_decoder.flow.rpt deleted file mode 100644 index b8b1298..0000000 --- a/38_decoder/38_decoder.flow.rpt +++ /dev/null @@ -1,121 +0,0 @@ -Flow report for 38_decoder -Tue Mar 08 15:12:42 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Flow Summary - 3. Flow Settings - 4. Flow Non-Default Global Settings - 5. Flow Elapsed Time - 6. Flow OS Summary - 7. Flow Log - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------------+ -; Flow Summary ; -+------------------------------------+----------------------------------------------+ -; Flow Status ; Successful - Tue Mar 08 15:12:42 2022 ; -; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; -; Revision Name ; 38_decoder ; -; Top-level Entity Name ; 38_decoder ; -; Family ; Cyclone II ; -; Device ; EP2C8Q208C8 ; -; Timing Models ; Final ; -; Met timing requirements ; Yes ; -; Total logic elements ; 8 / 8,256 ( < 1 % ) ; -; Total combinational functions ; 8 / 8,256 ( < 1 % ) ; -; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ; -; Total registers ; 0 ; -; Total pins ; 11 / 138 ( 8 % ) ; -; Total virtual pins ; 0 ; -; Total memory bits ; 0 / 165,888 ( 0 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; -; Total PLLs ; 0 / 2 ( 0 % ) ; -+------------------------------------+----------------------------------------------+ - - -+-----------------------------------------+ -; Flow Settings ; -+-------------------+---------------------+ -; Option ; Setting ; -+-------------------+---------------------+ -; Start date & time ; 03/08/2022 15:12:38 ; -; Main task ; Compilation ; -; Revision Name ; 38_decoder ; -+-------------------+---------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------+ -; Flow Non-Default Global Settings ; -+------------------------------------+-----------------------------------------------+---------------+-------------+----------------+ -; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; -+------------------------------------+-----------------------------------------------+---------------+-------------+----------------+ -; COMPILER_SIGNATURE_ID ; 220283517943889.164672355814724 ; -- ; -- ; -- ; -; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; -; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; -; MISC_FILE ; D:/projects/quartus/38_decoder/38_decoder.dpf ; -- ; -- ; -- ; -; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; -; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; -; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ; -+------------------------------------+-----------------------------------------------+---------------+-------------+----------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Flow Elapsed Time ; -+-------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; -+-------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 246 MB ; 00:00:00 ; -; Fitter ; 00:00:01 ; 1.0 ; 305 MB ; 00:00:01 ; -; Assembler ; 00:00:00 ; 1.0 ; 241 MB ; 00:00:00 ; -; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 198 MB ; 00:00:00 ; -; Total ; 00:00:01 ; -- ; -- ; 00:00:01 ; -+-------------------------+--------------+-------------------------+---------------------+------------------------------------+ - - -+------------------------------------------------------------------------------------------+ -; Flow OS Summary ; -+-------------------------+------------------+---------------+------------+----------------+ -; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; -+-------------------------+------------------+---------------+------------+----------------+ -; Analysis & Synthesis ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; -; Fitter ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; -; Assembler ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; -; Classic Timing Analyzer ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; -+-------------------------+------------------+---------------+------------+----------------+ - - ------------- -; Flow Log ; ------------- -quartus_map --read_settings_files=on --write_settings_files=off 38_decoder -c 38_decoder -quartus_fit --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder -quartus_asm --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder -quartus_tan --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder --timing_analysis_only - - - diff --git a/38_decoder/38_decoder.map.rpt b/38_decoder/38_decoder.map.rpt deleted file mode 100644 index 6f633ef..0000000 --- a/38_decoder/38_decoder.map.rpt +++ /dev/null @@ -1,218 +0,0 @@ -Analysis & Synthesis report for 38_decoder -Tue Mar 08 15:12:38 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Analysis & Synthesis Summary - 3. Analysis & Synthesis Settings - 4. Analysis & Synthesis Source Files Read - 5. Analysis & Synthesis Resource Usage Summary - 6. Analysis & Synthesis Resource Utilization by Entity - 7. General Register Statistics - 8. Analysis & Synthesis Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------------+ -; Analysis & Synthesis Summary ; -+------------------------------------+----------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Tue Mar 08 15:12:38 2022 ; -; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; -; Revision Name ; 38_decoder ; -; Top-level Entity Name ; 38_decoder ; -; Family ; Cyclone II ; -; Total logic elements ; 8 ; -; Total combinational functions ; 8 ; -; Dedicated logic registers ; 0 ; -; Total registers ; 0 ; -; Total pins ; 11 ; -; Total virtual pins ; 0 ; -; Total memory bits ; 0 ; -; Embedded Multiplier 9-bit elements ; 0 ; -; Total PLLs ; 0 ; -+------------------------------------+----------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Settings ; -+--------------------------------------------------------------+--------------------+--------------------+ -; Option ; Setting ; Default Value ; -+--------------------------------------------------------------+--------------------+--------------------+ -; Device ; EP2C8Q208C8 ; ; -; Top-level entity name ; 38_decoder ; 38_decoder ; -; Family name ; Cyclone II ; Stratix II ; -; Use Generated Physical Constraints File ; Off ; ; -; Use smart compilation ; Off ; Off ; -; Restructure Multiplexers ; Auto ; Auto ; -; Create Debugging Nodes for IP Cores ; Off ; Off ; -; Preserve fewer node names ; On ; On ; -; Disable OpenCore Plus hardware evaluation ; Off ; Off ; -; Verilog Version ; Verilog_2001 ; Verilog_2001 ; -; VHDL Version ; VHDL93 ; VHDL93 ; -; State Machine Processing ; Auto ; Auto ; -; Safe State Machine ; Off ; Off ; -; Extract Verilog State Machines ; On ; On ; -; Extract VHDL State Machines ; On ; On ; -; Ignore Verilog initial constructs ; Off ; Off ; -; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; -; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; -; Add Pass-Through Logic to Inferred RAMs ; On ; On ; -; Parallel Synthesis ; Off ; Off ; -; DSP Block Balancing ; Auto ; Auto ; -; NOT Gate Push-Back ; On ; On ; -; Power-Up Don't Care ; On ; On ; -; Remove Redundant Logic Cells ; Off ; Off ; -; Remove Duplicate Registers ; On ; On ; -; Ignore CARRY Buffers ; Off ; Off ; -; Ignore CASCADE Buffers ; Off ; Off ; -; Ignore GLOBAL Buffers ; Off ; Off ; -; Ignore ROW GLOBAL Buffers ; Off ; Off ; -; Ignore LCELL Buffers ; Off ; Off ; -; Ignore SOFT Buffers ; On ; On ; -; Limit AHDL Integers to 32 Bits ; Off ; Off ; -; Optimization Technique ; Balanced ; Balanced ; -; Carry Chain Length ; 70 ; 70 ; -; Auto Carry Chains ; On ; On ; -; Auto Open-Drain Pins ; On ; On ; -; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; -; Auto ROM Replacement ; On ; On ; -; Auto RAM Replacement ; On ; On ; -; Auto Shift Register Replacement ; Auto ; Auto ; -; Auto Clock Enable Replacement ; On ; On ; -; Strict RAM Replacement ; Off ; Off ; -; Allow Synchronous Control Signals ; On ; On ; -; Force Use of Synchronous Clear Signals ; Off ; Off ; -; Auto RAM to Logic Cell Conversion ; Off ; Off ; -; Auto Resource Sharing ; Off ; Off ; -; Allow Any RAM Size For Recognition ; Off ; Off ; -; Allow Any ROM Size For Recognition ; Off ; Off ; -; Allow Any Shift Register Size For Recognition ; Off ; Off ; -; Use LogicLock Constraints during Resource Balancing ; On ; On ; -; Ignore translate_off and synthesis_off directives ; Off ; Off ; -; Timing-Driven Synthesis ; Off ; Off ; -; Show Parameter Settings Tables in Synthesis Report ; On ; On ; -; Ignore Maximum Fan-Out Assignments ; Off ; Off ; -; Synchronization Register Chain Length ; 2 ; 2 ; -; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; -; HDL message level ; Level2 ; Level2 ; -; Suppress Register Optimization Related Messages ; Off ; Off ; -; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ; -; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; -; Clock MUX Protection ; On ; On ; -; Auto Gated Clock Conversion ; Off ; Off ; -; Block Design Naming ; Auto ; Auto ; -; SDC constraint protection ; Off ; Off ; -; Synthesis Effort ; Auto ; Auto ; -; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; -; Analysis & Synthesis Message Level ; Medium ; Medium ; -+--------------------------------------------------------------+--------------------+--------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+----------------------------------+-----------------+------------------------------------+-----------------------------------------------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; -+----------------------------------+-----------------+------------------------------------+-----------------------------------------------+ -; 38_decoder.bdf ; yes ; User Block Diagram/Schematic File ; D:/projects/quartus/38_decoder/38_decoder.bdf ; -+----------------------------------+-----------------+------------------------------------+-----------------------------------------------+ - - -+-----------------------------------------------------+ -; Analysis & Synthesis Resource Usage Summary ; -+---------------------------------------------+-------+ -; Resource ; Usage ; -+---------------------------------------------+-------+ -; Estimated Total logic elements ; 8 ; -; ; ; -; Total combinational functions ; 8 ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 0 ; -; -- 3 input functions ; 8 ; -; -- <=2 input functions ; 0 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 8 ; -; -- arithmetic mode ; 0 ; -; ; ; -; Total registers ; 0 ; -; -- Dedicated logic registers ; 0 ; -; -- I/O registers ; 0 ; -; ; ; -; I/O pins ; 11 ; -; Maximum fan-out node ; I2 ; -; Maximum fan-out ; 8 ; -; Total fan-out ; 32 ; -; Average fan-out ; 1.68 ; -+---------------------------------------------+-------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Resource Utilization by Entity ; -+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ -; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; -+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ -; |38_decoder ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 11 ; 0 ; |38_decoder ; work ; -+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ -Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. - - -+------------------------------------------------------+ -; General Register Statistics ; -+----------------------------------------------+-------+ -; Statistic ; Value ; -+----------------------------------------------+-------+ -; Total registers ; 0 ; -; Number of registers using Synchronous Clear ; 0 ; -; Number of registers using Synchronous Load ; 0 ; -; Number of registers using Asynchronous Clear ; 0 ; -; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 0 ; -; Number of registers using Preset ; 0 ; -+----------------------------------------------+-------+ - - -+-------------------------------+ -; Analysis & Synthesis Messages ; -+-------------------------------+ -Info: ******************************************************************* -Info: Running Quartus II Analysis & Synthesis - Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Tue Mar 08 15:12:38 2022 -Info: Command: quartus_map --read_settings_files=on --write_settings_files=off 38_decoder -c 38_decoder -Info: Found 1 design units, including 1 entities, in source file 38_decoder.bdf - Info: Found entity 1: 38_decoder -Info: Elaborating entity "38_decoder" for the top level hierarchy -Info: Implemented 19 device resources after synthesis - the final resource count might be different - Info: Implemented 3 input pins - Info: Implemented 8 output pins - Info: Implemented 8 logic cells -Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 250 megabytes - Info: Processing ended: Tue Mar 08 15:12:38 2022 - Info: Elapsed time: 00:00:00 - Info: Total CPU time (on all processors): 00:00:00 - - diff --git a/38_decoder/38_decoder.map.summary b/38_decoder/38_decoder.map.summary deleted file mode 100644 index e76f577..0000000 --- a/38_decoder/38_decoder.map.summary +++ /dev/null @@ -1,14 +0,0 @@ -Analysis & Synthesis Status : Successful - Tue Mar 08 15:12:38 2022 -Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition -Revision Name : 38_decoder -Top-level Entity Name : 38_decoder -Family : Cyclone II -Total logic elements : 8 - Total combinational functions : 8 - Dedicated logic registers : 0 -Total registers : 0 -Total pins : 11 -Total virtual pins : 0 -Total memory bits : 0 -Embedded Multiplier 9-bit elements : 0 -Total PLLs : 0 diff --git a/38_decoder/38_decoder.pin b/38_decoder/38_decoder.pin deleted file mode 100644 index 0a6f10c..0000000 --- a/38_decoder/38_decoder.pin +++ /dev/null @@ -1,278 +0,0 @@ - -- Copyright (C) 1991-2009 Altera Corporation - -- Your use of Altera Corporation's design tools, logic functions - -- and other software and tools, and its AMPP partner logic - -- functions, and any output files from any of the foregoing - -- (including device programming or simulation files), and any - -- associated documentation or information are expressly subject - -- to the terms and conditions of the Altera Program License - -- Subscription Agreement, Altera MegaCore Function License - -- Agreement, or other applicable license agreement, including, - -- without limitation, that your use is for the sole purpose of - -- programming logic devices manufactured by Altera and sold by - -- Altera or its authorized distributors. Please refer to the - -- applicable agreement for further details. - -- - -- This is a Quartus II output file. It is for reporting purposes only, and is - -- not intended for use as a Quartus II input file. This file cannot be used - -- to make Quartus II pin assignments - for instructions on how to make pin - -- assignments, please see Quartus II help. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- NC : No Connect. This pin has no internal connection to the device. - -- DNU : Do Not Use. This pin MUST NOT be connected. - -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). - -- VCCIO : Dedicated power pin, which MUST be connected to VCC - -- of its bank. - -- Bank 1: 3.3V - -- Bank 2: 3.3V - -- Bank 3: 3.3V - -- Bank 4: 3.3V - -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. - -- It can also be used to report unused dedicated pins. The connection - -- on the board for unused dedicated pins depends on whether this will - -- be used in a future design. One example is device migration. When - -- using device migration, refer to the device pin-tables. If it is a - -- GND pin in the pin table or if it will not be used in a future design - -- for another purpose the it MUST be connected to GND. If it is an unused - -- dedicated pin, then it can be connected to a valid signal on the board - -- (low, high, or toggling) if that signal is required for a different - -- revision of the design. - -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. - -- This pin should be connected to GND. It may also be connected to a - -- valid signal on the board (low, high, or toggling) if that signal - -- is required for a different revision of the design. - -- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17), - -- connect each pin marked GND* either individually through a 10k Ohm resistor - -- to GND or tie all pins together and connect through a single 10k Ohm resistor - -- to GND. - -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND - -- or leave it unconnected. - -- RESERVED : Unused I/O pin, which MUST be left unconnected. - -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. - -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. - -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. - -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- Pin directions (input, output or bidir) are based on device operating in user mode. - --------------------------------------------------------------------------------- - -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition -CHIP "38_decoder" ASSIGNED TO AN: EP2C8Q208C8 - -Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment -------------------------------------------------------------------------------------------------------------- -~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVTTL : : 1 : N -~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVTTL : : 1 : N -RESERVED_INPUT : 3 : : : : 1 : -RESERVED_INPUT : 4 : : : : 1 : -RESERVED_INPUT : 5 : : : : 1 : -RESERVED_INPUT : 6 : : : : 1 : -VCCIO1 : 7 : power : : 3.3V : 1 : -RESERVED_INPUT : 8 : : : : 1 : -GND : 9 : gnd : : : : -RESERVED_INPUT : 10 : : : : 1 : -RESERVED_INPUT : 11 : : : : 1 : -RESERVED_INPUT : 12 : : : : 1 : -RESERVED_INPUT : 13 : : : : 1 : -RESERVED_INPUT : 14 : : : : 1 : -RESERVED_INPUT : 15 : : : : 1 : -TDO : 16 : output : : : 1 : -TMS : 17 : input : : : 1 : -TCK : 18 : input : : : 1 : -TDI : 19 : input : : : 1 : -DATA0 : 20 : input : : : 1 : -DCLK : 21 : : : : 1 : -nCE : 22 : : : : 1 : -GND+ : 23 : : : : 1 : -GND+ : 24 : : : : 1 : -GND : 25 : gnd : : : : -nCONFIG : 26 : : : : 1 : -GND+ : 27 : : : : 1 : -GND+ : 28 : : : : 1 : -VCCIO1 : 29 : power : : 3.3V : 1 : -RESERVED_INPUT : 30 : : : : 1 : -RESERVED_INPUT : 31 : : : : 1 : -VCCINT : 32 : power : : 1.2V : : -RESERVED_INPUT : 33 : : : : 1 : -RESERVED_INPUT : 34 : : : : 1 : -RESERVED_INPUT : 35 : : : : 1 : -GND : 36 : gnd : : : : -RESERVED_INPUT : 37 : : : : 1 : -GND : 38 : gnd : : : : -RESERVED_INPUT : 39 : : : : 1 : -RESERVED_INPUT : 40 : : : : 1 : -RESERVED_INPUT : 41 : : : : 1 : -VCCIO1 : 42 : power : : 3.3V : 1 : -RESERVED_INPUT : 43 : : : : 1 : -RESERVED_INPUT : 44 : : : : 1 : -RESERVED_INPUT : 45 : : : : 1 : -RESERVED_INPUT : 46 : : : : 1 : -RESERVED_INPUT : 47 : : : : 1 : -RESERVED_INPUT : 48 : : : : 1 : -GND : 49 : gnd : : : : -GND_PLL1 : 50 : gnd : : : : -VCCD_PLL1 : 51 : power : : 1.2V : : -GND_PLL1 : 52 : gnd : : : : -VCCA_PLL1 : 53 : power : : 1.2V : : -GNDA_PLL1 : 54 : gnd : : : : -GND : 55 : gnd : : : : -RESERVED_INPUT : 56 : : : : 4 : -RESERVED_INPUT : 57 : : : : 4 : -RESERVED_INPUT : 58 : : : : 4 : -RESERVED_INPUT : 59 : : : : 4 : -RESERVED_INPUT : 60 : : : : 4 : -RESERVED_INPUT : 61 : : : : 4 : -VCCIO4 : 62 : power : : 3.3V : 4 : -RESERVED_INPUT : 63 : : : : 4 : -RESERVED_INPUT : 64 : : : : 4 : -GND : 65 : gnd : : : : -VCCINT : 66 : power : : 1.2V : : -RESERVED_INPUT : 67 : : : : 4 : -RESERVED_INPUT : 68 : : : : 4 : -RESERVED_INPUT : 69 : : : : 4 : -RESERVED_INPUT : 70 : : : : 4 : -VCCIO4 : 71 : power : : 3.3V : 4 : -RESERVED_INPUT : 72 : : : : 4 : -GND : 73 : gnd : : : : -RESERVED_INPUT : 74 : : : : 4 : -RESERVED_INPUT : 75 : : : : 4 : -RESERVED_INPUT : 76 : : : : 4 : -I0 : 77 : input : 3.3-V LVTTL : : 4 : Y -GND : 78 : gnd : : : : -VCCINT : 79 : power : : 1.2V : : -I1 : 80 : input : 3.3-V LVTTL : : 4 : Y -I2 : 81 : input : 3.3-V LVTTL : : 4 : Y -RESERVED_INPUT : 82 : : : : 4 : -VCCIO4 : 83 : power : : 3.3V : 4 : -RESERVED_INPUT : 84 : : : : 4 : -GND : 85 : gnd : : : : -RESERVED_INPUT : 86 : : : : 4 : -RESERVED_INPUT : 87 : : : : 4 : -RESERVED_INPUT : 88 : : : : 4 : -RESERVED_INPUT : 89 : : : : 4 : -RESERVED_INPUT : 90 : : : : 4 : -VCCIO4 : 91 : power : : 3.3V : 4 : -RESERVED_INPUT : 92 : : : : 4 : -GND : 93 : gnd : : : : -RESERVED_INPUT : 94 : : : : 4 : -RESERVED_INPUT : 95 : : : : 4 : -RESERVED_INPUT : 96 : : : : 4 : -RESERVED_INPUT : 97 : : : : 4 : -VCCIO4 : 98 : power : : 3.3V : 4 : -RESERVED_INPUT : 99 : : : : 4 : -GND : 100 : gnd : : : : -RESERVED_INPUT : 101 : : : : 4 : -RESERVED_INPUT : 102 : : : : 4 : -RESERVED_INPUT : 103 : : : : 4 : -RESERVED_INPUT : 104 : : : : 4 : -RESERVED_INPUT : 105 : : : : 3 : -RESERVED_INPUT : 106 : : : : 3 : -RESERVED_INPUT : 107 : : : : 3 : -~LVDS54p/nCEO~ : 108 : output : 3.3-V LVTTL : : 3 : N -VCCIO3 : 109 : power : : 3.3V : 3 : -RESERVED_INPUT : 110 : : : : 3 : -GND : 111 : gnd : : : : -RESERVED_INPUT : 112 : : : : 3 : -RESERVED_INPUT : 113 : : : : 3 : -RESERVED_INPUT : 114 : : : : 3 : -RESERVED_INPUT : 115 : : : : 3 : -RESERVED_INPUT : 116 : : : : 3 : -RESERVED_INPUT : 117 : : : : 3 : -RESERVED_INPUT : 118 : : : : 3 : -GND : 119 : gnd : : : : -VCCINT : 120 : power : : 1.2V : : -nSTATUS : 121 : : : : 3 : -VCCIO3 : 122 : power : : 3.3V : 3 : -CONF_DONE : 123 : : : : 3 : -GND : 124 : gnd : : : : -MSEL1 : 125 : : : : 3 : -MSEL0 : 126 : : : : 3 : -RESERVED_INPUT : 127 : : : : 3 : -RESERVED_INPUT : 128 : : : : 3 : -GND+ : 129 : : : : 3 : -GND+ : 130 : : : : 3 : -GND+ : 131 : : : : 3 : -GND+ : 132 : : : : 3 : -RESERVED_INPUT : 133 : : : : 3 : -RESERVED_INPUT : 134 : : : : 3 : -RESERVED_INPUT : 135 : : : : 3 : -VCCIO3 : 136 : power : : 3.3V : 3 : -RESERVED_INPUT : 137 : : : : 3 : -RESERVED_INPUT : 138 : : : : 3 : -RESERVED_INPUT : 139 : : : : 3 : -GND : 140 : gnd : : : : -RESERVED_INPUT : 141 : : : : 3 : -Y0 : 142 : output : 3.3-V LVTTL : : 3 : Y -Y1 : 143 : output : 3.3-V LVTTL : : 3 : Y -Y2 : 144 : output : 3.3-V LVTTL : : 3 : Y -Y3 : 145 : output : 3.3-V LVTTL : : 3 : Y -Y4 : 146 : output : 3.3-V LVTTL : : 3 : Y -Y5 : 147 : output : 3.3-V LVTTL : : 3 : Y -VCCIO3 : 148 : power : : 3.3V : 3 : -Y6 : 149 : output : 3.3-V LVTTL : : 3 : Y -Y7 : 150 : output : 3.3-V LVTTL : : 3 : Y -RESERVED_INPUT : 151 : : : : 3 : -RESERVED_INPUT : 152 : : : : 3 : -GND : 153 : gnd : : : : -GND_PLL2 : 154 : gnd : : : : -VCCD_PLL2 : 155 : power : : 1.2V : : -GND_PLL2 : 156 : gnd : : : : -VCCA_PLL2 : 157 : power : : 1.2V : : -GNDA_PLL2 : 158 : gnd : : : : -GND : 159 : gnd : : : : -RESERVED_INPUT : 160 : : : : 2 : -RESERVED_INPUT : 161 : : : : 2 : -RESERVED_INPUT : 162 : : : : 2 : -RESERVED_INPUT : 163 : : : : 2 : -RESERVED_INPUT : 164 : : : : 2 : -RESERVED_INPUT : 165 : : : : 2 : -VCCIO2 : 166 : power : : 3.3V : 2 : -GND : 167 : gnd : : : : -RESERVED_INPUT : 168 : : : : 2 : -RESERVED_INPUT : 169 : : : : 2 : -RESERVED_INPUT : 170 : : : : 2 : -RESERVED_INPUT : 171 : : : : 2 : -VCCIO2 : 172 : power : : 3.3V : 2 : -RESERVED_INPUT : 173 : : : : 2 : -GND : 174 : gnd : : : : -RESERVED_INPUT : 175 : : : : 2 : -RESERVED_INPUT : 176 : : : : 2 : -GND : 177 : gnd : : : : -VCCINT : 178 : power : : 1.2V : : -RESERVED_INPUT : 179 : : : : 2 : -RESERVED_INPUT : 180 : : : : 2 : -RESERVED_INPUT : 181 : : : : 2 : -RESERVED_INPUT : 182 : : : : 2 : -VCCIO2 : 183 : power : : 3.3V : 2 : -GND : 184 : gnd : : : : -RESERVED_INPUT : 185 : : : : 2 : -GND : 186 : gnd : : : : -RESERVED_INPUT : 187 : : : : 2 : -RESERVED_INPUT : 188 : : : : 2 : -RESERVED_INPUT : 189 : : : : 2 : -VCCINT : 190 : power : : 1.2V : : -RESERVED_INPUT : 191 : : : : 2 : -RESERVED_INPUT : 192 : : : : 2 : -RESERVED_INPUT : 193 : : : : 2 : -VCCIO2 : 194 : power : : 3.3V : 2 : -RESERVED_INPUT : 195 : : : : 2 : -GND : 196 : gnd : : : : -RESERVED_INPUT : 197 : : : : 2 : -RESERVED_INPUT : 198 : : : : 2 : -RESERVED_INPUT : 199 : : : : 2 : -RESERVED_INPUT : 200 : : : : 2 : -RESERVED_INPUT : 201 : : : : 2 : -VCCIO2 : 202 : power : : 3.3V : 2 : -RESERVED_INPUT : 203 : : : : 2 : -GND : 204 : gnd : : : : -RESERVED_INPUT : 205 : : : : 2 : -RESERVED_INPUT : 206 : : : : 2 : -RESERVED_INPUT : 207 : : : : 2 : -RESERVED_INPUT : 208 : : : : 2 : diff --git a/38_decoder/38_decoder.pof b/38_decoder/38_decoder.pof deleted file mode 100644 index 5959345..0000000 Binary files a/38_decoder/38_decoder.pof and /dev/null differ diff --git a/38_decoder/38_decoder.qws b/38_decoder/38_decoder.qws deleted file mode 100644 index 4e30f11..0000000 --- a/38_decoder/38_decoder.qws +++ /dev/null @@ -1,14 +0,0 @@ -[ProjectWorkspace] -ptn_Child1=Frames -[ProjectWorkspace.Frames] -ptn_Child1=ChildFrames -[ProjectWorkspace.Frames.ChildFrames] -ptn_Child1=Document-0 -[ProjectWorkspace.Frames.ChildFrames.Document-0] -ptn_Child1=ViewFrame-0 -[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0] -DocPathName=38_decoder.bdf -DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde} -IsChildFrameDetached=False -IsActiveChildFrame=True -ptn_Child1=StateMap diff --git a/38_decoder/38_decoder.sof b/38_decoder/38_decoder.sof deleted file mode 100644 index d8f3d1a..0000000 Binary files a/38_decoder/38_decoder.sof and /dev/null differ diff --git a/38_decoder/38_decoder.tan.rpt b/38_decoder/38_decoder.tan.rpt deleted file mode 100644 index 08fe936..0000000 --- a/38_decoder/38_decoder.tan.rpt +++ /dev/null @@ -1,149 +0,0 @@ -Classic Timing Analyzer report for 38_decoder -Tue Mar 08 15:12:42 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Timing Analyzer Summary - 3. Timing Analyzer Settings - 4. Parallel Compilation - 5. tpd - 6. Timing Analyzer Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------------------------------------------------+ -; Timing Analyzer Summary ; -+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ -; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; -+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ -; Worst-case tpd ; N/A ; None ; 13.172 ns ; I2 ; Y4 ; -- ; -- ; 0 ; -; Total number of failed paths ; ; ; ; ; ; ; ; 0 ; -+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ - - -+--------------------------------------------------------------------------------------------------------------------+ -; Timing Analyzer Settings ; -+---------------------------------------------------------------------+--------------------+------+----+-------------+ -; Option ; Setting ; From ; To ; Entity Name ; -+---------------------------------------------------------------------+--------------------+------+----+-------------+ -; Device Name ; EP2C8Q208C8 ; ; ; ; -; Timing Models ; Final ; ; ; ; -; Default hold multicycle ; Same as Multicycle ; ; ; ; -; Cut paths between unrelated clock domains ; On ; ; ; ; -; Cut off read during write signal paths ; On ; ; ; ; -; Cut off feedback from I/O pins ; On ; ; ; ; -; Report Combined Fast/Slow Timing ; Off ; ; ; ; -; Ignore Clock Settings ; Off ; ; ; ; -; Analyze latches as synchronous elements ; On ; ; ; ; -; Enable Recovery/Removal analysis ; Off ; ; ; ; -; Enable Clock Latency ; Off ; ; ; ; -; Use TimeQuest Timing Analyzer ; Off ; ; ; ; -; Minimum Core Junction Temperature ; 0 ; ; ; ; -; Maximum Core Junction Temperature ; 85 ; ; ; ; -; Number of source nodes to report per destination node ; 10 ; ; ; ; -; Number of destination nodes to report ; 10 ; ; ; ; -; Number of paths to report ; 200 ; ; ; ; -; Report Minimum Timing Checks ; Off ; ; ; ; -; Use Fast Timing Models ; Off ; ; ; ; -; Report IO Paths Separately ; Off ; ; ; ; -; Perform Multicorner Analysis ; On ; ; ; ; -; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ; -; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ; -; Output I/O Timing Endpoint ; Near End ; ; ; ; -+---------------------------------------------------------------------+--------------------+------+----+-------------+ - - -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 4 ; -; Maximum allowed ; 4 ; -; ; ; -; Average used ; 1.00 ; -; Maximum used ; 1 ; -; ; ; -; Usage by Processor ; % Time Used ; -; 1 processor ; 100.0% ; -; 2-4 processors ; 0.0% ; -+----------------------------+-------------+ - - -+---------------------------------------------------------+ -; tpd ; -+-------+-------------------+-----------------+------+----+ -; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ; -+-------+-------------------+-----------------+------+----+ -; N/A ; None ; 13.172 ns ; I2 ; Y4 ; -; N/A ; None ; 13.161 ns ; I2 ; Y6 ; -; N/A ; None ; 13.141 ns ; I2 ; Y5 ; -; N/A ; None ; 13.095 ns ; I2 ; Y7 ; -; N/A ; None ; 13.009 ns ; I2 ; Y3 ; -; N/A ; None ; 12.995 ns ; I2 ; Y0 ; -; N/A ; None ; 12.674 ns ; I1 ; Y6 ; -; N/A ; None ; 12.658 ns ; I0 ; Y5 ; -; N/A ; None ; 12.658 ns ; I1 ; Y4 ; -; N/A ; None ; 12.648 ns ; I1 ; Y3 ; -; N/A ; None ; 12.647 ns ; I2 ; Y1 ; -; N/A ; None ; 12.636 ns ; I0 ; Y3 ; -; N/A ; None ; 12.623 ns ; I1 ; Y7 ; -; N/A ; None ; 12.619 ns ; I0 ; Y7 ; -; N/A ; None ; 12.614 ns ; I0 ; Y4 ; -; N/A ; None ; 12.612 ns ; I1 ; Y5 ; -; N/A ; None ; 12.594 ns ; I0 ; Y6 ; -; N/A ; None ; 12.580 ns ; I1 ; Y0 ; -; N/A ; None ; 12.560 ns ; I2 ; Y2 ; -; N/A ; None ; 12.535 ns ; I0 ; Y0 ; -; N/A ; None ; 12.270 ns ; I0 ; Y1 ; -; N/A ; None ; 12.241 ns ; I1 ; Y1 ; -; N/A ; None ; 12.201 ns ; I1 ; Y2 ; -; N/A ; None ; 12.104 ns ; I0 ; Y2 ; -+-------+-------------------+-----------------+------+----+ - - -+--------------------------+ -; Timing Analyzer Messages ; -+--------------------------+ -Info: ******************************************************************* -Info: Running Quartus II Classic Timing Analyzer - Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Tue Mar 08 15:12:42 2022 -Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder --timing_analysis_only -Info: Parallel compilation is enabled and will use 4 of the 4 processors detected -Info: Longest tpd from source pin "I2" to destination pin "Y4" is 13.172 ns - Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_81; Fanout = 8; PIN Node = 'I2' - Info: 2: + IC(7.387 ns) + CELL(0.651 ns) = 9.012 ns; Loc. = LCCOMB_X33_Y13_N2; Fanout = 1; COMB Node = 'inst10~5' - Info: 3: + IC(1.054 ns) + CELL(3.106 ns) = 13.172 ns; Loc. = PIN_146; Fanout = 0; PIN Node = 'Y4' - Info: Total cell delay = 4.731 ns ( 35.92 % ) - Info: Total interconnect delay = 8.441 ns ( 64.08 % ) -Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 212 megabytes - Info: Processing ended: Tue Mar 08 15:12:42 2022 - Info: Elapsed time: 00:00:00 - Info: Total CPU time (on all processors): 00:00:00 - - diff --git a/38_decoder/38_decoder.tan.summary b/38_decoder/38_decoder.tan.summary deleted file mode 100644 index beb25fd..0000000 --- a/38_decoder/38_decoder.tan.summary +++ /dev/null @@ -1,26 +0,0 @@ --------------------------------------------------------------------------------------- -Timing Analyzer Summary --------------------------------------------------------------------------------------- - -Type : Worst-case tpd -Slack : N/A -Required Time : None -Actual Time : 13.172 ns -From : I2 -To : Y4 -From Clock : -- -To Clock : -- -Failed Paths : 0 - -Type : Total number of failed paths -Slack : -Required Time : -Actual Time : -From : -To : -From Clock : -To Clock : -Failed Paths : 0 - --------------------------------------------------------------------------------------- - diff --git a/38_decoder/db/38_decoder.(0).cnf.cdb b/38_decoder/db/38_decoder.(0).cnf.cdb deleted file mode 100644 index a153ce4..0000000 Binary files a/38_decoder/db/38_decoder.(0).cnf.cdb and /dev/null differ diff --git a/38_decoder/db/38_decoder.(0).cnf.hdb b/38_decoder/db/38_decoder.(0).cnf.hdb deleted file mode 100644 index 1277c6c..0000000 Binary files a/38_decoder/db/38_decoder.(0).cnf.hdb and /dev/null differ diff --git a/38_decoder/db/38_decoder.asm.qmsg b/38_decoder/db/38_decoder.asm.qmsg deleted file mode 100644 index 1c22f03..0000000 --- a/38_decoder/db/38_decoder.asm.qmsg +++ /dev/null @@ -1,7 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:12:41 2022 " "Info: Processing started: Tue Mar 08 15:12:41 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1} -{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:12:41 2022 " "Info: Processing ended: Tue Mar 08 15:12:41 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/38_decoder/db/38_decoder.asm_labs.ddb b/38_decoder/db/38_decoder.asm_labs.ddb deleted file mode 100644 index 5227a15..0000000 Binary files a/38_decoder/db/38_decoder.asm_labs.ddb and /dev/null differ diff --git a/38_decoder/db/38_decoder.cbx.xml b/38_decoder/db/38_decoder.cbx.xml deleted file mode 100644 index 1cdca43..0000000 --- a/38_decoder/db/38_decoder.cbx.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/38_decoder/db/38_decoder.cmp.bpm b/38_decoder/db/38_decoder.cmp.bpm deleted file mode 100644 index a588ab5..0000000 Binary files a/38_decoder/db/38_decoder.cmp.bpm and /dev/null differ diff --git a/38_decoder/db/38_decoder.cmp.cdb b/38_decoder/db/38_decoder.cmp.cdb deleted file mode 100644 index 3dc02b1..0000000 Binary files a/38_decoder/db/38_decoder.cmp.cdb and /dev/null differ diff --git a/38_decoder/db/38_decoder.cmp.ecobp b/38_decoder/db/38_decoder.cmp.ecobp deleted file mode 100644 index e05efff..0000000 Binary files a/38_decoder/db/38_decoder.cmp.ecobp and /dev/null differ diff --git a/38_decoder/db/38_decoder.cmp.hdb b/38_decoder/db/38_decoder.cmp.hdb deleted file mode 100644 index eeda646..0000000 Binary files a/38_decoder/db/38_decoder.cmp.hdb and /dev/null differ diff --git a/38_decoder/db/38_decoder.cmp.kpt b/38_decoder/db/38_decoder.cmp.kpt deleted file mode 100644 index b3d0454..0000000 --- a/38_decoder/db/38_decoder.cmp.kpt +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/38_decoder/db/38_decoder.cmp.logdb b/38_decoder/db/38_decoder.cmp.logdb deleted file mode 100644 index 626799f..0000000 --- a/38_decoder/db/38_decoder.cmp.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/38_decoder/db/38_decoder.cmp.rdb b/38_decoder/db/38_decoder.cmp.rdb deleted file mode 100644 index a939741..0000000 Binary files a/38_decoder/db/38_decoder.cmp.rdb and /dev/null differ diff --git a/38_decoder/db/38_decoder.cmp.tdb b/38_decoder/db/38_decoder.cmp.tdb deleted file mode 100644 index b4c7911..0000000 Binary files a/38_decoder/db/38_decoder.cmp.tdb and /dev/null differ diff --git a/38_decoder/db/38_decoder.cmp0.ddb b/38_decoder/db/38_decoder.cmp0.ddb deleted file mode 100644 index 2fb1195..0000000 Binary files a/38_decoder/db/38_decoder.cmp0.ddb and /dev/null differ diff --git a/38_decoder/db/38_decoder.cmp2.ddb b/38_decoder/db/38_decoder.cmp2.ddb deleted file mode 100644 index 982346f..0000000 Binary files a/38_decoder/db/38_decoder.cmp2.ddb and /dev/null differ diff --git a/38_decoder/db/38_decoder.cmp_merge.kpt b/38_decoder/db/38_decoder.cmp_merge.kpt deleted file mode 100644 index 403a29b..0000000 --- a/38_decoder/db/38_decoder.cmp_merge.kpt +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/38_decoder/db/38_decoder.db_info b/38_decoder/db/38_decoder.db_info deleted file mode 100644 index 8c38eaa..0000000 --- a/38_decoder/db/38_decoder.db_info +++ /dev/null @@ -1,3 +0,0 @@ -Quartus_Version = Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition -Version_Index = 167832322 -Creation_Time = Mon Mar 07 09:11:53 2022 diff --git a/38_decoder/db/38_decoder.eco.cdb b/38_decoder/db/38_decoder.eco.cdb deleted file mode 100644 index 6612017..0000000 Binary files a/38_decoder/db/38_decoder.eco.cdb and /dev/null differ diff --git a/38_decoder/db/38_decoder.fit.qmsg b/38_decoder/db/38_decoder.fit.qmsg deleted file mode 100644 index b7a5094..0000000 --- a/38_decoder/db/38_decoder.fit.qmsg +++ /dev/null @@ -1,35 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:12:39 2022 " "Info: Processing started: Tue Mar 08 15:12:39 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "IMPP_MPP_USER_DEVICE" "38_decoder EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"38_decoder\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1} -{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1} -{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y10 X34_Y19 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y10 to location X34_Y19" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} -{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y7 0 " "Info: Pin \"Y7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y0 0 " "Info: Pin \"Y0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y1 0 " "Info: Pin \"Y1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y2 0 " "Info: Pin \"Y2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y3 0 " "Info: Pin \"Y3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y4 0 " "Info: Pin \"Y4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y5 0 " "Info: Pin \"Y5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y6 0 " "Info: Pin \"Y6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/38_decoder/38_decoder.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/38_decoder/38_decoder.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "305 " "Info: Peak virtual memory: 305 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:12:40 2022 " "Info: Processing ended: Tue Mar 08 15:12:40 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/38_decoder/db/38_decoder.hier_info b/38_decoder/db/38_decoder.hier_info deleted file mode 100644 index 00ca1e3..0000000 --- a/38_decoder/db/38_decoder.hier_info +++ /dev/null @@ -1,26 +0,0 @@ -|38_decoder -Y7 <= inst3.DB_MAX_OUTPUT_PORT_TYPE -I2 => inst3.IN0 -I2 => inst.IN0 -I2 => inst6.IN0 -I2 => inst5.IN0 -I2 => inst4.IN0 -I1 => inst3.IN1 -I1 => inst1.IN0 -I1 => inst8.IN1 -I1 => inst7.IN1 -I1 => inst4.IN1 -I0 => inst3.IN2 -I0 => inst2.IN0 -I0 => inst9.IN2 -I0 => inst7.IN2 -I0 => inst5.IN2 -Y0 <= inst10.DB_MAX_OUTPUT_PORT_TYPE -Y1 <= inst9.DB_MAX_OUTPUT_PORT_TYPE -Y2 <= inst8.DB_MAX_OUTPUT_PORT_TYPE -Y3 <= inst7.DB_MAX_OUTPUT_PORT_TYPE -Y4 <= inst6.DB_MAX_OUTPUT_PORT_TYPE -Y5 <= inst5.DB_MAX_OUTPUT_PORT_TYPE -Y6 <= inst4.DB_MAX_OUTPUT_PORT_TYPE - - diff --git a/38_decoder/db/38_decoder.hif b/38_decoder/db/38_decoder.hif deleted file mode 100644 index 2a7a787..0000000 --- a/38_decoder/db/38_decoder.hif +++ /dev/null @@ -1,42 +0,0 @@ -Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition -11 -936 -OFF -OFF -OFF -ON -ON -ON -FV_OFF -Level2 -0 -0 -VRSM_ON -VHSM_ON -0 --- Start Library Paths -- --- End Library Paths -- --- Start VHDL Libraries -- --- End VHDL Libraries -- -# entity -38_decoder -# storage -db|38_decoder.(0).cnf -db|38_decoder.(0).cnf -# case_insensitive -# source_file -38_decoder.bdf -ce95eaa7a0801a2b705ca5ea74e4b7a -26 -# internal_option { -BLOCK_DESIGN_NAMING -AUTO -} -# hierarchies { -| -} -# macro_sequence - -# end -# complete - \ No newline at end of file diff --git a/38_decoder/db/38_decoder.lpc.html b/38_decoder/db/38_decoder.lpc.html deleted file mode 100644 index fd4875d..0000000 --- a/38_decoder/db/38_decoder.lpc.html +++ /dev/null @@ -1,18 +0,0 @@ - - - - - - - - - - - - - - - - - -
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
diff --git a/38_decoder/db/38_decoder.lpc.rdb b/38_decoder/db/38_decoder.lpc.rdb deleted file mode 100644 index 8bd163a..0000000 Binary files a/38_decoder/db/38_decoder.lpc.rdb and /dev/null differ diff --git a/38_decoder/db/38_decoder.lpc.txt b/38_decoder/db/38_decoder.lpc.txt deleted file mode 100644 index a463804..0000000 --- a/38_decoder/db/38_decoder.lpc.txt +++ /dev/null @@ -1,5 +0,0 @@ -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Legal Partition Candidates ; -+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ -; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; -+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/38_decoder/db/38_decoder.map.bpm b/38_decoder/db/38_decoder.map.bpm deleted file mode 100644 index a561200..0000000 Binary files a/38_decoder/db/38_decoder.map.bpm and /dev/null differ diff --git a/38_decoder/db/38_decoder.map.cdb b/38_decoder/db/38_decoder.map.cdb deleted file mode 100644 index 39e2f5e..0000000 Binary files a/38_decoder/db/38_decoder.map.cdb and /dev/null differ diff --git a/38_decoder/db/38_decoder.map.ecobp b/38_decoder/db/38_decoder.map.ecobp deleted file mode 100644 index e05efff..0000000 Binary files a/38_decoder/db/38_decoder.map.ecobp and /dev/null differ diff --git a/38_decoder/db/38_decoder.map.hdb b/38_decoder/db/38_decoder.map.hdb deleted file mode 100644 index ae5facc..0000000 Binary files a/38_decoder/db/38_decoder.map.hdb and /dev/null differ diff --git a/38_decoder/db/38_decoder.map.kpt b/38_decoder/db/38_decoder.map.kpt deleted file mode 100644 index 6ff2b4b..0000000 --- a/38_decoder/db/38_decoder.map.kpt +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/38_decoder/db/38_decoder.map.logdb b/38_decoder/db/38_decoder.map.logdb deleted file mode 100644 index 626799f..0000000 --- a/38_decoder/db/38_decoder.map.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/38_decoder/db/38_decoder.map.qmsg b/38_decoder/db/38_decoder.map.qmsg deleted file mode 100644 index 7d51101..0000000 --- a/38_decoder/db/38_decoder.map.qmsg +++ /dev/null @@ -1,7 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:12:38 2022 " "Info: Processing started: Tue Mar 08 15:12:38 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off 38_decoder -c 38_decoder " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off 38_decoder -c 38_decoder" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "38_decoder.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file 38_decoder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 38_decoder " "Info: Found entity 1: 38_decoder" { } { { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_START_ELABORATION_TOP" "38_decoder " "Info: Elaborating entity \"38_decoder\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_TM_SUMMARY" "19 " "Info: Implemented 19 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Info: Implemented 3 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:12:38 2022 " "Info: Processing ended: Tue Mar 08 15:12:38 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/38_decoder/db/38_decoder.map_bb.cdb b/38_decoder/db/38_decoder.map_bb.cdb deleted file mode 100644 index 52e3520..0000000 Binary files a/38_decoder/db/38_decoder.map_bb.cdb and /dev/null differ diff --git a/38_decoder/db/38_decoder.map_bb.hdb b/38_decoder/db/38_decoder.map_bb.hdb deleted file mode 100644 index 871b480..0000000 Binary files a/38_decoder/db/38_decoder.map_bb.hdb and /dev/null differ diff --git a/38_decoder/db/38_decoder.map_bb.logdb b/38_decoder/db/38_decoder.map_bb.logdb deleted file mode 100644 index 626799f..0000000 --- a/38_decoder/db/38_decoder.map_bb.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/38_decoder/db/38_decoder.pre_map.cdb b/38_decoder/db/38_decoder.pre_map.cdb deleted file mode 100644 index 8928020..0000000 Binary files a/38_decoder/db/38_decoder.pre_map.cdb and /dev/null differ diff --git a/38_decoder/db/38_decoder.pre_map.hdb b/38_decoder/db/38_decoder.pre_map.hdb deleted file mode 100644 index 41e732f..0000000 Binary files a/38_decoder/db/38_decoder.pre_map.hdb and /dev/null differ diff --git a/38_decoder/db/38_decoder.rtlv.hdb b/38_decoder/db/38_decoder.rtlv.hdb deleted file mode 100644 index c506974..0000000 Binary files a/38_decoder/db/38_decoder.rtlv.hdb and /dev/null differ diff --git a/38_decoder/db/38_decoder.rtlv_sg.cdb b/38_decoder/db/38_decoder.rtlv_sg.cdb deleted file mode 100644 index 294d082..0000000 Binary files a/38_decoder/db/38_decoder.rtlv_sg.cdb and /dev/null differ diff --git a/38_decoder/db/38_decoder.rtlv_sg_swap.cdb b/38_decoder/db/38_decoder.rtlv_sg_swap.cdb deleted file mode 100644 index bccc94e..0000000 Binary files a/38_decoder/db/38_decoder.rtlv_sg_swap.cdb and /dev/null differ diff --git a/38_decoder/db/38_decoder.sgdiff.cdb b/38_decoder/db/38_decoder.sgdiff.cdb deleted file mode 100644 index b12c775..0000000 Binary files a/38_decoder/db/38_decoder.sgdiff.cdb and /dev/null differ diff --git a/38_decoder/db/38_decoder.sgdiff.hdb b/38_decoder/db/38_decoder.sgdiff.hdb deleted file mode 100644 index 7b35d44..0000000 Binary files a/38_decoder/db/38_decoder.sgdiff.hdb and /dev/null differ diff --git a/38_decoder/db/38_decoder.sld_design_entry.sci b/38_decoder/db/38_decoder.sld_design_entry.sci deleted file mode 100644 index 904d003..0000000 Binary files a/38_decoder/db/38_decoder.sld_design_entry.sci and /dev/null differ diff --git a/38_decoder/db/38_decoder.sld_design_entry_dsc.sci b/38_decoder/db/38_decoder.sld_design_entry_dsc.sci deleted file mode 100644 index 2000bdc..0000000 Binary files a/38_decoder/db/38_decoder.sld_design_entry_dsc.sci and /dev/null differ diff --git a/38_decoder/db/38_decoder.syn_hier_info b/38_decoder/db/38_decoder.syn_hier_info deleted file mode 100644 index e69de29..0000000 diff --git a/38_decoder/db/38_decoder.tan.qmsg b/38_decoder/db/38_decoder.tan.qmsg deleted file mode 100644 index 0d4dd5e..0000000 --- a/38_decoder/db/38_decoder.tan.qmsg +++ /dev/null @@ -1,6 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:12:42 2022 " "Info: Processing started: Tue Mar 08 15:12:42 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "ITDB_FULL_TPD_RESULT" "I2 Y4 13.172 ns Longest " "Info: Longest tpd from source pin \"I2\" to destination pin \"Y4\" is 13.172 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns I2 1 PIN PIN_81 8 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_81; Fanout = 8; PIN Node = 'I2'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2 } "NODE_NAME" } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 144 32 200 160 "I2" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(7.387 ns) + CELL(0.651 ns) 9.012 ns inst10~5 2 COMB LCCOMB_X33_Y13_N2 1 " "Info: 2: + IC(7.387 ns) + CELL(0.651 ns) = 9.012 ns; Loc. = LCCOMB_X33_Y13_N2; Fanout = 1; COMB Node = 'inst10~5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.038 ns" { I2 inst10~5 } "NODE_NAME" } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 360 544 608 408 "inst10" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.054 ns) + CELL(3.106 ns) 13.172 ns Y4 3 PIN PIN_146 0 " "Info: 3: + IC(1.054 ns) + CELL(3.106 ns) = 13.172 ns; Loc. = PIN_146; Fanout = 0; PIN Node = 'Y4'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.160 ns" { inst10~5 Y4 } "NODE_NAME" } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 184 664 840 200 "Y4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.731 ns ( 35.92 % ) " "Info: Total cell delay = 4.731 ns ( 35.92 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.441 ns ( 64.08 % ) " "Info: Total interconnect delay = 8.441 ns ( 64.08 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "13.172 ns" { I2 inst10~5 Y4 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "13.172 ns" { I2 {} I2~combout {} inst10~5 {} Y4 {} } { 0.000ns 0.000ns 7.387ns 1.054ns } { 0.000ns 0.974ns 0.651ns 3.106ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:12:42 2022 " "Info: Processing ended: Tue Mar 08 15:12:42 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/38_decoder/db/38_decoder.tis_db_list.ddb b/38_decoder/db/38_decoder.tis_db_list.ddb deleted file mode 100644 index 2a9a6ed..0000000 Binary files a/38_decoder/db/38_decoder.tis_db_list.ddb and /dev/null differ diff --git a/38_decoder/db/38_decoder.tmw_info b/38_decoder/db/38_decoder.tmw_info deleted file mode 100644 index 6516e48..0000000 --- a/38_decoder/db/38_decoder.tmw_info +++ /dev/null @@ -1,6 +0,0 @@ -start_full_compilation:s:00:00:05 -start_analysis_synthesis:s:00:00:02-start_full_compilation -start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:01-start_full_compilation -start_assembler:s:00:00:02-start_full_compilation -start_timing_analyzer:s:00:00:00-start_full_compilation diff --git a/38_decoder/db/prev_cmp_38_decoder.asm.qmsg b/38_decoder/db/prev_cmp_38_decoder.asm.qmsg deleted file mode 100644 index 9297466..0000000 --- a/38_decoder/db/prev_cmp_38_decoder.asm.qmsg +++ /dev/null @@ -1,7 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 09:13:07 2022 " "Info: Processing started: Mon Mar 07 09:13:07 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1} -{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 09:13:07 2022 " "Info: Processing ended: Mon Mar 07 09:13:07 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/38_decoder/db/prev_cmp_38_decoder.fit.qmsg b/38_decoder/db/prev_cmp_38_decoder.fit.qmsg deleted file mode 100644 index a04d2f2..0000000 --- a/38_decoder/db/prev_cmp_38_decoder.fit.qmsg +++ /dev/null @@ -1,39 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 09:13:05 2022 " "Info: Processing started: Mon Mar 07 09:13:05 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "IMPP_MPP_USER_DEVICE" "38_decoder EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"38_decoder\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1} -{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "11 11 " "Warning: No exact pin location assignment(s) for 11 pins of 11 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y7 " "Info: Pin Y7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y7 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 40 664 840 56 "Y7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y0 " "Info: Pin Y0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y0 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 376 664 840 392 "Y0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y1 " "Info: Pin Y1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y1 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 328 664 840 344 "Y1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y2 " "Info: Pin Y2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y2 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 280 664 840 296 "Y2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y3 " "Info: Pin Y3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y3 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 232 664 840 248 "Y3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y4 " "Info: Pin Y4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y4 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 184 664 840 200 "Y4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y5 " "Info: Pin Y5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y5 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 136 664 840 152 "Y5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y6 " "Info: Pin Y6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y6 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 88 664 840 104 "Y6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "I2 " "Info: Pin I2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { I2 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 144 32 200 160 "I2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "I0 " "Info: Pin I0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { I0 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 328 32 200 344 "I0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "I1 " "Info: Pin I1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { I1 } } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 240 32 200 256 "I1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1} -{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1} -{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "11 unused 3.3V 3 8 0 " "Info: Number of I/O pins in group: 11 (unused VREF, 3.3V VCCIO, 3 input, 8 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 2 30 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 35 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 34 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 36 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X10_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} -{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y7 0 " "Info: Pin \"Y7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y0 0 " "Info: Pin \"Y0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y1 0 " "Info: Pin \"Y1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y2 0 " "Info: Pin \"Y2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y3 0 " "Info: Pin \"Y3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y4 0 " "Info: Pin \"Y4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y5 0 " "Info: Pin \"Y5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y6 0 " "Info: Pin \"Y6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/38_decoder/38_decoder.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/38_decoder/38_decoder.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "306 " "Info: Peak virtual memory: 306 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 09:13:06 2022 " "Info: Processing ended: Mon Mar 07 09:13:06 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/38_decoder/db/prev_cmp_38_decoder.map.qmsg b/38_decoder/db/prev_cmp_38_decoder.map.qmsg deleted file mode 100644 index bba0833..0000000 --- a/38_decoder/db/prev_cmp_38_decoder.map.qmsg +++ /dev/null @@ -1,7 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 09:13:04 2022 " "Info: Processing started: Mon Mar 07 09:13:04 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off 38_decoder -c 38_decoder " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off 38_decoder -c 38_decoder" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "38_decoder.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file 38_decoder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 38_decoder " "Info: Found entity 1: 38_decoder" { } { { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_START_ELABORATION_TOP" "38_decoder " "Info: Elaborating entity \"38_decoder\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_TM_SUMMARY" "19 " "Info: Implemented 19 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Info: Implemented 3 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "248 " "Info: Peak virtual memory: 248 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 09:13:04 2022 " "Info: Processing ended: Mon Mar 07 09:13:04 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/38_decoder/db/prev_cmp_38_decoder.tan.qmsg b/38_decoder/db/prev_cmp_38_decoder.tan.qmsg deleted file mode 100644 index a205924..0000000 --- a/38_decoder/db/prev_cmp_38_decoder.tan.qmsg +++ /dev/null @@ -1,6 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 09:13:08 2022 " "Info: Processing started: Mon Mar 07 09:13:08 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "ITDB_FULL_TPD_RESULT" "I2 Y2 13.383 ns Longest " "Info: Longest tpd from source pin \"I2\" to destination pin \"Y2\" is 13.383 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns I2 1 PIN PIN_41 8 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_41; Fanout = 8; PIN Node = 'I2'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2 } "NODE_NAME" } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 144 32 200 160 "I2" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.786 ns) + CELL(0.499 ns) 7.280 ns inst10~3 2 COMB LCCOMB_X1_Y7_N22 1 " "Info: 2: + IC(5.786 ns) + CELL(0.499 ns) = 7.280 ns; Loc. = LCCOMB_X1_Y7_N22; Fanout = 1; COMB Node = 'inst10~3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.285 ns" { I2 inst10~3 } "NODE_NAME" } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 360 544 608 408 "inst10" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.847 ns) + CELL(3.256 ns) 13.383 ns Y2 3 PIN PIN_195 0 " "Info: 3: + IC(2.847 ns) + CELL(3.256 ns) = 13.383 ns; Loc. = PIN_195; Fanout = 0; PIN Node = 'Y2'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.103 ns" { inst10~3 Y2 } "NODE_NAME" } } { "38_decoder.bdf" "" { Schematic "D:/projects/quartus/38_decoder/38_decoder.bdf" { { 280 664 840 296 "Y2" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.750 ns ( 35.49 % ) " "Info: Total cell delay = 4.750 ns ( 35.49 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.633 ns ( 64.51 % ) " "Info: Total interconnect delay = 8.633 ns ( 64.51 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "13.383 ns" { I2 inst10~3 Y2 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "13.383 ns" { I2 {} I2~combout {} inst10~3 {} Y2 {} } { 0.000ns 0.000ns 5.786ns 2.847ns } { 0.000ns 0.995ns 0.499ns 3.256ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 09:13:08 2022 " "Info: Processing ended: Mon Mar 07 09:13:08 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/38_decoder/incremental_db/README b/38_decoder/incremental_db/README deleted file mode 100644 index 9f62dcd..0000000 --- a/38_decoder/incremental_db/README +++ /dev/null @@ -1,11 +0,0 @@ -This folder contains data for incremental compilation. - -The compiled_partitions sub-folder contains previous compilation results for each partition. -As long as this folder is preserved, incremental compilation results from earlier compiles -can be re-used. To perform a clean compilation from source files for all partitions, both -the db and incremental_db folder should be removed. - -The imported_partitions sub-folder contains the last imported QXP for each imported partition. -As long as this folder is preserved, imported partitions will be automatically re-imported -when the db or incremental_db/compiled_partitions folders are removed. - diff --git a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.atm b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.atm deleted file mode 100644 index 120c51a..0000000 Binary files a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.atm and /dev/null differ diff --git a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.dfp b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.dfp deleted file mode 100644 index b1c67d6..0000000 Binary files a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.dfp and /dev/null differ diff --git a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.hdbx b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.hdbx deleted file mode 100644 index 815ddb3..0000000 Binary files a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.hdbx and /dev/null differ diff --git a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.kpt b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.kpt deleted file mode 100644 index c1e72d7..0000000 --- a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.kpt +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.logdb b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.logdb deleted file mode 100644 index 626799f..0000000 --- a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.rcf b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.rcf deleted file mode 100644 index 7ee905b..0000000 Binary files a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.cmp.rcf and /dev/null differ diff --git a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.atm b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.atm deleted file mode 100644 index e564434..0000000 Binary files a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.atm and /dev/null differ diff --git a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.dpi b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.dpi deleted file mode 100644 index b6b57a8..0000000 Binary files a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.dpi and /dev/null differ diff --git a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.hdbx b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.hdbx deleted file mode 100644 index 57e6d02..0000000 Binary files a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.hdbx and /dev/null differ diff --git a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.kpt b/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.kpt deleted file mode 100644 index 43f4226..0000000 --- a/38_decoder/incremental_db/compiled_partitions/38_decoder.root_partition.map.kpt +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/adder_8b/adder_8b.asm.rpt b/adder_8b/adder_8b.asm.rpt deleted file mode 100644 index 0389a29..0000000 --- a/adder_8b/adder_8b.asm.rpt +++ /dev/null @@ -1,129 +0,0 @@ -Assembler report for adder_8b -Mon Mar 07 11:28:58 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Assembler Summary - 3. Assembler Settings - 4. Assembler Generated Files - 5. Assembler Device Options: D:/projects/quartus/adder_8b/adder_8b.sof - 6. Assembler Device Options: D:/projects/quartus/adder_8b/adder_8b.pof - 7. Assembler Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+---------------------------------------------------------------+ -; Assembler Summary ; -+-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Mon Mar 07 11:28:58 2022 ; -; Revision Name ; adder_8b ; -; Top-level Entity Name ; adder_8b ; -; Family ; Cyclone II ; -; Device ; EP2C8Q208C8 ; -+-----------------------+---------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------+ -; Assembler Settings ; -+-----------------------------------------------------------------------------+----------+---------------+ -; Option ; Setting ; Default Value ; -+-----------------------------------------------------------------------------+----------+---------------+ -; Use smart compilation ; Off ; Off ; -; Generate compressed bitstreams ; On ; On ; -; Compression mode ; Off ; Off ; -; Clock source for configuration device ; Internal ; Internal ; -; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; -; Divide clock frequency by ; 1 ; 1 ; -; Auto user code ; Off ; Off ; -; Use configuration device ; On ; On ; -; Configuration device ; Auto ; Auto ; -; Configuration device auto user code ; Off ; Off ; -; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; -; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; -; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; -; Hexadecimal Output File start address ; 0 ; 0 ; -; Hexadecimal Output File count direction ; Up ; Up ; -; Release clears before tri-states ; Off ; Off ; -; Auto-restart configuration after error ; On ; On ; -; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ; -; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; -; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; -; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; -; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; -+-----------------------------------------------------------------------------+----------+---------------+ - - -+-------------------------------------------+ -; Assembler Generated Files ; -+-------------------------------------------+ -; File Name ; -+-------------------------------------------+ -; D:/projects/quartus/adder_8b/adder_8b.sof ; -; D:/projects/quartus/adder_8b/adder_8b.pof ; -+-------------------------------------------+ - - -+---------------------------------------------------------------------+ -; Assembler Device Options: D:/projects/quartus/adder_8b/adder_8b.sof ; -+----------------+----------------------------------------------------+ -; Option ; Setting ; -+----------------+----------------------------------------------------+ -; Device ; EP2C8Q208C8 ; -; JTAG usercode ; 0xFFFFFFFF ; -; Checksum ; 0x000C3C8E ; -+----------------+----------------------------------------------------+ - - -+---------------------------------------------------------------------+ -; Assembler Device Options: D:/projects/quartus/adder_8b/adder_8b.pof ; -+--------------------+------------------------------------------------+ -; Option ; Setting ; -+--------------------+------------------------------------------------+ -; Device ; EPCS4 ; -; JTAG usercode ; 0x00000000 ; -; Checksum ; 0x06EFBA32 ; -; Compression Ratio ; 3 ; -+--------------------+------------------------------------------------+ - - -+--------------------+ -; Assembler Messages ; -+--------------------+ -Info: ******************************************************************* -Info: Running Quartus II Assembler - Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Mon Mar 07 11:28:58 2022 -Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b -Info: Writing out detailed assembly data for power analysis -Info: Assembler is generating device programming files -Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled -Info: Quartus II Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 242 megabytes - Info: Processing ended: Mon Mar 07 11:28:58 2022 - Info: Elapsed time: 00:00:00 - Info: Total CPU time (on all processors): 00:00:00 - - diff --git a/adder_8b/adder_8b.done b/adder_8b/adder_8b.done deleted file mode 100644 index c3c07d5..0000000 --- a/adder_8b/adder_8b.done +++ /dev/null @@ -1 +0,0 @@ -Mon Mar 07 11:29:00 2022 diff --git a/adder_8b/adder_8b.fit.rpt b/adder_8b/adder_8b.fit.rpt deleted file mode 100644 index c079c15..0000000 --- a/adder_8b/adder_8b.fit.rpt +++ /dev/null @@ -1,1014 +0,0 @@ -Fitter report for adder_8b -Mon Mar 07 11:28:57 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Fitter Summary - 3. Fitter Settings - 4. Parallel Compilation - 5. Incremental Compilation Preservation Summary - 6. Incremental Compilation Partition Settings - 7. Incremental Compilation Placement Preservation - 8. Pin-Out File - 9. Fitter Resource Usage Summary - 10. Input Pins - 11. Output Pins - 12. I/O Bank Usage - 13. All Package Pins - 14. Output Pin Default Load For Reported TCO - 15. Fitter Resource Utilization by Entity - 16. Delay Chain Summary - 17. Pad To Core Delay Chain Fanout - 18. Non-Global High Fan-Out Signals - 19. Interconnect Usage Summary - 20. LAB Logic Elements - 21. LAB Signals Sourced - 22. LAB Signals Sourced Out - 23. LAB Distinct Inputs - 24. Fitter Device Options - 25. Operating Settings and Conditions - 26. Estimated Delay Added for Hold Timing - 27. Advanced Data - General - 28. Advanced Data - Placement Preparation - 29. Advanced Data - Placement - 30. Advanced Data - Routing - 31. Fitter Messages - 32. Fitter Suppressed Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------------+ -; Fitter Summary ; -+------------------------------------+----------------------------------------------+ -; Fitter Status ; Successful - Mon Mar 07 11:28:57 2022 ; -; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; -; Revision Name ; adder_8b ; -; Top-level Entity Name ; adder_8b ; -; Family ; Cyclone II ; -; Device ; EP2C8Q208C8 ; -; Timing Models ; Final ; -; Total logic elements ; 21 / 8,256 ( < 1 % ) ; -; Total combinational functions ; 21 / 8,256 ( < 1 % ) ; -; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ; -; Total registers ; 0 ; -; Total pins ; 26 / 138 ( 19 % ) ; -; Total virtual pins ; 0 ; -; Total memory bits ; 0 / 165,888 ( 0 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; -; Total PLLs ; 0 / 2 ( 0 % ) ; -+------------------------------------+----------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Settings ; -+--------------------------------------------------------------------+--------------------------------+--------------------------------+ -; Option ; Setting ; Default Value ; -+--------------------------------------------------------------------+--------------------------------+--------------------------------+ -; Device ; EP2C8Q208C8 ; ; -; Minimum Core Junction Temperature ; 0 ; ; -; Maximum Core Junction Temperature ; 85 ; ; -; Fit Attempts to Skip ; 0 ; 0.0 ; -; Device I/O Standard ; 3.3-V LVTTL ; ; -; Use smart compilation ; Off ; Off ; -; Use TimeQuest Timing Analyzer ; Off ; Off ; -; Router Timing Optimization Level ; Normal ; Normal ; -; Placement Effort Multiplier ; 1.0 ; 1.0 ; -; Router Effort Multiplier ; 1.0 ; 1.0 ; -; Always Enable Input Buffers ; Off ; Off ; -; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; -; Optimize Multi-Corner Timing ; Off ; Off ; -; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; -; Optimize Timing ; Normal compilation ; Normal compilation ; -; Optimize Timing for ECOs ; Off ; Off ; -; Regenerate full fit report during ECO compiles ; Off ; Off ; -; Optimize IOC Register Placement for Timing ; On ; On ; -; Limit to One Fitting Attempt ; Off ; Off ; -; Final Placement Optimizations ; Automatically ; Automatically ; -; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; -; Fitter Initial Placement Seed ; 1 ; 1 ; -; PCI I/O ; Off ; Off ; -; Weak Pull-Up Resistor ; Off ; Off ; -; Enable Bus-Hold Circuitry ; Off ; Off ; -; Auto Global Memory Control Signals ; Off ; Off ; -; Auto Packed Registers ; Auto ; Auto ; -; Auto Delay Chains ; On ; On ; -; Auto Merge PLLs ; On ; On ; -; Ignore PLL Mode When Merging PLLs ; Off ; Off ; -; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; -; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; -; Perform Register Duplication for Performance ; Off ; Off ; -; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; -; Perform Register Retiming for Performance ; Off ; Off ; -; Perform Asynchronous Signal Pipelining ; Off ; Off ; -; Fitter Effort ; Auto Fit ; Auto Fit ; -; Physical Synthesis Effort Level ; Normal ; Normal ; -; Auto Global Clock ; On ; On ; -; Auto Global Register Control Signals ; On ; On ; -; Stop After Congestion Map Generation ; Off ; Off ; -; Save Intermediate Fitting Results ; Off ; Off ; -; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; -+--------------------------------------------------------------------+--------------------------------+--------------------------------+ - - -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 4 ; -; Maximum allowed ; 4 ; -; ; ; -; Average used ; 1.00 ; -; Maximum used ; 4 ; -; ; ; -; Usage by Processor ; % Time Used ; -; 1 processor ; 100.0% ; -; 2-4 processors ; < 0.1% ; -+----------------------------+-------------+ - - -+----------------------------------------------+ -; Incremental Compilation Preservation Summary ; -+-------------------------+--------------------+ -; Type ; Value ; -+-------------------------+--------------------+ -; Placement ; ; -; -- Requested ; 0 / 47 ( 0.00 % ) ; -; -- Achieved ; 0 / 47 ( 0.00 % ) ; -; ; ; -; Routing (by Connection) ; ; -; -- Requested ; 0 / 0 ( 0.00 % ) ; -; -- Achieved ; 0 / 0 ( 0.00 % ) ; -+-------------------------+--------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Incremental Compilation Partition Settings ; -+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ -; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; -+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ -; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; -+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ - - -+--------------------------------------------------------------------------------------------+ -; Incremental Compilation Placement Preservation ; -+----------------+---------+-------------------+-------------------------+-------------------+ -; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; -+----------------+---------+-------------------+-------------------------+-------------------+ -; Top ; 47 ; 0 ; N/A ; Source File ; -+----------------+---------+-------------------+-------------------------+-------------------+ - - -+--------------+ -; Pin-Out File ; -+--------------+ -The pin-out file can be found in D:/projects/quartus/adder_8b/adder_8b.pin. - - -+--------------------------------------------------------------------+ -; Fitter Resource Usage Summary ; -+---------------------------------------------+----------------------+ -; Resource ; Usage ; -+---------------------------------------------+----------------------+ -; Total logic elements ; 21 / 8,256 ( < 1 % ) ; -; -- Combinational with no register ; 21 ; -; -- Register only ; 0 ; -; -- Combinational with a register ; 0 ; -; ; ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 9 ; -; -- 3 input functions ; 9 ; -; -- <=2 input functions ; 3 ; -; -- Register only ; 0 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 21 ; -; -- arithmetic mode ; 0 ; -; ; ; -; Total registers* ; 0 / 8,646 ( 0 % ) ; -; -- Dedicated logic registers ; 0 / 8,256 ( 0 % ) ; -; -- I/O registers ; 0 / 390 ( 0 % ) ; -; ; ; -; Total LABs: partially or completely used ; 2 / 516 ( < 1 % ) ; -; User inserted logic elements ; 0 ; -; Virtual pins ; 0 ; -; I/O pins ; 26 / 138 ( 19 % ) ; -; -- Clock pins ; 1 / 4 ( 25 % ) ; -; Global signals ; 0 ; -; M4Ks ; 0 / 36 ( 0 % ) ; -; Total block memory bits ; 0 / 165,888 ( 0 % ) ; -; Total block memory implementation bits ; 0 / 165,888 ( 0 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; -; PLLs ; 0 / 2 ( 0 % ) ; -; Global clocks ; 0 / 8 ( 0 % ) ; -; JTAGs ; 0 / 1 ( 0 % ) ; -; ASMI blocks ; 0 / 1 ( 0 % ) ; -; CRC blocks ; 0 / 1 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; -; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ; -; Maximum fan-out node ; 7400:inst8|4~0 ; -; Maximum fan-out ; 4 ; -; Highest non-global fan-out signal ; 7400:inst8|4~0 ; -; Highest non-global fan-out ; 4 ; -; Total fan-out ; 78 ; -; Average fan-out ; 1.56 ; -+---------------------------------------------+----------------------+ -* Register count does not include registers inside RAM blocks or DSP blocks. - - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Input Pins ; -+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ; -+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ -; A0 ; 77 ; 4 ; 18 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; A1 ; 80 ; 4 ; 23 ; 0 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; A2 ; 81 ; 4 ; 23 ; 0 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; A3 ; 82 ; 4 ; 23 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; A4 ; 84 ; 4 ; 25 ; 0 ; 3 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; A5 ; 86 ; 4 ; 25 ; 0 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; A6 ; 87 ; 4 ; 25 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; A7 ; 88 ; 4 ; 25 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; B0 ; 67 ; 4 ; 9 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; B1 ; 68 ; 4 ; 12 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; B2 ; 69 ; 4 ; 12 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; B3 ; 70 ; 4 ; 14 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; B4 ; 72 ; 4 ; 16 ; 0 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; B5 ; 74 ; 4 ; 16 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; B6 ; 75 ; 4 ; 16 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; B7 ; 76 ; 4 ; 18 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; CI ; 23 ; 1 ; 0 ; 9 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Output Pins ; -+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; -+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ -; CO ; 151 ; 3 ; 34 ; 17 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; S0 ; 142 ; 3 ; 34 ; 12 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; S1 ; 143 ; 3 ; 34 ; 13 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; S2 ; 144 ; 3 ; 34 ; 13 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; S3 ; 145 ; 3 ; 34 ; 14 ; 4 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; S4 ; 146 ; 3 ; 34 ; 15 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; S5 ; 147 ; 3 ; 34 ; 15 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; S6 ; 149 ; 3 ; 34 ; 16 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; S7 ; 150 ; 3 ; 34 ; 16 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ - - -+------------------------------------------------------------+ -; I/O Bank Usage ; -+----------+------------------+---------------+--------------+ -; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; -+----------+------------------+---------------+--------------+ -; 1 ; 3 / 32 ( 9 % ) ; 3.3V ; -- ; -; 2 ; 0 / 35 ( 0 % ) ; 3.3V ; -- ; -; 3 ; 10 / 35 ( 29 % ) ; 3.3V ; -- ; -; 4 ; 16 / 36 ( 44 % ) ; 3.3V ; -- ; -+----------+------------------+---------------+--------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; All Package Pins ; -+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; -+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -; 1 ; 0 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; -; 2 ; 1 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; -; 3 ; 2 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 4 ; 3 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 5 ; 4 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 6 ; 5 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 8 ; 6 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 10 ; 7 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 11 ; 8 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 12 ; 9 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 13 ; 10 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 14 ; 18 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 15 ; 19 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; -; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; -; 18 ; 22 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; -; 19 ; 23 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; -; 20 ; 24 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ; -; 21 ; 25 ; 1 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ; -; 22 ; 26 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; -; 23 ; 27 ; 1 ; CI ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 24 ; 28 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 26 ; 29 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; -; 27 ; 30 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 28 ; 31 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 30 ; 32 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 31 ; 33 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 33 ; 35 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 34 ; 36 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 35 ; 37 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 37 ; 39 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 39 ; 43 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 40 ; 44 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 41 ; 45 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 42 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 43 ; 48 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 44 ; 49 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 45 ; 50 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 46 ; 51 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 47 ; 52 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 48 ; 53 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 49 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 50 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; -; 51 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 52 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; -; 53 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 54 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; -; 55 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 56 ; 54 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 57 ; 55 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 58 ; 56 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 59 ; 57 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 60 ; 58 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 61 ; 59 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 63 ; 60 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 64 ; 61 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 67 ; 69 ; 4 ; B0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 68 ; 70 ; 4 ; B1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 69 ; 71 ; 4 ; B2 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 70 ; 74 ; 4 ; B3 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 71 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 72 ; 75 ; 4 ; B4 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 74 ; 76 ; 4 ; B5 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 75 ; 77 ; 4 ; B6 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 76 ; 78 ; 4 ; B7 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 77 ; 79 ; 4 ; A0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 80 ; 82 ; 4 ; A1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 81 ; 83 ; 4 ; A2 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 82 ; 84 ; 4 ; A3 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 83 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 84 ; 85 ; 4 ; A4 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 85 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 86 ; 86 ; 4 ; A5 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 87 ; 87 ; 4 ; A6 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 88 ; 88 ; 4 ; A7 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 89 ; 89 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 90 ; 90 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 91 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 92 ; 91 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 94 ; 92 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 95 ; 93 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 96 ; 94 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 97 ; 95 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 98 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 99 ; 96 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 100 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 101 ; 97 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 102 ; 98 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 103 ; 99 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 104 ; 100 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 105 ; 101 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 106 ; 102 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 107 ; 105 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 108 ; 106 ; 3 ; ~LVDS54p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 109 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 110 ; 107 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 111 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 112 ; 108 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 113 ; 109 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 114 ; 110 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 115 ; 112 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 116 ; 113 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 117 ; 114 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 118 ; 117 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 119 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 120 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 121 ; 121 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; -; 122 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 123 ; 122 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; -; 124 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 125 ; 123 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; -; 126 ; 124 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; -; 127 ; 125 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 128 ; 126 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 129 ; 127 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 130 ; 128 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 131 ; 129 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 132 ; 130 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 133 ; 131 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 134 ; 132 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 135 ; 133 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 136 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 137 ; 134 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 138 ; 135 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 139 ; 136 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 141 ; 137 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 142 ; 138 ; 3 ; S0 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 143 ; 141 ; 3 ; S1 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 144 ; 142 ; 3 ; S2 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 145 ; 143 ; 3 ; S3 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 146 ; 149 ; 3 ; S4 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 147 ; 150 ; 3 ; S5 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 148 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 149 ; 151 ; 3 ; S6 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 150 ; 152 ; 3 ; S7 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 151 ; 153 ; 3 ; CO ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 152 ; 154 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 153 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 154 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; -; 155 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 156 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; -; 157 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 158 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; -; 159 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 160 ; 155 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 161 ; 156 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 162 ; 157 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 163 ; 158 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 164 ; 159 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 165 ; 160 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 166 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 167 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 168 ; 161 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 169 ; 162 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 170 ; 163 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 171 ; 164 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 172 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 173 ; 165 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 174 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 175 ; 168 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 176 ; 169 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 177 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 178 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 179 ; 173 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 180 ; 174 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 181 ; 175 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 182 ; 176 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 183 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 184 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 185 ; 180 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 186 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 187 ; 181 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 188 ; 182 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 189 ; 183 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 190 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 191 ; 184 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 192 ; 185 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 193 ; 186 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 194 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 195 ; 187 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 196 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 197 ; 191 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 198 ; 192 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 199 ; 195 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 200 ; 196 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 201 ; 197 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 202 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 203 ; 198 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 204 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 205 ; 199 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 206 ; 200 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 207 ; 201 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 208 ; 202 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -Note: Pin directions (input, output or bidir) are based on device operating in user mode. - - -+-------------------------------------------------------------------------------+ -; Output Pin Default Load For Reported TCO ; -+----------------------------------+-------+------------------------------------+ -; I/O Standard ; Load ; Termination Resistance ; -+----------------------------------+-------+------------------------------------+ -; 3.3-V LVTTL ; 0 pF ; Not Available ; -; 3.3-V LVCMOS ; 0 pF ; Not Available ; -; 2.5 V ; 0 pF ; Not Available ; -; 1.8 V ; 0 pF ; Not Available ; -; 1.5 V ; 0 pF ; Not Available ; -; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ; -; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ; -; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; -; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; -; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; -; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; -; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; -; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; -; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; -; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; -; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ; -; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ; -; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ; -; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ; -; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ; -; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ; -; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ; -; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ; -; LVDS ; 0 pF ; 100 Ohm (Differential) ; -; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ; -; RSDS ; 0 pF ; 100 Ohm (Differential) ; -; Simple RSDS ; 0 pF ; Not Available ; -; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ; -+----------------------------------+-------+------------------------------------+ -Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Resource Utilization by Entity ; -+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------+--------------+ -; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; -+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------+--------------+ -; |adder_8b ; 21 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 26 ; 0 ; 21 (0) ; 0 (0) ; 0 (0) ; |adder_8b ; work ; -; |7400:inst13| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |adder_8b|7400:inst13 ; work ; -; |7400:inst18| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder_8b|7400:inst18 ; work ; -; |7400:inst23| ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 0 (0) ; |adder_8b|7400:inst23 ; work ; -; |7400:inst28| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder_8b|7400:inst28 ; work ; -; |7400:inst33| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |adder_8b|7400:inst33 ; work ; -; |7400:inst38| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder_8b|7400:inst38 ; work ; -; |7400:inst3| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |adder_8b|7400:inst3 ; work ; -; |7400:inst8| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder_8b|7400:inst8 ; work ; -; |7486:inst10| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder_8b|7486:inst10 ; work ; -; |7486:inst15| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder_8b|7486:inst15 ; work ; -; |7486:inst20| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder_8b|7486:inst20 ; work ; -; |7486:inst25| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder_8b|7486:inst25 ; work ; -; |7486:inst30| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder_8b|7486:inst30 ; work ; -; |7486:inst35| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder_8b|7486:inst35 ; work ; -; |7486:inst40| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder_8b|7486:inst40 ; work ; -; |7486:inst5| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder_8b|7486:inst5 ; work ; -+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------+--------------+ -Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. - - -+-------------------------------------------------------------------------------+ -; Delay Chain Summary ; -+------+----------+---------------+---------------+-----------------------+-----+ -; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; -+------+----------+---------------+---------------+-----------------------+-----+ -; CO ; Output ; -- ; -- ; -- ; -- ; -; S7 ; Output ; -- ; -- ; -- ; -- ; -; S0 ; Output ; -- ; -- ; -- ; -- ; -; S1 ; Output ; -- ; -- ; -- ; -- ; -; S2 ; Output ; -- ; -- ; -- ; -- ; -; S3 ; Output ; -- ; -- ; -- ; -- ; -; S4 ; Output ; -- ; -- ; -- ; -- ; -; S5 ; Output ; -- ; -- ; -- ; -- ; -; S6 ; Output ; -- ; -- ; -- ; -- ; -; A6 ; Input ; 6 ; 6 ; -- ; -- ; -; A3 ; Input ; 6 ; 6 ; -- ; -- ; -; B3 ; Input ; 6 ; 6 ; -- ; -- ; -; A4 ; Input ; 6 ; 6 ; -- ; -- ; -; A2 ; Input ; 6 ; 6 ; -- ; -- ; -; A0 ; Input ; 6 ; 6 ; -- ; -- ; -; CI ; Input ; 0 ; 0 ; -- ; -- ; -; B0 ; Input ; 6 ; 6 ; -- ; -- ; -; A1 ; Input ; 6 ; 6 ; -- ; -- ; -; B1 ; Input ; 6 ; 6 ; -- ; -- ; -; B2 ; Input ; 6 ; 6 ; -- ; -- ; -; B4 ; Input ; 6 ; 6 ; -- ; -- ; -; A5 ; Input ; 6 ; 6 ; -- ; -- ; -; B5 ; Input ; 6 ; 6 ; -- ; -- ; -; B6 ; Input ; 6 ; 6 ; -- ; -- ; -; A7 ; Input ; 6 ; 6 ; -- ; -- ; -; B7 ; Input ; 6 ; 6 ; -- ; -- ; -+------+----------+---------------+---------------+-----------------------+-----+ - - -+-------------------------------------------------------+ -; Pad To Core Delay Chain Fanout ; -+-------------------------+-------------------+---------+ -; Source Pin / Fanout ; Pad To Core Index ; Setting ; -+-------------------------+-------------------+---------+ -; A6 ; ; ; -; - 7400:inst33|4~0 ; 1 ; 6 ; -; - 7400:inst33|4~1 ; 1 ; 6 ; -; - 7486:inst35|4~0 ; 1 ; 6 ; -; A3 ; ; ; -; - 7400:inst23|4~8 ; 0 ; 6 ; -; - 7400:inst18|4~0 ; 0 ; 6 ; -; - 7486:inst20|4 ; 0 ; 6 ; -; B3 ; ; ; -; - 7400:inst23|4~8 ; 0 ; 6 ; -; - 7400:inst18|4~0 ; 0 ; 6 ; -; - 7486:inst20|4 ; 0 ; 6 ; -; A4 ; ; ; -; - 7400:inst23|4~8 ; 0 ; 6 ; -; - 7400:inst23|4~9 ; 0 ; 6 ; -; - 7486:inst25|4~0 ; 0 ; 6 ; -; A2 ; ; ; -; - 7400:inst13|4~0 ; 0 ; 6 ; -; - 7400:inst13|4~1 ; 0 ; 6 ; -; - 7486:inst15|4~0 ; 0 ; 6 ; -; - 7400:inst23|4~10 ; 0 ; 6 ; -; A0 ; ; ; -; - 7400:inst3|4~0 ; 0 ; 6 ; -; - 7400:inst3|4~1 ; 0 ; 6 ; -; - 7486:inst5|4~0 ; 0 ; 6 ; -; CI ; ; ; -; B0 ; ; ; -; - 7400:inst3|4~1 ; 0 ; 6 ; -; - 7486:inst5|4~0 ; 0 ; 6 ; -; A1 ; ; ; -; - 7400:inst8|4~0 ; 0 ; 6 ; -; - 7486:inst10|4 ; 0 ; 6 ; -; B1 ; ; ; -; - 7400:inst8|4~0 ; 0 ; 6 ; -; - 7486:inst10|4 ; 0 ; 6 ; -; B2 ; ; ; -; - 7400:inst13|4~1 ; 0 ; 6 ; -; - 7486:inst15|4~0 ; 0 ; 6 ; -; - 7400:inst23|4~10 ; 0 ; 6 ; -; B4 ; ; ; -; - 7400:inst23|4~9 ; 0 ; 6 ; -; - 7486:inst25|4~0 ; 0 ; 6 ; -; A5 ; ; ; -; - 7400:inst28|4~0 ; 0 ; 6 ; -; - 7486:inst30|4 ; 0 ; 6 ; -; B5 ; ; ; -; - 7400:inst28|4~0 ; 1 ; 6 ; -; - 7486:inst30|4 ; 1 ; 6 ; -; B6 ; ; ; -; - 7400:inst33|4~1 ; 1 ; 6 ; -; - 7486:inst35|4~0 ; 1 ; 6 ; -; A7 ; ; ; -; - 7400:inst38|4~0 ; 0 ; 6 ; -; - 7486:inst40|4 ; 0 ; 6 ; -; B7 ; ; ; -; - 7400:inst38|4~0 ; 0 ; 6 ; -; - 7486:inst40|4 ; 0 ; 6 ; -+-------------------------+-------------------+---------+ - - -+---------------------------------+ -; Non-Global High Fan-Out Signals ; -+------------------+--------------+ -; Name ; Fan-Out ; -+------------------+--------------+ -; A2 ; 4 ; -; 7400:inst8|4~0 ; 4 ; -; B2 ; 3 ; -; CI ; 3 ; -; A0 ; 3 ; -; A4 ; 3 ; -; B3 ; 3 ; -; A3 ; 3 ; -; A6 ; 3 ; -; 7400:inst28|4~0 ; 3 ; -; B7 ; 2 ; -; A7 ; 2 ; -; B6 ; 2 ; -; B5 ; 2 ; -; A5 ; 2 ; -; B4 ; 2 ; -; B1 ; 2 ; -; A1 ; 2 ; -; B0 ; 2 ; -; 7400:inst33|4~1 ; 2 ; -; 7400:inst33|4~0 ; 2 ; -; 7400:inst23|4~9 ; 2 ; -; 7400:inst18|4~0 ; 2 ; -; 7400:inst23|4~8 ; 2 ; -; 7400:inst13|4~1 ; 2 ; -; 7400:inst13|4~0 ; 2 ; -; 7400:inst3|4~1 ; 2 ; -; 7400:inst3|4~0 ; 2 ; -; 7400:inst23|4~10 ; 1 ; -; 7486:inst35|4~0 ; 1 ; -; 7486:inst30|4 ; 1 ; -; 7486:inst25|4~0 ; 1 ; -; 7486:inst20|4 ; 1 ; -; 7486:inst15|4~0 ; 1 ; -; 7486:inst10|4 ; 1 ; -; 7486:inst5|4~0 ; 1 ; -; 7486:inst40|4 ; 1 ; -; 7400:inst38|4~0 ; 1 ; -+------------------+--------------+ - - -+----------------------------------------------------+ -; Interconnect Usage Summary ; -+----------------------------+-----------------------+ -; Interconnect Resource Type ; Usage ; -+----------------------------+-----------------------+ -; Block interconnects ; 27 / 26,052 ( < 1 % ) ; -; C16 interconnects ; 7 / 1,156 ( < 1 % ) ; -; C4 interconnects ; 37 / 17,952 ( < 1 % ) ; -; Direct links ; 0 / 26,052 ( 0 % ) ; -; Global clocks ; 0 / 8 ( 0 % ) ; -; Local interconnects ; 11 / 8,256 ( < 1 % ) ; -; R24 interconnects ; 5 / 1,020 ( < 1 % ) ; -; R4 interconnects ; 47 / 22,440 ( < 1 % ) ; -+----------------------------+-----------------------+ - - -+---------------------------------------------------------------------------+ -; LAB Logic Elements ; -+---------------------------------------------+-----------------------------+ -; Number of Logic Elements (Average = 10.50) ; Number of LABs (Total = 2) ; -+---------------------------------------------+-----------------------------+ -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 1 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 0 ; -; 9 ; 0 ; -; 10 ; 0 ; -; 11 ; 0 ; -; 12 ; 0 ; -; 13 ; 0 ; -; 14 ; 0 ; -; 15 ; 0 ; -; 16 ; 1 ; -+---------------------------------------------+-----------------------------+ - - -+----------------------------------------------------------------------------+ -; LAB Signals Sourced ; -+----------------------------------------------+-----------------------------+ -; Number of Signals Sourced (Average = 10.50) ; Number of LABs (Total = 2) ; -+----------------------------------------------+-----------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 1 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 0 ; -; 9 ; 0 ; -; 10 ; 0 ; -; 11 ; 0 ; -; 12 ; 0 ; -; 13 ; 0 ; -; 14 ; 0 ; -; 15 ; 0 ; -; 16 ; 1 ; -+----------------------------------------------+-----------------------------+ - - -+-------------------------------------------------------------------------------+ -; LAB Signals Sourced Out ; -+-------------------------------------------------+-----------------------------+ -; Number of Signals Sourced Out (Average = 5.00) ; Number of LABs (Total = 2) ; -+-------------------------------------------------+-----------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 1 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 1 ; -+-------------------------------------------------+-----------------------------+ - - -+---------------------------------------------------------------------------+ -; LAB Distinct Inputs ; -+---------------------------------------------+-----------------------------+ -; Number of Distinct Inputs (Average = 9.00) ; Number of LABs (Total = 2) ; -+---------------------------------------------+-----------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 1 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 0 ; -; 9 ; 0 ; -; 10 ; 0 ; -; 11 ; 0 ; -; 12 ; 0 ; -; 13 ; 1 ; -+---------------------------------------------+-----------------------------+ - - -+-------------------------------------------------------------------------+ -; Fitter Device Options ; -+----------------------------------------------+--------------------------+ -; Option ; Setting ; -+----------------------------------------------+--------------------------+ -; Enable user-supplied start-up clock (CLKUSR) ; Off ; -; Enable device-wide reset (DEV_CLRn) ; Off ; -; Enable device-wide output enable (DEV_OE) ; Off ; -; Enable INIT_DONE output ; Off ; -; Configuration scheme ; Active Serial ; -; Error detection CRC ; Off ; -; nCEO ; As output driving ground ; -; ASDO,nCSO ; As input tri-stated ; -; Reserve all unused pins ; As input tri-stated ; -; Base pin-out file on sameframe device ; Off ; -+----------------------------------------------+--------------------------+ - - -+------------------------------------+ -; Operating Settings and Conditions ; -+---------------------------+--------+ -; Setting ; Value ; -+---------------------------+--------+ -; Nominal Core Voltage ; 1.20 V ; -; Low Junction Temperature ; 0 °C ; -; High Junction Temperature ; 85 °C ; -+---------------------------+--------+ - - -+------------------------------------------------------------+ -; Estimated Delay Added for Hold Timing ; -+-----------------+----------------------+-------------------+ -; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; -+-----------------+----------------------+-------------------+ - - -+----------------------------+ -; Advanced Data - General ; -+--------------------+-------+ -; Name ; Value ; -+--------------------+-------+ -; Status Code ; 0 ; -; Desired User Slack ; 0 ; -; Fit Attempts ; 1 ; -+--------------------+-------+ - - -+---------------------------------------------------------------------------------+ -; Advanced Data - Placement Preparation ; -+------------------------------------------------------------------+--------------+ -; Name ; Value ; -+------------------------------------------------------------------+--------------+ -; Auto Fit Point 1 - Fit Attempt 1 ; ff ; -; Mid Wire Use - Fit Attempt 1 ; 0 ; -; Mid Slack - Fit Attempt 1 ; 2147483639 ; -; Internal Atom Count - Fit Attempt 1 ; 22 ; -; LE/ALM Count - Fit Attempt 1 ; 22 ; -; LAB Count - Fit Attempt 1 ; 3 ; -; Outputs per Lab - Fit Attempt 1 ; 3.333 ; -; Inputs per LAB - Fit Attempt 1 ; 6.000 ; -; Global Inputs per LAB - Fit Attempt 1 ; 0.000 ; -; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:3 ; -; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:3 ; -; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:3 ; -; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:3 ; -; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:3 ; -; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:3 ; -; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:3 ; -; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:3 ; -; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:3 ; -; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:3 ; -; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:3 ; -; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:3 ; -; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;4:1;12:1 ; -; LEs in Chains - Fit Attempt 1 ; 0 ; -; LEs in Long Chains - Fit Attempt 1 ; 0 ; -; LABs with Chains - Fit Attempt 1 ; 0 ; -; LABs with Multiple Chains - Fit Attempt 1 ; 0 ; -; Time - Fit Attempt 1 ; 0 ; -+------------------------------------------------------------------+--------------+ - - -+-------------------------------------------------+ -; Advanced Data - Placement ; -+------------------------------------+------------+ -; Name ; Value ; -+------------------------------------+------------+ -; Auto Fit Point 2 - Fit Attempt 1 ; ff ; -; Auto Fit Point 5 - Fit Attempt 1 ; ff ; -; Mid Wire Use - Fit Attempt 1 ; 0 ; -; Mid Slack - Fit Attempt 1 ; 2147483639 ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 5 - Fit Attempt 1 ; ff ; -; Mid Wire Use - Fit Attempt 1 ; 0 ; -; Mid Slack - Fit Attempt 1 ; 2147483639 ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Late Wire Use - Fit Attempt 1 ; 0 ; -; Late Slack - Fit Attempt 1 ; 2147483639 ; -; Peak Regional Wire - Fit Attempt 1 ; 0.000 ; -; Auto Fit Point 7 - Fit Attempt 1 ; ff ; -; Time - Fit Attempt 1 ; 0 ; -+------------------------------------+------------+ - - -+---------------------------------------------------+ -; Advanced Data - Routing ; -+-------------------------------------+-------------+ -; Name ; Value ; -+-------------------------------------+-------------+ -; Early Slack - Fit Attempt 1 ; 2147483639 ; -; Early Wire Use - Fit Attempt 1 ; 0 ; -; Peak Regional Wire - Fit Attempt 1 ; 1 ; -; Mid Slack - Fit Attempt 1 ; 2147483639 ; -; Late Slack - Fit Attempt 1 ; -2147483648 ; -; Late Wire Use - Fit Attempt 1 ; 0 ; -; Time - Fit Attempt 1 ; 0 ; -; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016 ; -+-------------------------------------+-------------+ - - -+-----------------+ -; Fitter Messages ; -+-----------------+ -Info: ******************************************************************* -Info: Running Quartus II Fitter - Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Mon Mar 07 11:28:56 2022 -Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b -Info: Parallel compilation is enabled and will use 4 of the 4 processors detected -Info: Selected device EP2C8Q208C8 for design "adder_8b" -Info: Low junction temperature is 0 degrees C -Info: High junction temperature is 85 degrees C -Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time -Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices - Info: Device EP2C5Q208C8 is compatible - Info: Device EP2C5Q208I8 is compatible - Info: Device EP2C8Q208I8 is compatible -Info: Fitter converted 3 user pins into dedicated programming pins - Info: Pin ~ASDO~ is reserved at location 1 - Info: Pin ~nCSO~ is reserved at location 2 - Info: Pin ~LVDS54p/nCEO~ is reserved at location 108 -Info: Fitter is using the Classic Timing Analyzer -Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time. -Info: Starting register packing -Info: Finished register packing - Extra Info: No registers were packed into other blocks -Info: Fitter preparation operations ending: elapsed time is 00:00:00 -Info: Fitter placement preparation operations beginning -Info: Fitter placement preparation operations ending: elapsed time is 00:00:00 -Info: Fitter placement operations beginning -Info: Fitter placement was successful -Info: Fitter placement operations ending: elapsed time is 00:00:00 -Info: Fitter routing operations beginning -Info: Average interconnect usage is 0% of the available device resources - Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y9 -Info: Fitter routing operations ending: elapsed time is 00:00:00 -Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. - Info: Optimizations that may affect the design's routability were skipped - Info: Optimizations that may affect the design's timing were skipped -Info: Started post-fitting delay annotation -Warning: Found 9 output pins without output pin load capacitance assignment - Info: Pin "CO" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "S7" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "S0" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "S1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "S2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "S3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "S4" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "S5" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "S6" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis -Info: Delay annotation completed successfully -Info: Generated suppressed messages file D:/projects/quartus/adder_8b/adder_8b.fit.smsg -Info: Quartus II Fitter was successful. 0 errors, 1 warning - Info: Peak virtual memory: 305 megabytes - Info: Processing ended: Mon Mar 07 11:28:57 2022 - Info: Elapsed time: 00:00:01 - Info: Total CPU time (on all processors): 00:00:01 - - -+----------------------------+ -; Fitter Suppressed Messages ; -+----------------------------+ -The suppressed messages can be found in D:/projects/quartus/adder_8b/adder_8b.fit.smsg. - - diff --git a/adder_8b/adder_8b.fit.smsg b/adder_8b/adder_8b.fit.smsg deleted file mode 100644 index 14764e7..0000000 --- a/adder_8b/adder_8b.fit.smsg +++ /dev/null @@ -1,6 +0,0 @@ -Extra Info: Performing register packing on registers with non-logic cell location assignments -Extra Info: Completed register packing on registers with non-logic cell location assignments -Extra Info: Started Fast Input/Output/OE register processing -Extra Info: Finished Fast Input/Output/OE register processing -Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density -Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/adder_8b/adder_8b.fit.summary b/adder_8b/adder_8b.fit.summary deleted file mode 100644 index b6ffc12..0000000 --- a/adder_8b/adder_8b.fit.summary +++ /dev/null @@ -1,16 +0,0 @@ -Fitter Status : Successful - Mon Mar 07 11:28:57 2022 -Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition -Revision Name : adder_8b -Top-level Entity Name : adder_8b -Family : Cyclone II -Device : EP2C8Q208C8 -Timing Models : Final -Total logic elements : 21 / 8,256 ( < 1 % ) - Total combinational functions : 21 / 8,256 ( < 1 % ) - Dedicated logic registers : 0 / 8,256 ( 0 % ) -Total registers : 0 -Total pins : 26 / 138 ( 19 % ) -Total virtual pins : 0 -Total memory bits : 0 / 165,888 ( 0 % ) -Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % ) -Total PLLs : 0 / 2 ( 0 % ) diff --git a/adder_8b/adder_8b.flow.rpt b/adder_8b/adder_8b.flow.rpt deleted file mode 100644 index 3b89ce5..0000000 --- a/adder_8b/adder_8b.flow.rpt +++ /dev/null @@ -1,121 +0,0 @@ -Flow report for adder_8b -Mon Mar 07 11:28:59 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Flow Summary - 3. Flow Settings - 4. Flow Non-Default Global Settings - 5. Flow Elapsed Time - 6. Flow OS Summary - 7. Flow Log - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------------+ -; Flow Summary ; -+------------------------------------+----------------------------------------------+ -; Flow Status ; Successful - Mon Mar 07 11:28:59 2022 ; -; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; -; Revision Name ; adder_8b ; -; Top-level Entity Name ; adder_8b ; -; Family ; Cyclone II ; -; Device ; EP2C8Q208C8 ; -; Timing Models ; Final ; -; Met timing requirements ; Yes ; -; Total logic elements ; 21 / 8,256 ( < 1 % ) ; -; Total combinational functions ; 21 / 8,256 ( < 1 % ) ; -; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ; -; Total registers ; 0 ; -; Total pins ; 26 / 138 ( 19 % ) ; -; Total virtual pins ; 0 ; -; Total memory bits ; 0 / 165,888 ( 0 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; -; Total PLLs ; 0 / 2 ( 0 % ) ; -+------------------------------------+----------------------------------------------+ - - -+-----------------------------------------+ -; Flow Settings ; -+-------------------+---------------------+ -; Option ; Setting ; -+-------------------+---------------------+ -; Start date & time ; 03/07/2022 11:28:55 ; -; Main task ; Compilation ; -; Revision Name ; adder_8b ; -+-------------------+---------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Flow Non-Default Global Settings ; -+------------------------------------+-------------------------------------------+---------------+-------------+----------------+ -; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; -+------------------------------------+-------------------------------------------+---------------+-------------+----------------+ -; COMPILER_SIGNATURE_ID ; 220283517943889.164662373514744 ; -- ; -- ; -- ; -; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; -; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; -; MISC_FILE ; D:/projects/quartus/adder_8b/adder_8b.dpf ; -- ; -- ; -- ; -; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; -; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; -; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ; -+------------------------------------+-------------------------------------------+---------------+-------------+----------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Flow Elapsed Time ; -+-------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; -+-------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 246 MB ; 00:00:00 ; -; Fitter ; 00:00:01 ; 1.0 ; 305 MB ; 00:00:01 ; -; Assembler ; 00:00:00 ; 1.0 ; 242 MB ; 00:00:00 ; -; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 199 MB ; 00:00:00 ; -; Total ; 00:00:02 ; -- ; -- ; 00:00:01 ; -+-------------------------+--------------+-------------------------+---------------------+------------------------------------+ - - -+------------------------------------------------------------------------------------------+ -; Flow OS Summary ; -+-------------------------+------------------+---------------+------------+----------------+ -; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; -+-------------------------+------------------+---------------+------------+----------------+ -; Analysis & Synthesis ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; -; Fitter ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; -; Assembler ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; -; Classic Timing Analyzer ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; -+-------------------------+------------------+---------------+------------+----------------+ - - ------------- -; Flow Log ; ------------- -quartus_map --read_settings_files=on --write_settings_files=off adder_8b -c adder_8b -quartus_fit --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b -quartus_asm --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b -quartus_tan --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b --timing_analysis_only - - - diff --git a/adder_8b/adder_8b.map.rpt b/adder_8b/adder_8b.map.rpt deleted file mode 100644 index 9c6e794..0000000 --- a/adder_8b/adder_8b.map.rpt +++ /dev/null @@ -1,240 +0,0 @@ -Analysis & Synthesis report for adder_8b -Mon Mar 07 11:28:55 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Analysis & Synthesis Summary - 3. Analysis & Synthesis Settings - 4. Analysis & Synthesis Source Files Read - 5. Analysis & Synthesis Resource Usage Summary - 6. Analysis & Synthesis Resource Utilization by Entity - 7. General Register Statistics - 8. Analysis & Synthesis Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------------+ -; Analysis & Synthesis Summary ; -+------------------------------------+----------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Mon Mar 07 11:28:55 2022 ; -; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; -; Revision Name ; adder_8b ; -; Top-level Entity Name ; adder_8b ; -; Family ; Cyclone II ; -; Total logic elements ; 21 ; -; Total combinational functions ; 21 ; -; Dedicated logic registers ; 0 ; -; Total registers ; 0 ; -; Total pins ; 26 ; -; Total virtual pins ; 0 ; -; Total memory bits ; 0 ; -; Embedded Multiplier 9-bit elements ; 0 ; -; Total PLLs ; 0 ; -+------------------------------------+----------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Settings ; -+--------------------------------------------------------------+--------------------+--------------------+ -; Option ; Setting ; Default Value ; -+--------------------------------------------------------------+--------------------+--------------------+ -; Device ; EP2C8Q208C8 ; ; -; Top-level entity name ; adder_8b ; adder_8b ; -; Family name ; Cyclone II ; Stratix II ; -; Use Generated Physical Constraints File ; Off ; ; -; Use smart compilation ; Off ; Off ; -; Restructure Multiplexers ; Auto ; Auto ; -; Create Debugging Nodes for IP Cores ; Off ; Off ; -; Preserve fewer node names ; On ; On ; -; Disable OpenCore Plus hardware evaluation ; Off ; Off ; -; Verilog Version ; Verilog_2001 ; Verilog_2001 ; -; VHDL Version ; VHDL93 ; VHDL93 ; -; State Machine Processing ; Auto ; Auto ; -; Safe State Machine ; Off ; Off ; -; Extract Verilog State Machines ; On ; On ; -; Extract VHDL State Machines ; On ; On ; -; Ignore Verilog initial constructs ; Off ; Off ; -; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; -; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; -; Add Pass-Through Logic to Inferred RAMs ; On ; On ; -; Parallel Synthesis ; Off ; Off ; -; DSP Block Balancing ; Auto ; Auto ; -; NOT Gate Push-Back ; On ; On ; -; Power-Up Don't Care ; On ; On ; -; Remove Redundant Logic Cells ; Off ; Off ; -; Remove Duplicate Registers ; On ; On ; -; Ignore CARRY Buffers ; Off ; Off ; -; Ignore CASCADE Buffers ; Off ; Off ; -; Ignore GLOBAL Buffers ; Off ; Off ; -; Ignore ROW GLOBAL Buffers ; Off ; Off ; -; Ignore LCELL Buffers ; Off ; Off ; -; Ignore SOFT Buffers ; On ; On ; -; Limit AHDL Integers to 32 Bits ; Off ; Off ; -; Optimization Technique ; Balanced ; Balanced ; -; Carry Chain Length ; 70 ; 70 ; -; Auto Carry Chains ; On ; On ; -; Auto Open-Drain Pins ; On ; On ; -; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; -; Auto ROM Replacement ; On ; On ; -; Auto RAM Replacement ; On ; On ; -; Auto Shift Register Replacement ; Auto ; Auto ; -; Auto Clock Enable Replacement ; On ; On ; -; Strict RAM Replacement ; Off ; Off ; -; Allow Synchronous Control Signals ; On ; On ; -; Force Use of Synchronous Clear Signals ; Off ; Off ; -; Auto RAM to Logic Cell Conversion ; Off ; Off ; -; Auto Resource Sharing ; Off ; Off ; -; Allow Any RAM Size For Recognition ; Off ; Off ; -; Allow Any ROM Size For Recognition ; Off ; Off ; -; Allow Any Shift Register Size For Recognition ; Off ; Off ; -; Use LogicLock Constraints during Resource Balancing ; On ; On ; -; Ignore translate_off and synthesis_off directives ; Off ; Off ; -; Timing-Driven Synthesis ; Off ; Off ; -; Show Parameter Settings Tables in Synthesis Report ; On ; On ; -; Ignore Maximum Fan-Out Assignments ; Off ; Off ; -; Synchronization Register Chain Length ; 2 ; 2 ; -; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; -; HDL message level ; Level2 ; Level2 ; -; Suppress Register Optimization Related Messages ; Off ; Off ; -; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ; -; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; -; Clock MUX Protection ; On ; On ; -; Auto Gated Clock Conversion ; Off ; Off ; -; Block Design Naming ; Auto ; Auto ; -; SDC constraint protection ; Off ; Off ; -; Synthesis Effort ; Auto ; Auto ; -; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; -; Analysis & Synthesis Message Level ; Medium ; Medium ; -+--------------------------------------------------------------+--------------------+--------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; -+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------+ -; adder_8b.bdf ; yes ; User Block Diagram/Schematic File ; D:/projects/quartus/adder_8b/adder_8b.bdf ; -; 7400.bdf ; yes ; Megafunction ; d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf ; -; 7486.bdf ; yes ; Megafunction ; d:/altera/90sp2/quartus/libraries/others/maxplus2/7486.bdf ; -+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------+ - - -+--------------------------------------------------------------+ -; Analysis & Synthesis Resource Usage Summary ; -+---------------------------------------------+----------------+ -; Resource ; Usage ; -+---------------------------------------------+----------------+ -; Estimated Total logic elements ; 21 ; -; ; ; -; Total combinational functions ; 21 ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 9 ; -; -- 3 input functions ; 9 ; -; -- <=2 input functions ; 3 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 21 ; -; -- arithmetic mode ; 0 ; -; ; ; -; Total registers ; 0 ; -; -- Dedicated logic registers ; 0 ; -; -- I/O registers ; 0 ; -; ; ; -; I/O pins ; 26 ; -; Maximum fan-out node ; 7400:inst8|4~0 ; -; Maximum fan-out ; 4 ; -; Total fan-out ; 78 ; -; Average fan-out ; 1.66 ; -+---------------------------------------------+----------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Resource Utilization by Entity ; -+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------+--------------+ -; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; -+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------+--------------+ -; |adder_8b ; 21 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 26 ; 0 ; |adder_8b ; work ; -; |7400:inst13| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7400:inst13 ; work ; -; |7400:inst18| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7400:inst18 ; work ; -; |7400:inst23| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7400:inst23 ; work ; -; |7400:inst28| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7400:inst28 ; work ; -; |7400:inst33| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7400:inst33 ; work ; -; |7400:inst38| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7400:inst38 ; work ; -; |7400:inst3| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7400:inst3 ; work ; -; |7400:inst8| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7400:inst8 ; work ; -; |7486:inst10| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7486:inst10 ; work ; -; |7486:inst15| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7486:inst15 ; work ; -; |7486:inst20| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7486:inst20 ; work ; -; |7486:inst25| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7486:inst25 ; work ; -; |7486:inst30| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7486:inst30 ; work ; -; |7486:inst35| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7486:inst35 ; work ; -; |7486:inst40| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7486:inst40 ; work ; -; |7486:inst5| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder_8b|7486:inst5 ; work ; -+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------+--------------+ -Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. - - -+------------------------------------------------------+ -; General Register Statistics ; -+----------------------------------------------+-------+ -; Statistic ; Value ; -+----------------------------------------------+-------+ -; Total registers ; 0 ; -; Number of registers using Synchronous Clear ; 0 ; -; Number of registers using Synchronous Load ; 0 ; -; Number of registers using Asynchronous Clear ; 0 ; -; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 0 ; -; Number of registers using Preset ; 0 ; -+----------------------------------------------+-------+ - - -+-------------------------------+ -; Analysis & Synthesis Messages ; -+-------------------------------+ -Info: ******************************************************************* -Info: Running Quartus II Analysis & Synthesis - Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Mon Mar 07 11:28:54 2022 -Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adder_8b -c adder_8b -Info: Found 1 design units, including 1 entities, in source file adder_8b.bdf - Info: Found entity 1: adder_8b -Info: Elaborating entity "adder_8b" for the top level hierarchy -Info: Elaborating entity "7400" for hierarchy "7400:inst38" -Info: Elaborated megafunction instantiation "7400:inst38" -Info: Elaborating entity "7486" for hierarchy "7486:inst" -Info: Elaborated megafunction instantiation "7486:inst" -Info: Implemented 47 device resources after synthesis - the final resource count might be different - Info: Implemented 17 input pins - Info: Implemented 9 output pins - Info: Implemented 21 logic cells -Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 250 megabytes - Info: Processing ended: Mon Mar 07 11:28:55 2022 - Info: Elapsed time: 00:00:01 - Info: Total CPU time (on all processors): 00:00:01 - - diff --git a/adder_8b/adder_8b.map.summary b/adder_8b/adder_8b.map.summary deleted file mode 100644 index cdd9d47..0000000 --- a/adder_8b/adder_8b.map.summary +++ /dev/null @@ -1,14 +0,0 @@ -Analysis & Synthesis Status : Successful - Mon Mar 07 11:28:55 2022 -Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition -Revision Name : adder_8b -Top-level Entity Name : adder_8b -Family : Cyclone II -Total logic elements : 21 - Total combinational functions : 21 - Dedicated logic registers : 0 -Total registers : 0 -Total pins : 26 -Total virtual pins : 0 -Total memory bits : 0 -Embedded Multiplier 9-bit elements : 0 -Total PLLs : 0 diff --git a/adder_8b/adder_8b.pin b/adder_8b/adder_8b.pin deleted file mode 100644 index 55a9646..0000000 --- a/adder_8b/adder_8b.pin +++ /dev/null @@ -1,278 +0,0 @@ - -- Copyright (C) 1991-2009 Altera Corporation - -- Your use of Altera Corporation's design tools, logic functions - -- and other software and tools, and its AMPP partner logic - -- functions, and any output files from any of the foregoing - -- (including device programming or simulation files), and any - -- associated documentation or information are expressly subject - -- to the terms and conditions of the Altera Program License - -- Subscription Agreement, Altera MegaCore Function License - -- Agreement, or other applicable license agreement, including, - -- without limitation, that your use is for the sole purpose of - -- programming logic devices manufactured by Altera and sold by - -- Altera or its authorized distributors. Please refer to the - -- applicable agreement for further details. - -- - -- This is a Quartus II output file. It is for reporting purposes only, and is - -- not intended for use as a Quartus II input file. This file cannot be used - -- to make Quartus II pin assignments - for instructions on how to make pin - -- assignments, please see Quartus II help. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- NC : No Connect. This pin has no internal connection to the device. - -- DNU : Do Not Use. This pin MUST NOT be connected. - -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). - -- VCCIO : Dedicated power pin, which MUST be connected to VCC - -- of its bank. - -- Bank 1: 3.3V - -- Bank 2: 3.3V - -- Bank 3: 3.3V - -- Bank 4: 3.3V - -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. - -- It can also be used to report unused dedicated pins. The connection - -- on the board for unused dedicated pins depends on whether this will - -- be used in a future design. One example is device migration. When - -- using device migration, refer to the device pin-tables. If it is a - -- GND pin in the pin table or if it will not be used in a future design - -- for another purpose the it MUST be connected to GND. If it is an unused - -- dedicated pin, then it can be connected to a valid signal on the board - -- (low, high, or toggling) if that signal is required for a different - -- revision of the design. - -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. - -- This pin should be connected to GND. It may also be connected to a - -- valid signal on the board (low, high, or toggling) if that signal - -- is required for a different revision of the design. - -- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17), - -- connect each pin marked GND* either individually through a 10k Ohm resistor - -- to GND or tie all pins together and connect through a single 10k Ohm resistor - -- to GND. - -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND - -- or leave it unconnected. - -- RESERVED : Unused I/O pin, which MUST be left unconnected. - -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. - -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. - -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. - -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- Pin directions (input, output or bidir) are based on device operating in user mode. - --------------------------------------------------------------------------------- - -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition -CHIP "adder_8b" ASSIGNED TO AN: EP2C8Q208C8 - -Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment -------------------------------------------------------------------------------------------------------------- -~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVTTL : : 1 : N -~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVTTL : : 1 : N -RESERVED_INPUT : 3 : : : : 1 : -RESERVED_INPUT : 4 : : : : 1 : -RESERVED_INPUT : 5 : : : : 1 : -RESERVED_INPUT : 6 : : : : 1 : -VCCIO1 : 7 : power : : 3.3V : 1 : -RESERVED_INPUT : 8 : : : : 1 : -GND : 9 : gnd : : : : -RESERVED_INPUT : 10 : : : : 1 : -RESERVED_INPUT : 11 : : : : 1 : -RESERVED_INPUT : 12 : : : : 1 : -RESERVED_INPUT : 13 : : : : 1 : -RESERVED_INPUT : 14 : : : : 1 : -RESERVED_INPUT : 15 : : : : 1 : -TDO : 16 : output : : : 1 : -TMS : 17 : input : : : 1 : -TCK : 18 : input : : : 1 : -TDI : 19 : input : : : 1 : -DATA0 : 20 : input : : : 1 : -DCLK : 21 : : : : 1 : -nCE : 22 : : : : 1 : -CI : 23 : input : 3.3-V LVTTL : : 1 : Y -GND+ : 24 : : : : 1 : -GND : 25 : gnd : : : : -nCONFIG : 26 : : : : 1 : -GND+ : 27 : : : : 1 : -GND+ : 28 : : : : 1 : -VCCIO1 : 29 : power : : 3.3V : 1 : -RESERVED_INPUT : 30 : : : : 1 : -RESERVED_INPUT : 31 : : : : 1 : -VCCINT : 32 : power : : 1.2V : : -RESERVED_INPUT : 33 : : : : 1 : -RESERVED_INPUT : 34 : : : : 1 : -RESERVED_INPUT : 35 : : : : 1 : -GND : 36 : gnd : : : : -RESERVED_INPUT : 37 : : : : 1 : -GND : 38 : gnd : : : : -RESERVED_INPUT : 39 : : : : 1 : -RESERVED_INPUT : 40 : : : : 1 : -RESERVED_INPUT : 41 : : : : 1 : -VCCIO1 : 42 : power : : 3.3V : 1 : -RESERVED_INPUT : 43 : : : : 1 : -RESERVED_INPUT : 44 : : : : 1 : -RESERVED_INPUT : 45 : : : : 1 : -RESERVED_INPUT : 46 : : : : 1 : -RESERVED_INPUT : 47 : : : : 1 : -RESERVED_INPUT : 48 : : : : 1 : -GND : 49 : gnd : : : : -GND_PLL1 : 50 : gnd : : : : -VCCD_PLL1 : 51 : power : : 1.2V : : -GND_PLL1 : 52 : gnd : : : : -VCCA_PLL1 : 53 : power : : 1.2V : : -GNDA_PLL1 : 54 : gnd : : : : -GND : 55 : gnd : : : : -RESERVED_INPUT : 56 : : : : 4 : -RESERVED_INPUT : 57 : : : : 4 : -RESERVED_INPUT : 58 : : : : 4 : -RESERVED_INPUT : 59 : : : : 4 : -RESERVED_INPUT : 60 : : : : 4 : -RESERVED_INPUT : 61 : : : : 4 : -VCCIO4 : 62 : power : : 3.3V : 4 : -RESERVED_INPUT : 63 : : : : 4 : -RESERVED_INPUT : 64 : : : : 4 : -GND : 65 : gnd : : : : -VCCINT : 66 : power : : 1.2V : : -B0 : 67 : input : 3.3-V LVTTL : : 4 : Y -B1 : 68 : input : 3.3-V LVTTL : : 4 : Y -B2 : 69 : input : 3.3-V LVTTL : : 4 : Y -B3 : 70 : input : 3.3-V LVTTL : : 4 : Y -VCCIO4 : 71 : power : : 3.3V : 4 : -B4 : 72 : input : 3.3-V LVTTL : : 4 : Y -GND : 73 : gnd : : : : -B5 : 74 : input : 3.3-V LVTTL : : 4 : Y -B6 : 75 : input : 3.3-V LVTTL : : 4 : Y -B7 : 76 : input : 3.3-V LVTTL : : 4 : Y -A0 : 77 : input : 3.3-V LVTTL : : 4 : Y -GND : 78 : gnd : : : : -VCCINT : 79 : power : : 1.2V : : -A1 : 80 : input : 3.3-V LVTTL : : 4 : Y -A2 : 81 : input : 3.3-V LVTTL : : 4 : Y -A3 : 82 : input : 3.3-V LVTTL : : 4 : Y -VCCIO4 : 83 : power : : 3.3V : 4 : -A4 : 84 : input : 3.3-V LVTTL : : 4 : Y -GND : 85 : gnd : : : : -A5 : 86 : input : 3.3-V LVTTL : : 4 : Y -A6 : 87 : input : 3.3-V LVTTL : : 4 : Y -A7 : 88 : input : 3.3-V LVTTL : : 4 : Y -RESERVED_INPUT : 89 : : : : 4 : -RESERVED_INPUT : 90 : : : : 4 : -VCCIO4 : 91 : power : : 3.3V : 4 : -RESERVED_INPUT : 92 : : : : 4 : -GND : 93 : gnd : : : : -RESERVED_INPUT : 94 : : : : 4 : -RESERVED_INPUT : 95 : : : : 4 : -RESERVED_INPUT : 96 : : : : 4 : -RESERVED_INPUT : 97 : : : : 4 : -VCCIO4 : 98 : power : : 3.3V : 4 : -RESERVED_INPUT : 99 : : : : 4 : -GND : 100 : gnd : : : : -RESERVED_INPUT : 101 : : : : 4 : -RESERVED_INPUT : 102 : : : : 4 : -RESERVED_INPUT : 103 : : : : 4 : -RESERVED_INPUT : 104 : : : : 4 : -RESERVED_INPUT : 105 : : : : 3 : -RESERVED_INPUT : 106 : : : : 3 : -RESERVED_INPUT : 107 : : : : 3 : -~LVDS54p/nCEO~ : 108 : output : 3.3-V LVTTL : : 3 : N -VCCIO3 : 109 : power : : 3.3V : 3 : -RESERVED_INPUT : 110 : : : : 3 : -GND : 111 : gnd : : : : -RESERVED_INPUT : 112 : : : : 3 : -RESERVED_INPUT : 113 : : : : 3 : -RESERVED_INPUT : 114 : : : : 3 : -RESERVED_INPUT : 115 : : : : 3 : -RESERVED_INPUT : 116 : : : : 3 : -RESERVED_INPUT : 117 : : : : 3 : -RESERVED_INPUT : 118 : : : : 3 : -GND : 119 : gnd : : : : -VCCINT : 120 : power : : 1.2V : : -nSTATUS : 121 : : : : 3 : -VCCIO3 : 122 : power : : 3.3V : 3 : -CONF_DONE : 123 : : : : 3 : -GND : 124 : gnd : : : : -MSEL1 : 125 : : : : 3 : -MSEL0 : 126 : : : : 3 : -RESERVED_INPUT : 127 : : : : 3 : -RESERVED_INPUT : 128 : : : : 3 : -GND+ : 129 : : : : 3 : -GND+ : 130 : : : : 3 : -GND+ : 131 : : : : 3 : -GND+ : 132 : : : : 3 : -RESERVED_INPUT : 133 : : : : 3 : -RESERVED_INPUT : 134 : : : : 3 : -RESERVED_INPUT : 135 : : : : 3 : -VCCIO3 : 136 : power : : 3.3V : 3 : -RESERVED_INPUT : 137 : : : : 3 : -RESERVED_INPUT : 138 : : : : 3 : -RESERVED_INPUT : 139 : : : : 3 : -GND : 140 : gnd : : : : -RESERVED_INPUT : 141 : : : : 3 : -S0 : 142 : output : 3.3-V LVTTL : : 3 : Y -S1 : 143 : output : 3.3-V LVTTL : : 3 : Y -S2 : 144 : output : 3.3-V LVTTL : : 3 : Y -S3 : 145 : output : 3.3-V LVTTL : : 3 : Y -S4 : 146 : output : 3.3-V LVTTL : : 3 : Y -S5 : 147 : output : 3.3-V LVTTL : : 3 : Y -VCCIO3 : 148 : power : : 3.3V : 3 : -S6 : 149 : output : 3.3-V LVTTL : : 3 : Y -S7 : 150 : output : 3.3-V LVTTL : : 3 : Y -CO : 151 : output : 3.3-V LVTTL : : 3 : Y -RESERVED_INPUT : 152 : : : : 3 : -GND : 153 : gnd : : : : -GND_PLL2 : 154 : gnd : : : : -VCCD_PLL2 : 155 : power : : 1.2V : : -GND_PLL2 : 156 : gnd : : : : -VCCA_PLL2 : 157 : power : : 1.2V : : -GNDA_PLL2 : 158 : gnd : : : : -GND : 159 : gnd : : : : -RESERVED_INPUT : 160 : : : : 2 : -RESERVED_INPUT : 161 : : : : 2 : -RESERVED_INPUT : 162 : : : : 2 : -RESERVED_INPUT : 163 : : : : 2 : -RESERVED_INPUT : 164 : : : : 2 : -RESERVED_INPUT : 165 : : : : 2 : -VCCIO2 : 166 : power : : 3.3V : 2 : -GND : 167 : gnd : : : : -RESERVED_INPUT : 168 : : : : 2 : -RESERVED_INPUT : 169 : : : : 2 : -RESERVED_INPUT : 170 : : : : 2 : -RESERVED_INPUT : 171 : : : : 2 : -VCCIO2 : 172 : power : : 3.3V : 2 : -RESERVED_INPUT : 173 : : : : 2 : -GND : 174 : gnd : : : : -RESERVED_INPUT : 175 : : : : 2 : -RESERVED_INPUT : 176 : : : : 2 : -GND : 177 : gnd : : : : -VCCINT : 178 : power : : 1.2V : : -RESERVED_INPUT : 179 : : : : 2 : -RESERVED_INPUT : 180 : : : : 2 : -RESERVED_INPUT : 181 : : : : 2 : -RESERVED_INPUT : 182 : : : : 2 : -VCCIO2 : 183 : power : : 3.3V : 2 : -GND : 184 : gnd : : : : -RESERVED_INPUT : 185 : : : : 2 : -GND : 186 : gnd : : : : -RESERVED_INPUT : 187 : : : : 2 : -RESERVED_INPUT : 188 : : : : 2 : -RESERVED_INPUT : 189 : : : : 2 : -VCCINT : 190 : power : : 1.2V : : -RESERVED_INPUT : 191 : : : : 2 : -RESERVED_INPUT : 192 : : : : 2 : -RESERVED_INPUT : 193 : : : : 2 : -VCCIO2 : 194 : power : : 3.3V : 2 : -RESERVED_INPUT : 195 : : : : 2 : -GND : 196 : gnd : : : : -RESERVED_INPUT : 197 : : : : 2 : -RESERVED_INPUT : 198 : : : : 2 : -RESERVED_INPUT : 199 : : : : 2 : -RESERVED_INPUT : 200 : : : : 2 : -RESERVED_INPUT : 201 : : : : 2 : -VCCIO2 : 202 : power : : 3.3V : 2 : -RESERVED_INPUT : 203 : : : : 2 : -GND : 204 : gnd : : : : -RESERVED_INPUT : 205 : : : : 2 : -RESERVED_INPUT : 206 : : : : 2 : -RESERVED_INPUT : 207 : : : : 2 : -RESERVED_INPUT : 208 : : : : 2 : diff --git a/adder_8b/adder_8b.pof b/adder_8b/adder_8b.pof deleted file mode 100644 index 16bf68f..0000000 Binary files a/adder_8b/adder_8b.pof and /dev/null differ diff --git a/adder_8b/adder_8b.qws b/adder_8b/adder_8b.qws deleted file mode 100644 index 9b540c2..0000000 --- a/adder_8b/adder_8b.qws +++ /dev/null @@ -1,14 +0,0 @@ -[ProjectWorkspace] -ptn_Child1=Frames -[ProjectWorkspace.Frames] -ptn_Child1=ChildFrames -[ProjectWorkspace.Frames.ChildFrames] -ptn_Child1=Document-0 -[ProjectWorkspace.Frames.ChildFrames.Document-0] -ptn_Child1=ViewFrame-0 -[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0] -DocPathName=adder_8b.bdf -DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde} -IsChildFrameDetached=False -IsActiveChildFrame=True -ptn_Child1=StateMap diff --git a/adder_8b/adder_8b.sof b/adder_8b/adder_8b.sof deleted file mode 100644 index 18edc05..0000000 Binary files a/adder_8b/adder_8b.sof and /dev/null differ diff --git a/adder_8b/adder_8b.tan.rpt b/adder_8b/adder_8b.tan.rpt deleted file mode 100644 index 8d0407b..0000000 --- a/adder_8b/adder_8b.tan.rpt +++ /dev/null @@ -1,229 +0,0 @@ -Classic Timing Analyzer report for adder_8b -Mon Mar 07 11:28:59 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Timing Analyzer Summary - 3. Timing Analyzer Settings - 4. Parallel Compilation - 5. tpd - 6. Timing Analyzer Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------------------------------------------------+ -; Timing Analyzer Summary ; -+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ -; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; -+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ -; Worst-case tpd ; N/A ; None ; 22.018 ns ; B0 ; CO ; -- ; -- ; 0 ; -; Total number of failed paths ; ; ; ; ; ; ; ; 0 ; -+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ - - -+--------------------------------------------------------------------------------------------------------------------+ -; Timing Analyzer Settings ; -+---------------------------------------------------------------------+--------------------+------+----+-------------+ -; Option ; Setting ; From ; To ; Entity Name ; -+---------------------------------------------------------------------+--------------------+------+----+-------------+ -; Device Name ; EP2C8Q208C8 ; ; ; ; -; Timing Models ; Final ; ; ; ; -; Default hold multicycle ; Same as Multicycle ; ; ; ; -; Cut paths between unrelated clock domains ; On ; ; ; ; -; Cut off read during write signal paths ; On ; ; ; ; -; Cut off feedback from I/O pins ; On ; ; ; ; -; Report Combined Fast/Slow Timing ; Off ; ; ; ; -; Ignore Clock Settings ; Off ; ; ; ; -; Analyze latches as synchronous elements ; On ; ; ; ; -; Enable Recovery/Removal analysis ; Off ; ; ; ; -; Enable Clock Latency ; Off ; ; ; ; -; Use TimeQuest Timing Analyzer ; Off ; ; ; ; -; Minimum Core Junction Temperature ; 0 ; ; ; ; -; Maximum Core Junction Temperature ; 85 ; ; ; ; -; Number of source nodes to report per destination node ; 10 ; ; ; ; -; Number of destination nodes to report ; 10 ; ; ; ; -; Number of paths to report ; 200 ; ; ; ; -; Report Minimum Timing Checks ; Off ; ; ; ; -; Use Fast Timing Models ; Off ; ; ; ; -; Report IO Paths Separately ; Off ; ; ; ; -; Perform Multicorner Analysis ; On ; ; ; ; -; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ; -; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ; -; Output I/O Timing Endpoint ; Near End ; ; ; ; -+---------------------------------------------------------------------+--------------------+------+----+-------------+ - - -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 4 ; -; Maximum allowed ; 4 ; -; ; ; -; Average used ; 1.00 ; -; Maximum used ; 1 ; -; ; ; -; Usage by Processor ; % Time Used ; -; 1 processor ; 100.0% ; -; 2-4 processors ; 0.0% ; -+----------------------------+-------------+ - - -+---------------------------------------------------------+ -; tpd ; -+-------+-------------------+-----------------+------+----+ -; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ; -+-------+-------------------+-----------------+------+----+ -; N/A ; None ; 22.018 ns ; B0 ; CO ; -; N/A ; None ; 21.780 ns ; B0 ; S7 ; -; N/A ; None ; 21.052 ns ; B1 ; CO ; -; N/A ; None ; 20.864 ns ; A0 ; CO ; -; N/A ; None ; 20.814 ns ; B1 ; S7 ; -; N/A ; None ; 20.626 ns ; A0 ; S7 ; -; N/A ; None ; 20.579 ns ; A1 ; CO ; -; N/A ; None ; 20.442 ns ; B0 ; S6 ; -; N/A ; None ; 20.341 ns ; A1 ; S7 ; -; N/A ; None ; 20.259 ns ; B2 ; CO ; -; N/A ; None ; 20.021 ns ; B2 ; S7 ; -; N/A ; None ; 19.812 ns ; A2 ; CO ; -; N/A ; None ; 19.574 ns ; A2 ; S7 ; -; N/A ; None ; 19.476 ns ; B1 ; S6 ; -; N/A ; None ; 19.288 ns ; A0 ; S6 ; -; N/A ; None ; 19.089 ns ; B0 ; S5 ; -; N/A ; None ; 19.003 ns ; A1 ; S6 ; -; N/A ; None ; 18.831 ns ; B3 ; CO ; -; N/A ; None ; 18.728 ns ; A3 ; CO ; -; N/A ; None ; 18.683 ns ; B2 ; S6 ; -; N/A ; None ; 18.593 ns ; B3 ; S7 ; -; N/A ; None ; 18.490 ns ; A3 ; S7 ; -; N/A ; None ; 18.303 ns ; B0 ; S4 ; -; N/A ; None ; 18.291 ns ; A4 ; CO ; -; N/A ; None ; 18.236 ns ; A2 ; S6 ; -; N/A ; None ; 18.123 ns ; B1 ; S5 ; -; N/A ; None ; 18.053 ns ; A4 ; S7 ; -; N/A ; None ; 17.935 ns ; A0 ; S5 ; -; N/A ; None ; 17.650 ns ; A1 ; S5 ; -; N/A ; None ; 17.587 ns ; B4 ; CO ; -; N/A ; None ; 17.447 ns ; CI ; CO ; -; N/A ; None ; 17.370 ns ; B0 ; S3 ; -; N/A ; None ; 17.349 ns ; B4 ; S7 ; -; N/A ; None ; 17.337 ns ; B1 ; S4 ; -; N/A ; None ; 17.330 ns ; B2 ; S5 ; -; N/A ; None ; 17.255 ns ; B3 ; S6 ; -; N/A ; None ; 17.209 ns ; CI ; S7 ; -; N/A ; None ; 17.202 ns ; A5 ; CO ; -; N/A ; None ; 17.152 ns ; A3 ; S6 ; -; N/A ; None ; 17.149 ns ; A0 ; S4 ; -; N/A ; None ; 16.987 ns ; B5 ; CO ; -; N/A ; None ; 16.964 ns ; A5 ; S7 ; -; N/A ; None ; 16.883 ns ; A2 ; S5 ; -; N/A ; None ; 16.864 ns ; A1 ; S4 ; -; N/A ; None ; 16.749 ns ; B5 ; S7 ; -; N/A ; None ; 16.715 ns ; A4 ; S6 ; -; N/A ; None ; 16.544 ns ; B2 ; S4 ; -; N/A ; None ; 16.404 ns ; B1 ; S3 ; -; N/A ; None ; 16.306 ns ; B0 ; S2 ; -; N/A ; None ; 16.216 ns ; A0 ; S3 ; -; N/A ; None ; 16.097 ns ; A2 ; S4 ; -; N/A ; None ; 16.011 ns ; B4 ; S6 ; -; N/A ; None ; 15.931 ns ; A1 ; S3 ; -; N/A ; None ; 15.902 ns ; B3 ; S5 ; -; N/A ; None ; 15.871 ns ; CI ; S6 ; -; N/A ; None ; 15.799 ns ; A3 ; S5 ; -; N/A ; None ; 15.626 ns ; A5 ; S6 ; -; N/A ; None ; 15.611 ns ; B2 ; S3 ; -; N/A ; None ; 15.411 ns ; B5 ; S6 ; -; N/A ; None ; 15.366 ns ; A4 ; S5 ; -; N/A ; None ; 15.340 ns ; B1 ; S2 ; -; N/A ; None ; 15.164 ns ; A2 ; S3 ; -; N/A ; None ; 15.152 ns ; A0 ; S2 ; -; N/A ; None ; 15.116 ns ; B3 ; S4 ; -; N/A ; None ; 15.042 ns ; B6 ; CO ; -; N/A ; None ; 15.013 ns ; A3 ; S4 ; -; N/A ; None ; 14.892 ns ; B0 ; S1 ; -; N/A ; None ; 14.867 ns ; A1 ; S2 ; -; N/A ; None ; 14.804 ns ; B6 ; S7 ; -; N/A ; None ; 14.658 ns ; B4 ; S5 ; -; N/A ; None ; 14.543 ns ; B2 ; S2 ; -; N/A ; None ; 14.518 ns ; CI ; S5 ; -; N/A ; None ; 14.282 ns ; A5 ; S5 ; -; N/A ; None ; 14.173 ns ; B3 ; S3 ; -; N/A ; None ; 14.162 ns ; B0 ; S0 ; -; N/A ; None ; 14.098 ns ; A2 ; S2 ; -; N/A ; None ; 14.088 ns ; A4 ; S4 ; -; N/A ; None ; 14.077 ns ; A3 ; S3 ; -; N/A ; None ; 14.063 ns ; B5 ; S5 ; -; N/A ; None ; 14.043 ns ; B7 ; CO ; -; N/A ; None ; 13.974 ns ; A6 ; CO ; -; N/A ; None ; 13.933 ns ; B1 ; S1 ; -; N/A ; None ; 13.865 ns ; B4 ; S4 ; -; N/A ; None ; 13.816 ns ; B7 ; S7 ; -; N/A ; None ; 13.738 ns ; A0 ; S1 ; -; N/A ; None ; 13.736 ns ; A6 ; S7 ; -; N/A ; None ; 13.732 ns ; CI ; S4 ; -; N/A ; None ; 13.470 ns ; A1 ; S1 ; -; N/A ; None ; 13.462 ns ; B6 ; S6 ; -; N/A ; None ; 13.415 ns ; A7 ; CO ; -; N/A ; None ; 13.184 ns ; A7 ; S7 ; -; N/A ; None ; 13.004 ns ; A0 ; S0 ; -; N/A ; None ; 12.799 ns ; CI ; S3 ; -; N/A ; None ; 12.403 ns ; A6 ; S6 ; -; N/A ; None ; 11.735 ns ; CI ; S2 ; -; N/A ; None ; 10.321 ns ; CI ; S1 ; -; N/A ; None ; 9.587 ns ; CI ; S0 ; -+-------+-------------------+-----------------+------+----+ - - -+--------------------------+ -; Timing Analyzer Messages ; -+--------------------------+ -Info: ******************************************************************* -Info: Running Quartus II Classic Timing Analyzer - Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Mon Mar 07 11:28:59 2022 -Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b --timing_analysis_only -Info: Parallel compilation is enabled and will use 4 of the 4 processors detected -Info: Longest tpd from source pin "B0" to destination pin "CO" is 22.018 ns - Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 2; PIN Node = 'B0' - Info: 2: + IC(6.491 ns) + CELL(0.624 ns) = 8.109 ns; Loc. = LCCOMB_X18_Y4_N2; Fanout = 2; COMB Node = '7400:inst3|4~1' - Info: 3: + IC(0.373 ns) + CELL(0.624 ns) = 9.106 ns; Loc. = LCCOMB_X18_Y4_N20; Fanout = 4; COMB Node = '7400:inst8|4~0' - Info: 4: + IC(0.407 ns) + CELL(0.370 ns) = 9.883 ns; Loc. = LCCOMB_X18_Y4_N16; Fanout = 2; COMB Node = '7400:inst13|4~1' - Info: 5: + IC(0.426 ns) + CELL(0.650 ns) = 10.959 ns; Loc. = LCCOMB_X18_Y4_N12; Fanout = 2; COMB Node = '7400:inst18|4~0' - Info: 6: + IC(0.408 ns) + CELL(0.650 ns) = 12.017 ns; Loc. = LCCOMB_X18_Y4_N30; Fanout = 2; COMB Node = '7400:inst23|4~9' - Info: 7: + IC(0.365 ns) + CELL(0.206 ns) = 12.588 ns; Loc. = LCCOMB_X18_Y4_N0; Fanout = 3; COMB Node = '7400:inst28|4~0' - Info: 8: + IC(2.636 ns) + CELL(0.370 ns) = 15.594 ns; Loc. = LCCOMB_X28_Y11_N26; Fanout = 2; COMB Node = '7400:inst33|4~1' - Info: 9: + IC(0.370 ns) + CELL(0.624 ns) = 16.588 ns; Loc. = LCCOMB_X28_Y11_N12; Fanout = 1; COMB Node = '7400:inst38|4~0' - Info: 10: + IC(2.150 ns) + CELL(3.280 ns) = 22.018 ns; Loc. = PIN_151; Fanout = 0; PIN Node = 'CO' - Info: Total cell delay = 8.392 ns ( 38.11 % ) - Info: Total interconnect delay = 13.626 ns ( 61.89 % ) -Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 213 megabytes - Info: Processing ended: Mon Mar 07 11:28:59 2022 - Info: Elapsed time: 00:00:00 - Info: Total CPU time (on all processors): 00:00:00 - - diff --git a/adder_8b/adder_8b.tan.summary b/adder_8b/adder_8b.tan.summary deleted file mode 100644 index 31339f3..0000000 --- a/adder_8b/adder_8b.tan.summary +++ /dev/null @@ -1,26 +0,0 @@ --------------------------------------------------------------------------------------- -Timing Analyzer Summary --------------------------------------------------------------------------------------- - -Type : Worst-case tpd -Slack : N/A -Required Time : None -Actual Time : 22.018 ns -From : B0 -To : CO -From Clock : -- -To Clock : -- -Failed Paths : 0 - -Type : Total number of failed paths -Slack : -Required Time : -Actual Time : -From : -To : -From Clock : -To Clock : -Failed Paths : 0 - --------------------------------------------------------------------------------------- - diff --git a/adder_8b/db/adder_8b.(0).cnf.cdb b/adder_8b/db/adder_8b.(0).cnf.cdb deleted file mode 100644 index 319fe50..0000000 Binary files a/adder_8b/db/adder_8b.(0).cnf.cdb and /dev/null differ diff --git a/adder_8b/db/adder_8b.(0).cnf.hdb b/adder_8b/db/adder_8b.(0).cnf.hdb deleted file mode 100644 index 6e2e7e6..0000000 Binary files a/adder_8b/db/adder_8b.(0).cnf.hdb and /dev/null differ diff --git a/adder_8b/db/adder_8b.(1).cnf.cdb b/adder_8b/db/adder_8b.(1).cnf.cdb deleted file mode 100644 index 30a8556..0000000 Binary files a/adder_8b/db/adder_8b.(1).cnf.cdb and /dev/null differ diff --git a/adder_8b/db/adder_8b.(1).cnf.hdb b/adder_8b/db/adder_8b.(1).cnf.hdb deleted file mode 100644 index 4795141..0000000 Binary files a/adder_8b/db/adder_8b.(1).cnf.hdb and /dev/null differ diff --git a/adder_8b/db/adder_8b.(2).cnf.cdb b/adder_8b/db/adder_8b.(2).cnf.cdb deleted file mode 100644 index 7623026..0000000 Binary files a/adder_8b/db/adder_8b.(2).cnf.cdb and /dev/null differ diff --git a/adder_8b/db/adder_8b.(2).cnf.hdb b/adder_8b/db/adder_8b.(2).cnf.hdb deleted file mode 100644 index 6ee954e..0000000 Binary files a/adder_8b/db/adder_8b.(2).cnf.hdb and /dev/null differ diff --git a/adder_8b/db/adder_8b.asm.qmsg b/adder_8b/db/adder_8b.asm.qmsg deleted file mode 100644 index 25f2d0b..0000000 --- a/adder_8b/db/adder_8b.asm.qmsg +++ /dev/null @@ -1,7 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:28:58 2022 " "Info: Processing started: Mon Mar 07 11:28:58 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1} -{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "242 " "Info: Peak virtual memory: 242 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:28:58 2022 " "Info: Processing ended: Mon Mar 07 11:28:58 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/adder_8b/db/adder_8b.asm_labs.ddb b/adder_8b/db/adder_8b.asm_labs.ddb deleted file mode 100644 index b001fb6..0000000 Binary files a/adder_8b/db/adder_8b.asm_labs.ddb and /dev/null differ diff --git a/adder_8b/db/adder_8b.cbx.xml b/adder_8b/db/adder_8b.cbx.xml deleted file mode 100644 index baec309..0000000 --- a/adder_8b/db/adder_8b.cbx.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/adder_8b/db/adder_8b.cmp.bpm b/adder_8b/db/adder_8b.cmp.bpm deleted file mode 100644 index 333f8e9..0000000 Binary files a/adder_8b/db/adder_8b.cmp.bpm and /dev/null differ diff --git a/adder_8b/db/adder_8b.cmp.cdb b/adder_8b/db/adder_8b.cmp.cdb deleted file mode 100644 index c5c753f..0000000 Binary files a/adder_8b/db/adder_8b.cmp.cdb and /dev/null differ diff --git a/adder_8b/db/adder_8b.cmp.ecobp b/adder_8b/db/adder_8b.cmp.ecobp deleted file mode 100644 index e05efff..0000000 Binary files a/adder_8b/db/adder_8b.cmp.ecobp and /dev/null differ diff --git a/adder_8b/db/adder_8b.cmp.hdb b/adder_8b/db/adder_8b.cmp.hdb deleted file mode 100644 index e5e14c8..0000000 Binary files a/adder_8b/db/adder_8b.cmp.hdb and /dev/null differ diff --git a/adder_8b/db/adder_8b.cmp.kpt b/adder_8b/db/adder_8b.cmp.kpt deleted file mode 100644 index fd30264..0000000 --- a/adder_8b/db/adder_8b.cmp.kpt +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/adder_8b/db/adder_8b.cmp.logdb b/adder_8b/db/adder_8b.cmp.logdb deleted file mode 100644 index 626799f..0000000 --- a/adder_8b/db/adder_8b.cmp.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/adder_8b/db/adder_8b.cmp.rdb b/adder_8b/db/adder_8b.cmp.rdb deleted file mode 100644 index e029167..0000000 Binary files a/adder_8b/db/adder_8b.cmp.rdb and /dev/null differ diff --git a/adder_8b/db/adder_8b.cmp.tdb b/adder_8b/db/adder_8b.cmp.tdb deleted file mode 100644 index 9302998..0000000 Binary files a/adder_8b/db/adder_8b.cmp.tdb and /dev/null differ diff --git a/adder_8b/db/adder_8b.cmp0.ddb b/adder_8b/db/adder_8b.cmp0.ddb deleted file mode 100644 index 50cd6fa..0000000 Binary files a/adder_8b/db/adder_8b.cmp0.ddb and /dev/null differ diff --git a/adder_8b/db/adder_8b.cmp2.ddb b/adder_8b/db/adder_8b.cmp2.ddb deleted file mode 100644 index a275f51..0000000 Binary files a/adder_8b/db/adder_8b.cmp2.ddb and /dev/null differ diff --git a/adder_8b/db/adder_8b.cmp_merge.kpt b/adder_8b/db/adder_8b.cmp_merge.kpt deleted file mode 100644 index e6e63e0..0000000 --- a/adder_8b/db/adder_8b.cmp_merge.kpt +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/adder_8b/db/adder_8b.db_info b/adder_8b/db/adder_8b.db_info deleted file mode 100644 index 89f88e0..0000000 --- a/adder_8b/db/adder_8b.db_info +++ /dev/null @@ -1,3 +0,0 @@ -Quartus_Version = Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition -Version_Index = 167832322 -Creation_Time = Mon Mar 07 10:21:41 2022 diff --git a/adder_8b/db/adder_8b.eco.cdb b/adder_8b/db/adder_8b.eco.cdb deleted file mode 100644 index 6612017..0000000 Binary files a/adder_8b/db/adder_8b.eco.cdb and /dev/null differ diff --git a/adder_8b/db/adder_8b.fit.qmsg b/adder_8b/db/adder_8b.fit.qmsg deleted file mode 100644 index dccb36a..0000000 --- a/adder_8b/db/adder_8b.fit.qmsg +++ /dev/null @@ -1,35 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:28:56 2022 " "Info: Processing started: Mon Mar 07 11:28:56 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "IMPP_MPP_USER_DEVICE" "adder_8b EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"adder_8b\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1} -{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1} -{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X11_Y0 X22_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} -{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "9 " "Warning: Found 9 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "CO 0 " "Info: Pin \"CO\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S7 0 " "Info: Pin \"S7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S0 0 " "Info: Pin \"S0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S1 0 " "Info: Pin \"S1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S2 0 " "Info: Pin \"S2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S3 0 " "Info: Pin \"S3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S4 0 " "Info: Pin \"S4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S5 0 " "Info: Pin \"S5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S6 0 " "Info: Pin \"S6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/adder_8b/adder_8b.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/adder_8b/adder_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "305 " "Info: Peak virtual memory: 305 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:28:57 2022 " "Info: Processing ended: Mon Mar 07 11:28:57 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/adder_8b/db/adder_8b.hier_info b/adder_8b/db/adder_8b.hier_info deleted file mode 100644 index 7be6838..0000000 --- a/adder_8b/db/adder_8b.hier_info +++ /dev/null @@ -1,286 +0,0 @@ -|adder_8b -CO <= 7400:inst38.1 -A7 => 7400:inst39.3 -A7 => 7486:inst36.2 -B7 => 7400:inst39.2 -B7 => 7486:inst36.3 -A6 => 7400:inst34.3 -A6 => 7486:inst31.2 -B6 => 7400:inst34.2 -B6 => 7486:inst31.3 -A5 => 7400:inst29.3 -A5 => 7486:inst26.2 -B5 => 7400:inst29.2 -B5 => 7486:inst26.3 -A4 => 7400:inst24.3 -A4 => 7486:inst21.2 -B4 => 7400:inst24.2 -B4 => 7486:inst21.3 -A3 => 7400:inst19.3 -A3 => 7486:inst16.2 -B3 => 7400:inst19.2 -B3 => 7486:inst16.3 -A2 => 7400:inst14.3 -A2 => 7486:inst11.2 -B2 => 7400:inst14.2 -B2 => 7486:inst11.3 -A1 => 7400:inst9.3 -A1 => 7486:inst6.2 -B1 => 7400:inst9.2 -B1 => 7486:inst6.3 -A0 => 7400:inst4.3 -A0 => 7486:inst.2 -B0 => 7400:inst4.2 -B0 => 7486:inst.3 -CI => 7400:inst2.3 -CI => 7486:inst5.3 -S7 <= 7486:inst40.1 -S0 <= 7486:inst5.1 -S1 <= 7486:inst10.1 -S2 <= 7486:inst15.1 -S3 <= 7486:inst20.1 -S4 <= 7486:inst25.1 -S5 <= 7486:inst30.1 -S6 <= 7486:inst35.1 - - -|adder_8b|7400:inst38 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7400:inst39 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7400:inst37 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7400:inst33 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7400:inst34 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7400:inst32 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7400:inst28 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7400:inst29 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7400:inst27 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7400:inst23 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7400:inst24 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7400:inst22 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7400:inst18 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7400:inst19 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7400:inst17 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7400:inst13 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7400:inst14 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7400:inst12 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7400:inst8 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7400:inst9 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7400:inst7 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7400:inst3 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7400:inst4 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7400:inst2 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7486:inst -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7486:inst6 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7486:inst11 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7486:inst16 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7486:inst21 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7486:inst26 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7486:inst31 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7486:inst36 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7486:inst40 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7486:inst5 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7486:inst10 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7486:inst15 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7486:inst20 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7486:inst25 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7486:inst30 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - -|adder_8b|7486:inst35 -1 <= 4.DB_MAX_OUTPUT_PORT_TYPE -2 => 4.IN0 -3 => 4.IN1 - - diff --git a/adder_8b/db/adder_8b.hif b/adder_8b/db/adder_8b.hif deleted file mode 100644 index e5ca282..0000000 --- a/adder_8b/db/adder_8b.hif +++ /dev/null @@ -1,120 +0,0 @@ -Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition -11 -936 -OFF -OFF -OFF -ON -ON -ON -FV_OFF -Level2 -0 -0 -VRSM_ON -VHSM_ON -0 --- Start Library Paths -- --- End Library Paths -- --- Start VHDL Libraries -- --- End VHDL Libraries -- -# entity -adder_8b -# storage -db|adder_8b.(0).cnf -db|adder_8b.(0).cnf -# case_insensitive -# source_file -adder_8b.bdf -a2e51ddcd21f2ca4364ec3cc2afc185 -26 -# internal_option { -BLOCK_DESIGN_NAMING -AUTO -} -# hierarchies { -| -} -# macro_sequence - -# end -# entity -7400 -# storage -db|adder_8b.(1).cnf -db|adder_8b.(1).cnf -# case_insensitive -# source_file -..|..|..|altera|90sp2|quartus|libraries|others|maxplus2|7400.bdf -2bbb3be4da5c8a854468ca6be3dac -26 -# internal_option { -BLOCK_DESIGN_NAMING -AUTO -} -# hierarchies { -7400:inst38 -7400:inst39 -7400:inst37 -7400:inst33 -7400:inst34 -7400:inst32 -7400:inst28 -7400:inst29 -7400:inst27 -7400:inst23 -7400:inst24 -7400:inst22 -7400:inst18 -7400:inst19 -7400:inst17 -7400:inst13 -7400:inst14 -7400:inst12 -7400:inst8 -7400:inst9 -7400:inst7 -7400:inst3 -7400:inst4 -7400:inst2 -} -# macro_sequence - -# end -# entity -7486 -# storage -db|adder_8b.(2).cnf -db|adder_8b.(2).cnf -# case_insensitive -# source_file -..|..|..|altera|90sp2|quartus|libraries|others|maxplus2|7486.bdf -66760dceba984b0dca8067dd21fcf -26 -# internal_option { -BLOCK_DESIGN_NAMING -AUTO -} -# hierarchies { -7486:inst -7486:inst6 -7486:inst11 -7486:inst16 -7486:inst21 -7486:inst26 -7486:inst31 -7486:inst36 -7486:inst40 -7486:inst5 -7486:inst10 -7486:inst15 -7486:inst20 -7486:inst25 -7486:inst30 -7486:inst35 -} -# macro_sequence - -# end -# complete - \ No newline at end of file diff --git a/adder_8b/db/adder_8b.lpc.html b/adder_8b/db/adder_8b.lpc.html deleted file mode 100644 index fd4875d..0000000 --- a/adder_8b/db/adder_8b.lpc.html +++ /dev/null @@ -1,18 +0,0 @@ - - - - - - - - - - - - - - - - - -
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
diff --git a/adder_8b/db/adder_8b.lpc.rdb b/adder_8b/db/adder_8b.lpc.rdb deleted file mode 100644 index 8bd163a..0000000 Binary files a/adder_8b/db/adder_8b.lpc.rdb and /dev/null differ diff --git a/adder_8b/db/adder_8b.lpc.txt b/adder_8b/db/adder_8b.lpc.txt deleted file mode 100644 index a463804..0000000 --- a/adder_8b/db/adder_8b.lpc.txt +++ /dev/null @@ -1,5 +0,0 @@ -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Legal Partition Candidates ; -+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ -; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; -+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/adder_8b/db/adder_8b.map.bpm b/adder_8b/db/adder_8b.map.bpm deleted file mode 100644 index 6b400b8..0000000 Binary files a/adder_8b/db/adder_8b.map.bpm and /dev/null differ diff --git a/adder_8b/db/adder_8b.map.cdb b/adder_8b/db/adder_8b.map.cdb deleted file mode 100644 index e55bf57..0000000 Binary files a/adder_8b/db/adder_8b.map.cdb and /dev/null differ diff --git a/adder_8b/db/adder_8b.map.ecobp b/adder_8b/db/adder_8b.map.ecobp deleted file mode 100644 index e05efff..0000000 Binary files a/adder_8b/db/adder_8b.map.ecobp and /dev/null differ diff --git a/adder_8b/db/adder_8b.map.hdb b/adder_8b/db/adder_8b.map.hdb deleted file mode 100644 index c639357..0000000 Binary files a/adder_8b/db/adder_8b.map.hdb and /dev/null differ diff --git a/adder_8b/db/adder_8b.map.kpt b/adder_8b/db/adder_8b.map.kpt deleted file mode 100644 index 8bd14c8..0000000 --- a/adder_8b/db/adder_8b.map.kpt +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/adder_8b/db/adder_8b.map.logdb b/adder_8b/db/adder_8b.map.logdb deleted file mode 100644 index 626799f..0000000 --- a/adder_8b/db/adder_8b.map.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/adder_8b/db/adder_8b.map.qmsg b/adder_8b/db/adder_8b.map.qmsg deleted file mode 100644 index a0e05b9..0000000 --- a/adder_8b/db/adder_8b.map.qmsg +++ /dev/null @@ -1,11 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:28:54 2022 " "Info: Processing started: Mon Mar 07 11:28:54 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off adder_8b -c adder_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adder_8b -c adder_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adder_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file adder_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 adder_8b " "Info: Found entity 1: adder_8b" { } { { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_START_ELABORATION_TOP" "adder_8b " "Info: Elaborating entity \"adder_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7400 7400:inst38 " "Info: Elaborating entity \"7400\" for hierarchy \"7400:inst38\"" { } { { "adder_8b.bdf" "inst38" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 184 400 464 224 "inst38" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} -{ "Info" "ISGN_ELABORATION_HEADER" "7400:inst38 " "Info: Elaborated megafunction instantiation \"7400:inst38\"" { } { { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 184 400 464 224 "inst38" "" } } } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7486 7486:inst " "Info: Elaborating entity \"7486\" for hierarchy \"7486:inst\"" { } { { "adder_8b.bdf" "inst" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2096 272 336 2136 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} -{ "Info" "ISGN_ELABORATION_HEADER" "7486:inst " "Info: Elaborated megafunction instantiation \"7486:inst\"" { } { { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2096 272 336 2136 "inst" "" } } } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_TM_SUMMARY" "47 " "Info: Implemented 47 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "17 " "Info: Implemented 17 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Info: Implemented 9 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "21 " "Info: Implemented 21 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:28:55 2022 " "Info: Processing ended: Mon Mar 07 11:28:55 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/adder_8b/db/adder_8b.map_bb.cdb b/adder_8b/db/adder_8b.map_bb.cdb deleted file mode 100644 index 90e0434..0000000 Binary files a/adder_8b/db/adder_8b.map_bb.cdb and /dev/null differ diff --git a/adder_8b/db/adder_8b.map_bb.hdb b/adder_8b/db/adder_8b.map_bb.hdb deleted file mode 100644 index fb153dc..0000000 Binary files a/adder_8b/db/adder_8b.map_bb.hdb and /dev/null differ diff --git a/adder_8b/db/adder_8b.map_bb.logdb b/adder_8b/db/adder_8b.map_bb.logdb deleted file mode 100644 index 626799f..0000000 --- a/adder_8b/db/adder_8b.map_bb.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/adder_8b/db/adder_8b.pre_map.cdb b/adder_8b/db/adder_8b.pre_map.cdb deleted file mode 100644 index 6d220fc..0000000 Binary files a/adder_8b/db/adder_8b.pre_map.cdb and /dev/null differ diff --git a/adder_8b/db/adder_8b.pre_map.hdb b/adder_8b/db/adder_8b.pre_map.hdb deleted file mode 100644 index 70558d1..0000000 Binary files a/adder_8b/db/adder_8b.pre_map.hdb and /dev/null differ diff --git a/adder_8b/db/adder_8b.rtlv.hdb b/adder_8b/db/adder_8b.rtlv.hdb deleted file mode 100644 index b908ac5..0000000 Binary files a/adder_8b/db/adder_8b.rtlv.hdb and /dev/null differ diff --git a/adder_8b/db/adder_8b.rtlv_sg.cdb b/adder_8b/db/adder_8b.rtlv_sg.cdb deleted file mode 100644 index 6f1ac1e..0000000 Binary files a/adder_8b/db/adder_8b.rtlv_sg.cdb and /dev/null differ diff --git a/adder_8b/db/adder_8b.rtlv_sg_swap.cdb b/adder_8b/db/adder_8b.rtlv_sg_swap.cdb deleted file mode 100644 index 1459f59..0000000 Binary files a/adder_8b/db/adder_8b.rtlv_sg_swap.cdb and /dev/null differ diff --git a/adder_8b/db/adder_8b.sgdiff.cdb b/adder_8b/db/adder_8b.sgdiff.cdb deleted file mode 100644 index c6d7ce3..0000000 Binary files a/adder_8b/db/adder_8b.sgdiff.cdb and /dev/null differ diff --git a/adder_8b/db/adder_8b.sgdiff.hdb b/adder_8b/db/adder_8b.sgdiff.hdb deleted file mode 100644 index 50a3264..0000000 Binary files a/adder_8b/db/adder_8b.sgdiff.hdb and /dev/null differ diff --git a/adder_8b/db/adder_8b.sld_design_entry.sci b/adder_8b/db/adder_8b.sld_design_entry.sci deleted file mode 100644 index 904d003..0000000 Binary files a/adder_8b/db/adder_8b.sld_design_entry.sci and /dev/null differ diff --git a/adder_8b/db/adder_8b.sld_design_entry_dsc.sci b/adder_8b/db/adder_8b.sld_design_entry_dsc.sci deleted file mode 100644 index 2000bdc..0000000 Binary files a/adder_8b/db/adder_8b.sld_design_entry_dsc.sci and /dev/null differ diff --git a/adder_8b/db/adder_8b.syn_hier_info b/adder_8b/db/adder_8b.syn_hier_info deleted file mode 100644 index e69de29..0000000 diff --git a/adder_8b/db/adder_8b.tan.qmsg b/adder_8b/db/adder_8b.tan.qmsg deleted file mode 100644 index 22927b9..0000000 --- a/adder_8b/db/adder_8b.tan.qmsg +++ /dev/null @@ -1,6 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:28:59 2022 " "Info: Processing started: Mon Mar 07 11:28:59 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "ITDB_FULL_TPD_RESULT" "B0 CO 22.018 ns Longest " "Info: Longest tpd from source pin \"B0\" to destination pin \"CO\" is 22.018 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns B0 1 PIN PIN_67 2 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 2; PIN Node = 'B0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B0 } "NODE_NAME" } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2120 48 216 2136 "B0" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.491 ns) + CELL(0.624 ns) 8.109 ns 7400:inst3\|4~1 2 COMB LCCOMB_X18_Y4_N2 2 " "Info: 2: + IC(6.491 ns) + CELL(0.624 ns) = 8.109 ns; Loc. = LCCOMB_X18_Y4_N2; Fanout = 2; COMB Node = '7400:inst3\|4~1'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.115 ns" { B0 7400:inst3|4~1 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.373 ns) + CELL(0.624 ns) 9.106 ns 7400:inst8\|4~0 3 COMB LCCOMB_X18_Y4_N20 4 " "Info: 3: + IC(0.373 ns) + CELL(0.624 ns) = 9.106 ns; Loc. = LCCOMB_X18_Y4_N20; Fanout = 4; COMB Node = '7400:inst8\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.997 ns" { 7400:inst3|4~1 7400:inst8|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.407 ns) + CELL(0.370 ns) 9.883 ns 7400:inst13\|4~1 4 COMB LCCOMB_X18_Y4_N16 2 " "Info: 4: + IC(0.407 ns) + CELL(0.370 ns) = 9.883 ns; Loc. = LCCOMB_X18_Y4_N16; Fanout = 2; COMB Node = '7400:inst13\|4~1'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.777 ns" { 7400:inst8|4~0 7400:inst13|4~1 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.426 ns) + CELL(0.650 ns) 10.959 ns 7400:inst18\|4~0 5 COMB LCCOMB_X18_Y4_N12 2 " "Info: 5: + IC(0.426 ns) + CELL(0.650 ns) = 10.959 ns; Loc. = LCCOMB_X18_Y4_N12; Fanout = 2; COMB Node = '7400:inst18\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.076 ns" { 7400:inst13|4~1 7400:inst18|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.408 ns) + CELL(0.650 ns) 12.017 ns 7400:inst23\|4~9 6 COMB LCCOMB_X18_Y4_N30 2 " "Info: 6: + IC(0.408 ns) + CELL(0.650 ns) = 12.017 ns; Loc. = LCCOMB_X18_Y4_N30; Fanout = 2; COMB Node = '7400:inst23\|4~9'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.058 ns" { 7400:inst18|4~0 7400:inst23|4~9 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.206 ns) 12.588 ns 7400:inst28\|4~0 7 COMB LCCOMB_X18_Y4_N0 3 " "Info: 7: + IC(0.365 ns) + CELL(0.206 ns) = 12.588 ns; Loc. = LCCOMB_X18_Y4_N0; Fanout = 3; COMB Node = '7400:inst28\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.571 ns" { 7400:inst23|4~9 7400:inst28|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.636 ns) + CELL(0.370 ns) 15.594 ns 7400:inst33\|4~1 8 COMB LCCOMB_X28_Y11_N26 2 " "Info: 8: + IC(2.636 ns) + CELL(0.370 ns) = 15.594 ns; Loc. = LCCOMB_X28_Y11_N26; Fanout = 2; COMB Node = '7400:inst33\|4~1'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.006 ns" { 7400:inst28|4~0 7400:inst33|4~1 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.370 ns) + CELL(0.624 ns) 16.588 ns 7400:inst38\|4~0 9 COMB LCCOMB_X28_Y11_N12 1 " "Info: 9: + IC(0.370 ns) + CELL(0.624 ns) = 16.588 ns; Loc. = LCCOMB_X28_Y11_N12; Fanout = 1; COMB Node = '7400:inst38\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.994 ns" { 7400:inst33|4~1 7400:inst38|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.150 ns) + CELL(3.280 ns) 22.018 ns CO 10 PIN PIN_151 0 " "Info: 10: + IC(2.150 ns) + CELL(3.280 ns) = 22.018 ns; Loc. = PIN_151; Fanout = 0; PIN Node = 'CO'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.430 ns" { 7400:inst38|4~0 CO } "NODE_NAME" } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 32 504 680 48 "CO" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.392 ns ( 38.11 % ) " "Info: Total cell delay = 8.392 ns ( 38.11 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "13.626 ns ( 61.89 % ) " "Info: Total interconnect delay = 13.626 ns ( 61.89 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "22.018 ns" { B0 7400:inst3|4~1 7400:inst8|4~0 7400:inst13|4~1 7400:inst18|4~0 7400:inst23|4~9 7400:inst28|4~0 7400:inst33|4~1 7400:inst38|4~0 CO } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "22.018 ns" { B0 {} B0~combout {} 7400:inst3|4~1 {} 7400:inst8|4~0 {} 7400:inst13|4~1 {} 7400:inst18|4~0 {} 7400:inst23|4~9 {} 7400:inst28|4~0 {} 7400:inst33|4~1 {} 7400:inst38|4~0 {} CO {} } { 0.000ns 0.000ns 6.491ns 0.373ns 0.407ns 0.426ns 0.408ns 0.365ns 2.636ns 0.370ns 2.150ns } { 0.000ns 0.994ns 0.624ns 0.624ns 0.370ns 0.650ns 0.650ns 0.206ns 0.370ns 0.624ns 3.280ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "213 " "Info: Peak virtual memory: 213 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:28:59 2022 " "Info: Processing ended: Mon Mar 07 11:28:59 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/adder_8b/db/adder_8b.tis_db_list.ddb b/adder_8b/db/adder_8b.tis_db_list.ddb deleted file mode 100644 index 2a9a6ed..0000000 Binary files a/adder_8b/db/adder_8b.tis_db_list.ddb and /dev/null differ diff --git a/adder_8b/db/adder_8b.tmw_info b/adder_8b/db/adder_8b.tmw_info deleted file mode 100644 index f9d7d70..0000000 --- a/adder_8b/db/adder_8b.tmw_info +++ /dev/null @@ -1,6 +0,0 @@ -start_full_compilation:s:00:00:06 -start_analysis_synthesis:s:00:00:02-start_full_compilation -start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:02-start_full_compilation -start_assembler:s:00:00:01-start_full_compilation -start_timing_analyzer:s:00:00:01-start_full_compilation diff --git a/adder_8b/db/prev_cmp_adder_8b.asm.qmsg b/adder_8b/db/prev_cmp_adder_8b.asm.qmsg deleted file mode 100644 index 3d63743..0000000 --- a/adder_8b/db/prev_cmp_adder_8b.asm.qmsg +++ /dev/null @@ -1,7 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:22:24 2022 " "Info: Processing started: Mon Mar 07 10:22:24 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1} -{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "242 " "Info: Peak virtual memory: 242 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 10:22:24 2022 " "Info: Processing ended: Mon Mar 07 10:22:24 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/adder_8b/db/prev_cmp_adder_8b.fit.qmsg b/adder_8b/db/prev_cmp_adder_8b.fit.qmsg deleted file mode 100644 index 5e266ed..0000000 --- a/adder_8b/db/prev_cmp_adder_8b.fit.qmsg +++ /dev/null @@ -1,39 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:22:22 2022 " "Info: Processing started: Mon Mar 07 10:22:22 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "IMPP_MPP_USER_DEVICE" "adder_8b EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"adder_8b\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1} -{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "26 26 " "Warning: No exact pin location assignment(s) for 26 pins of 26 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CO " "Info: Pin CO not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { CO } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 32 504 680 48 "CO" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CO } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S7 " "Info: Pin S7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S7 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 64 504 680 80 "S7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S0 " "Info: Pin S0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S0 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2120 504 680 2136 "S0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S1 " "Info: Pin S1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S1 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1840 504 680 1856 "S1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S2 " "Info: Pin S2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S2 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1544 504 680 1560 "S2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S3 " "Info: Pin S3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S3 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1248 504 680 1264 "S3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S4 " "Info: Pin S4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S4 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 952 504 680 968 "S4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S5 " "Info: Pin S5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S5 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 656 504 680 672 "S5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S6 " "Info: Pin S6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S6 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 360 504 680 376 "S6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A6 " "Info: Pin A6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A6 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 344 48 216 360 "A6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A3 " "Info: Pin A3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A3 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1232 48 216 1248 "A3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B3 " "Info: Pin B3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B3 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1248 48 216 1264 "B3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A4 " "Info: Pin A4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A4 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 936 48 216 952 "A4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A2 " "Info: Pin A2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A2 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1528 48 216 1544 "A2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A0 " "Info: Pin A0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A0 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2104 48 216 2120 "A0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CI " "Info: Pin CI not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { CI } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2136 48 216 2152 "CI" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CI } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B0 " "Info: Pin B0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B0 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2120 48 216 2136 "B0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A1 " "Info: Pin A1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A1 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1824 48 216 1840 "A1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B1 " "Info: Pin B1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B1 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1840 48 216 1856 "B1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B2 " "Info: Pin B2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B2 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1544 48 216 1560 "B2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B4 " "Info: Pin B4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B4 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 952 48 216 968 "B4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A5 " "Info: Pin A5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A5 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 640 48 216 656 "A5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B5 " "Info: Pin B5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B5 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 656 48 216 672 "B5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B6 " "Info: Pin B6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B6 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 360 48 216 376 "B6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A7 " "Info: Pin A7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A7 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 48 48 216 64 "A7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B7 " "Info: Pin B7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B7 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 64 48 216 80 "B7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1} -{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1} -{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "26 unused 3.3V 17 9 0 " "Info: Number of I/O pins in group: 26 (unused VREF, 3.3V VCCIO, 17 input, 9 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 2 30 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 35 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 34 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 36 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X10_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} -{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "9 " "Warning: Found 9 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "CO 0 " "Info: Pin \"CO\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S7 0 " "Info: Pin \"S7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S0 0 " "Info: Pin \"S0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S1 0 " "Info: Pin \"S1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S2 0 " "Info: Pin \"S2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S3 0 " "Info: Pin \"S3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S4 0 " "Info: Pin \"S4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S5 0 " "Info: Pin \"S5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S6 0 " "Info: Pin \"S6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/adder_8b/adder_8b.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/adder_8b/adder_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "305 " "Info: Peak virtual memory: 305 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 10:22:23 2022 " "Info: Processing ended: Mon Mar 07 10:22:23 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/adder_8b/db/prev_cmp_adder_8b.map.qmsg b/adder_8b/db/prev_cmp_adder_8b.map.qmsg deleted file mode 100644 index ca9ca77..0000000 --- a/adder_8b/db/prev_cmp_adder_8b.map.qmsg +++ /dev/null @@ -1,11 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:22:20 2022 " "Info: Processing started: Mon Mar 07 10:22:20 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off adder_8b -c adder_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adder_8b -c adder_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adder_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file adder_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 adder_8b " "Info: Found entity 1: adder_8b" { } { { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_START_ELABORATION_TOP" "adder_8b " "Info: Elaborating entity \"adder_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7400 7400:inst38 " "Info: Elaborating entity \"7400\" for hierarchy \"7400:inst38\"" { } { { "adder_8b.bdf" "inst38" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 184 400 464 224 "inst38" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} -{ "Info" "ISGN_ELABORATION_HEADER" "7400:inst38 " "Info: Elaborated megafunction instantiation \"7400:inst38\"" { } { { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 184 400 464 224 "inst38" "" } } } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7486 7486:inst " "Info: Elaborating entity \"7486\" for hierarchy \"7486:inst\"" { } { { "adder_8b.bdf" "inst" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2096 272 336 2136 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} -{ "Info" "ISGN_ELABORATION_HEADER" "7486:inst " "Info: Elaborated megafunction instantiation \"7486:inst\"" { } { { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2096 272 336 2136 "inst" "" } } } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_TM_SUMMARY" "47 " "Info: Implemented 47 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "17 " "Info: Implemented 17 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Info: Implemented 9 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "21 " "Info: Implemented 21 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "248 " "Info: Peak virtual memory: 248 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 10:22:21 2022 " "Info: Processing ended: Mon Mar 07 10:22:21 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/adder_8b/db/prev_cmp_adder_8b.tan.qmsg b/adder_8b/db/prev_cmp_adder_8b.tan.qmsg deleted file mode 100644 index 14356c5..0000000 --- a/adder_8b/db/prev_cmp_adder_8b.tan.qmsg +++ /dev/null @@ -1,6 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:22:25 2022 " "Info: Processing started: Mon Mar 07 10:22:25 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "ITDB_FULL_TPD_RESULT" "A1 CO 19.344 ns Longest " "Info: Longest tpd from source pin \"A1\" to destination pin \"CO\" is 19.344 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns A1 1 PIN PIN_57 2 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_57; Fanout = 2; PIN Node = 'A1'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A1 } "NODE_NAME" } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1824 48 216 1840 "A1" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.202 ns) + CELL(0.651 ns) 7.847 ns 7400:inst8\|4~0 2 COMB LCCOMB_X1_Y7_N12 4 " "Info: 2: + IC(6.202 ns) + CELL(0.651 ns) = 7.847 ns; Loc. = LCCOMB_X1_Y7_N12; Fanout = 4; COMB Node = '7400:inst8\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.853 ns" { A1 7400:inst8|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.391 ns) + CELL(0.206 ns) 8.444 ns 7400:inst13\|4~1 3 COMB LCCOMB_X1_Y7_N8 2 " "Info: 3: + IC(0.391 ns) + CELL(0.206 ns) = 8.444 ns; Loc. = LCCOMB_X1_Y7_N8; Fanout = 2; COMB Node = '7400:inst13\|4~1'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.597 ns" { 7400:inst8|4~0 7400:inst13|4~1 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.387 ns) + CELL(0.370 ns) 9.201 ns 7400:inst18\|4~0 4 COMB LCCOMB_X1_Y7_N4 2 " "Info: 4: + IC(0.387 ns) + CELL(0.370 ns) = 9.201 ns; Loc. = LCCOMB_X1_Y7_N4; Fanout = 2; COMB Node = '7400:inst18\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.757 ns" { 7400:inst13|4~1 7400:inst18|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.387 ns) + CELL(0.370 ns) 9.958 ns 7400:inst23\|4~9 5 COMB LCCOMB_X1_Y7_N6 2 " "Info: 5: + IC(0.387 ns) + CELL(0.370 ns) = 9.958 ns; Loc. = LCCOMB_X1_Y7_N6; Fanout = 2; COMB Node = '7400:inst23\|4~9'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.757 ns" { 7400:inst18|4~0 7400:inst23|4~9 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.412 ns) + CELL(0.650 ns) 11.020 ns 7400:inst28\|4~0 6 COMB LCCOMB_X1_Y7_N0 3 " "Info: 6: + IC(0.412 ns) + CELL(0.650 ns) = 11.020 ns; Loc. = LCCOMB_X1_Y7_N0; Fanout = 3; COMB Node = '7400:inst28\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.062 ns" { 7400:inst23|4~9 7400:inst28|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.736 ns) + CELL(0.206 ns) 12.962 ns 7400:inst33\|4~0 7 COMB LCCOMB_X1_Y15_N24 2 " "Info: 7: + IC(1.736 ns) + CELL(0.206 ns) = 12.962 ns; Loc. = LCCOMB_X1_Y15_N24; Fanout = 2; COMB Node = '7400:inst33\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.942 ns" { 7400:inst28|4~0 7400:inst33|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.396 ns) + CELL(0.651 ns) 14.009 ns 7400:inst38\|4~0 8 COMB LCCOMB_X1_Y15_N4 1 " "Info: 8: + IC(0.396 ns) + CELL(0.651 ns) = 14.009 ns; Loc. = LCCOMB_X1_Y15_N4; Fanout = 1; COMB Node = '7400:inst38\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.047 ns" { 7400:inst33|4~0 7400:inst38|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.039 ns) + CELL(3.296 ns) 19.344 ns CO 9 PIN PIN_58 0 " "Info: 9: + IC(2.039 ns) + CELL(3.296 ns) = 19.344 ns; Loc. = PIN_58; Fanout = 0; PIN Node = 'CO'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.335 ns" { 7400:inst38|4~0 CO } "NODE_NAME" } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 32 504 680 48 "CO" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.394 ns ( 38.22 % ) " "Info: Total cell delay = 7.394 ns ( 38.22 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "11.950 ns ( 61.78 % ) " "Info: Total interconnect delay = 11.950 ns ( 61.78 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "19.344 ns" { A1 7400:inst8|4~0 7400:inst13|4~1 7400:inst18|4~0 7400:inst23|4~9 7400:inst28|4~0 7400:inst33|4~0 7400:inst38|4~0 CO } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "19.344 ns" { A1 {} A1~combout {} 7400:inst8|4~0 {} 7400:inst13|4~1 {} 7400:inst18|4~0 {} 7400:inst23|4~9 {} 7400:inst28|4~0 {} 7400:inst33|4~0 {} 7400:inst38|4~0 {} CO {} } { 0.000ns 0.000ns 6.202ns 0.391ns 0.387ns 0.387ns 0.412ns 1.736ns 0.396ns 2.039ns } { 0.000ns 0.994ns 0.651ns 0.206ns 0.370ns 0.370ns 0.650ns 0.206ns 0.651ns 3.296ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 10:22:25 2022 " "Info: Processing ended: Mon Mar 07 10:22:25 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/adder_8b/incremental_db/README b/adder_8b/incremental_db/README deleted file mode 100644 index 9f62dcd..0000000 --- a/adder_8b/incremental_db/README +++ /dev/null @@ -1,11 +0,0 @@ -This folder contains data for incremental compilation. - -The compiled_partitions sub-folder contains previous compilation results for each partition. -As long as this folder is preserved, incremental compilation results from earlier compiles -can be re-used. To perform a clean compilation from source files for all partitions, both -the db and incremental_db folder should be removed. - -The imported_partitions sub-folder contains the last imported QXP for each imported partition. -As long as this folder is preserved, imported partitions will be automatically re-imported -when the db or incremental_db/compiled_partitions folders are removed. - diff --git a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.atm b/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.atm deleted file mode 100644 index 75f3669..0000000 Binary files a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.atm and /dev/null differ diff --git a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.dfp b/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.dfp deleted file mode 100644 index b1c67d6..0000000 Binary files a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.dfp and /dev/null differ diff --git a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.hdbx b/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.hdbx deleted file mode 100644 index 94b88f3..0000000 Binary files a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.hdbx and /dev/null differ diff --git a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.kpt b/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.kpt deleted file mode 100644 index c1e72d7..0000000 --- a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.kpt +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.logdb b/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.logdb deleted file mode 100644 index 626799f..0000000 --- a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.rcf b/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.rcf deleted file mode 100644 index 0b52b28..0000000 Binary files a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.rcf and /dev/null differ diff --git a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.map.atm b/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.map.atm deleted file mode 100644 index 9f52d79..0000000 Binary files a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.map.atm and /dev/null differ diff --git a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.map.dpi b/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.map.dpi deleted file mode 100644 index cd608df..0000000 Binary files a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.map.dpi and /dev/null differ diff --git a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.map.hdbx b/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.map.hdbx deleted file mode 100644 index f47544c..0000000 Binary files a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.map.hdbx and /dev/null differ diff --git a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.map.kpt b/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.map.kpt deleted file mode 100644 index c380cc7..0000000 --- a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.map.kpt +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/double_selector_8b/db/double_selector_8b.(0).cnf.cdb b/double_selector_8b/db/double_selector_8b.(0).cnf.cdb deleted file mode 100644 index 5ce4906..0000000 Binary files a/double_selector_8b/db/double_selector_8b.(0).cnf.cdb and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.(0).cnf.hdb b/double_selector_8b/db/double_selector_8b.(0).cnf.hdb deleted file mode 100644 index 054e176..0000000 Binary files a/double_selector_8b/db/double_selector_8b.(0).cnf.hdb and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.asm.qmsg b/double_selector_8b/db/double_selector_8b.asm.qmsg deleted file mode 100644 index 9137121..0000000 --- a/double_selector_8b/db/double_selector_8b.asm.qmsg +++ /dev/null @@ -1,7 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:22:46 2022 " "Info: Processing started: Mon Mar 07 11:22:46 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1} -{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:22:46 2022 " "Info: Processing ended: Mon Mar 07 11:22:46 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/double_selector_8b/db/double_selector_8b.asm_labs.ddb b/double_selector_8b/db/double_selector_8b.asm_labs.ddb deleted file mode 100644 index 17df122..0000000 Binary files a/double_selector_8b/db/double_selector_8b.asm_labs.ddb and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.cbx.xml b/double_selector_8b/db/double_selector_8b.cbx.xml deleted file mode 100644 index 0706c40..0000000 --- a/double_selector_8b/db/double_selector_8b.cbx.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/double_selector_8b/db/double_selector_8b.cmp.bpm b/double_selector_8b/db/double_selector_8b.cmp.bpm deleted file mode 100644 index b178f62..0000000 Binary files a/double_selector_8b/db/double_selector_8b.cmp.bpm and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.cmp.cdb b/double_selector_8b/db/double_selector_8b.cmp.cdb deleted file mode 100644 index 63b3f44..0000000 Binary files a/double_selector_8b/db/double_selector_8b.cmp.cdb and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.cmp.ecobp b/double_selector_8b/db/double_selector_8b.cmp.ecobp deleted file mode 100644 index e05efff..0000000 Binary files a/double_selector_8b/db/double_selector_8b.cmp.ecobp and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.cmp.hdb b/double_selector_8b/db/double_selector_8b.cmp.hdb deleted file mode 100644 index d222470..0000000 Binary files a/double_selector_8b/db/double_selector_8b.cmp.hdb and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.cmp.kpt b/double_selector_8b/db/double_selector_8b.cmp.kpt deleted file mode 100644 index 45362cb..0000000 --- a/double_selector_8b/db/double_selector_8b.cmp.kpt +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/double_selector_8b/db/double_selector_8b.cmp.logdb b/double_selector_8b/db/double_selector_8b.cmp.logdb deleted file mode 100644 index 626799f..0000000 --- a/double_selector_8b/db/double_selector_8b.cmp.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/double_selector_8b/db/double_selector_8b.cmp.rdb b/double_selector_8b/db/double_selector_8b.cmp.rdb deleted file mode 100644 index 323137d..0000000 Binary files a/double_selector_8b/db/double_selector_8b.cmp.rdb and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.cmp.tdb b/double_selector_8b/db/double_selector_8b.cmp.tdb deleted file mode 100644 index 9144a32..0000000 Binary files a/double_selector_8b/db/double_selector_8b.cmp.tdb and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.cmp0.ddb b/double_selector_8b/db/double_selector_8b.cmp0.ddb deleted file mode 100644 index 1409b5e..0000000 Binary files a/double_selector_8b/db/double_selector_8b.cmp0.ddb and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.cmp2.ddb b/double_selector_8b/db/double_selector_8b.cmp2.ddb deleted file mode 100644 index 5c5ef95..0000000 Binary files a/double_selector_8b/db/double_selector_8b.cmp2.ddb and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.cmp_merge.kpt b/double_selector_8b/db/double_selector_8b.cmp_merge.kpt deleted file mode 100644 index a0a9dd2..0000000 --- a/double_selector_8b/db/double_selector_8b.cmp_merge.kpt +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/double_selector_8b/db/double_selector_8b.db_info b/double_selector_8b/db/double_selector_8b.db_info deleted file mode 100644 index 82c5a61..0000000 --- a/double_selector_8b/db/double_selector_8b.db_info +++ /dev/null @@ -1,3 +0,0 @@ -Quartus_Version = Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition -Version_Index = 167832322 -Creation_Time = Mon Mar 07 11:06:00 2022 diff --git a/double_selector_8b/db/double_selector_8b.eco.cdb b/double_selector_8b/db/double_selector_8b.eco.cdb deleted file mode 100644 index 6612017..0000000 Binary files a/double_selector_8b/db/double_selector_8b.eco.cdb and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.fit.qmsg b/double_selector_8b/db/double_selector_8b.fit.qmsg deleted file mode 100644 index 8947a74..0000000 --- a/double_selector_8b/db/double_selector_8b.fit.qmsg +++ /dev/null @@ -1,35 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:22:44 2022 " "Info: Processing started: Mon Mar 07 11:22:44 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "IMPP_MPP_USER_DEVICE" "double_selector_8b EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"double_selector_8b\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1} -{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1} -{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y0 X34_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X34_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} -{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y0 0 " "Info: Pin \"Y0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y1 0 " "Info: Pin \"Y1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y2 0 " "Info: Pin \"Y2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y3 0 " "Info: Pin \"Y3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y4 0 " "Info: Pin \"Y4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y5 0 " "Info: Pin \"Y5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y6 0 " "Info: Pin \"Y6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y7 0 " "Info: Pin \"Y7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/double_selector_8b/double_selector_8b.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/double_selector_8b/double_selector_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "307 " "Info: Peak virtual memory: 307 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:22:45 2022 " "Info: Processing ended: Mon Mar 07 11:22:45 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/double_selector_8b/db/double_selector_8b.hier_info b/double_selector_8b/db/double_selector_8b.hier_info deleted file mode 100644 index d4be631..0000000 --- a/double_selector_8b/db/double_selector_8b.hier_info +++ /dev/null @@ -1,43 +0,0 @@ -|double_selector_8b -Y0 <= inst1.DB_MAX_OUTPUT_PORT_TYPE -b0 => inst25.IN0 -BY => inst25.IN1 -BY => inst26.IN1 -BY => inst27.IN1 -BY => inst28.IN1 -BY => inst29.IN1 -BY => inst30.IN1 -BY => inst31.IN1 -BY => inst32.IN1 -a0 => inst24.IN0 -AY => inst24.IN1 -AY => inst23.IN1 -AY => inst22.IN1 -AY => inst21.IN1 -AY => inst.IN1 -AY => inst18.IN1 -AY => inst19.IN1 -AY => inst20.IN1 -Y1 <= inst2.DB_MAX_OUTPUT_PORT_TYPE -b1 => inst26.IN0 -a1 => inst23.IN0 -Y2 <= inst3.DB_MAX_OUTPUT_PORT_TYPE -b2 => inst27.IN0 -a2 => inst22.IN0 -Y3 <= inst4.DB_MAX_OUTPUT_PORT_TYPE -b3 => inst28.IN0 -a3 => inst21.IN0 -Y4 <= inst5.DB_MAX_OUTPUT_PORT_TYPE -b4 => inst29.IN0 -a4 => inst.IN0 -Y5 <= inst6.DB_MAX_OUTPUT_PORT_TYPE -b5 => inst30.IN0 -a5 => inst18.IN0 -Y6 <= inst7.DB_MAX_OUTPUT_PORT_TYPE -b6 => inst31.IN0 -a6 => inst19.IN0 -Y7 <= inst8.DB_MAX_OUTPUT_PORT_TYPE -b7 => inst32.IN0 -a7 => inst20.IN0 - - diff --git a/double_selector_8b/db/double_selector_8b.hif b/double_selector_8b/db/double_selector_8b.hif deleted file mode 100644 index d85a08f..0000000 --- a/double_selector_8b/db/double_selector_8b.hif +++ /dev/null @@ -1,42 +0,0 @@ -Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition -11 -936 -OFF -OFF -OFF -ON -ON -ON -FV_OFF -Level2 -0 -0 -VRSM_ON -VHSM_ON -0 --- Start Library Paths -- --- End Library Paths -- --- Start VHDL Libraries -- --- End VHDL Libraries -- -# entity -double_selector_8b -# storage -db|double_selector_8b.(0).cnf -db|double_selector_8b.(0).cnf -# case_insensitive -# source_file -double_selector_8b.bdf -175873c0dd68c1f8d97dd4bedd5ca23 -26 -# internal_option { -BLOCK_DESIGN_NAMING -AUTO -} -# hierarchies { -| -} -# macro_sequence - -# end -# complete - \ No newline at end of file diff --git a/double_selector_8b/db/double_selector_8b.lpc.html b/double_selector_8b/db/double_selector_8b.lpc.html deleted file mode 100644 index fd4875d..0000000 --- a/double_selector_8b/db/double_selector_8b.lpc.html +++ /dev/null @@ -1,18 +0,0 @@ - - - - - - - - - - - - - - - - - -
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
diff --git a/double_selector_8b/db/double_selector_8b.lpc.rdb b/double_selector_8b/db/double_selector_8b.lpc.rdb deleted file mode 100644 index 8bd163a..0000000 Binary files a/double_selector_8b/db/double_selector_8b.lpc.rdb and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.lpc.txt b/double_selector_8b/db/double_selector_8b.lpc.txt deleted file mode 100644 index a463804..0000000 --- a/double_selector_8b/db/double_selector_8b.lpc.txt +++ /dev/null @@ -1,5 +0,0 @@ -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Legal Partition Candidates ; -+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ -; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; -+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/double_selector_8b/db/double_selector_8b.map.bpm b/double_selector_8b/db/double_selector_8b.map.bpm deleted file mode 100644 index 238bb68..0000000 Binary files a/double_selector_8b/db/double_selector_8b.map.bpm and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.map.cdb b/double_selector_8b/db/double_selector_8b.map.cdb deleted file mode 100644 index 145b848..0000000 Binary files a/double_selector_8b/db/double_selector_8b.map.cdb and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.map.ecobp b/double_selector_8b/db/double_selector_8b.map.ecobp deleted file mode 100644 index e05efff..0000000 Binary files a/double_selector_8b/db/double_selector_8b.map.ecobp and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.map.hdb b/double_selector_8b/db/double_selector_8b.map.hdb deleted file mode 100644 index 6d78a2c..0000000 Binary files a/double_selector_8b/db/double_selector_8b.map.hdb and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.map.kpt b/double_selector_8b/db/double_selector_8b.map.kpt deleted file mode 100644 index 491f4b2..0000000 --- a/double_selector_8b/db/double_selector_8b.map.kpt +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/double_selector_8b/db/double_selector_8b.map.logdb b/double_selector_8b/db/double_selector_8b.map.logdb deleted file mode 100644 index 626799f..0000000 --- a/double_selector_8b/db/double_selector_8b.map.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/double_selector_8b/db/double_selector_8b.map.qmsg b/double_selector_8b/db/double_selector_8b.map.qmsg deleted file mode 100644 index 0551647..0000000 --- a/double_selector_8b/db/double_selector_8b.map.qmsg +++ /dev/null @@ -1,7 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:22:43 2022 " "Info: Processing started: Mon Mar 07 11:22:43 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off double_selector_8b -c double_selector_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off double_selector_8b -c double_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "double_selector_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file double_selector_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 double_selector_8b " "Info: Found entity 1: double_selector_8b" { } { { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_START_ELABORATION_TOP" "double_selector_8b " "Info: Elaborating entity \"double_selector_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_TM_SUMMARY" "34 " "Info: Implemented 34 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "18 " "Info: Implemented 18 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:22:43 2022 " "Info: Processing ended: Mon Mar 07 11:22:43 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/double_selector_8b/db/double_selector_8b.map_bb.cdb b/double_selector_8b/db/double_selector_8b.map_bb.cdb deleted file mode 100644 index 4bfa27a..0000000 Binary files a/double_selector_8b/db/double_selector_8b.map_bb.cdb and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.map_bb.hdb b/double_selector_8b/db/double_selector_8b.map_bb.hdb deleted file mode 100644 index b075daa..0000000 Binary files a/double_selector_8b/db/double_selector_8b.map_bb.hdb and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.map_bb.logdb b/double_selector_8b/db/double_selector_8b.map_bb.logdb deleted file mode 100644 index 626799f..0000000 --- a/double_selector_8b/db/double_selector_8b.map_bb.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/double_selector_8b/db/double_selector_8b.pre_map.cdb b/double_selector_8b/db/double_selector_8b.pre_map.cdb deleted file mode 100644 index f516281..0000000 Binary files a/double_selector_8b/db/double_selector_8b.pre_map.cdb and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.pre_map.hdb b/double_selector_8b/db/double_selector_8b.pre_map.hdb deleted file mode 100644 index 161ae71..0000000 Binary files a/double_selector_8b/db/double_selector_8b.pre_map.hdb and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.rtlv.hdb b/double_selector_8b/db/double_selector_8b.rtlv.hdb deleted file mode 100644 index 67f8688..0000000 Binary files a/double_selector_8b/db/double_selector_8b.rtlv.hdb and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.rtlv_sg.cdb b/double_selector_8b/db/double_selector_8b.rtlv_sg.cdb deleted file mode 100644 index 5bd4828..0000000 Binary files a/double_selector_8b/db/double_selector_8b.rtlv_sg.cdb and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.rtlv_sg_swap.cdb b/double_selector_8b/db/double_selector_8b.rtlv_sg_swap.cdb deleted file mode 100644 index bccc94e..0000000 Binary files a/double_selector_8b/db/double_selector_8b.rtlv_sg_swap.cdb and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.sgdiff.cdb b/double_selector_8b/db/double_selector_8b.sgdiff.cdb deleted file mode 100644 index c37bb12..0000000 Binary files a/double_selector_8b/db/double_selector_8b.sgdiff.cdb and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.sgdiff.hdb b/double_selector_8b/db/double_selector_8b.sgdiff.hdb deleted file mode 100644 index 7984dfd..0000000 Binary files a/double_selector_8b/db/double_selector_8b.sgdiff.hdb and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.sld_design_entry.sci b/double_selector_8b/db/double_selector_8b.sld_design_entry.sci deleted file mode 100644 index 904d003..0000000 Binary files a/double_selector_8b/db/double_selector_8b.sld_design_entry.sci and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.sld_design_entry_dsc.sci b/double_selector_8b/db/double_selector_8b.sld_design_entry_dsc.sci deleted file mode 100644 index 2000bdc..0000000 Binary files a/double_selector_8b/db/double_selector_8b.sld_design_entry_dsc.sci and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.syn_hier_info b/double_selector_8b/db/double_selector_8b.syn_hier_info deleted file mode 100644 index e69de29..0000000 diff --git a/double_selector_8b/db/double_selector_8b.tan.qmsg b/double_selector_8b/db/double_selector_8b.tan.qmsg deleted file mode 100644 index 2f6e0ca..0000000 --- a/double_selector_8b/db/double_selector_8b.tan.qmsg +++ /dev/null @@ -1,6 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:22:47 2022 " "Info: Processing started: Mon Mar 07 11:22:47 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "ITDB_FULL_TPD_RESULT" "b6 Y6 14.785 ns Longest " "Info: Longest tpd from source pin \"b6\" to destination pin \"Y6\" is 14.785 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns b6 1 PIN PIN_75 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_75; Fanout = 1; PIN Node = 'b6'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b6 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 664 64 232 680 "b6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.679 ns) + CELL(0.651 ns) 8.304 ns inst7 2 COMB LCCOMB_X25_Y2_N12 1 " "Info: 2: + IC(6.679 ns) + CELL(0.651 ns) = 8.304 ns; Loc. = LCCOMB_X25_Y2_N12; Fanout = 1; COMB Node = 'inst7'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.330 ns" { b6 inst7 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 392 664 728 440 "inst7" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.365 ns) + CELL(3.116 ns) 14.785 ns Y6 3 PIN PIN_149 0 " "Info: 3: + IC(3.365 ns) + CELL(3.116 ns) = 14.785 ns; Loc. = PIN_149; Fanout = 0; PIN Node = 'Y6'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.481 ns" { inst7 Y6 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 408 816 992 424 "Y6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.741 ns ( 32.07 % ) " "Info: Total cell delay = 4.741 ns ( 32.07 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "10.044 ns ( 67.93 % ) " "Info: Total interconnect delay = 10.044 ns ( 67.93 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "14.785 ns" { b6 inst7 Y6 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "14.785 ns" { b6 {} b6~combout {} inst7 {} Y6 {} } { 0.000ns 0.000ns 6.679ns 3.365ns } { 0.000ns 0.974ns 0.651ns 3.116ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:22:47 2022 " "Info: Processing ended: Mon Mar 07 11:22:47 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/double_selector_8b/db/double_selector_8b.tis_db_list.ddb b/double_selector_8b/db/double_selector_8b.tis_db_list.ddb deleted file mode 100644 index 2a9a6ed..0000000 Binary files a/double_selector_8b/db/double_selector_8b.tis_db_list.ddb and /dev/null differ diff --git a/double_selector_8b/db/double_selector_8b.tmw_info b/double_selector_8b/db/double_selector_8b.tmw_info deleted file mode 100644 index 6516e48..0000000 --- a/double_selector_8b/db/double_selector_8b.tmw_info +++ /dev/null @@ -1,6 +0,0 @@ -start_full_compilation:s:00:00:05 -start_analysis_synthesis:s:00:00:02-start_full_compilation -start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:01-start_full_compilation -start_assembler:s:00:00:02-start_full_compilation -start_timing_analyzer:s:00:00:00-start_full_compilation diff --git a/double_selector_8b/db/prev_cmp_double_selector_8b.asm.qmsg b/double_selector_8b/db/prev_cmp_double_selector_8b.asm.qmsg deleted file mode 100644 index d249efb..0000000 --- a/double_selector_8b/db/prev_cmp_double_selector_8b.asm.qmsg +++ /dev/null @@ -1,7 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:20:35 2022 " "Info: Processing started: Mon Mar 07 11:20:35 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1} -{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:20:36 2022 " "Info: Processing ended: Mon Mar 07 11:20:36 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/double_selector_8b/db/prev_cmp_double_selector_8b.fit.qmsg b/double_selector_8b/db/prev_cmp_double_selector_8b.fit.qmsg deleted file mode 100644 index 8adea03..0000000 --- a/double_selector_8b/db/prev_cmp_double_selector_8b.fit.qmsg +++ /dev/null @@ -1,36 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:20:34 2022 " "Info: Processing started: Mon Mar 07 11:20:34 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "IMPP_MPP_USER_DEVICE" "double_selector_8b EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"double_selector_8b\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1} -{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1} -{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y0 X34_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X34_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} -{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y0 0 " "Info: Pin \"Y0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y1 0 " "Info: Pin \"Y1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y2 0 " "Info: Pin \"Y2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y3 0 " "Info: Pin \"Y3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y4 0 " "Info: Pin \"Y4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y5 0 " "Info: Pin \"Y5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y6 0 " "Info: Pin \"Y6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y7 0 " "Info: Pin \"Y7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/double_selector_8b/double_selector_8b.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/double_selector_8b/double_selector_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "306 " "Info: Peak virtual memory: 306 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:20:35 2022 " "Info: Processing ended: Mon Mar 07 11:20:35 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/double_selector_8b/db/prev_cmp_double_selector_8b.map.qmsg b/double_selector_8b/db/prev_cmp_double_selector_8b.map.qmsg deleted file mode 100644 index 247e595..0000000 --- a/double_selector_8b/db/prev_cmp_double_selector_8b.map.qmsg +++ /dev/null @@ -1,7 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:20:32 2022 " "Info: Processing started: Mon Mar 07 11:20:32 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off double_selector_8b -c double_selector_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off double_selector_8b -c double_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "double_selector_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file double_selector_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 double_selector_8b " "Info: Found entity 1: double_selector_8b" { } { { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_START_ELABORATION_TOP" "double_selector_8b " "Info: Elaborating entity \"double_selector_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_TM_SUMMARY" "34 " "Info: Implemented 34 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "18 " "Info: Implemented 18 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:20:33 2022 " "Info: Processing ended: Mon Mar 07 11:20:33 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/double_selector_8b/db/prev_cmp_double_selector_8b.qmsg b/double_selector_8b/db/prev_cmp_double_selector_8b.qmsg deleted file mode 100644 index d43f8c3..0000000 --- a/double_selector_8b/db/prev_cmp_double_selector_8b.qmsg +++ /dev/null @@ -1,57 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:20:32 2022 " "Info: Processing started: Mon Mar 07 11:20:32 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off double_selector_8b -c double_selector_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off double_selector_8b -c double_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "double_selector_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file double_selector_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 double_selector_8b " "Info: Found entity 1: double_selector_8b" { } { { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_START_ELABORATION_TOP" "double_selector_8b " "Info: Elaborating entity \"double_selector_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_TM_SUMMARY" "34 " "Info: Implemented 34 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "18 " "Info: Implemented 18 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:20:33 2022 " "Info: Processing ended: Mon Mar 07 11:20:33 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:20:34 2022 " "Info: Processing started: Mon Mar 07 11:20:34 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "IMPP_MPP_USER_DEVICE" "double_selector_8b EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"double_selector_8b\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1} -{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1} -{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y0 X34_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X34_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} -{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y0 0 " "Info: Pin \"Y0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y1 0 " "Info: Pin \"Y1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y2 0 " "Info: Pin \"Y2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y3 0 " "Info: Pin \"Y3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y4 0 " "Info: Pin \"Y4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y5 0 " "Info: Pin \"Y5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y6 0 " "Info: Pin \"Y6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y7 0 " "Info: Pin \"Y7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/double_selector_8b/double_selector_8b.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/double_selector_8b/double_selector_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "306 " "Info: Peak virtual memory: 306 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:20:35 2022 " "Info: Processing ended: Mon Mar 07 11:20:35 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:20:35 2022 " "Info: Processing started: Mon Mar 07 11:20:35 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1} -{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:20:36 2022 " "Info: Processing ended: Mon Mar 07 11:20:36 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:20:37 2022 " "Info: Processing started: Mon Mar 07 11:20:37 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "ITDB_FULL_TPD_RESULT" "b6 Y6 14.785 ns Longest " "Info: Longest tpd from source pin \"b6\" to destination pin \"Y6\" is 14.785 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns b6 1 PIN PIN_75 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_75; Fanout = 1; PIN Node = 'b6'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b6 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 664 64 232 680 "b6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.679 ns) + CELL(0.651 ns) 8.304 ns inst7 2 COMB LCCOMB_X25_Y2_N12 1 " "Info: 2: + IC(6.679 ns) + CELL(0.651 ns) = 8.304 ns; Loc. = LCCOMB_X25_Y2_N12; Fanout = 1; COMB Node = 'inst7'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.330 ns" { b6 inst7 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 392 664 728 440 "inst7" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.365 ns) + CELL(3.116 ns) 14.785 ns Y6 3 PIN PIN_149 0 " "Info: 3: + IC(3.365 ns) + CELL(3.116 ns) = 14.785 ns; Loc. = PIN_149; Fanout = 0; PIN Node = 'Y6'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.481 ns" { inst7 Y6 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 408 816 992 424 "Y6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.741 ns ( 32.07 % ) " "Info: Total cell delay = 4.741 ns ( 32.07 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "10.044 ns ( 67.93 % ) " "Info: Total interconnect delay = 10.044 ns ( 67.93 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "14.785 ns" { b6 inst7 Y6 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "14.785 ns" { b6 {} b6~combout {} inst7 {} Y6 {} } { 0.000ns 0.000ns 6.679ns 3.365ns } { 0.000ns 0.974ns 0.651ns 3.116ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:20:37 2022 " "Info: Processing ended: Mon Mar 07 11:20:37 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 2 s " "Info: Quartus II Full Compilation was successful. 0 errors, 2 warnings" { } { } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/double_selector_8b/db/prev_cmp_double_selector_8b.tan.qmsg b/double_selector_8b/db/prev_cmp_double_selector_8b.tan.qmsg deleted file mode 100644 index 48e0594..0000000 --- a/double_selector_8b/db/prev_cmp_double_selector_8b.tan.qmsg +++ /dev/null @@ -1,6 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:20:37 2022 " "Info: Processing started: Mon Mar 07 11:20:37 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "ITDB_FULL_TPD_RESULT" "b6 Y6 14.785 ns Longest " "Info: Longest tpd from source pin \"b6\" to destination pin \"Y6\" is 14.785 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns b6 1 PIN PIN_75 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_75; Fanout = 1; PIN Node = 'b6'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b6 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 664 64 232 680 "b6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.679 ns) + CELL(0.651 ns) 8.304 ns inst7 2 COMB LCCOMB_X25_Y2_N12 1 " "Info: 2: + IC(6.679 ns) + CELL(0.651 ns) = 8.304 ns; Loc. = LCCOMB_X25_Y2_N12; Fanout = 1; COMB Node = 'inst7'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.330 ns" { b6 inst7 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 392 664 728 440 "inst7" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.365 ns) + CELL(3.116 ns) 14.785 ns Y6 3 PIN PIN_149 0 " "Info: 3: + IC(3.365 ns) + CELL(3.116 ns) = 14.785 ns; Loc. = PIN_149; Fanout = 0; PIN Node = 'Y6'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.481 ns" { inst7 Y6 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 408 816 992 424 "Y6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.741 ns ( 32.07 % ) " "Info: Total cell delay = 4.741 ns ( 32.07 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "10.044 ns ( 67.93 % ) " "Info: Total interconnect delay = 10.044 ns ( 67.93 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "14.785 ns" { b6 inst7 Y6 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "14.785 ns" { b6 {} b6~combout {} inst7 {} Y6 {} } { 0.000ns 0.000ns 6.679ns 3.365ns } { 0.000ns 0.974ns 0.651ns 3.116ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:20:37 2022 " "Info: Processing ended: Mon Mar 07 11:20:37 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/double_selector_8b/double_selector_8b.asm.rpt b/double_selector_8b/double_selector_8b.asm.rpt deleted file mode 100644 index 7acc524..0000000 --- a/double_selector_8b/double_selector_8b.asm.rpt +++ /dev/null @@ -1,129 +0,0 @@ -Assembler report for double_selector_8b -Mon Mar 07 11:22:46 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Assembler Summary - 3. Assembler Settings - 4. Assembler Generated Files - 5. Assembler Device Options: D:/projects/quartus/double_selector_8b/double_selector_8b.sof - 6. Assembler Device Options: D:/projects/quartus/double_selector_8b/double_selector_8b.pof - 7. Assembler Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+---------------------------------------------------------------+ -; Assembler Summary ; -+-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Mon Mar 07 11:22:46 2022 ; -; Revision Name ; double_selector_8b ; -; Top-level Entity Name ; double_selector_8b ; -; Family ; Cyclone II ; -; Device ; EP2C8Q208C8 ; -+-----------------------+---------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------+ -; Assembler Settings ; -+-----------------------------------------------------------------------------+----------+---------------+ -; Option ; Setting ; Default Value ; -+-----------------------------------------------------------------------------+----------+---------------+ -; Use smart compilation ; Off ; Off ; -; Generate compressed bitstreams ; On ; On ; -; Compression mode ; Off ; Off ; -; Clock source for configuration device ; Internal ; Internal ; -; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; -; Divide clock frequency by ; 1 ; 1 ; -; Auto user code ; Off ; Off ; -; Use configuration device ; On ; On ; -; Configuration device ; Auto ; Auto ; -; Configuration device auto user code ; Off ; Off ; -; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; -; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; -; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; -; Hexadecimal Output File start address ; 0 ; 0 ; -; Hexadecimal Output File count direction ; Up ; Up ; -; Release clears before tri-states ; Off ; Off ; -; Auto-restart configuration after error ; On ; On ; -; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ; -; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; -; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; -; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; -; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; -+-----------------------------------------------------------------------------+----------+---------------+ - - -+---------------------------------------------------------------+ -; Assembler Generated Files ; -+---------------------------------------------------------------+ -; File Name ; -+---------------------------------------------------------------+ -; D:/projects/quartus/double_selector_8b/double_selector_8b.sof ; -; D:/projects/quartus/double_selector_8b/double_selector_8b.pof ; -+---------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------+ -; Assembler Device Options: D:/projects/quartus/double_selector_8b/double_selector_8b.sof ; -+----------------+------------------------------------------------------------------------+ -; Option ; Setting ; -+----------------+------------------------------------------------------------------------+ -; Device ; EP2C8Q208C8 ; -; JTAG usercode ; 0xFFFFFFFF ; -; Checksum ; 0x000C2319 ; -+----------------+------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------+ -; Assembler Device Options: D:/projects/quartus/double_selector_8b/double_selector_8b.pof ; -+--------------------+--------------------------------------------------------------------+ -; Option ; Setting ; -+--------------------+--------------------------------------------------------------------+ -; Device ; EPCS4 ; -; JTAG usercode ; 0x00000000 ; -; Checksum ; 0x06EFE4CF ; -; Compression Ratio ; 3 ; -+--------------------+--------------------------------------------------------------------+ - - -+--------------------+ -; Assembler Messages ; -+--------------------+ -Info: ******************************************************************* -Info: Running Quartus II Assembler - Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Mon Mar 07 11:22:46 2022 -Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b -Info: Writing out detailed assembly data for power analysis -Info: Assembler is generating device programming files -Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled -Info: Quartus II Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 241 megabytes - Info: Processing ended: Mon Mar 07 11:22:46 2022 - Info: Elapsed time: 00:00:00 - Info: Total CPU time (on all processors): 00:00:00 - - diff --git a/double_selector_8b/double_selector_8b.done b/double_selector_8b/double_selector_8b.done deleted file mode 100644 index 42c6fdc..0000000 --- a/double_selector_8b/double_selector_8b.done +++ /dev/null @@ -1 +0,0 @@ -Mon Mar 07 11:22:47 2022 diff --git a/double_selector_8b/double_selector_8b.fit.rpt b/double_selector_8b/double_selector_8b.fit.rpt deleted file mode 100644 index 59b0dd9..0000000 --- a/double_selector_8b/double_selector_8b.fit.rpt +++ /dev/null @@ -1,961 +0,0 @@ -Fitter report for double_selector_8b -Mon Mar 07 11:22:45 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Fitter Summary - 3. Fitter Settings - 4. Parallel Compilation - 5. Incremental Compilation Preservation Summary - 6. Incremental Compilation Partition Settings - 7. Incremental Compilation Placement Preservation - 8. Pin-Out File - 9. Fitter Resource Usage Summary - 10. Input Pins - 11. Output Pins - 12. I/O Bank Usage - 13. All Package Pins - 14. Output Pin Default Load For Reported TCO - 15. Fitter Resource Utilization by Entity - 16. Delay Chain Summary - 17. Pad To Core Delay Chain Fanout - 18. Non-Global High Fan-Out Signals - 19. Interconnect Usage Summary - 20. LAB Logic Elements - 21. LAB Signals Sourced - 22. LAB Signals Sourced Out - 23. LAB Distinct Inputs - 24. Fitter Device Options - 25. Operating Settings and Conditions - 26. Estimated Delay Added for Hold Timing - 27. Advanced Data - General - 28. Advanced Data - Placement Preparation - 29. Advanced Data - Placement - 30. Advanced Data - Routing - 31. Fitter Messages - 32. Fitter Suppressed Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------------+ -; Fitter Summary ; -+------------------------------------+----------------------------------------------+ -; Fitter Status ; Successful - Mon Mar 07 11:22:45 2022 ; -; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; -; Revision Name ; double_selector_8b ; -; Top-level Entity Name ; double_selector_8b ; -; Family ; Cyclone II ; -; Device ; EP2C8Q208C8 ; -; Timing Models ; Final ; -; Total logic elements ; 8 / 8,256 ( < 1 % ) ; -; Total combinational functions ; 8 / 8,256 ( < 1 % ) ; -; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ; -; Total registers ; 0 ; -; Total pins ; 26 / 138 ( 19 % ) ; -; Total virtual pins ; 0 ; -; Total memory bits ; 0 / 165,888 ( 0 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; -; Total PLLs ; 0 / 2 ( 0 % ) ; -+------------------------------------+----------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Settings ; -+--------------------------------------------------------------------+--------------------------------+--------------------------------+ -; Option ; Setting ; Default Value ; -+--------------------------------------------------------------------+--------------------------------+--------------------------------+ -; Device ; EP2C8Q208C8 ; ; -; Minimum Core Junction Temperature ; 0 ; ; -; Maximum Core Junction Temperature ; 85 ; ; -; Fit Attempts to Skip ; 0 ; 0.0 ; -; Device I/O Standard ; 3.3-V LVTTL ; ; -; Use smart compilation ; Off ; Off ; -; Use TimeQuest Timing Analyzer ; Off ; Off ; -; Router Timing Optimization Level ; Normal ; Normal ; -; Placement Effort Multiplier ; 1.0 ; 1.0 ; -; Router Effort Multiplier ; 1.0 ; 1.0 ; -; Always Enable Input Buffers ; Off ; Off ; -; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; -; Optimize Multi-Corner Timing ; Off ; Off ; -; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; -; Optimize Timing ; Normal compilation ; Normal compilation ; -; Optimize Timing for ECOs ; Off ; Off ; -; Regenerate full fit report during ECO compiles ; Off ; Off ; -; Optimize IOC Register Placement for Timing ; On ; On ; -; Limit to One Fitting Attempt ; Off ; Off ; -; Final Placement Optimizations ; Automatically ; Automatically ; -; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; -; Fitter Initial Placement Seed ; 1 ; 1 ; -; PCI I/O ; Off ; Off ; -; Weak Pull-Up Resistor ; Off ; Off ; -; Enable Bus-Hold Circuitry ; Off ; Off ; -; Auto Global Memory Control Signals ; Off ; Off ; -; Auto Packed Registers ; Auto ; Auto ; -; Auto Delay Chains ; On ; On ; -; Auto Merge PLLs ; On ; On ; -; Ignore PLL Mode When Merging PLLs ; Off ; Off ; -; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; -; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; -; Perform Register Duplication for Performance ; Off ; Off ; -; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; -; Perform Register Retiming for Performance ; Off ; Off ; -; Perform Asynchronous Signal Pipelining ; Off ; Off ; -; Fitter Effort ; Auto Fit ; Auto Fit ; -; Physical Synthesis Effort Level ; Normal ; Normal ; -; Auto Global Clock ; On ; On ; -; Auto Global Register Control Signals ; On ; On ; -; Stop After Congestion Map Generation ; Off ; Off ; -; Save Intermediate Fitting Results ; Off ; Off ; -; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; -+--------------------------------------------------------------------+--------------------------------+--------------------------------+ - - -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 4 ; -; Maximum allowed ; 4 ; -; ; ; -; Average used ; 1.00 ; -; Maximum used ; 4 ; -; ; ; -; Usage by Processor ; % Time Used ; -; 1 processor ; 100.0% ; -; 2-4 processors ; < 0.1% ; -+----------------------------+-------------+ - - -+----------------------------------------------+ -; Incremental Compilation Preservation Summary ; -+-------------------------+--------------------+ -; Type ; Value ; -+-------------------------+--------------------+ -; Placement ; ; -; -- Requested ; 0 / 34 ( 0.00 % ) ; -; -- Achieved ; 0 / 34 ( 0.00 % ) ; -; ; ; -; Routing (by Connection) ; ; -; -- Requested ; 0 / 0 ( 0.00 % ) ; -; -- Achieved ; 0 / 0 ( 0.00 % ) ; -+-------------------------+--------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Incremental Compilation Partition Settings ; -+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ -; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; -+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ -; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; -+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ - - -+--------------------------------------------------------------------------------------------+ -; Incremental Compilation Placement Preservation ; -+----------------+---------+-------------------+-------------------------+-------------------+ -; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; -+----------------+---------+-------------------+-------------------------+-------------------+ -; Top ; 34 ; 0 ; N/A ; Source File ; -+----------------+---------+-------------------+-------------------------+-------------------+ - - -+--------------+ -; Pin-Out File ; -+--------------+ -The pin-out file can be found in D:/projects/quartus/double_selector_8b/double_selector_8b.pin. - - -+-------------------------------------------------------------------+ -; Fitter Resource Usage Summary ; -+---------------------------------------------+---------------------+ -; Resource ; Usage ; -+---------------------------------------------+---------------------+ -; Total logic elements ; 8 / 8,256 ( < 1 % ) ; -; -- Combinational with no register ; 8 ; -; -- Register only ; 0 ; -; -- Combinational with a register ; 0 ; -; ; ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 8 ; -; -- 3 input functions ; 0 ; -; -- <=2 input functions ; 0 ; -; -- Register only ; 0 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 8 ; -; -- arithmetic mode ; 0 ; -; ; ; -; Total registers* ; 0 / 8,646 ( 0 % ) ; -; -- Dedicated logic registers ; 0 / 8,256 ( 0 % ) ; -; -- I/O registers ; 0 / 390 ( 0 % ) ; -; ; ; -; Total LABs: partially or completely used ; 1 / 516 ( < 1 % ) ; -; User inserted logic elements ; 0 ; -; Virtual pins ; 0 ; -; I/O pins ; 26 / 138 ( 19 % ) ; -; -- Clock pins ; 1 / 4 ( 25 % ) ; -; Global signals ; 0 ; -; M4Ks ; 0 / 36 ( 0 % ) ; -; Total block memory bits ; 0 / 165,888 ( 0 % ) ; -; Total block memory implementation bits ; 0 / 165,888 ( 0 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; -; PLLs ; 0 / 2 ( 0 % ) ; -; Global clocks ; 0 / 8 ( 0 % ) ; -; JTAGs ; 0 / 1 ( 0 % ) ; -; ASMI blocks ; 0 / 1 ( 0 % ) ; -; CRC blocks ; 0 / 1 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; -; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ; -; Maximum fan-out node ; AY ; -; Maximum fan-out ; 8 ; -; Highest non-global fan-out signal ; AY ; -; Highest non-global fan-out ; 8 ; -; Total fan-out ; 40 ; -; Average fan-out ; 1.08 ; -+---------------------------------------------+---------------------+ -* Register count does not include registers inside RAM blocks or DSP blocks. - - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Input Pins ; -+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ; -+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ -; AY ; 23 ; 1 ; 0 ; 9 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; BY ; 24 ; 1 ; 0 ; 9 ; 1 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; a0 ; 77 ; 4 ; 18 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; a1 ; 80 ; 4 ; 23 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; a2 ; 81 ; 4 ; 23 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; a3 ; 82 ; 4 ; 23 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; a4 ; 84 ; 4 ; 25 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; a5 ; 86 ; 4 ; 25 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; a6 ; 87 ; 4 ; 25 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; a7 ; 88 ; 4 ; 25 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; b0 ; 67 ; 4 ; 9 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; b1 ; 68 ; 4 ; 12 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; b2 ; 69 ; 4 ; 12 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; b3 ; 70 ; 4 ; 14 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; b4 ; 72 ; 4 ; 16 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; b5 ; 74 ; 4 ; 16 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; b6 ; 75 ; 4 ; 16 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; b7 ; 76 ; 4 ; 18 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Output Pins ; -+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; -+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ -; Y0 ; 142 ; 3 ; 34 ; 12 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; Y1 ; 143 ; 3 ; 34 ; 13 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; Y2 ; 144 ; 3 ; 34 ; 13 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; Y3 ; 145 ; 3 ; 34 ; 14 ; 4 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; Y4 ; 146 ; 3 ; 34 ; 15 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; Y5 ; 147 ; 3 ; 34 ; 15 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; Y6 ; 149 ; 3 ; 34 ; 16 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; Y7 ; 150 ; 3 ; 34 ; 16 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ - - -+------------------------------------------------------------+ -; I/O Bank Usage ; -+----------+------------------+---------------+--------------+ -; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; -+----------+------------------+---------------+--------------+ -; 1 ; 4 / 32 ( 13 % ) ; 3.3V ; -- ; -; 2 ; 0 / 35 ( 0 % ) ; 3.3V ; -- ; -; 3 ; 9 / 35 ( 26 % ) ; 3.3V ; -- ; -; 4 ; 16 / 36 ( 44 % ) ; 3.3V ; -- ; -+----------+------------------+---------------+--------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; All Package Pins ; -+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; -+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -; 1 ; 0 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; -; 2 ; 1 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; -; 3 ; 2 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 4 ; 3 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 5 ; 4 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 6 ; 5 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 8 ; 6 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 10 ; 7 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 11 ; 8 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 12 ; 9 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 13 ; 10 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 14 ; 18 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 15 ; 19 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; -; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; -; 18 ; 22 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; -; 19 ; 23 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; -; 20 ; 24 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ; -; 21 ; 25 ; 1 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ; -; 22 ; 26 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; -; 23 ; 27 ; 1 ; AY ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 24 ; 28 ; 1 ; BY ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 26 ; 29 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; -; 27 ; 30 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 28 ; 31 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 30 ; 32 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 31 ; 33 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 33 ; 35 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 34 ; 36 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 35 ; 37 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 37 ; 39 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 39 ; 43 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 40 ; 44 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 41 ; 45 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 42 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 43 ; 48 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 44 ; 49 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 45 ; 50 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 46 ; 51 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 47 ; 52 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 48 ; 53 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 49 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 50 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; -; 51 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 52 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; -; 53 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 54 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; -; 55 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 56 ; 54 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 57 ; 55 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 58 ; 56 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 59 ; 57 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 60 ; 58 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 61 ; 59 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 63 ; 60 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 64 ; 61 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 67 ; 69 ; 4 ; b0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 68 ; 70 ; 4 ; b1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 69 ; 71 ; 4 ; b2 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 70 ; 74 ; 4 ; b3 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 71 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 72 ; 75 ; 4 ; b4 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 74 ; 76 ; 4 ; b5 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 75 ; 77 ; 4 ; b6 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 76 ; 78 ; 4 ; b7 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 77 ; 79 ; 4 ; a0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 80 ; 82 ; 4 ; a1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 81 ; 83 ; 4 ; a2 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 82 ; 84 ; 4 ; a3 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 83 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 84 ; 85 ; 4 ; a4 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 85 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 86 ; 86 ; 4 ; a5 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 87 ; 87 ; 4 ; a6 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 88 ; 88 ; 4 ; a7 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 89 ; 89 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 90 ; 90 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 91 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 92 ; 91 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 94 ; 92 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 95 ; 93 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 96 ; 94 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 97 ; 95 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 98 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 99 ; 96 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 100 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 101 ; 97 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 102 ; 98 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 103 ; 99 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 104 ; 100 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 105 ; 101 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 106 ; 102 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 107 ; 105 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 108 ; 106 ; 3 ; ~LVDS54p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 109 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 110 ; 107 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 111 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 112 ; 108 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 113 ; 109 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 114 ; 110 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 115 ; 112 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 116 ; 113 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 117 ; 114 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 118 ; 117 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 119 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 120 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 121 ; 121 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; -; 122 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 123 ; 122 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; -; 124 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 125 ; 123 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; -; 126 ; 124 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; -; 127 ; 125 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 128 ; 126 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 129 ; 127 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 130 ; 128 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 131 ; 129 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 132 ; 130 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 133 ; 131 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 134 ; 132 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 135 ; 133 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 136 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 137 ; 134 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 138 ; 135 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 139 ; 136 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 141 ; 137 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 142 ; 138 ; 3 ; Y0 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 143 ; 141 ; 3 ; Y1 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 144 ; 142 ; 3 ; Y2 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 145 ; 143 ; 3 ; Y3 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 146 ; 149 ; 3 ; Y4 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 147 ; 150 ; 3 ; Y5 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 148 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 149 ; 151 ; 3 ; Y6 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 150 ; 152 ; 3 ; Y7 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 151 ; 153 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 152 ; 154 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 153 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 154 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; -; 155 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 156 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; -; 157 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 158 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; -; 159 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 160 ; 155 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 161 ; 156 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 162 ; 157 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 163 ; 158 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 164 ; 159 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 165 ; 160 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 166 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 167 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 168 ; 161 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 169 ; 162 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 170 ; 163 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 171 ; 164 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 172 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 173 ; 165 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 174 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 175 ; 168 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 176 ; 169 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 177 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 178 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 179 ; 173 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 180 ; 174 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 181 ; 175 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 182 ; 176 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 183 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 184 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 185 ; 180 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 186 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 187 ; 181 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 188 ; 182 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 189 ; 183 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 190 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 191 ; 184 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 192 ; 185 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 193 ; 186 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 194 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 195 ; 187 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 196 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 197 ; 191 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 198 ; 192 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 199 ; 195 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 200 ; 196 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 201 ; 197 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 202 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 203 ; 198 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 204 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 205 ; 199 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 206 ; 200 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 207 ; 201 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 208 ; 202 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -Note: Pin directions (input, output or bidir) are based on device operating in user mode. - - -+-------------------------------------------------------------------------------+ -; Output Pin Default Load For Reported TCO ; -+----------------------------------+-------+------------------------------------+ -; I/O Standard ; Load ; Termination Resistance ; -+----------------------------------+-------+------------------------------------+ -; 3.3-V LVTTL ; 0 pF ; Not Available ; -; 3.3-V LVCMOS ; 0 pF ; Not Available ; -; 2.5 V ; 0 pF ; Not Available ; -; 1.8 V ; 0 pF ; Not Available ; -; 1.5 V ; 0 pF ; Not Available ; -; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ; -; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ; -; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; -; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; -; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; -; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; -; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; -; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; -; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; -; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; -; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ; -; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ; -; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ; -; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ; -; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ; -; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ; -; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ; -; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ; -; LVDS ; 0 pF ; 100 Ohm (Differential) ; -; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ; -; RSDS ; 0 pF ; 100 Ohm (Differential) ; -; Simple RSDS ; 0 pF ; Not Available ; -; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ; -+----------------------------------+-------+------------------------------------+ -Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Resource Utilization by Entity ; -+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ -; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; -+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ -; |double_selector_8b ; 8 (8) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 26 ; 0 ; 8 (8) ; 0 (0) ; 0 (0) ; |double_selector_8b ; work ; -+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ -Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. - - -+-------------------------------------------------------------------------------+ -; Delay Chain Summary ; -+------+----------+---------------+---------------+-----------------------+-----+ -; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; -+------+----------+---------------+---------------+-----------------------+-----+ -; Y0 ; Output ; -- ; -- ; -- ; -- ; -; Y1 ; Output ; -- ; -- ; -- ; -- ; -; Y2 ; Output ; -- ; -- ; -- ; -- ; -; Y3 ; Output ; -- ; -- ; -- ; -- ; -; Y4 ; Output ; -- ; -- ; -- ; -- ; -; Y5 ; Output ; -- ; -- ; -- ; -- ; -; Y6 ; Output ; -- ; -- ; -- ; -- ; -; Y7 ; Output ; -- ; -- ; -- ; -- ; -; b0 ; Input ; 6 ; 6 ; -- ; -- ; -; a0 ; Input ; 6 ; 6 ; -- ; -- ; -; AY ; Input ; 0 ; 0 ; -- ; -- ; -; BY ; Input ; 0 ; 0 ; -- ; -- ; -; a1 ; Input ; 6 ; 6 ; -- ; -- ; -; b1 ; Input ; 6 ; 6 ; -- ; -- ; -; a2 ; Input ; 6 ; 6 ; -- ; -- ; -; b2 ; Input ; 6 ; 6 ; -- ; -- ; -; a3 ; Input ; 6 ; 6 ; -- ; -- ; -; b3 ; Input ; 6 ; 6 ; -- ; -- ; -; a4 ; Input ; 6 ; 6 ; -- ; -- ; -; b4 ; Input ; 6 ; 6 ; -- ; -- ; -; a5 ; Input ; 6 ; 6 ; -- ; -- ; -; b5 ; Input ; 6 ; 6 ; -- ; -- ; -; a6 ; Input ; 6 ; 6 ; -- ; -- ; -; b6 ; Input ; 6 ; 6 ; -- ; -- ; -; a7 ; Input ; 6 ; 6 ; -- ; -- ; -; b7 ; Input ; 6 ; 6 ; -- ; -- ; -+------+----------+---------------+---------------+-----------------------+-----+ - - -+---------------------------------------------------+ -; Pad To Core Delay Chain Fanout ; -+---------------------+-------------------+---------+ -; Source Pin / Fanout ; Pad To Core Index ; Setting ; -+---------------------+-------------------+---------+ -; b0 ; ; ; -; - inst1 ; 0 ; 6 ; -; a0 ; ; ; -; - inst1 ; 0 ; 6 ; -; AY ; ; ; -; BY ; ; ; -; a1 ; ; ; -; - inst2 ; 0 ; 6 ; -; b1 ; ; ; -; - inst2 ; 0 ; 6 ; -; a2 ; ; ; -; - inst3 ; 0 ; 6 ; -; b2 ; ; ; -; - inst3 ; 0 ; 6 ; -; a3 ; ; ; -; - inst4 ; 0 ; 6 ; -; b3 ; ; ; -; - inst4 ; 1 ; 6 ; -; a4 ; ; ; -; - inst5 ; 0 ; 6 ; -; b4 ; ; ; -; - inst5 ; 0 ; 6 ; -; a5 ; ; ; -; - inst6 ; 0 ; 6 ; -; b5 ; ; ; -; - inst6 ; 0 ; 6 ; -; a6 ; ; ; -; - inst7 ; 0 ; 6 ; -; b6 ; ; ; -; - inst7 ; 0 ; 6 ; -; a7 ; ; ; -; - inst8 ; 0 ; 6 ; -; b7 ; ; ; -; - inst8 ; 0 ; 6 ; -+---------------------+-------------------+---------+ - - -+---------------------------------+ -; Non-Global High Fan-Out Signals ; -+-------+-------------------------+ -; Name ; Fan-Out ; -+-------+-------------------------+ -; BY ; 8 ; -; AY ; 8 ; -; b7 ; 1 ; -; a7 ; 1 ; -; b6 ; 1 ; -; a6 ; 1 ; -; b5 ; 1 ; -; a5 ; 1 ; -; b4 ; 1 ; -; a4 ; 1 ; -; b3 ; 1 ; -; a3 ; 1 ; -; b2 ; 1 ; -; a2 ; 1 ; -; b1 ; 1 ; -; a1 ; 1 ; -; a0 ; 1 ; -; b0 ; 1 ; -; inst8 ; 1 ; -; inst7 ; 1 ; -; inst6 ; 1 ; -; inst5 ; 1 ; -; inst4 ; 1 ; -; inst3 ; 1 ; -; inst2 ; 1 ; -; inst1 ; 1 ; -+-------+-------------------------+ - - -+----------------------------------------------------+ -; Interconnect Usage Summary ; -+----------------------------+-----------------------+ -; Interconnect Resource Type ; Usage ; -+----------------------------+-----------------------+ -; Block interconnects ; 26 / 26,052 ( < 1 % ) ; -; C16 interconnects ; 7 / 1,156 ( < 1 % ) ; -; C4 interconnects ; 42 / 17,952 ( < 1 % ) ; -; Direct links ; 0 / 26,052 ( 0 % ) ; -; Global clocks ; 0 / 8 ( 0 % ) ; -; Local interconnects ; 0 / 8,256 ( 0 % ) ; -; R24 interconnects ; 9 / 1,020 ( < 1 % ) ; -; R4 interconnects ; 33 / 22,440 ( < 1 % ) ; -+----------------------------+-----------------------+ - - -+--------------------------------------------------------------------------+ -; LAB Logic Elements ; -+--------------------------------------------+-----------------------------+ -; Number of Logic Elements (Average = 8.00) ; Number of LABs (Total = 1) ; -+--------------------------------------------+-----------------------------+ -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 1 ; -; 9 ; 0 ; -; 10 ; 0 ; -; 11 ; 0 ; -; 12 ; 0 ; -; 13 ; 0 ; -; 14 ; 0 ; -; 15 ; 0 ; -; 16 ; 0 ; -+--------------------------------------------+-----------------------------+ - - -+---------------------------------------------------------------------------+ -; LAB Signals Sourced ; -+---------------------------------------------+-----------------------------+ -; Number of Signals Sourced (Average = 8.00) ; Number of LABs (Total = 1) ; -+---------------------------------------------+-----------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 1 ; -+---------------------------------------------+-----------------------------+ - - -+-------------------------------------------------------------------------------+ -; LAB Signals Sourced Out ; -+-------------------------------------------------+-----------------------------+ -; Number of Signals Sourced Out (Average = 8.00) ; Number of LABs (Total = 1) ; -+-------------------------------------------------+-----------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 1 ; -+-------------------------------------------------+-----------------------------+ - - -+----------------------------------------------------------------------------+ -; LAB Distinct Inputs ; -+----------------------------------------------+-----------------------------+ -; Number of Distinct Inputs (Average = 18.00) ; Number of LABs (Total = 1) ; -+----------------------------------------------+-----------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 0 ; -; 9 ; 0 ; -; 10 ; 0 ; -; 11 ; 0 ; -; 12 ; 0 ; -; 13 ; 0 ; -; 14 ; 0 ; -; 15 ; 0 ; -; 16 ; 0 ; -; 17 ; 0 ; -; 18 ; 1 ; -+----------------------------------------------+-----------------------------+ - - -+-------------------------------------------------------------------------+ -; Fitter Device Options ; -+----------------------------------------------+--------------------------+ -; Option ; Setting ; -+----------------------------------------------+--------------------------+ -; Enable user-supplied start-up clock (CLKUSR) ; Off ; -; Enable device-wide reset (DEV_CLRn) ; Off ; -; Enable device-wide output enable (DEV_OE) ; Off ; -; Enable INIT_DONE output ; Off ; -; Configuration scheme ; Active Serial ; -; Error detection CRC ; Off ; -; nCEO ; As output driving ground ; -; ASDO,nCSO ; As input tri-stated ; -; Reserve all unused pins ; As input tri-stated ; -; Base pin-out file on sameframe device ; Off ; -+----------------------------------------------+--------------------------+ - - -+------------------------------------+ -; Operating Settings and Conditions ; -+---------------------------+--------+ -; Setting ; Value ; -+---------------------------+--------+ -; Nominal Core Voltage ; 1.20 V ; -; Low Junction Temperature ; 0 °C ; -; High Junction Temperature ; 85 °C ; -+---------------------------+--------+ - - -+------------------------------------------------------------+ -; Estimated Delay Added for Hold Timing ; -+-----------------+----------------------+-------------------+ -; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; -+-----------------+----------------------+-------------------+ - - -+----------------------------+ -; Advanced Data - General ; -+--------------------+-------+ -; Name ; Value ; -+--------------------+-------+ -; Status Code ; 0 ; -; Desired User Slack ; 0 ; -; Fit Attempts ; 1 ; -+--------------------+-------+ - - -+-------------------------------------------------------------------------------+ -; Advanced Data - Placement Preparation ; -+------------------------------------------------------------------+------------+ -; Name ; Value ; -+------------------------------------------------------------------+------------+ -; Auto Fit Point 1 - Fit Attempt 1 ; ff ; -; Mid Wire Use - Fit Attempt 1 ; 0 ; -; Mid Slack - Fit Attempt 1 ; 2147483639 ; -; Internal Atom Count - Fit Attempt 1 ; 9 ; -; LE/ALM Count - Fit Attempt 1 ; 9 ; -; LAB Count - Fit Attempt 1 ; 2 ; -; Outputs per Lab - Fit Attempt 1 ; 4.000 ; -; Inputs per LAB - Fit Attempt 1 ; 9.000 ; -; Global Inputs per LAB - Fit Attempt 1 ; 0.000 ; -; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:1 ; -; LEs in Chains - Fit Attempt 1 ; 0 ; -; LEs in Long Chains - Fit Attempt 1 ; 0 ; -; LABs with Chains - Fit Attempt 1 ; 0 ; -; LABs with Multiple Chains - Fit Attempt 1 ; 0 ; -; Time - Fit Attempt 1 ; 0 ; -+------------------------------------------------------------------+------------+ - - -+-------------------------------------------------+ -; Advanced Data - Placement ; -+------------------------------------+------------+ -; Name ; Value ; -+------------------------------------+------------+ -; Auto Fit Point 2 - Fit Attempt 1 ; ff ; -; Early Wire Use - Fit Attempt 1 ; 0 ; -; Early Slack - Fit Attempt 1 ; 2147483639 ; -; Auto Fit Point 5 - Fit Attempt 1 ; ff ; -; Mid Wire Use - Fit Attempt 1 ; 0 ; -; Mid Slack - Fit Attempt 1 ; 2147483639 ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 5 - Fit Attempt 1 ; ff ; -; Mid Wire Use - Fit Attempt 1 ; 0 ; -; Mid Slack - Fit Attempt 1 ; 2147483639 ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Late Wire Use - Fit Attempt 1 ; 0 ; -; Late Slack - Fit Attempt 1 ; 2147483639 ; -; Peak Regional Wire - Fit Attempt 1 ; 0.000 ; -; Auto Fit Point 7 - Fit Attempt 1 ; ff ; -; Time - Fit Attempt 1 ; 0 ; -+------------------------------------+------------+ - - -+--------------------------------------------------+ -; Advanced Data - Routing ; -+------------------------------------+-------------+ -; Name ; Value ; -+------------------------------------+-------------+ -; Early Slack - Fit Attempt 1 ; 2147483639 ; -; Early Wire Use - Fit Attempt 1 ; 0 ; -; Peak Regional Wire - Fit Attempt 1 ; 1 ; -; Mid Slack - Fit Attempt 1 ; 2147483639 ; -; Late Slack - Fit Attempt 1 ; -2147483648 ; -; Late Wire Use - Fit Attempt 1 ; 0 ; -; Time - Fit Attempt 1 ; 0 ; -+------------------------------------+-------------+ - - -+-----------------+ -; Fitter Messages ; -+-----------------+ -Info: ******************************************************************* -Info: Running Quartus II Fitter - Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Mon Mar 07 11:22:44 2022 -Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b -Info: Parallel compilation is enabled and will use 4 of the 4 processors detected -Info: Selected device EP2C8Q208C8 for design "double_selector_8b" -Info: Low junction temperature is 0 degrees C -Info: High junction temperature is 85 degrees C -Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time -Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices - Info: Device EP2C5Q208C8 is compatible - Info: Device EP2C5Q208I8 is compatible - Info: Device EP2C8Q208I8 is compatible -Info: Fitter converted 3 user pins into dedicated programming pins - Info: Pin ~ASDO~ is reserved at location 1 - Info: Pin ~nCSO~ is reserved at location 2 - Info: Pin ~LVDS54p/nCEO~ is reserved at location 108 -Info: Fitter is using the Classic Timing Analyzer -Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time. -Info: Starting register packing -Info: Finished register packing - Extra Info: No registers were packed into other blocks -Info: Fitter preparation operations ending: elapsed time is 00:00:00 -Info: Fitter placement preparation operations beginning -Info: Fitter placement preparation operations ending: elapsed time is 00:00:00 -Info: Fitter placement operations beginning -Info: Fitter placement was successful -Info: Fitter placement operations ending: elapsed time is 00:00:00 -Info: Fitter routing operations beginning -Info: Average interconnect usage is 0% of the available device resources - Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X34_Y9 -Info: Fitter routing operations ending: elapsed time is 00:00:00 -Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. - Info: Optimizations that may affect the design's routability were skipped - Info: Optimizations that may affect the design's timing were skipped -Info: Started post-fitting delay annotation -Warning: Found 8 output pins without output pin load capacitance assignment - Info: Pin "Y0" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Y1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Y2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Y3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Y4" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Y5" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Y6" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Y7" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis -Info: Delay annotation completed successfully -Info: Generated suppressed messages file D:/projects/quartus/double_selector_8b/double_selector_8b.fit.smsg -Info: Quartus II Fitter was successful. 0 errors, 1 warning - Info: Peak virtual memory: 307 megabytes - Info: Processing ended: Mon Mar 07 11:22:45 2022 - Info: Elapsed time: 00:00:01 - Info: Total CPU time (on all processors): 00:00:01 - - -+----------------------------+ -; Fitter Suppressed Messages ; -+----------------------------+ -The suppressed messages can be found in D:/projects/quartus/double_selector_8b/double_selector_8b.fit.smsg. - - diff --git a/double_selector_8b/double_selector_8b.fit.smsg b/double_selector_8b/double_selector_8b.fit.smsg deleted file mode 100644 index 14764e7..0000000 --- a/double_selector_8b/double_selector_8b.fit.smsg +++ /dev/null @@ -1,6 +0,0 @@ -Extra Info: Performing register packing on registers with non-logic cell location assignments -Extra Info: Completed register packing on registers with non-logic cell location assignments -Extra Info: Started Fast Input/Output/OE register processing -Extra Info: Finished Fast Input/Output/OE register processing -Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density -Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/double_selector_8b/double_selector_8b.fit.summary b/double_selector_8b/double_selector_8b.fit.summary deleted file mode 100644 index 69240c2..0000000 --- a/double_selector_8b/double_selector_8b.fit.summary +++ /dev/null @@ -1,16 +0,0 @@ -Fitter Status : Successful - Mon Mar 07 11:22:45 2022 -Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition -Revision Name : double_selector_8b -Top-level Entity Name : double_selector_8b -Family : Cyclone II -Device : EP2C8Q208C8 -Timing Models : Final -Total logic elements : 8 / 8,256 ( < 1 % ) - Total combinational functions : 8 / 8,256 ( < 1 % ) - Dedicated logic registers : 0 / 8,256 ( 0 % ) -Total registers : 0 -Total pins : 26 / 138 ( 19 % ) -Total virtual pins : 0 -Total memory bits : 0 / 165,888 ( 0 % ) -Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % ) -Total PLLs : 0 / 2 ( 0 % ) diff --git a/double_selector_8b/double_selector_8b.flow.rpt b/double_selector_8b/double_selector_8b.flow.rpt deleted file mode 100644 index 959e6e9..0000000 --- a/double_selector_8b/double_selector_8b.flow.rpt +++ /dev/null @@ -1,121 +0,0 @@ -Flow report for double_selector_8b -Mon Mar 07 11:22:47 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Flow Summary - 3. Flow Settings - 4. Flow Non-Default Global Settings - 5. Flow Elapsed Time - 6. Flow OS Summary - 7. Flow Log - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------------+ -; Flow Summary ; -+------------------------------------+----------------------------------------------+ -; Flow Status ; Successful - Mon Mar 07 11:22:47 2022 ; -; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; -; Revision Name ; double_selector_8b ; -; Top-level Entity Name ; double_selector_8b ; -; Family ; Cyclone II ; -; Device ; EP2C8Q208C8 ; -; Timing Models ; Final ; -; Met timing requirements ; Yes ; -; Total logic elements ; 8 / 8,256 ( < 1 % ) ; -; Total combinational functions ; 8 / 8,256 ( < 1 % ) ; -; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ; -; Total registers ; 0 ; -; Total pins ; 26 / 138 ( 19 % ) ; -; Total virtual pins ; 0 ; -; Total memory bits ; 0 / 165,888 ( 0 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; -; Total PLLs ; 0 / 2 ( 0 % ) ; -+------------------------------------+----------------------------------------------+ - - -+-----------------------------------------+ -; Flow Settings ; -+-------------------+---------------------+ -; Option ; Setting ; -+-------------------+---------------------+ -; Start date & time ; 03/07/2022 11:22:43 ; -; Main task ; Compilation ; -; Revision Name ; double_selector_8b ; -+-------------------+---------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Flow Non-Default Global Settings ; -+------------------------------------+---------------------------------------------------------------+---------------+-------------+----------------+ -; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; -+------------------------------------+---------------------------------------------------------------+---------------+-------------+----------------+ -; COMPILER_SIGNATURE_ID ; 220283517943889.164662336312624 ; -- ; -- ; -- ; -; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; -; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; -; MISC_FILE ; D:/projects/quartus/double_selector_8b/double_selector_8b.dpf ; -- ; -- ; -- ; -; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; -; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; -; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ; -+------------------------------------+---------------------------------------------------------------+---------------+-------------+----------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Flow Elapsed Time ; -+-------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; -+-------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 246 MB ; 00:00:00 ; -; Fitter ; 00:00:01 ; 1.0 ; 307 MB ; 00:00:01 ; -; Assembler ; 00:00:00 ; 1.0 ; 241 MB ; 00:00:00 ; -; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 198 MB ; 00:00:00 ; -; Total ; 00:00:01 ; -- ; -- ; 00:00:01 ; -+-------------------------+--------------+-------------------------+---------------------+------------------------------------+ - - -+------------------------------------------------------------------------------------------+ -; Flow OS Summary ; -+-------------------------+------------------+---------------+------------+----------------+ -; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; -+-------------------------+------------------+---------------+------------+----------------+ -; Analysis & Synthesis ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; -; Fitter ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; -; Assembler ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; -; Classic Timing Analyzer ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; -+-------------------------+------------------+---------------+------------+----------------+ - - ------------- -; Flow Log ; ------------- -quartus_map --read_settings_files=on --write_settings_files=off double_selector_8b -c double_selector_8b -quartus_fit --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b -quartus_asm --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b -quartus_tan --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b --timing_analysis_only - - - diff --git a/double_selector_8b/double_selector_8b.map.rpt b/double_selector_8b/double_selector_8b.map.rpt deleted file mode 100644 index 0b9d6f6..0000000 --- a/double_selector_8b/double_selector_8b.map.rpt +++ /dev/null @@ -1,218 +0,0 @@ -Analysis & Synthesis report for double_selector_8b -Mon Mar 07 11:22:43 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Analysis & Synthesis Summary - 3. Analysis & Synthesis Settings - 4. Analysis & Synthesis Source Files Read - 5. Analysis & Synthesis Resource Usage Summary - 6. Analysis & Synthesis Resource Utilization by Entity - 7. General Register Statistics - 8. Analysis & Synthesis Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------------+ -; Analysis & Synthesis Summary ; -+------------------------------------+----------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Mon Mar 07 11:22:43 2022 ; -; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; -; Revision Name ; double_selector_8b ; -; Top-level Entity Name ; double_selector_8b ; -; Family ; Cyclone II ; -; Total logic elements ; 8 ; -; Total combinational functions ; 8 ; -; Dedicated logic registers ; 0 ; -; Total registers ; 0 ; -; Total pins ; 26 ; -; Total virtual pins ; 0 ; -; Total memory bits ; 0 ; -; Embedded Multiplier 9-bit elements ; 0 ; -; Total PLLs ; 0 ; -+------------------------------------+----------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Settings ; -+--------------------------------------------------------------+--------------------+--------------------+ -; Option ; Setting ; Default Value ; -+--------------------------------------------------------------+--------------------+--------------------+ -; Device ; EP2C8Q208C8 ; ; -; Top-level entity name ; double_selector_8b ; double_selector_8b ; -; Family name ; Cyclone II ; Stratix II ; -; Use Generated Physical Constraints File ; Off ; ; -; Use smart compilation ; Off ; Off ; -; Restructure Multiplexers ; Auto ; Auto ; -; Create Debugging Nodes for IP Cores ; Off ; Off ; -; Preserve fewer node names ; On ; On ; -; Disable OpenCore Plus hardware evaluation ; Off ; Off ; -; Verilog Version ; Verilog_2001 ; Verilog_2001 ; -; VHDL Version ; VHDL93 ; VHDL93 ; -; State Machine Processing ; Auto ; Auto ; -; Safe State Machine ; Off ; Off ; -; Extract Verilog State Machines ; On ; On ; -; Extract VHDL State Machines ; On ; On ; -; Ignore Verilog initial constructs ; Off ; Off ; -; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; -; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; -; Add Pass-Through Logic to Inferred RAMs ; On ; On ; -; Parallel Synthesis ; Off ; Off ; -; DSP Block Balancing ; Auto ; Auto ; -; NOT Gate Push-Back ; On ; On ; -; Power-Up Don't Care ; On ; On ; -; Remove Redundant Logic Cells ; Off ; Off ; -; Remove Duplicate Registers ; On ; On ; -; Ignore CARRY Buffers ; Off ; Off ; -; Ignore CASCADE Buffers ; Off ; Off ; -; Ignore GLOBAL Buffers ; Off ; Off ; -; Ignore ROW GLOBAL Buffers ; Off ; Off ; -; Ignore LCELL Buffers ; Off ; Off ; -; Ignore SOFT Buffers ; On ; On ; -; Limit AHDL Integers to 32 Bits ; Off ; Off ; -; Optimization Technique ; Balanced ; Balanced ; -; Carry Chain Length ; 70 ; 70 ; -; Auto Carry Chains ; On ; On ; -; Auto Open-Drain Pins ; On ; On ; -; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; -; Auto ROM Replacement ; On ; On ; -; Auto RAM Replacement ; On ; On ; -; Auto Shift Register Replacement ; Auto ; Auto ; -; Auto Clock Enable Replacement ; On ; On ; -; Strict RAM Replacement ; Off ; Off ; -; Allow Synchronous Control Signals ; On ; On ; -; Force Use of Synchronous Clear Signals ; Off ; Off ; -; Auto RAM to Logic Cell Conversion ; Off ; Off ; -; Auto Resource Sharing ; Off ; Off ; -; Allow Any RAM Size For Recognition ; Off ; Off ; -; Allow Any ROM Size For Recognition ; Off ; Off ; -; Allow Any Shift Register Size For Recognition ; Off ; Off ; -; Use LogicLock Constraints during Resource Balancing ; On ; On ; -; Ignore translate_off and synthesis_off directives ; Off ; Off ; -; Timing-Driven Synthesis ; Off ; Off ; -; Show Parameter Settings Tables in Synthesis Report ; On ; On ; -; Ignore Maximum Fan-Out Assignments ; Off ; Off ; -; Synchronization Register Chain Length ; 2 ; 2 ; -; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; -; HDL message level ; Level2 ; Level2 ; -; Suppress Register Optimization Related Messages ; Off ; Off ; -; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ; -; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; -; Clock MUX Protection ; On ; On ; -; Auto Gated Clock Conversion ; Off ; Off ; -; Block Design Naming ; Auto ; Auto ; -; SDC constraint protection ; Off ; Off ; -; Synthesis Effort ; Auto ; Auto ; -; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; -; Analysis & Synthesis Message Level ; Medium ; Medium ; -+--------------------------------------------------------------+--------------------+--------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; -+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+ -; double_selector_8b.bdf ; yes ; User Block Diagram/Schematic File ; D:/projects/quartus/double_selector_8b/double_selector_8b.bdf ; -+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+ - - -+-----------------------------------------------------+ -; Analysis & Synthesis Resource Usage Summary ; -+---------------------------------------------+-------+ -; Resource ; Usage ; -+---------------------------------------------+-------+ -; Estimated Total logic elements ; 8 ; -; ; ; -; Total combinational functions ; 8 ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 8 ; -; -- 3 input functions ; 0 ; -; -- <=2 input functions ; 0 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 8 ; -; -- arithmetic mode ; 0 ; -; ; ; -; Total registers ; 0 ; -; -- Dedicated logic registers ; 0 ; -; -- I/O registers ; 0 ; -; ; ; -; I/O pins ; 26 ; -; Maximum fan-out node ; AY ; -; Maximum fan-out ; 8 ; -; Total fan-out ; 40 ; -; Average fan-out ; 1.18 ; -+---------------------------------------------+-------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Resource Utilization by Entity ; -+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ -; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; -+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ -; |double_selector_8b ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 26 ; 0 ; |double_selector_8b ; work ; -+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ -Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. - - -+------------------------------------------------------+ -; General Register Statistics ; -+----------------------------------------------+-------+ -; Statistic ; Value ; -+----------------------------------------------+-------+ -; Total registers ; 0 ; -; Number of registers using Synchronous Clear ; 0 ; -; Number of registers using Synchronous Load ; 0 ; -; Number of registers using Asynchronous Clear ; 0 ; -; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 0 ; -; Number of registers using Preset ; 0 ; -+----------------------------------------------+-------+ - - -+-------------------------------+ -; Analysis & Synthesis Messages ; -+-------------------------------+ -Info: ******************************************************************* -Info: Running Quartus II Analysis & Synthesis - Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Mon Mar 07 11:22:43 2022 -Info: Command: quartus_map --read_settings_files=on --write_settings_files=off double_selector_8b -c double_selector_8b -Info: Found 1 design units, including 1 entities, in source file double_selector_8b.bdf - Info: Found entity 1: double_selector_8b -Info: Elaborating entity "double_selector_8b" for the top level hierarchy -Info: Implemented 34 device resources after synthesis - the final resource count might be different - Info: Implemented 18 input pins - Info: Implemented 8 output pins - Info: Implemented 8 logic cells -Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 250 megabytes - Info: Processing ended: Mon Mar 07 11:22:43 2022 - Info: Elapsed time: 00:00:00 - Info: Total CPU time (on all processors): 00:00:00 - - diff --git a/double_selector_8b/double_selector_8b.map.summary b/double_selector_8b/double_selector_8b.map.summary deleted file mode 100644 index 22369a7..0000000 --- a/double_selector_8b/double_selector_8b.map.summary +++ /dev/null @@ -1,14 +0,0 @@ -Analysis & Synthesis Status : Successful - Mon Mar 07 11:22:43 2022 -Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition -Revision Name : double_selector_8b -Top-level Entity Name : double_selector_8b -Family : Cyclone II -Total logic elements : 8 - Total combinational functions : 8 - Dedicated logic registers : 0 -Total registers : 0 -Total pins : 26 -Total virtual pins : 0 -Total memory bits : 0 -Embedded Multiplier 9-bit elements : 0 -Total PLLs : 0 diff --git a/double_selector_8b/double_selector_8b.pin b/double_selector_8b/double_selector_8b.pin deleted file mode 100644 index 3b67fe5..0000000 --- a/double_selector_8b/double_selector_8b.pin +++ /dev/null @@ -1,278 +0,0 @@ - -- Copyright (C) 1991-2009 Altera Corporation - -- Your use of Altera Corporation's design tools, logic functions - -- and other software and tools, and its AMPP partner logic - -- functions, and any output files from any of the foregoing - -- (including device programming or simulation files), and any - -- associated documentation or information are expressly subject - -- to the terms and conditions of the Altera Program License - -- Subscription Agreement, Altera MegaCore Function License - -- Agreement, or other applicable license agreement, including, - -- without limitation, that your use is for the sole purpose of - -- programming logic devices manufactured by Altera and sold by - -- Altera or its authorized distributors. Please refer to the - -- applicable agreement for further details. - -- - -- This is a Quartus II output file. It is for reporting purposes only, and is - -- not intended for use as a Quartus II input file. This file cannot be used - -- to make Quartus II pin assignments - for instructions on how to make pin - -- assignments, please see Quartus II help. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- NC : No Connect. This pin has no internal connection to the device. - -- DNU : Do Not Use. This pin MUST NOT be connected. - -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). - -- VCCIO : Dedicated power pin, which MUST be connected to VCC - -- of its bank. - -- Bank 1: 3.3V - -- Bank 2: 3.3V - -- Bank 3: 3.3V - -- Bank 4: 3.3V - -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. - -- It can also be used to report unused dedicated pins. The connection - -- on the board for unused dedicated pins depends on whether this will - -- be used in a future design. One example is device migration. When - -- using device migration, refer to the device pin-tables. If it is a - -- GND pin in the pin table or if it will not be used in a future design - -- for another purpose the it MUST be connected to GND. If it is an unused - -- dedicated pin, then it can be connected to a valid signal on the board - -- (low, high, or toggling) if that signal is required for a different - -- revision of the design. - -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. - -- This pin should be connected to GND. It may also be connected to a - -- valid signal on the board (low, high, or toggling) if that signal - -- is required for a different revision of the design. - -- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17), - -- connect each pin marked GND* either individually through a 10k Ohm resistor - -- to GND or tie all pins together and connect through a single 10k Ohm resistor - -- to GND. - -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND - -- or leave it unconnected. - -- RESERVED : Unused I/O pin, which MUST be left unconnected. - -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. - -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. - -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. - -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- Pin directions (input, output or bidir) are based on device operating in user mode. - --------------------------------------------------------------------------------- - -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition -CHIP "double_selector_8b" ASSIGNED TO AN: EP2C8Q208C8 - -Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment -------------------------------------------------------------------------------------------------------------- -~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVTTL : : 1 : N -~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVTTL : : 1 : N -RESERVED_INPUT : 3 : : : : 1 : -RESERVED_INPUT : 4 : : : : 1 : -RESERVED_INPUT : 5 : : : : 1 : -RESERVED_INPUT : 6 : : : : 1 : -VCCIO1 : 7 : power : : 3.3V : 1 : -RESERVED_INPUT : 8 : : : : 1 : -GND : 9 : gnd : : : : -RESERVED_INPUT : 10 : : : : 1 : -RESERVED_INPUT : 11 : : : : 1 : -RESERVED_INPUT : 12 : : : : 1 : -RESERVED_INPUT : 13 : : : : 1 : -RESERVED_INPUT : 14 : : : : 1 : -RESERVED_INPUT : 15 : : : : 1 : -TDO : 16 : output : : : 1 : -TMS : 17 : input : : : 1 : -TCK : 18 : input : : : 1 : -TDI : 19 : input : : : 1 : -DATA0 : 20 : input : : : 1 : -DCLK : 21 : : : : 1 : -nCE : 22 : : : : 1 : -AY : 23 : input : 3.3-V LVTTL : : 1 : Y -BY : 24 : input : 3.3-V LVTTL : : 1 : Y -GND : 25 : gnd : : : : -nCONFIG : 26 : : : : 1 : -GND+ : 27 : : : : 1 : -GND+ : 28 : : : : 1 : -VCCIO1 : 29 : power : : 3.3V : 1 : -RESERVED_INPUT : 30 : : : : 1 : -RESERVED_INPUT : 31 : : : : 1 : -VCCINT : 32 : power : : 1.2V : : -RESERVED_INPUT : 33 : : : : 1 : -RESERVED_INPUT : 34 : : : : 1 : -RESERVED_INPUT : 35 : : : : 1 : -GND : 36 : gnd : : : : -RESERVED_INPUT : 37 : : : : 1 : -GND : 38 : gnd : : : : -RESERVED_INPUT : 39 : : : : 1 : -RESERVED_INPUT : 40 : : : : 1 : -RESERVED_INPUT : 41 : : : : 1 : -VCCIO1 : 42 : power : : 3.3V : 1 : -RESERVED_INPUT : 43 : : : : 1 : -RESERVED_INPUT : 44 : : : : 1 : -RESERVED_INPUT : 45 : : : : 1 : -RESERVED_INPUT : 46 : : : : 1 : -RESERVED_INPUT : 47 : : : : 1 : -RESERVED_INPUT : 48 : : : : 1 : -GND : 49 : gnd : : : : -GND_PLL1 : 50 : gnd : : : : -VCCD_PLL1 : 51 : power : : 1.2V : : -GND_PLL1 : 52 : gnd : : : : -VCCA_PLL1 : 53 : power : : 1.2V : : -GNDA_PLL1 : 54 : gnd : : : : -GND : 55 : gnd : : : : -RESERVED_INPUT : 56 : : : : 4 : -RESERVED_INPUT : 57 : : : : 4 : -RESERVED_INPUT : 58 : : : : 4 : -RESERVED_INPUT : 59 : : : : 4 : -RESERVED_INPUT : 60 : : : : 4 : -RESERVED_INPUT : 61 : : : : 4 : -VCCIO4 : 62 : power : : 3.3V : 4 : -RESERVED_INPUT : 63 : : : : 4 : -RESERVED_INPUT : 64 : : : : 4 : -GND : 65 : gnd : : : : -VCCINT : 66 : power : : 1.2V : : -b0 : 67 : input : 3.3-V LVTTL : : 4 : Y -b1 : 68 : input : 3.3-V LVTTL : : 4 : Y -b2 : 69 : input : 3.3-V LVTTL : : 4 : Y -b3 : 70 : input : 3.3-V LVTTL : : 4 : Y -VCCIO4 : 71 : power : : 3.3V : 4 : -b4 : 72 : input : 3.3-V LVTTL : : 4 : Y -GND : 73 : gnd : : : : -b5 : 74 : input : 3.3-V LVTTL : : 4 : Y -b6 : 75 : input : 3.3-V LVTTL : : 4 : Y -b7 : 76 : input : 3.3-V LVTTL : : 4 : Y -a0 : 77 : input : 3.3-V LVTTL : : 4 : Y -GND : 78 : gnd : : : : -VCCINT : 79 : power : : 1.2V : : -a1 : 80 : input : 3.3-V LVTTL : : 4 : Y -a2 : 81 : input : 3.3-V LVTTL : : 4 : Y -a3 : 82 : input : 3.3-V LVTTL : : 4 : Y -VCCIO4 : 83 : power : : 3.3V : 4 : -a4 : 84 : input : 3.3-V LVTTL : : 4 : Y -GND : 85 : gnd : : : : -a5 : 86 : input : 3.3-V LVTTL : : 4 : Y -a6 : 87 : input : 3.3-V LVTTL : : 4 : Y -a7 : 88 : input : 3.3-V LVTTL : : 4 : Y -RESERVED_INPUT : 89 : : : : 4 : -RESERVED_INPUT : 90 : : : : 4 : -VCCIO4 : 91 : power : : 3.3V : 4 : -RESERVED_INPUT : 92 : : : : 4 : -GND : 93 : gnd : : : : -RESERVED_INPUT : 94 : : : : 4 : -RESERVED_INPUT : 95 : : : : 4 : -RESERVED_INPUT : 96 : : : : 4 : -RESERVED_INPUT : 97 : : : : 4 : -VCCIO4 : 98 : power : : 3.3V : 4 : -RESERVED_INPUT : 99 : : : : 4 : -GND : 100 : gnd : : : : -RESERVED_INPUT : 101 : : : : 4 : -RESERVED_INPUT : 102 : : : : 4 : -RESERVED_INPUT : 103 : : : : 4 : -RESERVED_INPUT : 104 : : : : 4 : -RESERVED_INPUT : 105 : : : : 3 : -RESERVED_INPUT : 106 : : : : 3 : -RESERVED_INPUT : 107 : : : : 3 : -~LVDS54p/nCEO~ : 108 : output : 3.3-V LVTTL : : 3 : N -VCCIO3 : 109 : power : : 3.3V : 3 : -RESERVED_INPUT : 110 : : : : 3 : -GND : 111 : gnd : : : : -RESERVED_INPUT : 112 : : : : 3 : -RESERVED_INPUT : 113 : : : : 3 : -RESERVED_INPUT : 114 : : : : 3 : -RESERVED_INPUT : 115 : : : : 3 : -RESERVED_INPUT : 116 : : : : 3 : -RESERVED_INPUT : 117 : : : : 3 : -RESERVED_INPUT : 118 : : : : 3 : -GND : 119 : gnd : : : : -VCCINT : 120 : power : : 1.2V : : -nSTATUS : 121 : : : : 3 : -VCCIO3 : 122 : power : : 3.3V : 3 : -CONF_DONE : 123 : : : : 3 : -GND : 124 : gnd : : : : -MSEL1 : 125 : : : : 3 : -MSEL0 : 126 : : : : 3 : -RESERVED_INPUT : 127 : : : : 3 : -RESERVED_INPUT : 128 : : : : 3 : -GND+ : 129 : : : : 3 : -GND+ : 130 : : : : 3 : -GND+ : 131 : : : : 3 : -GND+ : 132 : : : : 3 : -RESERVED_INPUT : 133 : : : : 3 : -RESERVED_INPUT : 134 : : : : 3 : -RESERVED_INPUT : 135 : : : : 3 : -VCCIO3 : 136 : power : : 3.3V : 3 : -RESERVED_INPUT : 137 : : : : 3 : -RESERVED_INPUT : 138 : : : : 3 : -RESERVED_INPUT : 139 : : : : 3 : -GND : 140 : gnd : : : : -RESERVED_INPUT : 141 : : : : 3 : -Y0 : 142 : output : 3.3-V LVTTL : : 3 : Y -Y1 : 143 : output : 3.3-V LVTTL : : 3 : Y -Y2 : 144 : output : 3.3-V LVTTL : : 3 : Y -Y3 : 145 : output : 3.3-V LVTTL : : 3 : Y -Y4 : 146 : output : 3.3-V LVTTL : : 3 : Y -Y5 : 147 : output : 3.3-V LVTTL : : 3 : Y -VCCIO3 : 148 : power : : 3.3V : 3 : -Y6 : 149 : output : 3.3-V LVTTL : : 3 : Y -Y7 : 150 : output : 3.3-V LVTTL : : 3 : Y -RESERVED_INPUT : 151 : : : : 3 : -RESERVED_INPUT : 152 : : : : 3 : -GND : 153 : gnd : : : : -GND_PLL2 : 154 : gnd : : : : -VCCD_PLL2 : 155 : power : : 1.2V : : -GND_PLL2 : 156 : gnd : : : : -VCCA_PLL2 : 157 : power : : 1.2V : : -GNDA_PLL2 : 158 : gnd : : : : -GND : 159 : gnd : : : : -RESERVED_INPUT : 160 : : : : 2 : -RESERVED_INPUT : 161 : : : : 2 : -RESERVED_INPUT : 162 : : : : 2 : -RESERVED_INPUT : 163 : : : : 2 : -RESERVED_INPUT : 164 : : : : 2 : -RESERVED_INPUT : 165 : : : : 2 : -VCCIO2 : 166 : power : : 3.3V : 2 : -GND : 167 : gnd : : : : -RESERVED_INPUT : 168 : : : : 2 : -RESERVED_INPUT : 169 : : : : 2 : -RESERVED_INPUT : 170 : : : : 2 : -RESERVED_INPUT : 171 : : : : 2 : -VCCIO2 : 172 : power : : 3.3V : 2 : -RESERVED_INPUT : 173 : : : : 2 : -GND : 174 : gnd : : : : -RESERVED_INPUT : 175 : : : : 2 : -RESERVED_INPUT : 176 : : : : 2 : -GND : 177 : gnd : : : : -VCCINT : 178 : power : : 1.2V : : -RESERVED_INPUT : 179 : : : : 2 : -RESERVED_INPUT : 180 : : : : 2 : -RESERVED_INPUT : 181 : : : : 2 : -RESERVED_INPUT : 182 : : : : 2 : -VCCIO2 : 183 : power : : 3.3V : 2 : -GND : 184 : gnd : : : : -RESERVED_INPUT : 185 : : : : 2 : -GND : 186 : gnd : : : : -RESERVED_INPUT : 187 : : : : 2 : -RESERVED_INPUT : 188 : : : : 2 : -RESERVED_INPUT : 189 : : : : 2 : -VCCINT : 190 : power : : 1.2V : : -RESERVED_INPUT : 191 : : : : 2 : -RESERVED_INPUT : 192 : : : : 2 : -RESERVED_INPUT : 193 : : : : 2 : -VCCIO2 : 194 : power : : 3.3V : 2 : -RESERVED_INPUT : 195 : : : : 2 : -GND : 196 : gnd : : : : -RESERVED_INPUT : 197 : : : : 2 : -RESERVED_INPUT : 198 : : : : 2 : -RESERVED_INPUT : 199 : : : : 2 : -RESERVED_INPUT : 200 : : : : 2 : -RESERVED_INPUT : 201 : : : : 2 : -VCCIO2 : 202 : power : : 3.3V : 2 : -RESERVED_INPUT : 203 : : : : 2 : -GND : 204 : gnd : : : : -RESERVED_INPUT : 205 : : : : 2 : -RESERVED_INPUT : 206 : : : : 2 : -RESERVED_INPUT : 207 : : : : 2 : -RESERVED_INPUT : 208 : : : : 2 : diff --git a/double_selector_8b/double_selector_8b.pof b/double_selector_8b/double_selector_8b.pof deleted file mode 100644 index 00ffa17..0000000 Binary files a/double_selector_8b/double_selector_8b.pof and /dev/null differ diff --git a/double_selector_8b/double_selector_8b.qws b/double_selector_8b/double_selector_8b.qws deleted file mode 100644 index b5f620c..0000000 --- a/double_selector_8b/double_selector_8b.qws +++ /dev/null @@ -1,14 +0,0 @@ -[ProjectWorkspace] -ptn_Child1=Frames -[ProjectWorkspace.Frames] -ptn_Child1=ChildFrames -[ProjectWorkspace.Frames.ChildFrames] -ptn_Child1=Document-0 -[ProjectWorkspace.Frames.ChildFrames.Document-0] -ptn_Child1=ViewFrame-0 -[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0] -DocPathName=double_selector_8b.bdf -DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde} -IsChildFrameDetached=False -IsActiveChildFrame=True -ptn_Child1=StateMap diff --git a/double_selector_8b/double_selector_8b.sof b/double_selector_8b/double_selector_8b.sof deleted file mode 100644 index 45626a8..0000000 Binary files a/double_selector_8b/double_selector_8b.sof and /dev/null differ diff --git a/double_selector_8b/double_selector_8b.tan.rpt b/double_selector_8b/double_selector_8b.tan.rpt deleted file mode 100644 index b33f819..0000000 --- a/double_selector_8b/double_selector_8b.tan.rpt +++ /dev/null @@ -1,157 +0,0 @@ -Classic Timing Analyzer report for double_selector_8b -Mon Mar 07 11:22:47 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Timing Analyzer Summary - 3. Timing Analyzer Settings - 4. Parallel Compilation - 5. tpd - 6. Timing Analyzer Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------------------------------------------------+ -; Timing Analyzer Summary ; -+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ -; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; -+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ -; Worst-case tpd ; N/A ; None ; 14.785 ns ; b6 ; Y6 ; -- ; -- ; 0 ; -; Total number of failed paths ; ; ; ; ; ; ; ; 0 ; -+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ - - -+--------------------------------------------------------------------------------------------------------------------+ -; Timing Analyzer Settings ; -+---------------------------------------------------------------------+--------------------+------+----+-------------+ -; Option ; Setting ; From ; To ; Entity Name ; -+---------------------------------------------------------------------+--------------------+------+----+-------------+ -; Device Name ; EP2C8Q208C8 ; ; ; ; -; Timing Models ; Final ; ; ; ; -; Default hold multicycle ; Same as Multicycle ; ; ; ; -; Cut paths between unrelated clock domains ; On ; ; ; ; -; Cut off read during write signal paths ; On ; ; ; ; -; Cut off feedback from I/O pins ; On ; ; ; ; -; Report Combined Fast/Slow Timing ; Off ; ; ; ; -; Ignore Clock Settings ; Off ; ; ; ; -; Analyze latches as synchronous elements ; On ; ; ; ; -; Enable Recovery/Removal analysis ; Off ; ; ; ; -; Enable Clock Latency ; Off ; ; ; ; -; Use TimeQuest Timing Analyzer ; Off ; ; ; ; -; Minimum Core Junction Temperature ; 0 ; ; ; ; -; Maximum Core Junction Temperature ; 85 ; ; ; ; -; Number of source nodes to report per destination node ; 10 ; ; ; ; -; Number of destination nodes to report ; 10 ; ; ; ; -; Number of paths to report ; 200 ; ; ; ; -; Report Minimum Timing Checks ; Off ; ; ; ; -; Use Fast Timing Models ; Off ; ; ; ; -; Report IO Paths Separately ; Off ; ; ; ; -; Perform Multicorner Analysis ; On ; ; ; ; -; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ; -; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ; -; Output I/O Timing Endpoint ; Near End ; ; ; ; -+---------------------------------------------------------------------+--------------------+------+----+-------------+ - - -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 4 ; -; Maximum allowed ; 4 ; -; ; ; -; Average used ; 1.00 ; -; Maximum used ; 1 ; -; ; ; -; Usage by Processor ; % Time Used ; -; 1 processor ; 100.0% ; -; 2-4 processors ; 0.0% ; -+----------------------------+-------------+ - - -+---------------------------------------------------------+ -; tpd ; -+-------+-------------------+-----------------+------+----+ -; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ; -+-------+-------------------+-----------------+------+----+ -; N/A ; None ; 14.785 ns ; b6 ; Y6 ; -; N/A ; None ; 14.732 ns ; b5 ; Y5 ; -; N/A ; None ; 14.623 ns ; b0 ; Y0 ; -; N/A ; None ; 14.408 ns ; b4 ; Y4 ; -; N/A ; None ; 14.174 ns ; b1 ; Y1 ; -; N/A ; None ; 14.155 ns ; b7 ; Y7 ; -; N/A ; None ; 14.070 ns ; b2 ; Y2 ; -; N/A ; None ; 14.007 ns ; b3 ; Y3 ; -; N/A ; None ; 13.636 ns ; a0 ; Y0 ; -; N/A ; None ; 13.392 ns ; a6 ; Y6 ; -; N/A ; None ; 13.327 ns ; a5 ; Y5 ; -; N/A ; None ; 13.142 ns ; a3 ; Y3 ; -; N/A ; None ; 13.132 ns ; a2 ; Y2 ; -; N/A ; None ; 12.984 ns ; a7 ; Y7 ; -; N/A ; None ; 12.917 ns ; a4 ; Y4 ; -; N/A ; None ; 12.863 ns ; a1 ; Y1 ; -; N/A ; None ; 10.926 ns ; AY ; Y6 ; -; N/A ; None ; 10.880 ns ; AY ; Y5 ; -; N/A ; None ; 10.740 ns ; BY ; Y6 ; -; N/A ; None ; 10.694 ns ; BY ; Y5 ; -; N/A ; None ; 10.632 ns ; BY ; Y3 ; -; N/A ; None ; 10.630 ns ; BY ; Y2 ; -; N/A ; None ; 10.571 ns ; BY ; Y1 ; -; N/A ; None ; 10.534 ns ; AY ; Y7 ; -; N/A ; None ; 10.528 ns ; AY ; Y3 ; -; N/A ; None ; 10.506 ns ; AY ; Y2 ; -; N/A ; None ; 10.484 ns ; AY ; Y0 ; -; N/A ; None ; 10.463 ns ; AY ; Y4 ; -; N/A ; None ; 10.459 ns ; AY ; Y1 ; -; N/A ; None ; 10.346 ns ; BY ; Y7 ; -; N/A ; None ; 10.288 ns ; BY ; Y4 ; -; N/A ; None ; 10.285 ns ; BY ; Y0 ; -+-------+-------------------+-----------------+------+----+ - - -+--------------------------+ -; Timing Analyzer Messages ; -+--------------------------+ -Info: ******************************************************************* -Info: Running Quartus II Classic Timing Analyzer - Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Mon Mar 07 11:22:47 2022 -Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b --timing_analysis_only -Info: Parallel compilation is enabled and will use 4 of the 4 processors detected -Info: Longest tpd from source pin "b6" to destination pin "Y6" is 14.785 ns - Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_75; Fanout = 1; PIN Node = 'b6' - Info: 2: + IC(6.679 ns) + CELL(0.651 ns) = 8.304 ns; Loc. = LCCOMB_X25_Y2_N12; Fanout = 1; COMB Node = 'inst7' - Info: 3: + IC(3.365 ns) + CELL(3.116 ns) = 14.785 ns; Loc. = PIN_149; Fanout = 0; PIN Node = 'Y6' - Info: Total cell delay = 4.741 ns ( 32.07 % ) - Info: Total interconnect delay = 10.044 ns ( 67.93 % ) -Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 212 megabytes - Info: Processing ended: Mon Mar 07 11:22:47 2022 - Info: Elapsed time: 00:00:00 - Info: Total CPU time (on all processors): 00:00:00 - - diff --git a/double_selector_8b/double_selector_8b.tan.summary b/double_selector_8b/double_selector_8b.tan.summary deleted file mode 100644 index e39f4c1..0000000 --- a/double_selector_8b/double_selector_8b.tan.summary +++ /dev/null @@ -1,26 +0,0 @@ --------------------------------------------------------------------------------------- -Timing Analyzer Summary --------------------------------------------------------------------------------------- - -Type : Worst-case tpd -Slack : N/A -Required Time : None -Actual Time : 14.785 ns -From : b6 -To : Y6 -From Clock : -- -To Clock : -- -Failed Paths : 0 - -Type : Total number of failed paths -Slack : -Required Time : -Actual Time : -From : -To : -From Clock : -To Clock : -Failed Paths : 0 - --------------------------------------------------------------------------------------- - diff --git a/double_selector_8b/incremental_db/README b/double_selector_8b/incremental_db/README deleted file mode 100644 index 9f62dcd..0000000 --- a/double_selector_8b/incremental_db/README +++ /dev/null @@ -1,11 +0,0 @@ -This folder contains data for incremental compilation. - -The compiled_partitions sub-folder contains previous compilation results for each partition. -As long as this folder is preserved, incremental compilation results from earlier compiles -can be re-used. To perform a clean compilation from source files for all partitions, both -the db and incremental_db folder should be removed. - -The imported_partitions sub-folder contains the last imported QXP for each imported partition. -As long as this folder is preserved, imported partitions will be automatically re-imported -when the db or incremental_db/compiled_partitions folders are removed. - diff --git a/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.atm b/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.atm deleted file mode 100644 index 42a32b0..0000000 Binary files a/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.atm and /dev/null differ diff --git a/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.dfp b/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.dfp deleted file mode 100644 index b1c67d6..0000000 Binary files a/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.dfp and /dev/null differ diff --git a/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.hdbx b/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.hdbx deleted file mode 100644 index 0761db7..0000000 Binary files a/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.hdbx and /dev/null differ diff --git a/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.kpt b/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.kpt deleted file mode 100644 index c1e72d7..0000000 --- a/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.kpt +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.logdb b/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.logdb deleted file mode 100644 index 626799f..0000000 --- a/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.rcf b/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.rcf deleted file mode 100644 index c2c32ef..0000000 Binary files a/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.rcf and /dev/null differ diff --git a/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.map.atm b/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.map.atm deleted file mode 100644 index e61f1f0..0000000 Binary files a/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.map.atm and /dev/null differ diff --git a/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.map.dpi b/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.map.dpi deleted file mode 100644 index 5d6b23c..0000000 Binary files a/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.map.dpi and /dev/null differ diff --git a/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.map.hdbx b/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.map.hdbx deleted file mode 100644 index e717b3a..0000000 Binary files a/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.map.hdbx and /dev/null differ diff --git a/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.map.kpt b/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.map.kpt deleted file mode 100644 index 94168b0..0000000 --- a/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.map.kpt +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/register_8b/db/prev_cmp_register_8b.asm.qmsg b/register_8b/db/prev_cmp_register_8b.asm.qmsg deleted file mode 100644 index 6284d55..0000000 --- a/register_8b/db/prev_cmp_register_8b.asm.qmsg +++ /dev/null @@ -1,7 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:08:36 2022 " "Info: Processing started: Tue Mar 08 15:08:36 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off register_8b -c register_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off register_8b -c register_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1} -{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:08:36 2022 " "Info: Processing ended: Tue Mar 08 15:08:36 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/register_8b/db/prev_cmp_register_8b.fit.qmsg b/register_8b/db/prev_cmp_register_8b.fit.qmsg deleted file mode 100644 index 35bea3b..0000000 --- a/register_8b/db/prev_cmp_register_8b.fit.qmsg +++ /dev/null @@ -1,36 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:08:34 2022 " "Info: Processing started: Tue Mar 08 15:08:34 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off register_8b -c register_8b " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off register_8b -c register_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "IMPP_MPP_USER_DEVICE" "register_8b EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"register_8b\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1} -{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1} -{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y10 X34_Y19 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y10 to location X34_Y19" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} -{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q7 0 " "Info: Pin \"Q7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q6 0 " "Info: Pin \"Q6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q5 0 " "Info: Pin \"Q5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q4 0 " "Info: Pin \"Q4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q3 0 " "Info: Pin \"Q3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q2 0 " "Info: Pin \"Q2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q1 0 " "Info: Pin \"Q1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q0 0 " "Info: Pin \"Q0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/register_8b/register_8b.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/register_8b/register_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "306 " "Info: Peak virtual memory: 306 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:08:35 2022 " "Info: Processing ended: Tue Mar 08 15:08:35 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/register_8b/db/prev_cmp_register_8b.map.qmsg b/register_8b/db/prev_cmp_register_8b.map.qmsg deleted file mode 100644 index ca9da1d..0000000 --- a/register_8b/db/prev_cmp_register_8b.map.qmsg +++ /dev/null @@ -1,7 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:08:32 2022 " "Info: Processing started: Tue Mar 08 15:08:32 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off register_8b -c register_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off register_8b -c register_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "register_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file register_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 register_8b " "Info: Found entity 1: register_8b" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_START_ELABORATION_TOP" "register_8b " "Info: Elaborating entity \"register_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_TM_SUMMARY" "26 " "Info: Implemented 26 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Info: Implemented 10 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:08:33 2022 " "Info: Processing ended: Tue Mar 08 15:08:33 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/register_8b/db/prev_cmp_register_8b.qmsg b/register_8b/db/prev_cmp_register_8b.qmsg deleted file mode 100644 index 06cbfd4..0000000 --- a/register_8b/db/prev_cmp_register_8b.qmsg +++ /dev/null @@ -1,61 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:08:32 2022 " "Info: Processing started: Tue Mar 08 15:08:32 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off register_8b -c register_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off register_8b -c register_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "register_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file register_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 register_8b " "Info: Found entity 1: register_8b" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_START_ELABORATION_TOP" "register_8b " "Info: Elaborating entity \"register_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_TM_SUMMARY" "26 " "Info: Implemented 26 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Info: Implemented 10 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:08:33 2022 " "Info: Processing ended: Tue Mar 08 15:08:33 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:08:34 2022 " "Info: Processing started: Tue Mar 08 15:08:34 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off register_8b -c register_8b " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off register_8b -c register_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "IMPP_MPP_USER_DEVICE" "register_8b EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"register_8b\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1} -{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1} -{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y10 X34_Y19 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y10 to location X34_Y19" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} -{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q7 0 " "Info: Pin \"Q7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q6 0 " "Info: Pin \"Q6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q5 0 " "Info: Pin \"Q5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q4 0 " "Info: Pin \"Q4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q3 0 " "Info: Pin \"Q3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q2 0 " "Info: Pin \"Q2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q1 0 " "Info: Pin \"Q1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q0 0 " "Info: Pin \"Q0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/register_8b/register_8b.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/register_8b/register_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "306 " "Info: Peak virtual memory: 306 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:08:35 2022 " "Info: Processing ended: Tue Mar 08 15:08:35 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:08:36 2022 " "Info: Processing started: Tue Mar 08 15:08:36 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off register_8b -c register_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off register_8b -c register_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1} -{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:08:36 2022 " "Info: Processing ended: Tue Mar 08 15:08:36 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:08:37 2022 " "Info: Processing started: Tue Mar 08 15:08:37 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off register_8b -c register_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off register_8b -c register_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CP " "Info: Assuming node \"CP\" is an undefined clock" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } { "d:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CP" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1} -{ "Info" "ITAN_NO_REG2REG_EXIST" "CP " "Info: No valid register-to-register data paths exist for clock \"CP\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0 -1} -{ "Info" "ITDB_TSU_RESULT" "inst8 D0 CP 3.273 ns register " "Info: tsu for register \"inst8\" (data pin = \"D0\", clock pin = \"CP\") is 3.273 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.692 ns + Longest pin register " "Info: + Longest pin to register delay is 7.692 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns D0 1 PIN PIN_77 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_77; Fanout = 1; PIN Node = 'D0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { D0 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 752 32 200 768 "D0" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.404 ns) + CELL(0.206 ns) 7.584 ns inst8~feeder 2 COMB LCCOMB_X25_Y1_N22 1 " "Info: 2: + IC(6.404 ns) + CELL(0.206 ns) = 7.584 ns; Loc. = LCCOMB_X25_Y1_N22; Fanout = 1; COMB Node = 'inst8~feeder'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.610 ns" { D0 inst8~feeder } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 736 344 408 816 "inst8" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.692 ns inst8 3 REG LCFF_X25_Y1_N23 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.692 ns; Loc. = LCFF_X25_Y1_N23; Fanout = 1; REG Node = 'inst8'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { inst8~feeder inst8 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 736 344 408 816 "inst8" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.288 ns ( 16.74 % ) " "Info: Total cell delay = 1.288 ns ( 16.74 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.404 ns ( 83.26 % ) " "Info: Total interconnect delay = 6.404 ns ( 83.26 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.692 ns" { D0 inst8~feeder inst8 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "7.692 ns" { D0 {} D0~combout {} inst8~feeder {} inst8 {} } { 0.000ns 0.000ns 6.404ns 0.000ns } { 0.000ns 0.974ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 736 344 408 816 "inst8" "" } } } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CP destination 4.379 ns - Shortest register " "Info: - Shortest clock path from clock \"CP\" to destination register is 4.379 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns CP 1 CLK PIN_67 8 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CP } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.719 ns) + CELL(0.666 ns) 4.379 ns inst8 2 REG LCFF_X25_Y1_N23 1 " "Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N23; Fanout = 1; REG Node = 'inst8'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.385 ns" { CP inst8 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 736 344 408 816 "inst8" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 37.91 % ) " "Info: Total cell delay = 1.660 ns ( 37.91 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.719 ns ( 62.09 % ) " "Info: Total interconnect delay = 2.719 ns ( 62.09 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst8 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst8 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.692 ns" { D0 inst8~feeder inst8 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "7.692 ns" { D0 {} D0~combout {} inst8~feeder {} inst8 {} } { 0.000ns 0.000ns 6.404ns 0.000ns } { 0.000ns 0.974ns 0.206ns 0.108ns } "" } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst8 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst8 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1} -{ "Info" "ITDB_FULL_TCO_RESULT" "CP Q5 inst3 11.227 ns register " "Info: tco from clock \"CP\" to destination pin \"Q5\" through register \"inst3\" is 11.227 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CP source 4.379 ns + Longest register " "Info: + Longest clock path from clock \"CP\" to source register is 4.379 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns CP 1 CLK PIN_67 8 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CP } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.719 ns) + CELL(0.666 ns) 4.379 ns inst3 2 REG LCFF_X25_Y1_N29 1 " "Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.385 ns" { CP inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 37.91 % ) " "Info: Total cell delay = 1.660 ns ( 37.91 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.719 ns ( 62.09 % ) " "Info: Total interconnect delay = 2.719 ns ( 62.09 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst3 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.544 ns + Longest register pin " "Info: + Longest register to pin delay is 6.544 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst3 1 REG LCFF_X25_Y1_N29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.428 ns) + CELL(3.116 ns) 6.544 ns Q5 2 PIN PIN_147 0 " "Info: 2: + IC(3.428 ns) + CELL(3.116 ns) = 6.544 ns; Loc. = PIN_147; Fanout = 0; PIN Node = 'Q5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.544 ns" { inst3 Q5 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 272 464 640 288 "Q5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.116 ns ( 47.62 % ) " "Info: Total cell delay = 3.116 ns ( 47.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.428 ns ( 52.38 % ) " "Info: Total interconnect delay = 3.428 ns ( 52.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.544 ns" { inst3 Q5 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.544 ns" { inst3 {} Q5 {} } { 0.000ns 3.428ns } { 0.000ns 3.116ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst3 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.544 ns" { inst3 Q5 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.544 ns" { inst3 {} Q5 {} } { 0.000ns 3.428ns } { 0.000ns 3.116ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1} -{ "Info" "ITDB_TH_RESULT" "inst3 D5 CP -2.294 ns register " "Info: th for register \"inst3\" (data pin = \"D5\", clock pin = \"CP\") is -2.294 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CP destination 4.379 ns + Longest register " "Info: + Longest clock path from clock \"CP\" to destination register is 4.379 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns CP 1 CLK PIN_67 8 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CP } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.719 ns) + CELL(0.666 ns) 4.379 ns inst3 2 REG LCFF_X25_Y1_N29 1 " "Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.385 ns" { CP inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 37.91 % ) " "Info: Total cell delay = 1.660 ns ( 37.91 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.719 ns ( 62.09 % ) " "Info: Total interconnect delay = 2.719 ns ( 62.09 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst3 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.979 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.979 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.964 ns) 0.964 ns D5 1 PIN PIN_86 1 " "Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_86; Fanout = 1; PIN Node = 'D5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { D5 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 272 32 200 288 "D5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.701 ns) + CELL(0.206 ns) 6.871 ns inst3~feeder 2 COMB LCCOMB_X25_Y1_N28 1 " "Info: 2: + IC(5.701 ns) + CELL(0.206 ns) = 6.871 ns; Loc. = LCCOMB_X25_Y1_N28; Fanout = 1; COMB Node = 'inst3~feeder'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.907 ns" { D5 inst3~feeder } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 6.979 ns inst3 3 REG LCFF_X25_Y1_N29 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 6.979 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { inst3~feeder inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.278 ns ( 18.31 % ) " "Info: Total cell delay = 1.278 ns ( 18.31 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.701 ns ( 81.69 % ) " "Info: Total interconnect delay = 5.701 ns ( 81.69 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.979 ns" { D5 inst3~feeder inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.979 ns" { D5 {} D5~combout {} inst3~feeder {} inst3 {} } { 0.000ns 0.000ns 5.701ns 0.000ns } { 0.000ns 0.964ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst3 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.979 ns" { D5 inst3~feeder inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.979 ns" { D5 {} D5~combout {} inst3~feeder {} inst3 {} } { 0.000ns 0.000ns 5.701ns 0.000ns } { 0.000ns 0.964ns 0.206ns 0.108ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:08:37 2022 " "Info: Processing ended: Tue Mar 08 15:08:37 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 3 s " "Info: Quartus II Full Compilation was successful. 0 errors, 3 warnings" { } { } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/register_8b/db/prev_cmp_register_8b.tan.qmsg b/register_8b/db/prev_cmp_register_8b.tan.qmsg deleted file mode 100644 index 805fd16..0000000 --- a/register_8b/db/prev_cmp_register_8b.tan.qmsg +++ /dev/null @@ -1,10 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:08:37 2022 " "Info: Processing started: Tue Mar 08 15:08:37 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off register_8b -c register_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off register_8b -c register_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CP " "Info: Assuming node \"CP\" is an undefined clock" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } { "d:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CP" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1} -{ "Info" "ITAN_NO_REG2REG_EXIST" "CP " "Info: No valid register-to-register data paths exist for clock \"CP\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0 -1} -{ "Info" "ITDB_TSU_RESULT" "inst8 D0 CP 3.273 ns register " "Info: tsu for register \"inst8\" (data pin = \"D0\", clock pin = \"CP\") is 3.273 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.692 ns + Longest pin register " "Info: + Longest pin to register delay is 7.692 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns D0 1 PIN PIN_77 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_77; Fanout = 1; PIN Node = 'D0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { D0 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 752 32 200 768 "D0" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.404 ns) + CELL(0.206 ns) 7.584 ns inst8~feeder 2 COMB LCCOMB_X25_Y1_N22 1 " "Info: 2: + IC(6.404 ns) + CELL(0.206 ns) = 7.584 ns; Loc. = LCCOMB_X25_Y1_N22; Fanout = 1; COMB Node = 'inst8~feeder'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.610 ns" { D0 inst8~feeder } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 736 344 408 816 "inst8" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.692 ns inst8 3 REG LCFF_X25_Y1_N23 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.692 ns; Loc. = LCFF_X25_Y1_N23; Fanout = 1; REG Node = 'inst8'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { inst8~feeder inst8 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 736 344 408 816 "inst8" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.288 ns ( 16.74 % ) " "Info: Total cell delay = 1.288 ns ( 16.74 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.404 ns ( 83.26 % ) " "Info: Total interconnect delay = 6.404 ns ( 83.26 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.692 ns" { D0 inst8~feeder inst8 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "7.692 ns" { D0 {} D0~combout {} inst8~feeder {} inst8 {} } { 0.000ns 0.000ns 6.404ns 0.000ns } { 0.000ns 0.974ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 736 344 408 816 "inst8" "" } } } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CP destination 4.379 ns - Shortest register " "Info: - Shortest clock path from clock \"CP\" to destination register is 4.379 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns CP 1 CLK PIN_67 8 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CP } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.719 ns) + CELL(0.666 ns) 4.379 ns inst8 2 REG LCFF_X25_Y1_N23 1 " "Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N23; Fanout = 1; REG Node = 'inst8'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.385 ns" { CP inst8 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 736 344 408 816 "inst8" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 37.91 % ) " "Info: Total cell delay = 1.660 ns ( 37.91 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.719 ns ( 62.09 % ) " "Info: Total interconnect delay = 2.719 ns ( 62.09 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst8 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst8 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.692 ns" { D0 inst8~feeder inst8 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "7.692 ns" { D0 {} D0~combout {} inst8~feeder {} inst8 {} } { 0.000ns 0.000ns 6.404ns 0.000ns } { 0.000ns 0.974ns 0.206ns 0.108ns } "" } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst8 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst8 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1} -{ "Info" "ITDB_FULL_TCO_RESULT" "CP Q5 inst3 11.227 ns register " "Info: tco from clock \"CP\" to destination pin \"Q5\" through register \"inst3\" is 11.227 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CP source 4.379 ns + Longest register " "Info: + Longest clock path from clock \"CP\" to source register is 4.379 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns CP 1 CLK PIN_67 8 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CP } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.719 ns) + CELL(0.666 ns) 4.379 ns inst3 2 REG LCFF_X25_Y1_N29 1 " "Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.385 ns" { CP inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 37.91 % ) " "Info: Total cell delay = 1.660 ns ( 37.91 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.719 ns ( 62.09 % ) " "Info: Total interconnect delay = 2.719 ns ( 62.09 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst3 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.544 ns + Longest register pin " "Info: + Longest register to pin delay is 6.544 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst3 1 REG LCFF_X25_Y1_N29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.428 ns) + CELL(3.116 ns) 6.544 ns Q5 2 PIN PIN_147 0 " "Info: 2: + IC(3.428 ns) + CELL(3.116 ns) = 6.544 ns; Loc. = PIN_147; Fanout = 0; PIN Node = 'Q5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.544 ns" { inst3 Q5 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 272 464 640 288 "Q5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.116 ns ( 47.62 % ) " "Info: Total cell delay = 3.116 ns ( 47.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.428 ns ( 52.38 % ) " "Info: Total interconnect delay = 3.428 ns ( 52.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.544 ns" { inst3 Q5 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.544 ns" { inst3 {} Q5 {} } { 0.000ns 3.428ns } { 0.000ns 3.116ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst3 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.544 ns" { inst3 Q5 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.544 ns" { inst3 {} Q5 {} } { 0.000ns 3.428ns } { 0.000ns 3.116ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1} -{ "Info" "ITDB_TH_RESULT" "inst3 D5 CP -2.294 ns register " "Info: th for register \"inst3\" (data pin = \"D5\", clock pin = \"CP\") is -2.294 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CP destination 4.379 ns + Longest register " "Info: + Longest clock path from clock \"CP\" to destination register is 4.379 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns CP 1 CLK PIN_67 8 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CP } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.719 ns) + CELL(0.666 ns) 4.379 ns inst3 2 REG LCFF_X25_Y1_N29 1 " "Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.385 ns" { CP inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 37.91 % ) " "Info: Total cell delay = 1.660 ns ( 37.91 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.719 ns ( 62.09 % ) " "Info: Total interconnect delay = 2.719 ns ( 62.09 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst3 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.979 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.979 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.964 ns) 0.964 ns D5 1 PIN PIN_86 1 " "Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_86; Fanout = 1; PIN Node = 'D5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { D5 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 272 32 200 288 "D5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.701 ns) + CELL(0.206 ns) 6.871 ns inst3~feeder 2 COMB LCCOMB_X25_Y1_N28 1 " "Info: 2: + IC(5.701 ns) + CELL(0.206 ns) = 6.871 ns; Loc. = LCCOMB_X25_Y1_N28; Fanout = 1; COMB Node = 'inst3~feeder'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.907 ns" { D5 inst3~feeder } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 6.979 ns inst3 3 REG LCFF_X25_Y1_N29 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 6.979 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { inst3~feeder inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.278 ns ( 18.31 % ) " "Info: Total cell delay = 1.278 ns ( 18.31 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.701 ns ( 81.69 % ) " "Info: Total interconnect delay = 5.701 ns ( 81.69 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.979 ns" { D5 inst3~feeder inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.979 ns" { D5 {} D5~combout {} inst3~feeder {} inst3 {} } { 0.000ns 0.000ns 5.701ns 0.000ns } { 0.000ns 0.964ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst3 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.979 ns" { D5 inst3~feeder inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.979 ns" { D5 {} D5~combout {} inst3~feeder {} inst3 {} } { 0.000ns 0.000ns 5.701ns 0.000ns } { 0.000ns 0.964ns 0.206ns 0.108ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:08:37 2022 " "Info: Processing ended: Tue Mar 08 15:08:37 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/register_8b/db/register_8b.(0).cnf.cdb b/register_8b/db/register_8b.(0).cnf.cdb deleted file mode 100644 index 252bdf3..0000000 Binary files a/register_8b/db/register_8b.(0).cnf.cdb and /dev/null differ diff --git a/register_8b/db/register_8b.(0).cnf.hdb b/register_8b/db/register_8b.(0).cnf.hdb deleted file mode 100644 index 7f81ca7..0000000 Binary files a/register_8b/db/register_8b.(0).cnf.hdb and /dev/null differ diff --git a/register_8b/db/register_8b.asm.qmsg b/register_8b/db/register_8b.asm.qmsg deleted file mode 100644 index e8d2711..0000000 --- a/register_8b/db/register_8b.asm.qmsg +++ /dev/null @@ -1,7 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:08:52 2022 " "Info: Processing started: Tue Mar 08 15:08:52 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off register_8b -c register_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off register_8b -c register_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1} -{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:08:53 2022 " "Info: Processing ended: Tue Mar 08 15:08:53 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/register_8b/db/register_8b.asm_labs.ddb b/register_8b/db/register_8b.asm_labs.ddb deleted file mode 100644 index 9db65b1..0000000 Binary files a/register_8b/db/register_8b.asm_labs.ddb and /dev/null differ diff --git a/register_8b/db/register_8b.cbx.xml b/register_8b/db/register_8b.cbx.xml deleted file mode 100644 index 1794d22..0000000 --- a/register_8b/db/register_8b.cbx.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/register_8b/db/register_8b.cmp.bpm b/register_8b/db/register_8b.cmp.bpm deleted file mode 100644 index ccaf79b..0000000 Binary files a/register_8b/db/register_8b.cmp.bpm and /dev/null differ diff --git a/register_8b/db/register_8b.cmp.cdb b/register_8b/db/register_8b.cmp.cdb deleted file mode 100644 index 4b976f3..0000000 Binary files a/register_8b/db/register_8b.cmp.cdb and /dev/null differ diff --git a/register_8b/db/register_8b.cmp.ecobp b/register_8b/db/register_8b.cmp.ecobp deleted file mode 100644 index e05efff..0000000 Binary files a/register_8b/db/register_8b.cmp.ecobp and /dev/null differ diff --git a/register_8b/db/register_8b.cmp.hdb b/register_8b/db/register_8b.cmp.hdb deleted file mode 100644 index e0b4dcf..0000000 Binary files a/register_8b/db/register_8b.cmp.hdb and /dev/null differ diff --git a/register_8b/db/register_8b.cmp.kpt b/register_8b/db/register_8b.cmp.kpt deleted file mode 100644 index 7dcef92..0000000 --- a/register_8b/db/register_8b.cmp.kpt +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/register_8b/db/register_8b.cmp.logdb b/register_8b/db/register_8b.cmp.logdb deleted file mode 100644 index 626799f..0000000 --- a/register_8b/db/register_8b.cmp.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/register_8b/db/register_8b.cmp.rdb b/register_8b/db/register_8b.cmp.rdb deleted file mode 100644 index 73b57b3..0000000 Binary files a/register_8b/db/register_8b.cmp.rdb and /dev/null differ diff --git a/register_8b/db/register_8b.cmp.tdb b/register_8b/db/register_8b.cmp.tdb deleted file mode 100644 index 36da105..0000000 Binary files a/register_8b/db/register_8b.cmp.tdb and /dev/null differ diff --git a/register_8b/db/register_8b.cmp0.ddb b/register_8b/db/register_8b.cmp0.ddb deleted file mode 100644 index ca24315..0000000 Binary files a/register_8b/db/register_8b.cmp0.ddb and /dev/null differ diff --git a/register_8b/db/register_8b.cmp2.ddb b/register_8b/db/register_8b.cmp2.ddb deleted file mode 100644 index 59a9cbf..0000000 Binary files a/register_8b/db/register_8b.cmp2.ddb and /dev/null differ diff --git a/register_8b/db/register_8b.cmp_merge.kpt b/register_8b/db/register_8b.cmp_merge.kpt deleted file mode 100644 index 901c895..0000000 --- a/register_8b/db/register_8b.cmp_merge.kpt +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/register_8b/db/register_8b.db_info b/register_8b/db/register_8b.db_info deleted file mode 100644 index 12b4a80..0000000 --- a/register_8b/db/register_8b.db_info +++ /dev/null @@ -1,3 +0,0 @@ -Quartus_Version = Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition -Version_Index = 167832322 -Creation_Time = Mon Mar 07 09:08:50 2022 diff --git a/register_8b/db/register_8b.eco.cdb b/register_8b/db/register_8b.eco.cdb deleted file mode 100644 index 6612017..0000000 Binary files a/register_8b/db/register_8b.eco.cdb and /dev/null differ diff --git a/register_8b/db/register_8b.fit.qmsg b/register_8b/db/register_8b.fit.qmsg deleted file mode 100644 index 6411368..0000000 --- a/register_8b/db/register_8b.fit.qmsg +++ /dev/null @@ -1,35 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:08:50 2022 " "Info: Processing started: Tue Mar 08 15:08:50 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off register_8b -c register_8b " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off register_8b -c register_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "IMPP_MPP_USER_DEVICE" "register_8b EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"register_8b\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1} -{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1} -{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y10 X34_Y19 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y10 to location X34_Y19" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} -{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q7 0 " "Info: Pin \"Q7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q6 0 " "Info: Pin \"Q6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q5 0 " "Info: Pin \"Q5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q4 0 " "Info: Pin \"Q4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q3 0 " "Info: Pin \"Q3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q2 0 " "Info: Pin \"Q2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q1 0 " "Info: Pin \"Q1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Q0 0 " "Info: Pin \"Q0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/register_8b/register_8b.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/register_8b/register_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "306 " "Info: Peak virtual memory: 306 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:08:51 2022 " "Info: Processing ended: Tue Mar 08 15:08:51 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/register_8b/db/register_8b.hier_info b/register_8b/db/register_8b.hier_info deleted file mode 100644 index 82fc478..0000000 --- a/register_8b/db/register_8b.hier_info +++ /dev/null @@ -1,43 +0,0 @@ -|register_8b -Q7 <= inst.DB_MAX_OUTPUT_PORT_TYPE -CLR => inst.ACLR -CLR => inst.PRESET -CLR => inst2.ACLR -CLR => inst2.PRESET -CLR => inst3.ACLR -CLR => inst3.PRESET -CLR => inst4.ACLR -CLR => inst4.PRESET -CLR => inst5.ACLR -CLR => inst5.PRESET -CLR => inst6.ACLR -CLR => inst6.PRESET -CLR => inst7.ACLR -CLR => inst7.PRESET -CLR => inst8.ACLR -CLR => inst8.PRESET -CP => inst.CLK -CP => inst2.CLK -CP => inst3.CLK -CP => inst4.CLK -CP => inst5.CLK -CP => inst6.CLK -CP => inst7.CLK -CP => inst8.CLK -D7 => inst.DATAIN -Q6 <= inst2.DB_MAX_OUTPUT_PORT_TYPE -D6 => inst2.DATAIN -Q5 <= inst3.DB_MAX_OUTPUT_PORT_TYPE -D5 => inst3.DATAIN -Q4 <= inst4.DB_MAX_OUTPUT_PORT_TYPE -D4 => inst4.DATAIN -Q3 <= inst5.DB_MAX_OUTPUT_PORT_TYPE -D3 => inst5.DATAIN -Q2 <= inst6.DB_MAX_OUTPUT_PORT_TYPE -D2 => inst6.DATAIN -Q1 <= inst7.DB_MAX_OUTPUT_PORT_TYPE -D1 => inst7.DATAIN -Q0 <= inst8.DB_MAX_OUTPUT_PORT_TYPE -D0 => inst8.DATAIN - - diff --git a/register_8b/db/register_8b.hif b/register_8b/db/register_8b.hif deleted file mode 100644 index fedb6d4..0000000 --- a/register_8b/db/register_8b.hif +++ /dev/null @@ -1,42 +0,0 @@ -Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition -11 -936 -OFF -OFF -OFF -ON -ON -ON -FV_OFF -Level2 -0 -0 -VRSM_ON -VHSM_ON -0 --- Start Library Paths -- --- End Library Paths -- --- Start VHDL Libraries -- --- End VHDL Libraries -- -# entity -register_8b -# storage -db|register_8b.(0).cnf -db|register_8b.(0).cnf -# case_insensitive -# source_file -register_8b.bdf -15bb6d6fc64f9448fba2946de88c4c4d -26 -# internal_option { -BLOCK_DESIGN_NAMING -AUTO -} -# hierarchies { -| -} -# macro_sequence - -# end -# complete - \ No newline at end of file diff --git a/register_8b/db/register_8b.lpc.html b/register_8b/db/register_8b.lpc.html deleted file mode 100644 index fd4875d..0000000 --- a/register_8b/db/register_8b.lpc.html +++ /dev/null @@ -1,18 +0,0 @@ - - - - - - - - - - - - - - - - - -
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
diff --git a/register_8b/db/register_8b.lpc.rdb b/register_8b/db/register_8b.lpc.rdb deleted file mode 100644 index 8bd163a..0000000 Binary files a/register_8b/db/register_8b.lpc.rdb and /dev/null differ diff --git a/register_8b/db/register_8b.lpc.txt b/register_8b/db/register_8b.lpc.txt deleted file mode 100644 index a463804..0000000 --- a/register_8b/db/register_8b.lpc.txt +++ /dev/null @@ -1,5 +0,0 @@ -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Legal Partition Candidates ; -+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ -; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; -+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/register_8b/db/register_8b.map.bpm b/register_8b/db/register_8b.map.bpm deleted file mode 100644 index 42bbd6a..0000000 Binary files a/register_8b/db/register_8b.map.bpm and /dev/null differ diff --git a/register_8b/db/register_8b.map.cdb b/register_8b/db/register_8b.map.cdb deleted file mode 100644 index 230260c..0000000 Binary files a/register_8b/db/register_8b.map.cdb and /dev/null differ diff --git a/register_8b/db/register_8b.map.ecobp b/register_8b/db/register_8b.map.ecobp deleted file mode 100644 index e05efff..0000000 Binary files a/register_8b/db/register_8b.map.ecobp and /dev/null differ diff --git a/register_8b/db/register_8b.map.hdb b/register_8b/db/register_8b.map.hdb deleted file mode 100644 index 57c68ae..0000000 Binary files a/register_8b/db/register_8b.map.hdb and /dev/null differ diff --git a/register_8b/db/register_8b.map.kpt b/register_8b/db/register_8b.map.kpt deleted file mode 100644 index 319f882..0000000 --- a/register_8b/db/register_8b.map.kpt +++ /dev/null @@ -1,154 +0,0 @@ - - - - inst5 - - - inst6 - - - inst3 - - - inst4 - - - inst2 - - - inst7 - - - inst8 - - - inst - - - - - - - inst5 - - - inst6 - - - inst3 - - - inst4 - - - inst2 - - - inst7 - - - inst8 - - - inst - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/register_8b/db/register_8b.map.logdb b/register_8b/db/register_8b.map.logdb deleted file mode 100644 index 626799f..0000000 --- a/register_8b/db/register_8b.map.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/register_8b/db/register_8b.map.qmsg b/register_8b/db/register_8b.map.qmsg deleted file mode 100644 index 5ac8713..0000000 --- a/register_8b/db/register_8b.map.qmsg +++ /dev/null @@ -1,7 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:08:49 2022 " "Info: Processing started: Tue Mar 08 15:08:49 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off register_8b -c register_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off register_8b -c register_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "register_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file register_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 register_8b " "Info: Found entity 1: register_8b" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_START_ELABORATION_TOP" "register_8b " "Info: Elaborating entity \"register_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_TM_SUMMARY" "26 " "Info: Implemented 26 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Info: Implemented 10 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:08:50 2022 " "Info: Processing ended: Tue Mar 08 15:08:50 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/register_8b/db/register_8b.map_bb.cdb b/register_8b/db/register_8b.map_bb.cdb deleted file mode 100644 index 73be0da..0000000 Binary files a/register_8b/db/register_8b.map_bb.cdb and /dev/null differ diff --git a/register_8b/db/register_8b.map_bb.hdb b/register_8b/db/register_8b.map_bb.hdb deleted file mode 100644 index 728c705..0000000 Binary files a/register_8b/db/register_8b.map_bb.hdb and /dev/null differ diff --git a/register_8b/db/register_8b.map_bb.logdb b/register_8b/db/register_8b.map_bb.logdb deleted file mode 100644 index 626799f..0000000 --- a/register_8b/db/register_8b.map_bb.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/register_8b/db/register_8b.pre_map.cdb b/register_8b/db/register_8b.pre_map.cdb deleted file mode 100644 index e0265a8..0000000 Binary files a/register_8b/db/register_8b.pre_map.cdb and /dev/null differ diff --git a/register_8b/db/register_8b.pre_map.hdb b/register_8b/db/register_8b.pre_map.hdb deleted file mode 100644 index 53a2e71..0000000 Binary files a/register_8b/db/register_8b.pre_map.hdb and /dev/null differ diff --git a/register_8b/db/register_8b.rtlv.hdb b/register_8b/db/register_8b.rtlv.hdb deleted file mode 100644 index 9d5eab4..0000000 Binary files a/register_8b/db/register_8b.rtlv.hdb and /dev/null differ diff --git a/register_8b/db/register_8b.rtlv_sg.cdb b/register_8b/db/register_8b.rtlv_sg.cdb deleted file mode 100644 index 7065a70..0000000 Binary files a/register_8b/db/register_8b.rtlv_sg.cdb and /dev/null differ diff --git a/register_8b/db/register_8b.rtlv_sg_swap.cdb b/register_8b/db/register_8b.rtlv_sg_swap.cdb deleted file mode 100644 index bccc94e..0000000 Binary files a/register_8b/db/register_8b.rtlv_sg_swap.cdb and /dev/null differ diff --git a/register_8b/db/register_8b.sgdiff.cdb b/register_8b/db/register_8b.sgdiff.cdb deleted file mode 100644 index 9045fac..0000000 Binary files a/register_8b/db/register_8b.sgdiff.cdb and /dev/null differ diff --git a/register_8b/db/register_8b.sgdiff.hdb b/register_8b/db/register_8b.sgdiff.hdb deleted file mode 100644 index eaba118..0000000 Binary files a/register_8b/db/register_8b.sgdiff.hdb and /dev/null differ diff --git a/register_8b/db/register_8b.sld_design_entry.sci b/register_8b/db/register_8b.sld_design_entry.sci deleted file mode 100644 index 904d003..0000000 Binary files a/register_8b/db/register_8b.sld_design_entry.sci and /dev/null differ diff --git a/register_8b/db/register_8b.sld_design_entry_dsc.sci b/register_8b/db/register_8b.sld_design_entry_dsc.sci deleted file mode 100644 index 2000bdc..0000000 Binary files a/register_8b/db/register_8b.sld_design_entry_dsc.sci and /dev/null differ diff --git a/register_8b/db/register_8b.syn_hier_info b/register_8b/db/register_8b.syn_hier_info deleted file mode 100644 index e69de29..0000000 diff --git a/register_8b/db/register_8b.tan.qmsg b/register_8b/db/register_8b.tan.qmsg deleted file mode 100644 index fd4fe68..0000000 --- a/register_8b/db/register_8b.tan.qmsg +++ /dev/null @@ -1,10 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:08:53 2022 " "Info: Processing started: Tue Mar 08 15:08:53 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off register_8b -c register_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off register_8b -c register_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CP " "Info: Assuming node \"CP\" is an undefined clock" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } { "d:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CP" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1} -{ "Info" "ITAN_NO_REG2REG_EXIST" "CP " "Info: No valid register-to-register data paths exist for clock \"CP\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0 -1} -{ "Info" "ITDB_TSU_RESULT" "inst8 D0 CP 3.273 ns register " "Info: tsu for register \"inst8\" (data pin = \"D0\", clock pin = \"CP\") is 3.273 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.692 ns + Longest pin register " "Info: + Longest pin to register delay is 7.692 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns D0 1 PIN PIN_77 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_77; Fanout = 1; PIN Node = 'D0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { D0 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 752 32 200 768 "D0" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.404 ns) + CELL(0.206 ns) 7.584 ns inst8~feeder 2 COMB LCCOMB_X25_Y1_N22 1 " "Info: 2: + IC(6.404 ns) + CELL(0.206 ns) = 7.584 ns; Loc. = LCCOMB_X25_Y1_N22; Fanout = 1; COMB Node = 'inst8~feeder'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.610 ns" { D0 inst8~feeder } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 736 344 408 816 "inst8" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.692 ns inst8 3 REG LCFF_X25_Y1_N23 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.692 ns; Loc. = LCFF_X25_Y1_N23; Fanout = 1; REG Node = 'inst8'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { inst8~feeder inst8 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 736 344 408 816 "inst8" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.288 ns ( 16.74 % ) " "Info: Total cell delay = 1.288 ns ( 16.74 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.404 ns ( 83.26 % ) " "Info: Total interconnect delay = 6.404 ns ( 83.26 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.692 ns" { D0 inst8~feeder inst8 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "7.692 ns" { D0 {} D0~combout {} inst8~feeder {} inst8 {} } { 0.000ns 0.000ns 6.404ns 0.000ns } { 0.000ns 0.974ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 736 344 408 816 "inst8" "" } } } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CP destination 4.379 ns - Shortest register " "Info: - Shortest clock path from clock \"CP\" to destination register is 4.379 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns CP 1 CLK PIN_67 8 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CP } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.719 ns) + CELL(0.666 ns) 4.379 ns inst8 2 REG LCFF_X25_Y1_N23 1 " "Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N23; Fanout = 1; REG Node = 'inst8'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.385 ns" { CP inst8 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 736 344 408 816 "inst8" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 37.91 % ) " "Info: Total cell delay = 1.660 ns ( 37.91 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.719 ns ( 62.09 % ) " "Info: Total interconnect delay = 2.719 ns ( 62.09 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst8 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst8 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.692 ns" { D0 inst8~feeder inst8 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "7.692 ns" { D0 {} D0~combout {} inst8~feeder {} inst8 {} } { 0.000ns 0.000ns 6.404ns 0.000ns } { 0.000ns 0.974ns 0.206ns 0.108ns } "" } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst8 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst8 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1} -{ "Info" "ITDB_FULL_TCO_RESULT" "CP Q5 inst3 11.227 ns register " "Info: tco from clock \"CP\" to destination pin \"Q5\" through register \"inst3\" is 11.227 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CP source 4.379 ns + Longest register " "Info: + Longest clock path from clock \"CP\" to source register is 4.379 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns CP 1 CLK PIN_67 8 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CP } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.719 ns) + CELL(0.666 ns) 4.379 ns inst3 2 REG LCFF_X25_Y1_N29 1 " "Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.385 ns" { CP inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 37.91 % ) " "Info: Total cell delay = 1.660 ns ( 37.91 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.719 ns ( 62.09 % ) " "Info: Total interconnect delay = 2.719 ns ( 62.09 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst3 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.544 ns + Longest register pin " "Info: + Longest register to pin delay is 6.544 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst3 1 REG LCFF_X25_Y1_N29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.428 ns) + CELL(3.116 ns) 6.544 ns Q5 2 PIN PIN_147 0 " "Info: 2: + IC(3.428 ns) + CELL(3.116 ns) = 6.544 ns; Loc. = PIN_147; Fanout = 0; PIN Node = 'Q5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.544 ns" { inst3 Q5 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 272 464 640 288 "Q5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.116 ns ( 47.62 % ) " "Info: Total cell delay = 3.116 ns ( 47.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.428 ns ( 52.38 % ) " "Info: Total interconnect delay = 3.428 ns ( 52.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.544 ns" { inst3 Q5 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.544 ns" { inst3 {} Q5 {} } { 0.000ns 3.428ns } { 0.000ns 3.116ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst3 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.544 ns" { inst3 Q5 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.544 ns" { inst3 {} Q5 {} } { 0.000ns 3.428ns } { 0.000ns 3.116ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1} -{ "Info" "ITDB_TH_RESULT" "inst3 D5 CP -2.294 ns register " "Info: th for register \"inst3\" (data pin = \"D5\", clock pin = \"CP\") is -2.294 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CP destination 4.379 ns + Longest register " "Info: + Longest clock path from clock \"CP\" to destination register is 4.379 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns CP 1 CLK PIN_67 8 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CP } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.719 ns) + CELL(0.666 ns) 4.379 ns inst3 2 REG LCFF_X25_Y1_N29 1 " "Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.385 ns" { CP inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 37.91 % ) " "Info: Total cell delay = 1.660 ns ( 37.91 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.719 ns ( 62.09 % ) " "Info: Total interconnect delay = 2.719 ns ( 62.09 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst3 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.979 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.979 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.964 ns) 0.964 ns D5 1 PIN PIN_86 1 " "Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_86; Fanout = 1; PIN Node = 'D5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { D5 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 272 32 200 288 "D5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.701 ns) + CELL(0.206 ns) 6.871 ns inst3~feeder 2 COMB LCCOMB_X25_Y1_N28 1 " "Info: 2: + IC(5.701 ns) + CELL(0.206 ns) = 6.871 ns; Loc. = LCCOMB_X25_Y1_N28; Fanout = 1; COMB Node = 'inst3~feeder'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.907 ns" { D5 inst3~feeder } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 6.979 ns inst3 3 REG LCFF_X25_Y1_N29 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 6.979 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { inst3~feeder inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.278 ns ( 18.31 % ) " "Info: Total cell delay = 1.278 ns ( 18.31 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.701 ns ( 81.69 % ) " "Info: Total interconnect delay = 5.701 ns ( 81.69 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.979 ns" { D5 inst3~feeder inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.979 ns" { D5 {} D5~combout {} inst3~feeder {} inst3 {} } { 0.000ns 0.000ns 5.701ns 0.000ns } { 0.000ns 0.964ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst3 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.979 ns" { D5 inst3~feeder inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.979 ns" { D5 {} D5~combout {} inst3~feeder {} inst3 {} } { 0.000ns 0.000ns 5.701ns 0.000ns } { 0.000ns 0.964ns 0.206ns 0.108ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:08:53 2022 " "Info: Processing ended: Tue Mar 08 15:08:53 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/register_8b/db/register_8b.tis_db_list.ddb b/register_8b/db/register_8b.tis_db_list.ddb deleted file mode 100644 index 2a9a6ed..0000000 Binary files a/register_8b/db/register_8b.tis_db_list.ddb and /dev/null differ diff --git a/register_8b/db/register_8b.tmw_info b/register_8b/db/register_8b.tmw_info deleted file mode 100644 index 15a6255..0000000 --- a/register_8b/db/register_8b.tmw_info +++ /dev/null @@ -1,6 +0,0 @@ -start_full_compilation:s:00:00:05 -start_analysis_synthesis:s:00:00:01-start_full_compilation -start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:02-start_full_compilation -start_assembler:s:00:00:01-start_full_compilation -start_timing_analyzer:s:00:00:01-start_full_compilation diff --git a/register_8b/incremental_db/README b/register_8b/incremental_db/README deleted file mode 100644 index 9f62dcd..0000000 --- a/register_8b/incremental_db/README +++ /dev/null @@ -1,11 +0,0 @@ -This folder contains data for incremental compilation. - -The compiled_partitions sub-folder contains previous compilation results for each partition. -As long as this folder is preserved, incremental compilation results from earlier compiles -can be re-used. To perform a clean compilation from source files for all partitions, both -the db and incremental_db folder should be removed. - -The imported_partitions sub-folder contains the last imported QXP for each imported partition. -As long as this folder is preserved, imported partitions will be automatically re-imported -when the db or incremental_db/compiled_partitions folders are removed. - diff --git a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.atm b/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.atm deleted file mode 100644 index b1349b4..0000000 Binary files a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.atm and /dev/null differ diff --git a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.dfp b/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.dfp deleted file mode 100644 index b1c67d6..0000000 Binary files a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.dfp and /dev/null differ diff --git a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.hdbx b/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.hdbx deleted file mode 100644 index 9050718..0000000 Binary files a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.hdbx and /dev/null differ diff --git a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.kpt b/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.kpt deleted file mode 100644 index c1e72d7..0000000 --- a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.kpt +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.logdb b/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.logdb deleted file mode 100644 index 626799f..0000000 --- a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.rcf b/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.rcf deleted file mode 100644 index fbe14b8..0000000 Binary files a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.cmp.rcf and /dev/null differ diff --git a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.atm b/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.atm deleted file mode 100644 index b33cb9a..0000000 Binary files a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.atm and /dev/null differ diff --git a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.dpi b/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.dpi deleted file mode 100644 index 577e9d9..0000000 Binary files a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.dpi and /dev/null differ diff --git a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.hdbx b/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.hdbx deleted file mode 100644 index 64c73f4..0000000 Binary files a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.hdbx and /dev/null differ diff --git a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.kpt b/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.kpt deleted file mode 100644 index fb8eca1..0000000 --- a/register_8b/incremental_db/compiled_partitions/register_8b.root_partition.map.kpt +++ /dev/null @@ -1,154 +0,0 @@ - - - - inst5 - - - inst6 - - - inst3 - - - inst4 - - - inst2 - - - inst7 - - - inst8 - - - inst - - - - - - - inst5 - - - inst6 - - - inst3 - - - inst4 - - - inst2 - - - inst7 - - - inst8 - - - inst - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/register_8b/register_8b.asm.rpt b/register_8b/register_8b.asm.rpt deleted file mode 100644 index 5aa1b55..0000000 --- a/register_8b/register_8b.asm.rpt +++ /dev/null @@ -1,129 +0,0 @@ -Assembler report for register_8b -Tue Mar 08 15:08:53 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Assembler Summary - 3. Assembler Settings - 4. Assembler Generated Files - 5. Assembler Device Options: D:/projects/quartus/register_8b/register_8b.sof - 6. Assembler Device Options: D:/projects/quartus/register_8b/register_8b.pof - 7. Assembler Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+---------------------------------------------------------------+ -; Assembler Summary ; -+-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Tue Mar 08 15:08:53 2022 ; -; Revision Name ; register_8b ; -; Top-level Entity Name ; register_8b ; -; Family ; Cyclone II ; -; Device ; EP2C8Q208C8 ; -+-----------------------+---------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------+ -; Assembler Settings ; -+-----------------------------------------------------------------------------+----------+---------------+ -; Option ; Setting ; Default Value ; -+-----------------------------------------------------------------------------+----------+---------------+ -; Use smart compilation ; Off ; Off ; -; Generate compressed bitstreams ; On ; On ; -; Compression mode ; Off ; Off ; -; Clock source for configuration device ; Internal ; Internal ; -; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; -; Divide clock frequency by ; 1 ; 1 ; -; Auto user code ; Off ; Off ; -; Use configuration device ; On ; On ; -; Configuration device ; Auto ; Auto ; -; Configuration device auto user code ; Off ; Off ; -; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; -; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; -; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; -; Hexadecimal Output File start address ; 0 ; 0 ; -; Hexadecimal Output File count direction ; Up ; Up ; -; Release clears before tri-states ; Off ; Off ; -; Auto-restart configuration after error ; On ; On ; -; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ; -; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; -; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; -; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; -; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; -+-----------------------------------------------------------------------------+----------+---------------+ - - -+-------------------------------------------------+ -; Assembler Generated Files ; -+-------------------------------------------------+ -; File Name ; -+-------------------------------------------------+ -; D:/projects/quartus/register_8b/register_8b.sof ; -; D:/projects/quartus/register_8b/register_8b.pof ; -+-------------------------------------------------+ - - -+---------------------------------------------------------------------------+ -; Assembler Device Options: D:/projects/quartus/register_8b/register_8b.sof ; -+----------------+----------------------------------------------------------+ -; Option ; Setting ; -+----------------+----------------------------------------------------------+ -; Device ; EP2C8Q208C8 ; -; JTAG usercode ; 0xFFFFFFFF ; -; Checksum ; 0x000C0DB2 ; -+----------------+----------------------------------------------------------+ - - -+---------------------------------------------------------------------------+ -; Assembler Device Options: D:/projects/quartus/register_8b/register_8b.pof ; -+--------------------+------------------------------------------------------+ -; Option ; Setting ; -+--------------------+------------------------------------------------------+ -; Device ; EPCS4 ; -; JTAG usercode ; 0x00000000 ; -; Checksum ; 0x06F00D7C ; -; Compression Ratio ; 3 ; -+--------------------+------------------------------------------------------+ - - -+--------------------+ -; Assembler Messages ; -+--------------------+ -Info: ******************************************************************* -Info: Running Quartus II Assembler - Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Tue Mar 08 15:08:52 2022 -Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off register_8b -c register_8b -Info: Writing out detailed assembly data for power analysis -Info: Assembler is generating device programming files -Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled -Info: Quartus II Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 241 megabytes - Info: Processing ended: Tue Mar 08 15:08:53 2022 - Info: Elapsed time: 00:00:01 - Info: Total CPU time (on all processors): 00:00:00 - - diff --git a/register_8b/register_8b.done b/register_8b/register_8b.done deleted file mode 100644 index d78deed..0000000 --- a/register_8b/register_8b.done +++ /dev/null @@ -1 +0,0 @@ -Tue Mar 08 15:08:54 2022 diff --git a/register_8b/register_8b.fit.rpt b/register_8b/register_8b.fit.rpt deleted file mode 100644 index 74bf3d5..0000000 --- a/register_8b/register_8b.fit.rpt +++ /dev/null @@ -1,957 +0,0 @@ -Fitter report for register_8b -Tue Mar 08 15:08:51 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Fitter Summary - 3. Fitter Settings - 4. Parallel Compilation - 5. Incremental Compilation Preservation Summary - 6. Incremental Compilation Partition Settings - 7. Incremental Compilation Placement Preservation - 8. Pin-Out File - 9. Fitter Resource Usage Summary - 10. Input Pins - 11. Output Pins - 12. I/O Bank Usage - 13. All Package Pins - 14. Output Pin Default Load For Reported TCO - 15. Fitter Resource Utilization by Entity - 16. Delay Chain Summary - 17. Pad To Core Delay Chain Fanout - 18. Control Signals - 19. Non-Global High Fan-Out Signals - 20. Interconnect Usage Summary - 21. LAB Logic Elements - 22. LAB-wide Signals - 23. LAB Signals Sourced - 24. LAB Signals Sourced Out - 25. LAB Distinct Inputs - 26. Fitter Device Options - 27. Operating Settings and Conditions - 28. Estimated Delay Added for Hold Timing - 29. Advanced Data - General - 30. Advanced Data - Placement Preparation - 31. Advanced Data - Placement - 32. Advanced Data - Routing - 33. Fitter Messages - 34. Fitter Suppressed Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------------+ -; Fitter Summary ; -+------------------------------------+----------------------------------------------+ -; Fitter Status ; Successful - Tue Mar 08 15:08:51 2022 ; -; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; -; Revision Name ; register_8b ; -; Top-level Entity Name ; register_8b ; -; Family ; Cyclone II ; -; Device ; EP2C8Q208C8 ; -; Timing Models ; Final ; -; Total logic elements ; 8 / 8,256 ( < 1 % ) ; -; Total combinational functions ; 0 / 8,256 ( 0 % ) ; -; Dedicated logic registers ; 8 / 8,256 ( < 1 % ) ; -; Total registers ; 8 ; -; Total pins ; 18 / 138 ( 13 % ) ; -; Total virtual pins ; 0 ; -; Total memory bits ; 0 / 165,888 ( 0 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; -; Total PLLs ; 0 / 2 ( 0 % ) ; -+------------------------------------+----------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Settings ; -+--------------------------------------------------------------------+--------------------------------+--------------------------------+ -; Option ; Setting ; Default Value ; -+--------------------------------------------------------------------+--------------------------------+--------------------------------+ -; Device ; EP2C8Q208C8 ; ; -; Minimum Core Junction Temperature ; 0 ; ; -; Maximum Core Junction Temperature ; 85 ; ; -; Fit Attempts to Skip ; 0 ; 0.0 ; -; Device I/O Standard ; 3.3-V LVTTL ; ; -; Use smart compilation ; Off ; Off ; -; Use TimeQuest Timing Analyzer ; Off ; Off ; -; Router Timing Optimization Level ; Normal ; Normal ; -; Placement Effort Multiplier ; 1.0 ; 1.0 ; -; Router Effort Multiplier ; 1.0 ; 1.0 ; -; Always Enable Input Buffers ; Off ; Off ; -; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; -; Optimize Multi-Corner Timing ; Off ; Off ; -; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; -; Optimize Timing ; Normal compilation ; Normal compilation ; -; Optimize Timing for ECOs ; Off ; Off ; -; Regenerate full fit report during ECO compiles ; Off ; Off ; -; Optimize IOC Register Placement for Timing ; On ; On ; -; Limit to One Fitting Attempt ; Off ; Off ; -; Final Placement Optimizations ; Automatically ; Automatically ; -; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; -; Fitter Initial Placement Seed ; 1 ; 1 ; -; PCI I/O ; Off ; Off ; -; Weak Pull-Up Resistor ; Off ; Off ; -; Enable Bus-Hold Circuitry ; Off ; Off ; -; Auto Global Memory Control Signals ; Off ; Off ; -; Auto Packed Registers ; Auto ; Auto ; -; Auto Delay Chains ; On ; On ; -; Auto Merge PLLs ; On ; On ; -; Ignore PLL Mode When Merging PLLs ; Off ; Off ; -; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; -; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; -; Perform Register Duplication for Performance ; Off ; Off ; -; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; -; Perform Register Retiming for Performance ; Off ; Off ; -; Perform Asynchronous Signal Pipelining ; Off ; Off ; -; Fitter Effort ; Auto Fit ; Auto Fit ; -; Physical Synthesis Effort Level ; Normal ; Normal ; -; Auto Global Clock ; On ; On ; -; Auto Global Register Control Signals ; On ; On ; -; Stop After Congestion Map Generation ; Off ; Off ; -; Save Intermediate Fitting Results ; Off ; Off ; -; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; -+--------------------------------------------------------------------+--------------------------------+--------------------------------+ - - -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 4 ; -; Maximum allowed ; 4 ; -; ; ; -; Average used ; 1.00 ; -; Maximum used ; 4 ; -; ; ; -; Usage by Processor ; % Time Used ; -; 1 processor ; 100.0% ; -; 2-4 processors ; < 0.1% ; -+----------------------------+-------------+ - - -+----------------------------------------------+ -; Incremental Compilation Preservation Summary ; -+-------------------------+--------------------+ -; Type ; Value ; -+-------------------------+--------------------+ -; Placement ; ; -; -- Requested ; 0 / 26 ( 0.00 % ) ; -; -- Achieved ; 0 / 26 ( 0.00 % ) ; -; ; ; -; Routing (by Connection) ; ; -; -- Requested ; 0 / 0 ( 0.00 % ) ; -; -- Achieved ; 0 / 0 ( 0.00 % ) ; -+-------------------------+--------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Incremental Compilation Partition Settings ; -+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ -; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; -+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ -; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; -+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ - - -+--------------------------------------------------------------------------------------------+ -; Incremental Compilation Placement Preservation ; -+----------------+---------+-------------------+-------------------------+-------------------+ -; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; -+----------------+---------+-------------------+-------------------------+-------------------+ -; Top ; 26 ; 0 ; N/A ; Source File ; -+----------------+---------+-------------------+-------------------------+-------------------+ - - -+--------------+ -; Pin-Out File ; -+--------------+ -The pin-out file can be found in D:/projects/quartus/register_8b/register_8b.pin. - - -+-------------------------------------------------------------------+ -; Fitter Resource Usage Summary ; -+---------------------------------------------+---------------------+ -; Resource ; Usage ; -+---------------------------------------------+---------------------+ -; Total logic elements ; 8 / 8,256 ( < 1 % ) ; -; -- Combinational with no register ; 0 ; -; -- Register only ; 8 ; -; -- Combinational with a register ; 0 ; -; ; ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 0 ; -; -- 3 input functions ; 0 ; -; -- <=2 input functions ; 0 ; -; -- Register only ; 8 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 0 ; -; -- arithmetic mode ; 0 ; -; ; ; -; Total registers* ; 8 / 8,646 ( < 1 % ) ; -; -- Dedicated logic registers ; 8 / 8,256 ( < 1 % ) ; -; -- I/O registers ; 0 / 390 ( 0 % ) ; -; ; ; -; Total LABs: partially or completely used ; 1 / 516 ( < 1 % ) ; -; User inserted logic elements ; 0 ; -; Virtual pins ; 0 ; -; I/O pins ; 18 / 138 ( 13 % ) ; -; -- Clock pins ; 0 / 4 ( 0 % ) ; -; Global signals ; 0 ; -; M4Ks ; 0 / 36 ( 0 % ) ; -; Total block memory bits ; 0 / 165,888 ( 0 % ) ; -; Total block memory implementation bits ; 0 / 165,888 ( 0 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; -; PLLs ; 0 / 2 ( 0 % ) ; -; Global clocks ; 0 / 8 ( 0 % ) ; -; JTAGs ; 0 / 1 ( 0 % ) ; -; ASMI blocks ; 0 / 1 ( 0 % ) ; -; CRC blocks ; 0 / 1 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; -; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ; -; Maximum fan-out node ; CP ; -; Maximum fan-out ; 8 ; -; Highest non-global fan-out signal ; CP ; -; Highest non-global fan-out ; 8 ; -; Total fan-out ; 38 ; -; Average fan-out ; 1.09 ; -+---------------------------------------------+---------------------+ -* Register count does not include registers inside RAM blocks or DSP blocks. - - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Input Pins ; -+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ; -+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ -; CLR ; 68 ; 4 ; 12 ; 0 ; 1 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; CP ; 67 ; 4 ; 9 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; D0 ; 77 ; 4 ; 18 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; D1 ; 80 ; 4 ; 23 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; D2 ; 81 ; 4 ; 23 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; D3 ; 82 ; 4 ; 23 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; D4 ; 84 ; 4 ; 25 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; D5 ; 86 ; 4 ; 25 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; D6 ; 87 ; 4 ; 25 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; D7 ; 88 ; 4 ; 25 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Output Pins ; -+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; -+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ -; Q0 ; 142 ; 3 ; 34 ; 12 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; Q1 ; 143 ; 3 ; 34 ; 13 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; Q2 ; 144 ; 3 ; 34 ; 13 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; Q3 ; 145 ; 3 ; 34 ; 14 ; 4 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; Q4 ; 146 ; 3 ; 34 ; 15 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; Q5 ; 147 ; 3 ; 34 ; 15 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; Q6 ; 149 ; 3 ; 34 ; 16 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; Q7 ; 150 ; 3 ; 34 ; 16 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ - - -+------------------------------------------------------------+ -; I/O Bank Usage ; -+----------+------------------+---------------+--------------+ -; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; -+----------+------------------+---------------+--------------+ -; 1 ; 2 / 32 ( 6 % ) ; 3.3V ; -- ; -; 2 ; 0 / 35 ( 0 % ) ; 3.3V ; -- ; -; 3 ; 9 / 35 ( 26 % ) ; 3.3V ; -- ; -; 4 ; 10 / 36 ( 28 % ) ; 3.3V ; -- ; -+----------+------------------+---------------+--------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; All Package Pins ; -+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; -+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -; 1 ; 0 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; -; 2 ; 1 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; -; 3 ; 2 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 4 ; 3 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 5 ; 4 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 6 ; 5 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 8 ; 6 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 10 ; 7 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 11 ; 8 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 12 ; 9 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 13 ; 10 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 14 ; 18 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 15 ; 19 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; -; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; -; 18 ; 22 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; -; 19 ; 23 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; -; 20 ; 24 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ; -; 21 ; 25 ; 1 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ; -; 22 ; 26 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; -; 23 ; 27 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 24 ; 28 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 26 ; 29 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; -; 27 ; 30 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 28 ; 31 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 30 ; 32 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 31 ; 33 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 33 ; 35 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 34 ; 36 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 35 ; 37 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 37 ; 39 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 39 ; 43 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 40 ; 44 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 41 ; 45 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 42 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 43 ; 48 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 44 ; 49 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 45 ; 50 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 46 ; 51 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 47 ; 52 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 48 ; 53 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 49 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 50 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; -; 51 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 52 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; -; 53 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 54 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; -; 55 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 56 ; 54 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 57 ; 55 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 58 ; 56 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 59 ; 57 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 60 ; 58 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 61 ; 59 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 63 ; 60 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 64 ; 61 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 67 ; 69 ; 4 ; CP ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 68 ; 70 ; 4 ; CLR ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 69 ; 71 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 70 ; 74 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 71 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 72 ; 75 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 74 ; 76 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 75 ; 77 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 76 ; 78 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 77 ; 79 ; 4 ; D0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 80 ; 82 ; 4 ; D1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 81 ; 83 ; 4 ; D2 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 82 ; 84 ; 4 ; D3 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 83 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 84 ; 85 ; 4 ; D4 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 85 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 86 ; 86 ; 4 ; D5 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 87 ; 87 ; 4 ; D6 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 88 ; 88 ; 4 ; D7 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 89 ; 89 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 90 ; 90 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 91 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 92 ; 91 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 94 ; 92 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 95 ; 93 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 96 ; 94 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 97 ; 95 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 98 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 99 ; 96 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 100 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 101 ; 97 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 102 ; 98 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 103 ; 99 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 104 ; 100 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 105 ; 101 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 106 ; 102 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 107 ; 105 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 108 ; 106 ; 3 ; ~LVDS54p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 109 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 110 ; 107 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 111 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 112 ; 108 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 113 ; 109 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 114 ; 110 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 115 ; 112 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 116 ; 113 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 117 ; 114 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 118 ; 117 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 119 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 120 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 121 ; 121 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; -; 122 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 123 ; 122 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; -; 124 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 125 ; 123 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; -; 126 ; 124 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; -; 127 ; 125 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 128 ; 126 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 129 ; 127 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 130 ; 128 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 131 ; 129 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 132 ; 130 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 133 ; 131 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 134 ; 132 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 135 ; 133 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 136 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 137 ; 134 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 138 ; 135 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 139 ; 136 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 141 ; 137 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 142 ; 138 ; 3 ; Q0 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 143 ; 141 ; 3 ; Q1 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 144 ; 142 ; 3 ; Q2 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 145 ; 143 ; 3 ; Q3 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 146 ; 149 ; 3 ; Q4 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 147 ; 150 ; 3 ; Q5 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 148 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 149 ; 151 ; 3 ; Q6 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 150 ; 152 ; 3 ; Q7 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 151 ; 153 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 152 ; 154 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 153 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 154 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; -; 155 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 156 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; -; 157 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 158 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; -; 159 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 160 ; 155 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 161 ; 156 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 162 ; 157 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 163 ; 158 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 164 ; 159 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 165 ; 160 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 166 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 167 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 168 ; 161 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 169 ; 162 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 170 ; 163 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 171 ; 164 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 172 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 173 ; 165 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 174 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 175 ; 168 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 176 ; 169 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 177 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 178 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 179 ; 173 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 180 ; 174 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 181 ; 175 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 182 ; 176 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 183 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 184 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 185 ; 180 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 186 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 187 ; 181 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 188 ; 182 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 189 ; 183 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 190 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 191 ; 184 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 192 ; 185 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 193 ; 186 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 194 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 195 ; 187 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 196 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 197 ; 191 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 198 ; 192 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 199 ; 195 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 200 ; 196 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 201 ; 197 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 202 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 203 ; 198 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 204 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 205 ; 199 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 206 ; 200 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 207 ; 201 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 208 ; 202 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -Note: Pin directions (input, output or bidir) are based on device operating in user mode. - - -+-------------------------------------------------------------------------------+ -; Output Pin Default Load For Reported TCO ; -+----------------------------------+-------+------------------------------------+ -; I/O Standard ; Load ; Termination Resistance ; -+----------------------------------+-------+------------------------------------+ -; 3.3-V LVTTL ; 0 pF ; Not Available ; -; 3.3-V LVCMOS ; 0 pF ; Not Available ; -; 2.5 V ; 0 pF ; Not Available ; -; 1.8 V ; 0 pF ; Not Available ; -; 1.5 V ; 0 pF ; Not Available ; -; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ; -; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ; -; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; -; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; -; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; -; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; -; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; -; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; -; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; -; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; -; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ; -; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ; -; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ; -; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ; -; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ; -; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ; -; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ; -; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ; -; LVDS ; 0 pF ; 100 Ohm (Differential) ; -; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ; -; RSDS ; 0 pF ; 100 Ohm (Differential) ; -; Simple RSDS ; 0 pF ; Not Available ; -; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ; -+----------------------------------+-------+------------------------------------+ -Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Resource Utilization by Entity ; -+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ -; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; -+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ -; |register_8b ; 8 (8) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 18 ; 0 ; 0 (0) ; 8 (8) ; 0 (0) ; |register_8b ; work ; -+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ -Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. - - -+-------------------------------------------------------------------------------+ -; Delay Chain Summary ; -+------+----------+---------------+---------------+-----------------------+-----+ -; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; -+------+----------+---------------+---------------+-----------------------+-----+ -; Q7 ; Output ; -- ; -- ; -- ; -- ; -; Q6 ; Output ; -- ; -- ; -- ; -- ; -; Q5 ; Output ; -- ; -- ; -- ; -- ; -; Q4 ; Output ; -- ; -- ; -- ; -- ; -; Q3 ; Output ; -- ; -- ; -- ; -- ; -; Q2 ; Output ; -- ; -- ; -- ; -- ; -; Q1 ; Output ; -- ; -- ; -- ; -- ; -; Q0 ; Output ; -- ; -- ; -- ; -- ; -; D7 ; Input ; 6 ; 6 ; -- ; -- ; -; CP ; Input ; 0 ; 0 ; -- ; -- ; -; CLR ; Input ; 6 ; 6 ; -- ; -- ; -; D6 ; Input ; 6 ; 6 ; -- ; -- ; -; D5 ; Input ; 6 ; 6 ; -- ; -- ; -; D4 ; Input ; 6 ; 6 ; -- ; -- ; -; D3 ; Input ; 6 ; 6 ; -- ; -- ; -; D2 ; Input ; 6 ; 6 ; -- ; -- ; -; D1 ; Input ; 6 ; 6 ; -- ; -- ; -; D0 ; Input ; 6 ; 6 ; -- ; -- ; -+------+----------+---------------+---------------+-----------------------+-----+ - - -+---------------------------------------------------+ -; Pad To Core Delay Chain Fanout ; -+---------------------+-------------------+---------+ -; Source Pin / Fanout ; Pad To Core Index ; Setting ; -+---------------------+-------------------+---------+ -; D7 ; ; ; -; - inst ; 0 ; 6 ; -; CP ; ; ; -; - inst ; 1 ; 0 ; -; - inst2 ; 1 ; 0 ; -; - inst3 ; 1 ; 0 ; -; - inst4 ; 1 ; 0 ; -; - inst5 ; 1 ; 0 ; -; - inst6 ; 1 ; 0 ; -; - inst7 ; 1 ; 0 ; -; - inst8 ; 1 ; 0 ; -; CLR ; ; ; -; - inst ; 0 ; 6 ; -; - inst2 ; 0 ; 6 ; -; - inst3 ; 0 ; 6 ; -; - inst4 ; 0 ; 6 ; -; - inst5 ; 0 ; 6 ; -; - inst6 ; 0 ; 6 ; -; - inst7 ; 0 ; 6 ; -; - inst8 ; 0 ; 6 ; -; D6 ; ; ; -; - inst2~feeder ; 0 ; 6 ; -; D5 ; ; ; -; - inst3~feeder ; 0 ; 6 ; -; D4 ; ; ; -; - inst4~feeder ; 0 ; 6 ; -; D3 ; ; ; -; - inst5 ; 0 ; 6 ; -; D2 ; ; ; -; - inst6~feeder ; 1 ; 6 ; -; D1 ; ; ; -; - inst7~feeder ; 0 ; 6 ; -; D0 ; ; ; -; - inst8~feeder ; 0 ; 6 ; -+---------------------+-------------------+---------+ - - -+-------------------------------------------------------------------------------------------------------------------------+ -; Control Signals ; -+------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+ -; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; -+------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+ -; CLR ; PIN_68 ; 8 ; Async. clear ; no ; -- ; -- ; -- ; -; CP ; PIN_67 ; 8 ; Clock ; no ; -- ; -- ; -- ; -+------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+ - - -+---------------------------------+ -; Non-Global High Fan-Out Signals ; -+-------+-------------------------+ -; Name ; Fan-Out ; -+-------+-------------------------+ -; CLR ; 8 ; -; CP ; 8 ; -; D0 ; 1 ; -; D1 ; 1 ; -; D2 ; 1 ; -; D3 ; 1 ; -; D4 ; 1 ; -; D5 ; 1 ; -; D6 ; 1 ; -; D7 ; 1 ; -; inst8 ; 1 ; -; inst7 ; 1 ; -; inst6 ; 1 ; -; inst5 ; 1 ; -; inst4 ; 1 ; -; inst3 ; 1 ; -; inst2 ; 1 ; -; inst ; 1 ; -+-------+-------------------------+ - - -+----------------------------------------------------+ -; Interconnect Usage Summary ; -+----------------------------+-----------------------+ -; Interconnect Resource Type ; Usage ; -+----------------------------+-----------------------+ -; Block interconnects ; 18 / 26,052 ( < 1 % ) ; -; C16 interconnects ; 0 / 1,156 ( 0 % ) ; -; C4 interconnects ; 39 / 17,952 ( < 1 % ) ; -; Direct links ; 0 / 26,052 ( 0 % ) ; -; Global clocks ; 0 / 8 ( 0 % ) ; -; Local interconnects ; 0 / 8,256 ( 0 % ) ; -; R24 interconnects ; 1 / 1,020 ( < 1 % ) ; -; R4 interconnects ; 31 / 22,440 ( < 1 % ) ; -+----------------------------+-----------------------+ - - -+--------------------------------------------------------------------------+ -; LAB Logic Elements ; -+--------------------------------------------+-----------------------------+ -; Number of Logic Elements (Average = 8.00) ; Number of LABs (Total = 1) ; -+--------------------------------------------+-----------------------------+ -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 1 ; -; 9 ; 0 ; -; 10 ; 0 ; -; 11 ; 0 ; -; 12 ; 0 ; -; 13 ; 0 ; -; 14 ; 0 ; -; 15 ; 0 ; -; 16 ; 0 ; -+--------------------------------------------+-----------------------------+ - - -+------------------------------------------------------------------+ -; LAB-wide Signals ; -+------------------------------------+-----------------------------+ -; LAB-wide Signals (Average = 2.00) ; Number of LABs (Total = 1) ; -+------------------------------------+-----------------------------+ -; 1 Async. clear ; 1 ; -; 1 Clock ; 1 ; -+------------------------------------+-----------------------------+ - - -+----------------------------------------------------------------------------+ -; LAB Signals Sourced ; -+----------------------------------------------+-----------------------------+ -; Number of Signals Sourced (Average = 14.00) ; Number of LABs (Total = 1) ; -+----------------------------------------------+-----------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 0 ; -; 9 ; 0 ; -; 10 ; 0 ; -; 11 ; 0 ; -; 12 ; 0 ; -; 13 ; 0 ; -; 14 ; 1 ; -+----------------------------------------------+-----------------------------+ - - -+-------------------------------------------------------------------------------+ -; LAB Signals Sourced Out ; -+-------------------------------------------------+-----------------------------+ -; Number of Signals Sourced Out (Average = 8.00) ; Number of LABs (Total = 1) ; -+-------------------------------------------------+-----------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 1 ; -+-------------------------------------------------+-----------------------------+ - - -+----------------------------------------------------------------------------+ -; LAB Distinct Inputs ; -+----------------------------------------------+-----------------------------+ -; Number of Distinct Inputs (Average = 10.00) ; Number of LABs (Total = 1) ; -+----------------------------------------------+-----------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 0 ; -; 9 ; 0 ; -; 10 ; 1 ; -+----------------------------------------------+-----------------------------+ - - -+-------------------------------------------------------------------------+ -; Fitter Device Options ; -+----------------------------------------------+--------------------------+ -; Option ; Setting ; -+----------------------------------------------+--------------------------+ -; Enable user-supplied start-up clock (CLKUSR) ; Off ; -; Enable device-wide reset (DEV_CLRn) ; Off ; -; Enable device-wide output enable (DEV_OE) ; Off ; -; Enable INIT_DONE output ; Off ; -; Configuration scheme ; Active Serial ; -; Error detection CRC ; Off ; -; nCEO ; As output driving ground ; -; ASDO,nCSO ; As input tri-stated ; -; Reserve all unused pins ; As input tri-stated ; -; Base pin-out file on sameframe device ; Off ; -+----------------------------------------------+--------------------------+ - - -+------------------------------------+ -; Operating Settings and Conditions ; -+---------------------------+--------+ -; Setting ; Value ; -+---------------------------+--------+ -; Nominal Core Voltage ; 1.20 V ; -; Low Junction Temperature ; 0 °C ; -; High Junction Temperature ; 85 °C ; -+---------------------------+--------+ - - -+------------------------------------------------------------+ -; Estimated Delay Added for Hold Timing ; -+-----------------+----------------------+-------------------+ -; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; -+-----------------+----------------------+-------------------+ - - -+----------------------------+ -; Advanced Data - General ; -+--------------------+-------+ -; Name ; Value ; -+--------------------+-------+ -; Status Code ; 0 ; -; Desired User Slack ; 0 ; -; Fit Attempts ; 1 ; -+--------------------+-------+ - - -+-------------------------------------------------------------------------------+ -; Advanced Data - Placement Preparation ; -+------------------------------------------------------------------+------------+ -; Name ; Value ; -+------------------------------------------------------------------+------------+ -; Auto Fit Point 1 - Fit Attempt 1 ; ff ; -; Mid Wire Use - Fit Attempt 1 ; 0 ; -; Mid Slack - Fit Attempt 1 ; 2147483639 ; -; Internal Atom Count - Fit Attempt 1 ; 9 ; -; LE/ALM Count - Fit Attempt 1 ; 9 ; -; LAB Count - Fit Attempt 1 ; 2 ; -; Outputs per Lab - Fit Attempt 1 ; 4.000 ; -; Inputs per LAB - Fit Attempt 1 ; 5.000 ; -; Global Inputs per LAB - Fit Attempt 1 ; 0.000 ; -; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:1;1:1 ; -; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:1;2:1 ; -; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:1;2:1 ; -; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:1;2:1 ; -; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:1;1:1 ; -; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:1;1:1 ; -; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:1;1:1 ; -; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:1 ; -; LEs in Chains - Fit Attempt 1 ; 0 ; -; LEs in Long Chains - Fit Attempt 1 ; 0 ; -; LABs with Chains - Fit Attempt 1 ; 0 ; -; LABs with Multiple Chains - Fit Attempt 1 ; 0 ; -; Time - Fit Attempt 1 ; 0 ; -+------------------------------------------------------------------+------------+ - - -+-------------------------------------------------+ -; Advanced Data - Placement ; -+------------------------------------+------------+ -; Name ; Value ; -+------------------------------------+------------+ -; Auto Fit Point 2 - Fit Attempt 1 ; ff ; -; Early Wire Use - Fit Attempt 1 ; 0 ; -; Early Slack - Fit Attempt 1 ; 2147483639 ; -; Auto Fit Point 5 - Fit Attempt 1 ; ff ; -; Mid Wire Use - Fit Attempt 1 ; 0 ; -; Mid Slack - Fit Attempt 1 ; 2147483639 ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 5 - Fit Attempt 1 ; ff ; -; Mid Wire Use - Fit Attempt 1 ; 0 ; -; Mid Slack - Fit Attempt 1 ; 2147483639 ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Late Wire Use - Fit Attempt 1 ; 0 ; -; Late Slack - Fit Attempt 1 ; 2147483639 ; -; Peak Regional Wire - Fit Attempt 1 ; 0.000 ; -; Auto Fit Point 7 - Fit Attempt 1 ; ff ; -; Time - Fit Attempt 1 ; 0 ; -+------------------------------------+------------+ - - -+--------------------------------------------------+ -; Advanced Data - Routing ; -+------------------------------------+-------------+ -; Name ; Value ; -+------------------------------------+-------------+ -; Early Slack - Fit Attempt 1 ; 2147483639 ; -; Mid Slack - Fit Attempt 1 ; 2147483639 ; -; Late Slack - Fit Attempt 1 ; -2147483648 ; -; Early Wire Use - Fit Attempt 1 ; 0 ; -; Peak Regional Wire - Fit Attempt 1 ; 0 ; -; Late Wire Use - Fit Attempt 1 ; 0 ; -; Time - Fit Attempt 1 ; 0 ; -+------------------------------------+-------------+ - - -+-----------------+ -; Fitter Messages ; -+-----------------+ -Info: ******************************************************************* -Info: Running Quartus II Fitter - Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Tue Mar 08 15:08:50 2022 -Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off register_8b -c register_8b -Info: Parallel compilation is enabled and will use 4 of the 4 processors detected -Info: Selected device EP2C8Q208C8 for design "register_8b" -Info: Low junction temperature is 0 degrees C -Info: High junction temperature is 85 degrees C -Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time -Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices - Info: Device EP2C5Q208C8 is compatible - Info: Device EP2C5Q208I8 is compatible - Info: Device EP2C8Q208I8 is compatible -Info: Fitter converted 3 user pins into dedicated programming pins - Info: Pin ~ASDO~ is reserved at location 1 - Info: Pin ~nCSO~ is reserved at location 2 - Info: Pin ~LVDS54p/nCEO~ is reserved at location 108 -Info: Fitter is using the Classic Timing Analyzer -Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time. -Info: Starting register packing -Info: Finished register packing - Extra Info: No registers were packed into other blocks -Info: Fitter preparation operations ending: elapsed time is 00:00:00 -Info: Fitter placement preparation operations beginning -Info: Fitter placement preparation operations ending: elapsed time is 00:00:00 -Info: Fitter placement operations beginning -Info: Fitter placement was successful -Info: Fitter placement operations ending: elapsed time is 00:00:00 -Info: Fitter routing operations beginning -Info: Average interconnect usage is 0% of the available device resources - Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y10 to location X34_Y19 -Info: Fitter routing operations ending: elapsed time is 00:00:00 -Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. - Info: Optimizations that may affect the design's routability were skipped - Info: Optimizations that may affect the design's timing were skipped -Info: Started post-fitting delay annotation -Warning: Found 8 output pins without output pin load capacitance assignment - Info: Pin "Q7" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Q6" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Q5" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Q4" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Q3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Q2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Q1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Q0" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis -Info: Delay annotation completed successfully -Info: Generated suppressed messages file D:/projects/quartus/register_8b/register_8b.fit.smsg -Info: Quartus II Fitter was successful. 0 errors, 1 warning - Info: Peak virtual memory: 306 megabytes - Info: Processing ended: Tue Mar 08 15:08:51 2022 - Info: Elapsed time: 00:00:01 - Info: Total CPU time (on all processors): 00:00:01 - - -+----------------------------+ -; Fitter Suppressed Messages ; -+----------------------------+ -The suppressed messages can be found in D:/projects/quartus/register_8b/register_8b.fit.smsg. - - diff --git a/register_8b/register_8b.fit.smsg b/register_8b/register_8b.fit.smsg deleted file mode 100644 index 14764e7..0000000 --- a/register_8b/register_8b.fit.smsg +++ /dev/null @@ -1,6 +0,0 @@ -Extra Info: Performing register packing on registers with non-logic cell location assignments -Extra Info: Completed register packing on registers with non-logic cell location assignments -Extra Info: Started Fast Input/Output/OE register processing -Extra Info: Finished Fast Input/Output/OE register processing -Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density -Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/register_8b/register_8b.fit.summary b/register_8b/register_8b.fit.summary deleted file mode 100644 index bcfb082..0000000 --- a/register_8b/register_8b.fit.summary +++ /dev/null @@ -1,16 +0,0 @@ -Fitter Status : Successful - Tue Mar 08 15:08:51 2022 -Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition -Revision Name : register_8b -Top-level Entity Name : register_8b -Family : Cyclone II -Device : EP2C8Q208C8 -Timing Models : Final -Total logic elements : 8 / 8,256 ( < 1 % ) - Total combinational functions : 0 / 8,256 ( 0 % ) - Dedicated logic registers : 8 / 8,256 ( < 1 % ) -Total registers : 8 -Total pins : 18 / 138 ( 13 % ) -Total virtual pins : 0 -Total memory bits : 0 / 165,888 ( 0 % ) -Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % ) -Total PLLs : 0 / 2 ( 0 % ) diff --git a/register_8b/register_8b.flow.rpt b/register_8b/register_8b.flow.rpt deleted file mode 100644 index 1e8d711..0000000 --- a/register_8b/register_8b.flow.rpt +++ /dev/null @@ -1,121 +0,0 @@ -Flow report for register_8b -Tue Mar 08 15:08:53 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Flow Summary - 3. Flow Settings - 4. Flow Non-Default Global Settings - 5. Flow Elapsed Time - 6. Flow OS Summary - 7. Flow Log - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------------+ -; Flow Summary ; -+------------------------------------+----------------------------------------------+ -; Flow Status ; Successful - Tue Mar 08 15:08:53 2022 ; -; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; -; Revision Name ; register_8b ; -; Top-level Entity Name ; register_8b ; -; Family ; Cyclone II ; -; Device ; EP2C8Q208C8 ; -; Timing Models ; Final ; -; Met timing requirements ; Yes ; -; Total logic elements ; 8 / 8,256 ( < 1 % ) ; -; Total combinational functions ; 0 / 8,256 ( 0 % ) ; -; Dedicated logic registers ; 8 / 8,256 ( < 1 % ) ; -; Total registers ; 8 ; -; Total pins ; 18 / 138 ( 13 % ) ; -; Total virtual pins ; 0 ; -; Total memory bits ; 0 / 165,888 ( 0 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; -; Total PLLs ; 0 / 2 ( 0 % ) ; -+------------------------------------+----------------------------------------------+ - - -+-----------------------------------------+ -; Flow Settings ; -+-------------------+---------------------+ -; Option ; Setting ; -+-------------------+---------------------+ -; Start date & time ; 03/08/2022 15:08:49 ; -; Main task ; Compilation ; -; Revision Name ; register_8b ; -+-------------------+---------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------+ -; Flow Non-Default Global Settings ; -+------------------------------------+-------------------------------------------------+---------------+-------------+----------------+ -; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; -+------------------------------------+-------------------------------------------------+---------------+-------------+----------------+ -; COMPILER_SIGNATURE_ID ; 220283517943889.164672332913524 ; -- ; -- ; -- ; -; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; -; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; -; MISC_FILE ; D:/projects/quartus/register_8b/register_8b.dpf ; -- ; -- ; -- ; -; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; -; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; -; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ; -+------------------------------------+-------------------------------------------------+---------------+-------------+----------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Flow Elapsed Time ; -+-------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; -+-------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 246 MB ; 00:00:00 ; -; Fitter ; 00:00:01 ; 1.0 ; 306 MB ; 00:00:01 ; -; Assembler ; 00:00:01 ; 1.0 ; 241 MB ; 00:00:00 ; -; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 198 MB ; 00:00:00 ; -; Total ; 00:00:03 ; -- ; -- ; 00:00:01 ; -+-------------------------+--------------+-------------------------+---------------------+------------------------------------+ - - -+------------------------------------------------------------------------------------------+ -; Flow OS Summary ; -+-------------------------+------------------+---------------+------------+----------------+ -; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; -+-------------------------+------------------+---------------+------------+----------------+ -; Analysis & Synthesis ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; -; Fitter ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; -; Assembler ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; -; Classic Timing Analyzer ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; -+-------------------------+------------------+---------------+------------+----------------+ - - ------------- -; Flow Log ; ------------- -quartus_map --read_settings_files=on --write_settings_files=off register_8b -c register_8b -quartus_fit --read_settings_files=off --write_settings_files=off register_8b -c register_8b -quartus_asm --read_settings_files=off --write_settings_files=off register_8b -c register_8b -quartus_tan --read_settings_files=off --write_settings_files=off register_8b -c register_8b --timing_analysis_only - - - diff --git a/register_8b/register_8b.map.rpt b/register_8b/register_8b.map.rpt deleted file mode 100644 index a3f4246..0000000 --- a/register_8b/register_8b.map.rpt +++ /dev/null @@ -1,218 +0,0 @@ -Analysis & Synthesis report for register_8b -Tue Mar 08 15:08:50 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Analysis & Synthesis Summary - 3. Analysis & Synthesis Settings - 4. Analysis & Synthesis Source Files Read - 5. Analysis & Synthesis Resource Usage Summary - 6. Analysis & Synthesis Resource Utilization by Entity - 7. General Register Statistics - 8. Analysis & Synthesis Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------------+ -; Analysis & Synthesis Summary ; -+------------------------------------+----------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Tue Mar 08 15:08:50 2022 ; -; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; -; Revision Name ; register_8b ; -; Top-level Entity Name ; register_8b ; -; Family ; Cyclone II ; -; Total logic elements ; 8 ; -; Total combinational functions ; 0 ; -; Dedicated logic registers ; 8 ; -; Total registers ; 8 ; -; Total pins ; 18 ; -; Total virtual pins ; 0 ; -; Total memory bits ; 0 ; -; Embedded Multiplier 9-bit elements ; 0 ; -; Total PLLs ; 0 ; -+------------------------------------+----------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Settings ; -+--------------------------------------------------------------+--------------------+--------------------+ -; Option ; Setting ; Default Value ; -+--------------------------------------------------------------+--------------------+--------------------+ -; Device ; EP2C8Q208C8 ; ; -; Top-level entity name ; register_8b ; register_8b ; -; Family name ; Cyclone II ; Stratix II ; -; Use Generated Physical Constraints File ; Off ; ; -; Use smart compilation ; Off ; Off ; -; Restructure Multiplexers ; Auto ; Auto ; -; Create Debugging Nodes for IP Cores ; Off ; Off ; -; Preserve fewer node names ; On ; On ; -; Disable OpenCore Plus hardware evaluation ; Off ; Off ; -; Verilog Version ; Verilog_2001 ; Verilog_2001 ; -; VHDL Version ; VHDL93 ; VHDL93 ; -; State Machine Processing ; Auto ; Auto ; -; Safe State Machine ; Off ; Off ; -; Extract Verilog State Machines ; On ; On ; -; Extract VHDL State Machines ; On ; On ; -; Ignore Verilog initial constructs ; Off ; Off ; -; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; -; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; -; Add Pass-Through Logic to Inferred RAMs ; On ; On ; -; Parallel Synthesis ; Off ; Off ; -; DSP Block Balancing ; Auto ; Auto ; -; NOT Gate Push-Back ; On ; On ; -; Power-Up Don't Care ; On ; On ; -; Remove Redundant Logic Cells ; Off ; Off ; -; Remove Duplicate Registers ; On ; On ; -; Ignore CARRY Buffers ; Off ; Off ; -; Ignore CASCADE Buffers ; Off ; Off ; -; Ignore GLOBAL Buffers ; Off ; Off ; -; Ignore ROW GLOBAL Buffers ; Off ; Off ; -; Ignore LCELL Buffers ; Off ; Off ; -; Ignore SOFT Buffers ; On ; On ; -; Limit AHDL Integers to 32 Bits ; Off ; Off ; -; Optimization Technique ; Balanced ; Balanced ; -; Carry Chain Length ; 70 ; 70 ; -; Auto Carry Chains ; On ; On ; -; Auto Open-Drain Pins ; On ; On ; -; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; -; Auto ROM Replacement ; On ; On ; -; Auto RAM Replacement ; On ; On ; -; Auto Shift Register Replacement ; Auto ; Auto ; -; Auto Clock Enable Replacement ; On ; On ; -; Strict RAM Replacement ; Off ; Off ; -; Allow Synchronous Control Signals ; On ; On ; -; Force Use of Synchronous Clear Signals ; Off ; Off ; -; Auto RAM to Logic Cell Conversion ; Off ; Off ; -; Auto Resource Sharing ; Off ; Off ; -; Allow Any RAM Size For Recognition ; Off ; Off ; -; Allow Any ROM Size For Recognition ; Off ; Off ; -; Allow Any Shift Register Size For Recognition ; Off ; Off ; -; Use LogicLock Constraints during Resource Balancing ; On ; On ; -; Ignore translate_off and synthesis_off directives ; Off ; Off ; -; Timing-Driven Synthesis ; Off ; Off ; -; Show Parameter Settings Tables in Synthesis Report ; On ; On ; -; Ignore Maximum Fan-Out Assignments ; Off ; Off ; -; Synchronization Register Chain Length ; 2 ; 2 ; -; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; -; HDL message level ; Level2 ; Level2 ; -; Suppress Register Optimization Related Messages ; Off ; Off ; -; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ; -; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; -; Clock MUX Protection ; On ; On ; -; Auto Gated Clock Conversion ; Off ; Off ; -; Block Design Naming ; Auto ; Auto ; -; SDC constraint protection ; Off ; Off ; -; Synthesis Effort ; Auto ; Auto ; -; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; -; Analysis & Synthesis Message Level ; Medium ; Medium ; -+--------------------------------------------------------------+--------------------+--------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+----------------------------------+-----------------+------------------------------------+-------------------------------------------------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; -+----------------------------------+-----------------+------------------------------------+-------------------------------------------------+ -; register_8b.bdf ; yes ; User Block Diagram/Schematic File ; D:/projects/quartus/register_8b/register_8b.bdf ; -+----------------------------------+-----------------+------------------------------------+-------------------------------------------------+ - - -+-----------------------------------------------------+ -; Analysis & Synthesis Resource Usage Summary ; -+---------------------------------------------+-------+ -; Resource ; Usage ; -+---------------------------------------------+-------+ -; Estimated Total logic elements ; 8 ; -; ; ; -; Total combinational functions ; 0 ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 0 ; -; -- 3 input functions ; 0 ; -; -- <=2 input functions ; 0 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 0 ; -; -- arithmetic mode ; 0 ; -; ; ; -; Total registers ; 8 ; -; -- Dedicated logic registers ; 8 ; -; -- I/O registers ; 0 ; -; ; ; -; I/O pins ; 18 ; -; Maximum fan-out node ; CP ; -; Maximum fan-out ; 8 ; -; Total fan-out ; 32 ; -; Average fan-out ; 1.23 ; -+---------------------------------------------+-------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Resource Utilization by Entity ; -+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ -; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; -+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ -; |register_8b ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 18 ; 0 ; |register_8b ; work ; -+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ -Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. - - -+------------------------------------------------------+ -; General Register Statistics ; -+----------------------------------------------+-------+ -; Statistic ; Value ; -+----------------------------------------------+-------+ -; Total registers ; 8 ; -; Number of registers using Synchronous Clear ; 0 ; -; Number of registers using Synchronous Load ; 0 ; -; Number of registers using Asynchronous Clear ; 8 ; -; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 0 ; -; Number of registers using Preset ; 0 ; -+----------------------------------------------+-------+ - - -+-------------------------------+ -; Analysis & Synthesis Messages ; -+-------------------------------+ -Info: ******************************************************************* -Info: Running Quartus II Analysis & Synthesis - Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Tue Mar 08 15:08:49 2022 -Info: Command: quartus_map --read_settings_files=on --write_settings_files=off register_8b -c register_8b -Info: Found 1 design units, including 1 entities, in source file register_8b.bdf - Info: Found entity 1: register_8b -Info: Elaborating entity "register_8b" for the top level hierarchy -Info: Implemented 26 device resources after synthesis - the final resource count might be different - Info: Implemented 10 input pins - Info: Implemented 8 output pins - Info: Implemented 8 logic cells -Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 250 megabytes - Info: Processing ended: Tue Mar 08 15:08:50 2022 - Info: Elapsed time: 00:00:01 - Info: Total CPU time (on all processors): 00:00:00 - - diff --git a/register_8b/register_8b.map.summary b/register_8b/register_8b.map.summary deleted file mode 100644 index cd9157e..0000000 --- a/register_8b/register_8b.map.summary +++ /dev/null @@ -1,14 +0,0 @@ -Analysis & Synthesis Status : Successful - Tue Mar 08 15:08:50 2022 -Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition -Revision Name : register_8b -Top-level Entity Name : register_8b -Family : Cyclone II -Total logic elements : 8 - Total combinational functions : 0 - Dedicated logic registers : 8 -Total registers : 8 -Total pins : 18 -Total virtual pins : 0 -Total memory bits : 0 -Embedded Multiplier 9-bit elements : 0 -Total PLLs : 0 diff --git a/register_8b/register_8b.pin b/register_8b/register_8b.pin deleted file mode 100644 index df151d9..0000000 --- a/register_8b/register_8b.pin +++ /dev/null @@ -1,278 +0,0 @@ - -- Copyright (C) 1991-2009 Altera Corporation - -- Your use of Altera Corporation's design tools, logic functions - -- and other software and tools, and its AMPP partner logic - -- functions, and any output files from any of the foregoing - -- (including device programming or simulation files), and any - -- associated documentation or information are expressly subject - -- to the terms and conditions of the Altera Program License - -- Subscription Agreement, Altera MegaCore Function License - -- Agreement, or other applicable license agreement, including, - -- without limitation, that your use is for the sole purpose of - -- programming logic devices manufactured by Altera and sold by - -- Altera or its authorized distributors. Please refer to the - -- applicable agreement for further details. - -- - -- This is a Quartus II output file. It is for reporting purposes only, and is - -- not intended for use as a Quartus II input file. This file cannot be used - -- to make Quartus II pin assignments - for instructions on how to make pin - -- assignments, please see Quartus II help. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- NC : No Connect. This pin has no internal connection to the device. - -- DNU : Do Not Use. This pin MUST NOT be connected. - -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). - -- VCCIO : Dedicated power pin, which MUST be connected to VCC - -- of its bank. - -- Bank 1: 3.3V - -- Bank 2: 3.3V - -- Bank 3: 3.3V - -- Bank 4: 3.3V - -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. - -- It can also be used to report unused dedicated pins. The connection - -- on the board for unused dedicated pins depends on whether this will - -- be used in a future design. One example is device migration. When - -- using device migration, refer to the device pin-tables. If it is a - -- GND pin in the pin table or if it will not be used in a future design - -- for another purpose the it MUST be connected to GND. If it is an unused - -- dedicated pin, then it can be connected to a valid signal on the board - -- (low, high, or toggling) if that signal is required for a different - -- revision of the design. - -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. - -- This pin should be connected to GND. It may also be connected to a - -- valid signal on the board (low, high, or toggling) if that signal - -- is required for a different revision of the design. - -- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17), - -- connect each pin marked GND* either individually through a 10k Ohm resistor - -- to GND or tie all pins together and connect through a single 10k Ohm resistor - -- to GND. - -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND - -- or leave it unconnected. - -- RESERVED : Unused I/O pin, which MUST be left unconnected. - -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. - -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. - -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. - -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- Pin directions (input, output or bidir) are based on device operating in user mode. - --------------------------------------------------------------------------------- - -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition -CHIP "register_8b" ASSIGNED TO AN: EP2C8Q208C8 - -Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment -------------------------------------------------------------------------------------------------------------- -~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVTTL : : 1 : N -~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVTTL : : 1 : N -RESERVED_INPUT : 3 : : : : 1 : -RESERVED_INPUT : 4 : : : : 1 : -RESERVED_INPUT : 5 : : : : 1 : -RESERVED_INPUT : 6 : : : : 1 : -VCCIO1 : 7 : power : : 3.3V : 1 : -RESERVED_INPUT : 8 : : : : 1 : -GND : 9 : gnd : : : : -RESERVED_INPUT : 10 : : : : 1 : -RESERVED_INPUT : 11 : : : : 1 : -RESERVED_INPUT : 12 : : : : 1 : -RESERVED_INPUT : 13 : : : : 1 : -RESERVED_INPUT : 14 : : : : 1 : -RESERVED_INPUT : 15 : : : : 1 : -TDO : 16 : output : : : 1 : -TMS : 17 : input : : : 1 : -TCK : 18 : input : : : 1 : -TDI : 19 : input : : : 1 : -DATA0 : 20 : input : : : 1 : -DCLK : 21 : : : : 1 : -nCE : 22 : : : : 1 : -GND+ : 23 : : : : 1 : -GND+ : 24 : : : : 1 : -GND : 25 : gnd : : : : -nCONFIG : 26 : : : : 1 : -GND+ : 27 : : : : 1 : -GND+ : 28 : : : : 1 : -VCCIO1 : 29 : power : : 3.3V : 1 : -RESERVED_INPUT : 30 : : : : 1 : -RESERVED_INPUT : 31 : : : : 1 : -VCCINT : 32 : power : : 1.2V : : -RESERVED_INPUT : 33 : : : : 1 : -RESERVED_INPUT : 34 : : : : 1 : -RESERVED_INPUT : 35 : : : : 1 : -GND : 36 : gnd : : : : -RESERVED_INPUT : 37 : : : : 1 : -GND : 38 : gnd : : : : -RESERVED_INPUT : 39 : : : : 1 : -RESERVED_INPUT : 40 : : : : 1 : -RESERVED_INPUT : 41 : : : : 1 : -VCCIO1 : 42 : power : : 3.3V : 1 : -RESERVED_INPUT : 43 : : : : 1 : -RESERVED_INPUT : 44 : : : : 1 : -RESERVED_INPUT : 45 : : : : 1 : -RESERVED_INPUT : 46 : : : : 1 : -RESERVED_INPUT : 47 : : : : 1 : -RESERVED_INPUT : 48 : : : : 1 : -GND : 49 : gnd : : : : -GND_PLL1 : 50 : gnd : : : : -VCCD_PLL1 : 51 : power : : 1.2V : : -GND_PLL1 : 52 : gnd : : : : -VCCA_PLL1 : 53 : power : : 1.2V : : -GNDA_PLL1 : 54 : gnd : : : : -GND : 55 : gnd : : : : -RESERVED_INPUT : 56 : : : : 4 : -RESERVED_INPUT : 57 : : : : 4 : -RESERVED_INPUT : 58 : : : : 4 : -RESERVED_INPUT : 59 : : : : 4 : -RESERVED_INPUT : 60 : : : : 4 : -RESERVED_INPUT : 61 : : : : 4 : -VCCIO4 : 62 : power : : 3.3V : 4 : -RESERVED_INPUT : 63 : : : : 4 : -RESERVED_INPUT : 64 : : : : 4 : -GND : 65 : gnd : : : : -VCCINT : 66 : power : : 1.2V : : -CP : 67 : input : 3.3-V LVTTL : : 4 : Y -CLR : 68 : input : 3.3-V LVTTL : : 4 : Y -RESERVED_INPUT : 69 : : : : 4 : -RESERVED_INPUT : 70 : : : : 4 : -VCCIO4 : 71 : power : : 3.3V : 4 : -RESERVED_INPUT : 72 : : : : 4 : -GND : 73 : gnd : : : : -RESERVED_INPUT : 74 : : : : 4 : -RESERVED_INPUT : 75 : : : : 4 : -RESERVED_INPUT : 76 : : : : 4 : -D0 : 77 : input : 3.3-V LVTTL : : 4 : Y -GND : 78 : gnd : : : : -VCCINT : 79 : power : : 1.2V : : -D1 : 80 : input : 3.3-V LVTTL : : 4 : Y -D2 : 81 : input : 3.3-V LVTTL : : 4 : Y -D3 : 82 : input : 3.3-V LVTTL : : 4 : Y -VCCIO4 : 83 : power : : 3.3V : 4 : -D4 : 84 : input : 3.3-V LVTTL : : 4 : Y -GND : 85 : gnd : : : : -D5 : 86 : input : 3.3-V LVTTL : : 4 : Y -D6 : 87 : input : 3.3-V LVTTL : : 4 : Y -D7 : 88 : input : 3.3-V LVTTL : : 4 : Y -RESERVED_INPUT : 89 : : : : 4 : -RESERVED_INPUT : 90 : : : : 4 : -VCCIO4 : 91 : power : : 3.3V : 4 : -RESERVED_INPUT : 92 : : : : 4 : -GND : 93 : gnd : : : : -RESERVED_INPUT : 94 : : : : 4 : -RESERVED_INPUT : 95 : : : : 4 : -RESERVED_INPUT : 96 : : : : 4 : -RESERVED_INPUT : 97 : : : : 4 : -VCCIO4 : 98 : power : : 3.3V : 4 : -RESERVED_INPUT : 99 : : : : 4 : -GND : 100 : gnd : : : : -RESERVED_INPUT : 101 : : : : 4 : -RESERVED_INPUT : 102 : : : : 4 : -RESERVED_INPUT : 103 : : : : 4 : -RESERVED_INPUT : 104 : : : : 4 : -RESERVED_INPUT : 105 : : : : 3 : -RESERVED_INPUT : 106 : : : : 3 : -RESERVED_INPUT : 107 : : : : 3 : -~LVDS54p/nCEO~ : 108 : output : 3.3-V LVTTL : : 3 : N -VCCIO3 : 109 : power : : 3.3V : 3 : -RESERVED_INPUT : 110 : : : : 3 : -GND : 111 : gnd : : : : -RESERVED_INPUT : 112 : : : : 3 : -RESERVED_INPUT : 113 : : : : 3 : -RESERVED_INPUT : 114 : : : : 3 : -RESERVED_INPUT : 115 : : : : 3 : -RESERVED_INPUT : 116 : : : : 3 : -RESERVED_INPUT : 117 : : : : 3 : -RESERVED_INPUT : 118 : : : : 3 : -GND : 119 : gnd : : : : -VCCINT : 120 : power : : 1.2V : : -nSTATUS : 121 : : : : 3 : -VCCIO3 : 122 : power : : 3.3V : 3 : -CONF_DONE : 123 : : : : 3 : -GND : 124 : gnd : : : : -MSEL1 : 125 : : : : 3 : -MSEL0 : 126 : : : : 3 : -RESERVED_INPUT : 127 : : : : 3 : -RESERVED_INPUT : 128 : : : : 3 : -GND+ : 129 : : : : 3 : -GND+ : 130 : : : : 3 : -GND+ : 131 : : : : 3 : -GND+ : 132 : : : : 3 : -RESERVED_INPUT : 133 : : : : 3 : -RESERVED_INPUT : 134 : : : : 3 : -RESERVED_INPUT : 135 : : : : 3 : -VCCIO3 : 136 : power : : 3.3V : 3 : -RESERVED_INPUT : 137 : : : : 3 : -RESERVED_INPUT : 138 : : : : 3 : -RESERVED_INPUT : 139 : : : : 3 : -GND : 140 : gnd : : : : -RESERVED_INPUT : 141 : : : : 3 : -Q0 : 142 : output : 3.3-V LVTTL : : 3 : Y -Q1 : 143 : output : 3.3-V LVTTL : : 3 : Y -Q2 : 144 : output : 3.3-V LVTTL : : 3 : Y -Q3 : 145 : output : 3.3-V LVTTL : : 3 : Y -Q4 : 146 : output : 3.3-V LVTTL : : 3 : Y -Q5 : 147 : output : 3.3-V LVTTL : : 3 : Y -VCCIO3 : 148 : power : : 3.3V : 3 : -Q6 : 149 : output : 3.3-V LVTTL : : 3 : Y -Q7 : 150 : output : 3.3-V LVTTL : : 3 : Y -RESERVED_INPUT : 151 : : : : 3 : -RESERVED_INPUT : 152 : : : : 3 : -GND : 153 : gnd : : : : -GND_PLL2 : 154 : gnd : : : : -VCCD_PLL2 : 155 : power : : 1.2V : : -GND_PLL2 : 156 : gnd : : : : -VCCA_PLL2 : 157 : power : : 1.2V : : -GNDA_PLL2 : 158 : gnd : : : : -GND : 159 : gnd : : : : -RESERVED_INPUT : 160 : : : : 2 : -RESERVED_INPUT : 161 : : : : 2 : -RESERVED_INPUT : 162 : : : : 2 : -RESERVED_INPUT : 163 : : : : 2 : -RESERVED_INPUT : 164 : : : : 2 : -RESERVED_INPUT : 165 : : : : 2 : -VCCIO2 : 166 : power : : 3.3V : 2 : -GND : 167 : gnd : : : : -RESERVED_INPUT : 168 : : : : 2 : -RESERVED_INPUT : 169 : : : : 2 : -RESERVED_INPUT : 170 : : : : 2 : -RESERVED_INPUT : 171 : : : : 2 : -VCCIO2 : 172 : power : : 3.3V : 2 : -RESERVED_INPUT : 173 : : : : 2 : -GND : 174 : gnd : : : : -RESERVED_INPUT : 175 : : : : 2 : -RESERVED_INPUT : 176 : : : : 2 : -GND : 177 : gnd : : : : -VCCINT : 178 : power : : 1.2V : : -RESERVED_INPUT : 179 : : : : 2 : -RESERVED_INPUT : 180 : : : : 2 : -RESERVED_INPUT : 181 : : : : 2 : -RESERVED_INPUT : 182 : : : : 2 : -VCCIO2 : 183 : power : : 3.3V : 2 : -GND : 184 : gnd : : : : -RESERVED_INPUT : 185 : : : : 2 : -GND : 186 : gnd : : : : -RESERVED_INPUT : 187 : : : : 2 : -RESERVED_INPUT : 188 : : : : 2 : -RESERVED_INPUT : 189 : : : : 2 : -VCCINT : 190 : power : : 1.2V : : -RESERVED_INPUT : 191 : : : : 2 : -RESERVED_INPUT : 192 : : : : 2 : -RESERVED_INPUT : 193 : : : : 2 : -VCCIO2 : 194 : power : : 3.3V : 2 : -RESERVED_INPUT : 195 : : : : 2 : -GND : 196 : gnd : : : : -RESERVED_INPUT : 197 : : : : 2 : -RESERVED_INPUT : 198 : : : : 2 : -RESERVED_INPUT : 199 : : : : 2 : -RESERVED_INPUT : 200 : : : : 2 : -RESERVED_INPUT : 201 : : : : 2 : -VCCIO2 : 202 : power : : 3.3V : 2 : -RESERVED_INPUT : 203 : : : : 2 : -GND : 204 : gnd : : : : -RESERVED_INPUT : 205 : : : : 2 : -RESERVED_INPUT : 206 : : : : 2 : -RESERVED_INPUT : 207 : : : : 2 : -RESERVED_INPUT : 208 : : : : 2 : diff --git a/register_8b/register_8b.pof b/register_8b/register_8b.pof deleted file mode 100644 index ca378d9..0000000 Binary files a/register_8b/register_8b.pof and /dev/null differ diff --git a/register_8b/register_8b.qws b/register_8b/register_8b.qws deleted file mode 100644 index d554e16..0000000 --- a/register_8b/register_8b.qws +++ /dev/null @@ -1,14 +0,0 @@ -[ProjectWorkspace] -ptn_Child1=Frames -[ProjectWorkspace.Frames] -ptn_Child1=ChildFrames -[ProjectWorkspace.Frames.ChildFrames] -ptn_Child1=Document-0 -[ProjectWorkspace.Frames.ChildFrames.Document-0] -ptn_Child1=ViewFrame-0 -[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0] -DocPathName=register_8b.bdf -DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde} -IsChildFrameDetached=False -IsActiveChildFrame=True -ptn_Child1=StateMap diff --git a/register_8b/register_8b.sof b/register_8b/register_8b.sof deleted file mode 100644 index 61e382f..0000000 Binary files a/register_8b/register_8b.sof and /dev/null differ diff --git a/register_8b/register_8b.tan.rpt b/register_8b/register_8b.tan.rpt deleted file mode 100644 index 8585e8f..0000000 --- a/register_8b/register_8b.tan.rpt +++ /dev/null @@ -1,214 +0,0 @@ -Classic Timing Analyzer report for register_8b -Tue Mar 08 15:08:53 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Timing Analyzer Summary - 3. Timing Analyzer Settings - 4. Clock Settings Summary - 5. Parallel Compilation - 6. tsu - 7. tco - 8. th - 9. Timing Analyzer Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+---------------------------------------------------------------------------------------------------------------------------+ -; Timing Analyzer Summary ; -+------------------------------+-------+---------------+-------------+-------+-------+------------+----------+--------------+ -; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; -+------------------------------+-------+---------------+-------------+-------+-------+------------+----------+--------------+ -; Worst-case tsu ; N/A ; None ; 3.273 ns ; D0 ; inst8 ; -- ; CP ; 0 ; -; Worst-case tco ; N/A ; None ; 11.227 ns ; inst3 ; Q5 ; CP ; -- ; 0 ; -; Worst-case th ; N/A ; None ; -2.294 ns ; D5 ; inst3 ; -- ; CP ; 0 ; -; Total number of failed paths ; ; ; ; ; ; ; ; 0 ; -+------------------------------+-------+---------------+-------------+-------+-------+------------+----------+--------------+ - - -+--------------------------------------------------------------------------------------------------------------------+ -; Timing Analyzer Settings ; -+---------------------------------------------------------------------+--------------------+------+----+-------------+ -; Option ; Setting ; From ; To ; Entity Name ; -+---------------------------------------------------------------------+--------------------+------+----+-------------+ -; Device Name ; EP2C8Q208C8 ; ; ; ; -; Timing Models ; Final ; ; ; ; -; Default hold multicycle ; Same as Multicycle ; ; ; ; -; Cut paths between unrelated clock domains ; On ; ; ; ; -; Cut off read during write signal paths ; On ; ; ; ; -; Cut off feedback from I/O pins ; On ; ; ; ; -; Report Combined Fast/Slow Timing ; Off ; ; ; ; -; Ignore Clock Settings ; Off ; ; ; ; -; Analyze latches as synchronous elements ; On ; ; ; ; -; Enable Recovery/Removal analysis ; Off ; ; ; ; -; Enable Clock Latency ; Off ; ; ; ; -; Use TimeQuest Timing Analyzer ; Off ; ; ; ; -; Minimum Core Junction Temperature ; 0 ; ; ; ; -; Maximum Core Junction Temperature ; 85 ; ; ; ; -; Number of source nodes to report per destination node ; 10 ; ; ; ; -; Number of destination nodes to report ; 10 ; ; ; ; -; Number of paths to report ; 200 ; ; ; ; -; Report Minimum Timing Checks ; Off ; ; ; ; -; Use Fast Timing Models ; Off ; ; ; ; -; Report IO Paths Separately ; Off ; ; ; ; -; Perform Multicorner Analysis ; On ; ; ; ; -; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ; -; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ; -; Output I/O Timing Endpoint ; Near End ; ; ; ; -+---------------------------------------------------------------------+--------------------+------+----+-------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Settings Summary ; -+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ -; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ; -+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ -; CP ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ; -+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ - - -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 4 ; -; Maximum allowed ; 4 ; -; ; ; -; Average used ; 1.00 ; -; Maximum used ; 1 ; -; ; ; -; Usage by Processor ; % Time Used ; -; 1 processor ; 100.0% ; -; 2-4 processors ; 0.0% ; -+----------------------------+-------------+ - - -+-------------------------------------------------------------+ -; tsu ; -+-------+--------------+------------+------+-------+----------+ -; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ; -+-------+--------------+------------+------+-------+----------+ -; N/A ; None ; 3.273 ns ; D0 ; inst8 ; CP ; -; N/A ; None ; 2.730 ns ; D3 ; inst5 ; CP ; -; N/A ; None ; 2.724 ns ; D7 ; inst ; CP ; -; N/A ; None ; 2.599 ns ; D1 ; inst7 ; CP ; -; N/A ; None ; 2.597 ns ; D2 ; inst6 ; CP ; -; N/A ; None ; 2.569 ns ; D6 ; inst2 ; CP ; -; N/A ; None ; 2.567 ns ; D4 ; inst4 ; CP ; -; N/A ; None ; 2.560 ns ; D5 ; inst3 ; CP ; -+-------+--------------+------------+------+-------+----------+ - - -+-------------------------------------------------------------+ -; tco ; -+-------+--------------+------------+-------+----+------------+ -; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ; -+-------+--------------+------------+-------+----+------------+ -; N/A ; None ; 11.227 ns ; inst3 ; Q5 ; CP ; -; N/A ; None ; 11.226 ns ; inst2 ; Q6 ; CP ; -; N/A ; None ; 11.174 ns ; inst5 ; Q3 ; CP ; -; N/A ; None ; 11.161 ns ; inst4 ; Q4 ; CP ; -; N/A ; None ; 11.157 ns ; inst ; Q7 ; CP ; -; N/A ; None ; 10.809 ns ; inst8 ; Q0 ; CP ; -; N/A ; None ; 10.781 ns ; inst7 ; Q1 ; CP ; -; N/A ; None ; 10.767 ns ; inst6 ; Q2 ; CP ; -+-------+--------------+------------+-------+----+------------+ - - -+-------------------------------------------------------------------+ -; th ; -+---------------+-------------+-----------+------+-------+----------+ -; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ; -+---------------+-------------+-----------+------+-------+----------+ -; N/A ; None ; -2.294 ns ; D5 ; inst3 ; CP ; -; N/A ; None ; -2.301 ns ; D4 ; inst4 ; CP ; -; N/A ; None ; -2.303 ns ; D6 ; inst2 ; CP ; -; N/A ; None ; -2.331 ns ; D2 ; inst6 ; CP ; -; N/A ; None ; -2.333 ns ; D1 ; inst7 ; CP ; -; N/A ; None ; -2.458 ns ; D7 ; inst ; CP ; -; N/A ; None ; -2.464 ns ; D3 ; inst5 ; CP ; -; N/A ; None ; -3.007 ns ; D0 ; inst8 ; CP ; -+---------------+-------------+-----------+------+-------+----------+ - - -+--------------------------+ -; Timing Analyzer Messages ; -+--------------------------+ -Info: ******************************************************************* -Info: Running Quartus II Classic Timing Analyzer - Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Tue Mar 08 15:08:53 2022 -Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off register_8b -c register_8b --timing_analysis_only -Info: Parallel compilation is enabled and will use 4 of the 4 processors detected -Warning: Found pins functioning as undefined clocks and/or memory enables - Info: Assuming node "CP" is an undefined clock -Info: No valid register-to-register data paths exist for clock "CP" -Info: tsu for register "inst8" (data pin = "D0", clock pin = "CP") is 3.273 ns - Info: + Longest pin to register delay is 7.692 ns - Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_77; Fanout = 1; PIN Node = 'D0' - Info: 2: + IC(6.404 ns) + CELL(0.206 ns) = 7.584 ns; Loc. = LCCOMB_X25_Y1_N22; Fanout = 1; COMB Node = 'inst8~feeder' - Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.692 ns; Loc. = LCFF_X25_Y1_N23; Fanout = 1; REG Node = 'inst8' - Info: Total cell delay = 1.288 ns ( 16.74 % ) - Info: Total interconnect delay = 6.404 ns ( 83.26 % ) - Info: + Micro setup delay of destination is -0.040 ns - Info: - Shortest clock path from clock "CP" to destination register is 4.379 ns - Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP' - Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N23; Fanout = 1; REG Node = 'inst8' - Info: Total cell delay = 1.660 ns ( 37.91 % ) - Info: Total interconnect delay = 2.719 ns ( 62.09 % ) -Info: tco from clock "CP" to destination pin "Q5" through register "inst3" is 11.227 ns - Info: + Longest clock path from clock "CP" to source register is 4.379 ns - Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP' - Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3' - Info: Total cell delay = 1.660 ns ( 37.91 % ) - Info: Total interconnect delay = 2.719 ns ( 62.09 % ) - Info: + Micro clock to output delay of source is 0.304 ns - Info: + Longest register to pin delay is 6.544 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3' - Info: 2: + IC(3.428 ns) + CELL(3.116 ns) = 6.544 ns; Loc. = PIN_147; Fanout = 0; PIN Node = 'Q5' - Info: Total cell delay = 3.116 ns ( 47.62 % ) - Info: Total interconnect delay = 3.428 ns ( 52.38 % ) -Info: th for register "inst3" (data pin = "D5", clock pin = "CP") is -2.294 ns - Info: + Longest clock path from clock "CP" to destination register is 4.379 ns - Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP' - Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3' - Info: Total cell delay = 1.660 ns ( 37.91 % ) - Info: Total interconnect delay = 2.719 ns ( 62.09 % ) - Info: + Micro hold delay of destination is 0.306 ns - Info: - Shortest pin to register delay is 6.979 ns - Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_86; Fanout = 1; PIN Node = 'D5' - Info: 2: + IC(5.701 ns) + CELL(0.206 ns) = 6.871 ns; Loc. = LCCOMB_X25_Y1_N28; Fanout = 1; COMB Node = 'inst3~feeder' - Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 6.979 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3' - Info: Total cell delay = 1.278 ns ( 18.31 % ) - Info: Total interconnect delay = 5.701 ns ( 81.69 % ) -Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning - Info: Peak virtual memory: 212 megabytes - Info: Processing ended: Tue Mar 08 15:08:53 2022 - Info: Elapsed time: 00:00:00 - Info: Total CPU time (on all processors): 00:00:00 - - diff --git a/register_8b/register_8b.tan.summary b/register_8b/register_8b.tan.summary deleted file mode 100644 index 3c39e13..0000000 --- a/register_8b/register_8b.tan.summary +++ /dev/null @@ -1,46 +0,0 @@ --------------------------------------------------------------------------------------- -Timing Analyzer Summary --------------------------------------------------------------------------------------- - -Type : Worst-case tsu -Slack : N/A -Required Time : None -Actual Time : 3.273 ns -From : D0 -To : inst8 -From Clock : -- -To Clock : CP -Failed Paths : 0 - -Type : Worst-case tco -Slack : N/A -Required Time : None -Actual Time : 11.227 ns -From : inst3 -To : Q5 -From Clock : CP -To Clock : -- -Failed Paths : 0 - -Type : Worst-case th -Slack : N/A -Required Time : None -Actual Time : -2.294 ns -From : D5 -To : inst3 -From Clock : -- -To Clock : CP -Failed Paths : 0 - -Type : Total number of failed paths -Slack : -Required Time : -Actual Time : -From : -To : -From Clock : -To Clock : -Failed Paths : 0 - --------------------------------------------------------------------------------------- - diff --git a/shiftable_register/db/shiftable_register.db_info b/shiftable_register/db/shiftable_register.db_info deleted file mode 100644 index 13c1ea5..0000000 --- a/shiftable_register/db/shiftable_register.db_info +++ /dev/null @@ -1,3 +0,0 @@ -Quartus_Version = Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition -Version_Index = 167832322 -Creation_Time = Mon Mar 07 21:41:44 2022 diff --git a/shifter_8b/db/prev_cmp_shifter_8b.asm.qmsg b/shifter_8b/db/prev_cmp_shifter_8b.asm.qmsg deleted file mode 100644 index e680608..0000000 --- a/shifter_8b/db/prev_cmp_shifter_8b.asm.qmsg +++ /dev/null @@ -1,7 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:17:18 2022 " "Info: Processing started: Tue Mar 08 15:17:18 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1} -{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:17:18 2022 " "Info: Processing ended: Tue Mar 08 15:17:18 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/shifter_8b/db/prev_cmp_shifter_8b.fit.qmsg b/shifter_8b/db/prev_cmp_shifter_8b.fit.qmsg deleted file mode 100644 index 10af5de..0000000 --- a/shifter_8b/db/prev_cmp_shifter_8b.fit.qmsg +++ /dev/null @@ -1,35 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:17:16 2022 " "Info: Processing started: Tue Mar 08 15:17:16 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "IMPP_MPP_USER_DEVICE" "shifter_8b EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"shifter_8b\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1} -{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1} -{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y0 X34_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X34_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} -{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y0 0 " "Info: Pin \"Y0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y1 0 " "Info: Pin \"Y1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y2 0 " "Info: Pin \"Y2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y3 0 " "Info: Pin \"Y3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y4 0 " "Info: Pin \"Y4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y5 0 " "Info: Pin \"Y5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y6 0 " "Info: Pin \"Y6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y7 0 " "Info: Pin \"Y7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/shifter_8b/shifter_8b.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/shifter_8b/shifter_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "306 " "Info: Peak virtual memory: 306 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:17:17 2022 " "Info: Processing ended: Tue Mar 08 15:17:17 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/shifter_8b/db/prev_cmp_shifter_8b.map.qmsg b/shifter_8b/db/prev_cmp_shifter_8b.map.qmsg deleted file mode 100644 index 4893583..0000000 --- a/shifter_8b/db/prev_cmp_shifter_8b.map.qmsg +++ /dev/null @@ -1,9 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:17:15 2022 " "Info: Processing started: Tue Mar 08 15:17:15 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 shifter_8b " "Info: Found entity 1: shifter_8b" { } { { "shifter_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_START_ELABORATION_TOP" "shifter_8b " "Info: Elaborating entity \"shifter_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} -{ "Warning" "WSGN_SEARCH_FILE" "triple_selector_8b.bdf 1 1 " "Warning: Using design file triple_selector_8b.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 triple_selector_8b " "Info: Found entity 1: triple_selector_8b" { } { { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/triple_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "triple_selector_8b triple_selector_8b:inst " "Info: Elaborating entity \"triple_selector_8b\" for hierarchy \"triple_selector_8b:inst\"" { } { { "shifter_8b.bdf" "inst" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { { 32 488 584 512 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_TM_SUMMARY" "33 " "Info: Implemented 33 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Info: Implemented 11 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "14 " "Info: Implemented 14 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:17:15 2022 " "Info: Processing ended: Tue Mar 08 15:17:15 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/shifter_8b/db/prev_cmp_shifter_8b.qmsg b/shifter_8b/db/prev_cmp_shifter_8b.qmsg deleted file mode 100644 index 264ed4b..0000000 --- a/shifter_8b/db/prev_cmp_shifter_8b.qmsg +++ /dev/null @@ -1,62 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:15:53 2022 " "Info: Processing started: Mon Mar 07 11:15:53 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 shifter_8b " "Info: Found entity 1: shifter_8b" { } { { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_START_ELABORATION_TOP" "shifter_8b " "Info: Elaborating entity \"shifter_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} -{ "Warning" "WSGN_SEARCH_FILE" "triple_selector_8b.bdf 1 1 " "Warning: Using design file triple_selector_8b.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 triple_selector_8b " "Info: Found entity 1: triple_selector_8b" { } { { "triple_selector_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/triple_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "triple_selector_8b triple_selector_8b:inst " "Info: Elaborating entity \"triple_selector_8b\" for hierarchy \"triple_selector_8b:inst\"" { } { { "shifter_8b.bdf" "inst" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 32 488 584 512 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_TM_SUMMARY" "33 " "Info: Implemented 33 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Info: Implemented 11 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "14 " "Info: Implemented 14 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "229 " "Info: Peak virtual memory: 229 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:15:53 2022 " "Info: Processing ended: Mon Mar 07 11:15:53 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:15:54 2022 " "Info: Processing started: Mon Mar 07 11:15:54 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 6 " "Info: Parallel compilation is enabled and will use 4 of the 6 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "IMPP_MPP_USER_DEVICE" "shifter_8b EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"shifter_8b\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1} -{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "19 19 " "Warning: No exact pin location assignment(s) for 19 pins of 19 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y0 " "Info: Pin Y0 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y0 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 168 688 864 184 "Y0" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y1 " "Info: Pin Y1 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y1 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 152 688 864 168 "Y1" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y2 " "Info: Pin Y2 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y2 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 136 688 864 152 "Y2" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y3 " "Info: Pin Y3 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y3 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 120 688 864 136 "Y3" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y4 " "Info: Pin Y4 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y4 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 104 688 864 120 "Y4" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y5 " "Info: Pin Y5 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y5 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 88 688 864 104 "Y5" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y6 " "Info: Pin Y6 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y6 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 72 688 864 88 "Y6" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y7 " "Info: Pin Y7 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y7 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 56 688 864 72 "Y7" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A0 " "Info: Pin A0 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { A0 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 408 40 208 424 "A0" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A1 " "Info: Pin A1 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { A1 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 360 40 208 376 "A1" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "RM " "Info: Pin RM not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { RM } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 552 40 208 568 "RM" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { RM } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DM " "Info: Pin DM not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { DM } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 504 40 208 520 "DM" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DM } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LM " "Info: Pin LM not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { LM } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 456 40 208 472 "LM" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LM } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A2 " "Info: Pin A2 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { A2 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 312 40 208 328 "A2" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A3 " "Info: Pin A3 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { A3 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 264 40 208 280 "A3" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A4 " "Info: Pin A4 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { A4 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 216 40 208 232 "A4" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A5 " "Info: Pin A5 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { A5 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 168 40 208 184 "A5" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A6 " "Info: Pin A6 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { A6 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 120 40 208 136 "A6" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A7 " "Info: Pin A7 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { A7 } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 72 40 208 88 "A7" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1} -{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1} -{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "19 unused 3.3V 11 8 0 " "Info: Number of I/O pins in group: 19 (unused VREF, 3.3V VCCIO, 11 input, 8 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 2 30 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 35 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 34 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 36 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X10_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} -{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y0 0 " "Info: Pin \"Y0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y1 0 " "Info: Pin \"Y1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y2 0 " "Info: Pin \"Y2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y3 0 " "Info: Pin \"Y3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y4 0 " "Info: Pin \"Y4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y5 0 " "Info: Pin \"Y5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y6 0 " "Info: Pin \"Y6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y7 0 " "Info: Pin \"Y7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/dev/quartus/shifter_8b/shifter_8b.fit.smsg " "Info: Generated suppressed messages file D:/dev/quartus/shifter_8b/shifter_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "286 " "Info: Peak virtual memory: 286 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:15:55 2022 " "Info: Processing ended: Mon Mar 07 11:15:55 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:15:56 2022 " "Info: Processing started: Mon Mar 07 11:15:56 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1} -{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "221 " "Info: Peak virtual memory: 221 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:15:57 2022 " "Info: Processing ended: Mon Mar 07 11:15:57 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:15:57 2022 " "Info: Processing started: Mon Mar 07 11:15:57 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 6 " "Info: Parallel compilation is enabled and will use 4 of the 6 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "ITDB_FULL_TPD_RESULT" "A6 Y7 13.413 ns Longest " "Info: Longest tpd from source pin \"A6\" to destination pin \"Y7\" is 13.413 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns A6 1 PIN PIN_67 3 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 3; PIN Node = 'A6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A6 } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 120 40 208 136 "A6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.895 ns) + CELL(0.624 ns) 8.513 ns triple_selector_8b:inst\|inst31 2 COMB LCCOMB_X1_Y5_N10 1 " "Info: 2: + IC(6.895 ns) + CELL(0.624 ns) = 8.513 ns; Loc. = LCCOMB_X1_Y5_N10; Fanout = 1; COMB Node = 'triple_selector_8b:inst\|inst31'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.519 ns" { A6 triple_selector_8b:inst|inst31 } "NODE_NAME" } } { "triple_selector_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/triple_selector_8b.bdf" { { 64 488 552 112 "inst31" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.604 ns) + CELL(3.296 ns) 13.413 ns Y7 3 PIN PIN_60 0 " "Info: 3: + IC(1.604 ns) + CELL(3.296 ns) = 13.413 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'Y7'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.900 ns" { triple_selector_8b:inst|inst31 Y7 } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 56 688 864 72 "Y7" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.914 ns ( 36.64 % ) " "Info: Total cell delay = 4.914 ns ( 36.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.499 ns ( 63.36 % ) " "Info: Total interconnect delay = 8.499 ns ( 63.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "13.413 ns" { A6 triple_selector_8b:inst|inst31 Y7 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "13.413 ns" { A6 {} A6~combout {} triple_selector_8b:inst|inst31 {} Y7 {} } { 0.000ns 0.000ns 6.895ns 1.604ns } { 0.000ns 0.994ns 0.624ns 3.296ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "191 " "Info: Peak virtual memory: 191 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:15:58 2022 " "Info: Processing ended: Mon Mar 07 11:15:58 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 4 s " "Info: Quartus II Full Compilation was successful. 0 errors, 4 warnings" { } { } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/shifter_8b/db/prev_cmp_shifter_8b.tan.qmsg b/shifter_8b/db/prev_cmp_shifter_8b.tan.qmsg deleted file mode 100644 index ec16759..0000000 --- a/shifter_8b/db/prev_cmp_shifter_8b.tan.qmsg +++ /dev/null @@ -1,6 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:17:19 2022 " "Info: Processing started: Tue Mar 08 15:17:19 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "ITDB_FULL_TPD_RESULT" "LM Y5 15.661 ns Longest " "Info: Longest tpd from source pin \"LM\" to destination pin \"Y5\" is 15.661 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns LM 1 PIN PIN_69 7 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_69; Fanout = 7; PIN Node = 'LM'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LM } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { { 456 40 208 472 "LM" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.879 ns) + CELL(0.650 ns) 8.523 ns triple_selector_8b:inst\|inst23~0 2 COMB LCCOMB_X26_Y1_N18 1 " "Info: 2: + IC(6.879 ns) + CELL(0.650 ns) = 8.523 ns; Loc. = LCCOMB_X26_Y1_N18; Fanout = 1; COMB Node = 'triple_selector_8b:inst\|inst23~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.529 ns" { LM triple_selector_8b:inst|inst23~0 } "NODE_NAME" } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/triple_selector_8b.bdf" { { 352 488 552 400 "inst23" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.370 ns) + CELL(0.624 ns) 9.517 ns triple_selector_8b:inst\|inst23 3 COMB LCCOMB_X26_Y1_N20 1 " "Info: 3: + IC(0.370 ns) + CELL(0.624 ns) = 9.517 ns; Loc. = LCCOMB_X26_Y1_N20; Fanout = 1; COMB Node = 'triple_selector_8b:inst\|inst23'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.994 ns" { triple_selector_8b:inst|inst23~0 triple_selector_8b:inst|inst23 } "NODE_NAME" } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/triple_selector_8b.bdf" { { 352 488 552 400 "inst23" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.028 ns) + CELL(3.116 ns) 15.661 ns Y5 4 PIN PIN_147 0 " "Info: 4: + IC(3.028 ns) + CELL(3.116 ns) = 15.661 ns; Loc. = PIN_147; Fanout = 0; PIN Node = 'Y5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.144 ns" { triple_selector_8b:inst|inst23 Y5 } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { { 88 688 864 104 "Y5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.384 ns ( 34.38 % ) " "Info: Total cell delay = 5.384 ns ( 34.38 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "10.277 ns ( 65.62 % ) " "Info: Total interconnect delay = 10.277 ns ( 65.62 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "15.661 ns" { LM triple_selector_8b:inst|inst23~0 triple_selector_8b:inst|inst23 Y5 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "15.661 ns" { LM {} LM~combout {} triple_selector_8b:inst|inst23~0 {} triple_selector_8b:inst|inst23 {} Y5 {} } { 0.000ns 0.000ns 6.879ns 0.370ns 3.028ns } { 0.000ns 0.994ns 0.650ns 0.624ns 3.116ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:17:19 2022 " "Info: Processing ended: Tue Mar 08 15:17:19 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/shifter_8b/db/shifter_8b.(0).cnf.cdb b/shifter_8b/db/shifter_8b.(0).cnf.cdb deleted file mode 100644 index 33d503a..0000000 Binary files a/shifter_8b/db/shifter_8b.(0).cnf.cdb and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.(0).cnf.hdb b/shifter_8b/db/shifter_8b.(0).cnf.hdb deleted file mode 100644 index bb1d518..0000000 Binary files a/shifter_8b/db/shifter_8b.(0).cnf.hdb and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.(1).cnf.cdb b/shifter_8b/db/shifter_8b.(1).cnf.cdb deleted file mode 100644 index 8b10deb..0000000 Binary files a/shifter_8b/db/shifter_8b.(1).cnf.cdb and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.(1).cnf.hdb b/shifter_8b/db/shifter_8b.(1).cnf.hdb deleted file mode 100644 index 3145323..0000000 Binary files a/shifter_8b/db/shifter_8b.(1).cnf.hdb and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.ace_cmp.bpm b/shifter_8b/db/shifter_8b.ace_cmp.bpm deleted file mode 100644 index 19e7161..0000000 Binary files a/shifter_8b/db/shifter_8b.ace_cmp.bpm and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.ace_cmp.cdb b/shifter_8b/db/shifter_8b.ace_cmp.cdb deleted file mode 100644 index 8c75fb7..0000000 Binary files a/shifter_8b/db/shifter_8b.ace_cmp.cdb and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.ace_cmp.ecobp b/shifter_8b/db/shifter_8b.ace_cmp.ecobp deleted file mode 100644 index e05efff..0000000 Binary files a/shifter_8b/db/shifter_8b.ace_cmp.ecobp and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.ace_cmp.hdb b/shifter_8b/db/shifter_8b.ace_cmp.hdb deleted file mode 100644 index bbcc1eb..0000000 Binary files a/shifter_8b/db/shifter_8b.ace_cmp.hdb and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.asm.qmsg b/shifter_8b/db/shifter_8b.asm.qmsg deleted file mode 100644 index 5a628fe..0000000 --- a/shifter_8b/db/shifter_8b.asm.qmsg +++ /dev/null @@ -1,7 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 10 14:51:55 2022 " "Info: Processing started: Thu Mar 10 14:51:55 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1} -{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "221 " "Info: Peak virtual memory: 221 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 10 14:51:55 2022 " "Info: Processing ended: Thu Mar 10 14:51:55 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/shifter_8b/db/shifter_8b.asm_labs.ddb b/shifter_8b/db/shifter_8b.asm_labs.ddb deleted file mode 100644 index c62b6e0..0000000 Binary files a/shifter_8b/db/shifter_8b.asm_labs.ddb and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.cbx.xml b/shifter_8b/db/shifter_8b.cbx.xml deleted file mode 100644 index 987243c..0000000 --- a/shifter_8b/db/shifter_8b.cbx.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/shifter_8b/db/shifter_8b.cmp.bpm b/shifter_8b/db/shifter_8b.cmp.bpm deleted file mode 100644 index cc8429e..0000000 Binary files a/shifter_8b/db/shifter_8b.cmp.bpm and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.cmp.cdb b/shifter_8b/db/shifter_8b.cmp.cdb deleted file mode 100644 index 191e041..0000000 Binary files a/shifter_8b/db/shifter_8b.cmp.cdb and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.cmp.ecobp b/shifter_8b/db/shifter_8b.cmp.ecobp deleted file mode 100644 index e05efff..0000000 Binary files a/shifter_8b/db/shifter_8b.cmp.ecobp and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.cmp.hdb b/shifter_8b/db/shifter_8b.cmp.hdb deleted file mode 100644 index f2b265d..0000000 Binary files a/shifter_8b/db/shifter_8b.cmp.hdb and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.cmp.kpt b/shifter_8b/db/shifter_8b.cmp.kpt deleted file mode 100644 index af39f60..0000000 --- a/shifter_8b/db/shifter_8b.cmp.kpt +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/shifter_8b/db/shifter_8b.cmp.logdb b/shifter_8b/db/shifter_8b.cmp.logdb deleted file mode 100644 index 626799f..0000000 --- a/shifter_8b/db/shifter_8b.cmp.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/shifter_8b/db/shifter_8b.cmp.rdb b/shifter_8b/db/shifter_8b.cmp.rdb deleted file mode 100644 index 32139d8..0000000 Binary files a/shifter_8b/db/shifter_8b.cmp.rdb and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.cmp.tdb b/shifter_8b/db/shifter_8b.cmp.tdb deleted file mode 100644 index 61fb5c4..0000000 Binary files a/shifter_8b/db/shifter_8b.cmp.tdb and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.cmp0.ddb b/shifter_8b/db/shifter_8b.cmp0.ddb deleted file mode 100644 index 4128497..0000000 Binary files a/shifter_8b/db/shifter_8b.cmp0.ddb and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.cmp2.ddb b/shifter_8b/db/shifter_8b.cmp2.ddb deleted file mode 100644 index 181930e..0000000 Binary files a/shifter_8b/db/shifter_8b.cmp2.ddb and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.cmp_merge.kpt b/shifter_8b/db/shifter_8b.cmp_merge.kpt deleted file mode 100644 index 1564f30..0000000 --- a/shifter_8b/db/shifter_8b.cmp_merge.kpt +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/shifter_8b/db/shifter_8b.db_info b/shifter_8b/db/shifter_8b.db_info deleted file mode 100644 index c221daa..0000000 --- a/shifter_8b/db/shifter_8b.db_info +++ /dev/null @@ -1,3 +0,0 @@ -Quartus_Version = Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition -Version_Index = 167832322 -Creation_Time = Mon Mar 07 10:34:26 2022 diff --git a/shifter_8b/db/shifter_8b.eco.cdb b/shifter_8b/db/shifter_8b.eco.cdb deleted file mode 100644 index 6612017..0000000 Binary files a/shifter_8b/db/shifter_8b.eco.cdb and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.fit.qmsg b/shifter_8b/db/shifter_8b.fit.qmsg deleted file mode 100644 index ee17fa5..0000000 --- a/shifter_8b/db/shifter_8b.fit.qmsg +++ /dev/null @@ -1,38 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 10 14:51:52 2022 " "Info: Processing started: Thu Mar 10 14:51:52 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 6 " "Info: Parallel compilation is enabled and will use 4 of the 6 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "IMPP_MPP_USER_DEVICE" "shifter_8b EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"shifter_8b\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1} -{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "2 21 " "Warning: No exact pin location assignment(s) for 2 pins of 21 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "L " "Info: Pin L not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { L } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 600 40 208 616 "L" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { L } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R " "Info: Pin R not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { R } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 648 40 208 664 "R" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { R } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1} -{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1} -{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "2 unused 3.3V 2 0 0 " "Info: Number of I/O pins in group: 2 (unused VREF, 3.3V VCCIO, 2 input, 0 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 2 30 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 35 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.3V 9 26 " "Info: I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 9 total pin(s) used -- 26 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 11 25 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 11 total pin(s) used -- 25 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y10 X34_Y19 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y10 to location X34_Y19" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} -{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y0 0 " "Info: Pin \"Y0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y1 0 " "Info: Pin \"Y1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y2 0 " "Info: Pin \"Y2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y3 0 " "Info: Pin \"Y3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y4 0 " "Info: Pin \"Y4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y5 0 " "Info: Pin \"Y5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y6 0 " "Info: Pin \"Y6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y7 0 " "Info: Pin \"Y7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/dev/quartus/shifter_8b/shifter_8b.fit.smsg " "Info: Generated suppressed messages file D:/dev/quartus/shifter_8b/shifter_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "285 " "Info: Peak virtual memory: 285 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 10 14:51:54 2022 " "Info: Processing ended: Thu Mar 10 14:51:54 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/shifter_8b/db/shifter_8b.hier_info b/shifter_8b/db/shifter_8b.hier_info deleted file mode 100644 index 0f7cb74..0000000 --- a/shifter_8b/db/shifter_8b.hier_info +++ /dev/null @@ -1,97 +0,0 @@ -|shifter_8b -Y0 <= triple_selector_8b:inst.Y0 -A6 => triple_selector_8b:inst.A7 -A6 => triple_selector_8b:inst.B6 -A6 => triple_selector_8b:inst.C5 -A7 => triple_selector_8b:inst.B7 -A7 => triple_selector_8b:inst.C6 -R => triple_selector_8b:inst.C7 -A5 => triple_selector_8b:inst.A6 -A5 => triple_selector_8b:inst.B5 -A5 => triple_selector_8b:inst.C4 -A4 => triple_selector_8b:inst.A5 -A4 => triple_selector_8b:inst.B4 -A4 => triple_selector_8b:inst.C3 -A3 => triple_selector_8b:inst.A4 -A3 => triple_selector_8b:inst.B3 -A3 => triple_selector_8b:inst.C2 -A2 => triple_selector_8b:inst.A3 -A2 => triple_selector_8b:inst.B2 -A2 => triple_selector_8b:inst.C1 -A1 => triple_selector_8b:inst.A2 -A1 => triple_selector_8b:inst.B1 -A1 => triple_selector_8b:inst.C0 -A0 => triple_selector_8b:inst.A1 -A0 => triple_selector_8b:inst.B0 -L => triple_selector_8b:inst.A0 -LM => triple_selector_8b:inst.AY -DM => triple_selector_8b:inst.BY -RM => triple_selector_8b:inst.CY -Y1 <= triple_selector_8b:inst.Y1 -Y2 <= triple_selector_8b:inst.Y2 -Y3 <= triple_selector_8b:inst.Y3 -Y4 <= triple_selector_8b:inst.Y4 -Y5 <= triple_selector_8b:inst.Y5 -Y6 <= triple_selector_8b:inst.Y6 -Y7 <= triple_selector_8b:inst.Y7 - - -|shifter_8b|triple_selector_8b:inst -Y0 <= inst3.DB_MAX_OUTPUT_PORT_TYPE -B0 => inst1.IN0 -BY => inst1.IN1 -BY => inst5.IN1 -BY => inst9.IN1 -BY => inst13.IN1 -BY => inst16.IN1 -BY => inst21.IN1 -BY => inst24.IN1 -BY => inst29.IN1 -C0 => inst2.IN0 -CY => inst2.IN1 -CY => inst6.IN1 -CY => inst10.IN1 -CY => inst14.IN1 -CY => inst18.IN1 -CY => inst22.IN1 -CY => inst26.IN1 -CY => inst30.IN1 -A0 => inst.IN0 -AY => inst.IN1 -AY => inst4.IN1 -AY => inst8.IN1 -AY => inst12.IN1 -AY => inst17.IN1 -AY => inst20.IN1 -AY => inst25.IN1 -AY => inst28.IN1 -Y1 <= inst7.DB_MAX_OUTPUT_PORT_TYPE -B1 => inst5.IN0 -C1 => inst6.IN0 -A1 => inst4.IN0 -Y2 <= inst11.DB_MAX_OUTPUT_PORT_TYPE -B2 => inst9.IN0 -C2 => inst10.IN0 -A2 => inst8.IN0 -Y3 <= inst15.DB_MAX_OUTPUT_PORT_TYPE -B3 => inst13.IN0 -C3 => inst14.IN0 -A3 => inst12.IN0 -Y4 <= inst19.DB_MAX_OUTPUT_PORT_TYPE -B4 => inst16.IN0 -C4 => inst18.IN0 -A4 => inst17.IN0 -Y5 <= inst23.DB_MAX_OUTPUT_PORT_TYPE -B5 => inst21.IN0 -C5 => inst22.IN0 -A5 => inst20.IN0 -Y6 <= inst27.DB_MAX_OUTPUT_PORT_TYPE -B6 => inst24.IN0 -C6 => inst26.IN0 -A6 => inst25.IN0 -Y7 <= inst31.DB_MAX_OUTPUT_PORT_TYPE -B7 => inst29.IN0 -C7 => inst30.IN0 -A7 => inst28.IN0 - - diff --git a/shifter_8b/db/shifter_8b.hif b/shifter_8b/db/shifter_8b.hif deleted file mode 100644 index 64b1126..0000000 --- a/shifter_8b/db/shifter_8b.hif +++ /dev/null @@ -1,62 +0,0 @@ -Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition -11 -936 -OFF -OFF -OFF -ON -ON -ON -FV_OFF -Level2 -0 -0 -VRSM_ON -VHSM_ON -0 --- Start Library Paths -- --- End Library Paths -- --- Start VHDL Libraries -- --- End VHDL Libraries -- -# entity -triple_selector_8b -# storage -db|shifter_8b.(1).cnf -db|shifter_8b.(1).cnf -# case_insensitive -# source_file -triple_selector_8b.bdf -faf397453d6830c2ec2358bb378770 -26 -# internal_option { -BLOCK_DESIGN_NAMING -AUTO -} -# hierarchies { -triple_selector_8b:inst -} -# macro_sequence - -# end -# entity -shifter_8b -# storage -db|shifter_8b.(0).cnf -db|shifter_8b.(0).cnf -# case_insensitive -# source_file -shifter_8b.bdf -14397f4ea413e68c8a371bb5b73c93a -26 -# internal_option { -BLOCK_DESIGN_NAMING -AUTO -} -# hierarchies { -| -} -# macro_sequence - -# end -# complete - \ No newline at end of file diff --git a/shifter_8b/db/shifter_8b.lpc.html b/shifter_8b/db/shifter_8b.lpc.html deleted file mode 100644 index 10ca6de..0000000 --- a/shifter_8b/db/shifter_8b.lpc.html +++ /dev/null @@ -1,34 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
inst27000800000000
diff --git a/shifter_8b/db/shifter_8b.lpc.rdb b/shifter_8b/db/shifter_8b.lpc.rdb deleted file mode 100644 index 884f110..0000000 Binary files a/shifter_8b/db/shifter_8b.lpc.rdb and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.lpc.txt b/shifter_8b/db/shifter_8b.lpc.txt deleted file mode 100644 index 2bd42f8..0000000 --- a/shifter_8b/db/shifter_8b.lpc.txt +++ /dev/null @@ -1,7 +0,0 @@ -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Legal Partition Candidates ; -+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ -; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; -+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ -; inst ; 27 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/shifter_8b/db/shifter_8b.map.bpm b/shifter_8b/db/shifter_8b.map.bpm deleted file mode 100644 index 988c98c..0000000 Binary files a/shifter_8b/db/shifter_8b.map.bpm and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.map.cdb b/shifter_8b/db/shifter_8b.map.cdb deleted file mode 100644 index a617aba..0000000 Binary files a/shifter_8b/db/shifter_8b.map.cdb and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.map.ecobp b/shifter_8b/db/shifter_8b.map.ecobp deleted file mode 100644 index e05efff..0000000 Binary files a/shifter_8b/db/shifter_8b.map.ecobp and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.map.hdb b/shifter_8b/db/shifter_8b.map.hdb deleted file mode 100644 index 57e3b9a..0000000 Binary files a/shifter_8b/db/shifter_8b.map.hdb and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.map.kpt b/shifter_8b/db/shifter_8b.map.kpt deleted file mode 100644 index 65ba414..0000000 --- a/shifter_8b/db/shifter_8b.map.kpt +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/shifter_8b/db/shifter_8b.map.logdb b/shifter_8b/db/shifter_8b.map.logdb deleted file mode 100644 index 626799f..0000000 --- a/shifter_8b/db/shifter_8b.map.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/shifter_8b/db/shifter_8b.map.qmsg b/shifter_8b/db/shifter_8b.map.qmsg deleted file mode 100644 index 2349420..0000000 --- a/shifter_8b/db/shifter_8b.map.qmsg +++ /dev/null @@ -1,9 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 10 14:51:50 2022 " "Info: Processing started: Thu Mar 10 14:51:50 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 shifter_8b " "Info: Found entity 1: shifter_8b" { } { { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_START_ELABORATION_TOP" "shifter_8b " "Info: Elaborating entity \"shifter_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} -{ "Warning" "WSGN_SEARCH_FILE" "triple_selector_8b.bdf 1 1 " "Warning: Using design file triple_selector_8b.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 triple_selector_8b " "Info: Found entity 1: triple_selector_8b" { } { { "triple_selector_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/triple_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "triple_selector_8b triple_selector_8b:inst " "Info: Elaborating entity \"triple_selector_8b\" for hierarchy \"triple_selector_8b:inst\"" { } { { "shifter_8b.bdf" "inst" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 32 488 584 512 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_TM_SUMMARY" "37 " "Info: Implemented 37 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "13 " "Info: Implemented 13 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "16 " "Info: Implemented 16 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "229 " "Info: Peak virtual memory: 229 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 10 14:51:52 2022 " "Info: Processing ended: Thu Mar 10 14:51:52 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/shifter_8b/db/shifter_8b.map_bb.cdb b/shifter_8b/db/shifter_8b.map_bb.cdb deleted file mode 100644 index 0cab0de..0000000 Binary files a/shifter_8b/db/shifter_8b.map_bb.cdb and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.map_bb.hdb b/shifter_8b/db/shifter_8b.map_bb.hdb deleted file mode 100644 index 775b08c..0000000 Binary files a/shifter_8b/db/shifter_8b.map_bb.hdb and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.map_bb.logdb b/shifter_8b/db/shifter_8b.map_bb.logdb deleted file mode 100644 index 626799f..0000000 --- a/shifter_8b/db/shifter_8b.map_bb.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/shifter_8b/db/shifter_8b.pre_map.cdb b/shifter_8b/db/shifter_8b.pre_map.cdb deleted file mode 100644 index 7106886..0000000 Binary files a/shifter_8b/db/shifter_8b.pre_map.cdb and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.pre_map.hdb b/shifter_8b/db/shifter_8b.pre_map.hdb deleted file mode 100644 index 884b2a0..0000000 Binary files a/shifter_8b/db/shifter_8b.pre_map.hdb and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.rtlv.hdb b/shifter_8b/db/shifter_8b.rtlv.hdb deleted file mode 100644 index c3a5b2f..0000000 Binary files a/shifter_8b/db/shifter_8b.rtlv.hdb and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.rtlv_sg.cdb b/shifter_8b/db/shifter_8b.rtlv_sg.cdb deleted file mode 100644 index b7e94e7..0000000 Binary files a/shifter_8b/db/shifter_8b.rtlv_sg.cdb and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.rtlv_sg_swap.cdb b/shifter_8b/db/shifter_8b.rtlv_sg_swap.cdb deleted file mode 100644 index 5805851..0000000 Binary files a/shifter_8b/db/shifter_8b.rtlv_sg_swap.cdb and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.sgdiff.cdb b/shifter_8b/db/shifter_8b.sgdiff.cdb deleted file mode 100644 index d1a7ce5..0000000 Binary files a/shifter_8b/db/shifter_8b.sgdiff.cdb and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.sgdiff.hdb b/shifter_8b/db/shifter_8b.sgdiff.hdb deleted file mode 100644 index 1be715b..0000000 Binary files a/shifter_8b/db/shifter_8b.sgdiff.hdb and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.sld_design_entry.sci b/shifter_8b/db/shifter_8b.sld_design_entry.sci deleted file mode 100644 index 904d003..0000000 Binary files a/shifter_8b/db/shifter_8b.sld_design_entry.sci and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.sld_design_entry_dsc.sci b/shifter_8b/db/shifter_8b.sld_design_entry_dsc.sci deleted file mode 100644 index 2000bdc..0000000 Binary files a/shifter_8b/db/shifter_8b.sld_design_entry_dsc.sci and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.syn_hier_info b/shifter_8b/db/shifter_8b.syn_hier_info deleted file mode 100644 index e69de29..0000000 diff --git a/shifter_8b/db/shifter_8b.tan.qmsg b/shifter_8b/db/shifter_8b.tan.qmsg deleted file mode 100644 index ca06444..0000000 --- a/shifter_8b/db/shifter_8b.tan.qmsg +++ /dev/null @@ -1,6 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 10 14:51:56 2022 " "Info: Processing started: Thu Mar 10 14:51:56 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 6 " "Info: Parallel compilation is enabled and will use 4 of the 6 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "ITDB_FULL_TPD_RESULT" "LM Y6 15.646 ns Longest " "Info: Longest tpd from source pin \"LM\" to destination pin \"Y6\" is 15.646 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns LM 1 PIN PIN_69 8 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_69; Fanout = 8; PIN Node = 'LM'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LM } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 456 40 208 472 "LM" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.993 ns) + CELL(0.624 ns) 8.611 ns triple_selector_8b:inst\|inst27~0 2 COMB LCCOMB_X21_Y10_N24 1 " "Info: 2: + IC(6.993 ns) + CELL(0.624 ns) = 8.611 ns; Loc. = LCCOMB_X21_Y10_N24; Fanout = 1; COMB Node = 'triple_selector_8b:inst\|inst27~0'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.617 ns" { LM triple_selector_8b:inst|inst27~0 } "NODE_NAME" } } { "triple_selector_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/triple_selector_8b.bdf" { { 208 488 552 256 "inst27" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.395 ns) + CELL(0.651 ns) 9.657 ns triple_selector_8b:inst\|inst27 3 COMB LCCOMB_X21_Y10_N18 1 " "Info: 3: + IC(0.395 ns) + CELL(0.651 ns) = 9.657 ns; Loc. = LCCOMB_X21_Y10_N18; Fanout = 1; COMB Node = 'triple_selector_8b:inst\|inst27'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.046 ns" { triple_selector_8b:inst|inst27~0 triple_selector_8b:inst|inst27 } "NODE_NAME" } } { "triple_selector_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/triple_selector_8b.bdf" { { 208 488 552 256 "inst27" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.873 ns) + CELL(3.116 ns) 15.646 ns Y6 4 PIN PIN_149 0 " "Info: 4: + IC(2.873 ns) + CELL(3.116 ns) = 15.646 ns; Loc. = PIN_149; Fanout = 0; PIN Node = 'Y6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.989 ns" { triple_selector_8b:inst|inst27 Y6 } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 72 688 864 88 "Y6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.385 ns ( 34.42 % ) " "Info: Total cell delay = 5.385 ns ( 34.42 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "10.261 ns ( 65.58 % ) " "Info: Total interconnect delay = 10.261 ns ( 65.58 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "15.646 ns" { LM triple_selector_8b:inst|inst27~0 triple_selector_8b:inst|inst27 Y6 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "15.646 ns" { LM {} LM~combout {} triple_selector_8b:inst|inst27~0 {} triple_selector_8b:inst|inst27 {} Y6 {} } { 0.000ns 0.000ns 6.993ns 0.395ns 2.873ns } { 0.000ns 0.994ns 0.624ns 0.651ns 3.116ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "191 " "Info: Peak virtual memory: 191 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 10 14:51:56 2022 " "Info: Processing ended: Thu Mar 10 14:51:56 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/shifter_8b/db/shifter_8b.tis_db_list.ddb b/shifter_8b/db/shifter_8b.tis_db_list.ddb deleted file mode 100644 index 2a9a6ed..0000000 Binary files a/shifter_8b/db/shifter_8b.tis_db_list.ddb and /dev/null differ diff --git a/shifter_8b/db/shifter_8b.tmw_info b/shifter_8b/db/shifter_8b.tmw_info deleted file mode 100644 index 6320ab9..0000000 --- a/shifter_8b/db/shifter_8b.tmw_info +++ /dev/null @@ -1,6 +0,0 @@ -start_full_compilation:s:00:00:07 -start_analysis_synthesis:s:00:00:02-start_full_compilation -start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:02-start_full_compilation -start_assembler:s:00:00:02-start_full_compilation -start_timing_analyzer:s:00:00:01-start_full_compilation diff --git a/shifter_8b/incremental_db/README b/shifter_8b/incremental_db/README deleted file mode 100644 index 9f62dcd..0000000 --- a/shifter_8b/incremental_db/README +++ /dev/null @@ -1,11 +0,0 @@ -This folder contains data for incremental compilation. - -The compiled_partitions sub-folder contains previous compilation results for each partition. -As long as this folder is preserved, incremental compilation results from earlier compiles -can be re-used. To perform a clean compilation from source files for all partitions, both -the db and incremental_db folder should be removed. - -The imported_partitions sub-folder contains the last imported QXP for each imported partition. -As long as this folder is preserved, imported partitions will be automatically re-imported -when the db or incremental_db/compiled_partitions folders are removed. - diff --git a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.atm b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.atm deleted file mode 100644 index f04330e..0000000 Binary files a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.atm and /dev/null differ diff --git a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.dfp b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.dfp deleted file mode 100644 index b1c67d6..0000000 Binary files a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.dfp and /dev/null differ diff --git a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.hdbx b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.hdbx deleted file mode 100644 index 42118be..0000000 Binary files a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.hdbx and /dev/null differ diff --git a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.kpt b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.kpt deleted file mode 100644 index c1e72d7..0000000 --- a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.kpt +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.logdb b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.logdb deleted file mode 100644 index 626799f..0000000 --- a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.rcf b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.rcf deleted file mode 100644 index f7800b8..0000000 Binary files a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.rcf and /dev/null differ diff --git a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.atm b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.atm deleted file mode 100644 index 7539b6a..0000000 Binary files a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.atm and /dev/null differ diff --git a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.dpi b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.dpi deleted file mode 100644 index 30e6f1b..0000000 Binary files a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.dpi and /dev/null differ diff --git a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.hdbx b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.hdbx deleted file mode 100644 index ec5437c..0000000 Binary files a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.hdbx and /dev/null differ diff --git a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.kpt b/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.kpt deleted file mode 100644 index bed78aa..0000000 --- a/shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.kpt +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/shifter_8b/shifter_8b.asm.rpt b/shifter_8b/shifter_8b.asm.rpt deleted file mode 100644 index 9619932..0000000 --- a/shifter_8b/shifter_8b.asm.rpt +++ /dev/null @@ -1,129 +0,0 @@ -Assembler report for shifter_8b -Thu Mar 10 14:51:55 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Assembler Summary - 3. Assembler Settings - 4. Assembler Generated Files - 5. Assembler Device Options: D:/dev/quartus/shifter_8b/shifter_8b.sof - 6. Assembler Device Options: D:/dev/quartus/shifter_8b/shifter_8b.pof - 7. Assembler Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+---------------------------------------------------------------+ -; Assembler Summary ; -+-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Thu Mar 10 14:51:55 2022 ; -; Revision Name ; shifter_8b ; -; Top-level Entity Name ; shifter_8b ; -; Family ; Cyclone II ; -; Device ; EP2C8Q208C8 ; -+-----------------------+---------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------+ -; Assembler Settings ; -+-----------------------------------------------------------------------------+----------+---------------+ -; Option ; Setting ; Default Value ; -+-----------------------------------------------------------------------------+----------+---------------+ -; Use smart compilation ; Off ; Off ; -; Generate compressed bitstreams ; On ; On ; -; Compression mode ; Off ; Off ; -; Clock source for configuration device ; Internal ; Internal ; -; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; -; Divide clock frequency by ; 1 ; 1 ; -; Auto user code ; Off ; Off ; -; Use configuration device ; On ; On ; -; Configuration device ; Auto ; Auto ; -; Configuration device auto user code ; Off ; Off ; -; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; -; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; -; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; -; Hexadecimal Output File start address ; 0 ; 0 ; -; Hexadecimal Output File count direction ; Up ; Up ; -; Release clears before tri-states ; Off ; Off ; -; Auto-restart configuration after error ; On ; On ; -; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ; -; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; -; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; -; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; -; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; -+-----------------------------------------------------------------------------+----------+---------------+ - - -+------------------------------------------+ -; Assembler Generated Files ; -+------------------------------------------+ -; File Name ; -+------------------------------------------+ -; D:/dev/quartus/shifter_8b/shifter_8b.sof ; -; D:/dev/quartus/shifter_8b/shifter_8b.pof ; -+------------------------------------------+ - - -+--------------------------------------------------------------------+ -; Assembler Device Options: D:/dev/quartus/shifter_8b/shifter_8b.sof ; -+----------------+---------------------------------------------------+ -; Option ; Setting ; -+----------------+---------------------------------------------------+ -; Device ; EP2C8Q208C8 ; -; JTAG usercode ; 0xFFFFFFFF ; -; Checksum ; 0x000C2D71 ; -+----------------+---------------------------------------------------+ - - -+--------------------------------------------------------------------+ -; Assembler Device Options: D:/dev/quartus/shifter_8b/shifter_8b.pof ; -+--------------------+-----------------------------------------------+ -; Option ; Setting ; -+--------------------+-----------------------------------------------+ -; Device ; EPCS4 ; -; JTAG usercode ; 0x00000000 ; -; Checksum ; 0x06EFF64A ; -; Compression Ratio ; 3 ; -+--------------------+-----------------------------------------------+ - - -+--------------------+ -; Assembler Messages ; -+--------------------+ -Info: ******************************************************************* -Info: Running Quartus II Assembler - Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Thu Mar 10 14:51:55 2022 -Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b -Info: Writing out detailed assembly data for power analysis -Info: Assembler is generating device programming files -Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled -Info: Quartus II Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 221 megabytes - Info: Processing ended: Thu Mar 10 14:51:55 2022 - Info: Elapsed time: 00:00:00 - Info: Total CPU time (on all processors): 00:00:01 - - diff --git a/shifter_8b/shifter_8b.done b/shifter_8b/shifter_8b.done deleted file mode 100644 index b8bb2c4..0000000 --- a/shifter_8b/shifter_8b.done +++ /dev/null @@ -1 +0,0 @@ -Thu Mar 10 14:51:57 2022 diff --git a/shifter_8b/shifter_8b.fit.rpt b/shifter_8b/shifter_8b.fit.rpt deleted file mode 100644 index 13bb269..0000000 --- a/shifter_8b/shifter_8b.fit.rpt +++ /dev/null @@ -1,998 +0,0 @@ -Fitter report for shifter_8b -Thu Mar 10 14:51:54 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Fitter Summary - 3. Fitter Settings - 4. Parallel Compilation - 5. Incremental Compilation Preservation Summary - 6. Incremental Compilation Partition Settings - 7. Incremental Compilation Placement Preservation - 8. Pin-Out File - 9. Fitter Resource Usage Summary - 10. Input Pins - 11. Output Pins - 12. I/O Bank Usage - 13. All Package Pins - 14. Output Pin Default Load For Reported TCO - 15. Fitter Resource Utilization by Entity - 16. Delay Chain Summary - 17. Pad To Core Delay Chain Fanout - 18. Non-Global High Fan-Out Signals - 19. Interconnect Usage Summary - 20. LAB Logic Elements - 21. LAB Signals Sourced - 22. LAB Signals Sourced Out - 23. LAB Distinct Inputs - 24. Fitter Device Options - 25. Operating Settings and Conditions - 26. Estimated Delay Added for Hold Timing - 27. Advanced Data - General - 28. Advanced Data - Placement Preparation - 29. Advanced Data - Placement - 30. Advanced Data - Routing - 31. Fitter Messages - 32. Fitter Suppressed Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------------+ -; Fitter Summary ; -+------------------------------------+----------------------------------------------+ -; Fitter Status ; Successful - Thu Mar 10 14:51:54 2022 ; -; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; -; Revision Name ; shifter_8b ; -; Top-level Entity Name ; shifter_8b ; -; Family ; Cyclone II ; -; Device ; EP2C8Q208C8 ; -; Timing Models ; Final ; -; Total logic elements ; 16 / 8,256 ( < 1 % ) ; -; Total combinational functions ; 16 / 8,256 ( < 1 % ) ; -; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ; -; Total registers ; 0 ; -; Total pins ; 21 / 138 ( 15 % ) ; -; Total virtual pins ; 0 ; -; Total memory bits ; 0 / 165,888 ( 0 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; -; Total PLLs ; 0 / 2 ( 0 % ) ; -+------------------------------------+----------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Settings ; -+--------------------------------------------------------------------+--------------------------------+--------------------------------+ -; Option ; Setting ; Default Value ; -+--------------------------------------------------------------------+--------------------------------+--------------------------------+ -; Device ; EP2C8Q208C8 ; ; -; Minimum Core Junction Temperature ; 0 ; ; -; Maximum Core Junction Temperature ; 85 ; ; -; Fit Attempts to Skip ; 0 ; 0.0 ; -; Device I/O Standard ; 3.3-V LVTTL ; ; -; Use smart compilation ; Off ; Off ; -; Use TimeQuest Timing Analyzer ; Off ; Off ; -; Router Timing Optimization Level ; Normal ; Normal ; -; Placement Effort Multiplier ; 1.0 ; 1.0 ; -; Router Effort Multiplier ; 1.0 ; 1.0 ; -; Always Enable Input Buffers ; Off ; Off ; -; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; -; Optimize Multi-Corner Timing ; Off ; Off ; -; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; -; Optimize Timing ; Normal compilation ; Normal compilation ; -; Optimize Timing for ECOs ; Off ; Off ; -; Regenerate full fit report during ECO compiles ; Off ; Off ; -; Optimize IOC Register Placement for Timing ; On ; On ; -; Limit to One Fitting Attempt ; Off ; Off ; -; Final Placement Optimizations ; Automatically ; Automatically ; -; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; -; Fitter Initial Placement Seed ; 1 ; 1 ; -; PCI I/O ; Off ; Off ; -; Weak Pull-Up Resistor ; Off ; Off ; -; Enable Bus-Hold Circuitry ; Off ; Off ; -; Auto Global Memory Control Signals ; Off ; Off ; -; Auto Packed Registers ; Auto ; Auto ; -; Auto Delay Chains ; On ; On ; -; Auto Merge PLLs ; On ; On ; -; Ignore PLL Mode When Merging PLLs ; Off ; Off ; -; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; -; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; -; Perform Register Duplication for Performance ; Off ; Off ; -; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; -; Perform Register Retiming for Performance ; Off ; Off ; -; Perform Asynchronous Signal Pipelining ; Off ; Off ; -; Fitter Effort ; Auto Fit ; Auto Fit ; -; Physical Synthesis Effort Level ; Normal ; Normal ; -; Auto Global Clock ; On ; On ; -; Auto Global Register Control Signals ; On ; On ; -; Stop After Congestion Map Generation ; Off ; Off ; -; Save Intermediate Fitting Results ; Off ; Off ; -; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; -+--------------------------------------------------------------------+--------------------------------+--------------------------------+ - - -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 6 ; -; Maximum allowed ; 4 ; -; ; ; -; Average used ; 1.00 ; -; Maximum used ; 4 ; -; ; ; -; Usage by Processor ; % Time Used ; -; 1 processor ; 100.0% ; -; 2-4 processors ; < 0.1% ; -; 5-6 processors ; 0.0% ; -+----------------------------+-------------+ - - -+----------------------------------------------+ -; Incremental Compilation Preservation Summary ; -+-------------------------+--------------------+ -; Type ; Value ; -+-------------------------+--------------------+ -; Placement ; ; -; -- Requested ; 0 / 37 ( 0.00 % ) ; -; -- Achieved ; 0 / 37 ( 0.00 % ) ; -; ; ; -; Routing (by Connection) ; ; -; -- Requested ; 0 / 0 ( 0.00 % ) ; -; -- Achieved ; 0 / 0 ( 0.00 % ) ; -+-------------------------+--------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Incremental Compilation Partition Settings ; -+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ -; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; -+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ -; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; -+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ - - -+--------------------------------------------------------------------------------------------+ -; Incremental Compilation Placement Preservation ; -+----------------+---------+-------------------+-------------------------+-------------------+ -; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; -+----------------+---------+-------------------+-------------------------+-------------------+ -; Top ; 37 ; 0 ; N/A ; Source File ; -+----------------+---------+-------------------+-------------------------+-------------------+ - - -+--------------+ -; Pin-Out File ; -+--------------+ -The pin-out file can be found in D:/dev/quartus/shifter_8b/shifter_8b.pin. - - -+--------------------------------------------------------------------+ -; Fitter Resource Usage Summary ; -+---------------------------------------------+----------------------+ -; Resource ; Usage ; -+---------------------------------------------+----------------------+ -; Total logic elements ; 16 / 8,256 ( < 1 % ) ; -; -- Combinational with no register ; 16 ; -; -- Register only ; 0 ; -; -- Combinational with a register ; 0 ; -; ; ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 8 ; -; -- 3 input functions ; 8 ; -; -- <=2 input functions ; 0 ; -; -- Register only ; 0 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 16 ; -; -- arithmetic mode ; 0 ; -; ; ; -; Total registers* ; 0 / 8,646 ( 0 % ) ; -; -- Dedicated logic registers ; 0 / 8,256 ( 0 % ) ; -; -- I/O registers ; 0 / 390 ( 0 % ) ; -; ; ; -; Total LABs: partially or completely used ; 1 / 516 ( < 1 % ) ; -; User inserted logic elements ; 0 ; -; Virtual pins ; 0 ; -; I/O pins ; 21 / 138 ( 15 % ) ; -; -- Clock pins ; 0 / 4 ( 0 % ) ; -; Global signals ; 0 ; -; M4Ks ; 0 / 36 ( 0 % ) ; -; Total block memory bits ; 0 / 165,888 ( 0 % ) ; -; Total block memory implementation bits ; 0 / 165,888 ( 0 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; -; PLLs ; 0 / 2 ( 0 % ) ; -; Global clocks ; 0 / 8 ( 0 % ) ; -; JTAGs ; 0 / 1 ( 0 % ) ; -; ASMI blocks ; 0 / 1 ( 0 % ) ; -; CRC blocks ; 0 / 1 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; -; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ; -; Maximum fan-out node ; LM ; -; Maximum fan-out ; 8 ; -; Highest non-global fan-out signal ; LM ; -; Highest non-global fan-out ; 8 ; -; Total fan-out ; 64 ; -; Average fan-out ; 1.60 ; -+---------------------------------------------+----------------------+ -* Register count does not include registers inside RAM blocks or DSP blocks. - - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Input Pins ; -+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ; -+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ -; A0 ; 77 ; 4 ; 18 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; A1 ; 80 ; 4 ; 23 ; 0 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; A2 ; 81 ; 4 ; 23 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; A3 ; 82 ; 4 ; 23 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; A4 ; 84 ; 4 ; 25 ; 0 ; 3 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; A5 ; 86 ; 4 ; 25 ; 0 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; A6 ; 87 ; 4 ; 25 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; A7 ; 88 ; 4 ; 25 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; DM ; 68 ; 4 ; 12 ; 0 ; 1 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; L ; 92 ; 4 ; 28 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; LM ; 69 ; 4 ; 12 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -; R ; 76 ; 4 ; 18 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; RM ; 67 ; 4 ; 9 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; -+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Output Pins ; -+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; -+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ -; Y0 ; 142 ; 3 ; 34 ; 12 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; Y1 ; 143 ; 3 ; 34 ; 13 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; Y2 ; 144 ; 3 ; 34 ; 13 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; Y3 ; 145 ; 3 ; 34 ; 14 ; 4 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; Y4 ; 146 ; 3 ; 34 ; 15 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; Y5 ; 147 ; 3 ; 34 ; 15 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; Y6 ; 149 ; 3 ; 34 ; 16 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -; Y7 ; 150 ; 3 ; 34 ; 16 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ; -+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ - - -+------------------------------------------------------------+ -; I/O Bank Usage ; -+----------+------------------+---------------+--------------+ -; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; -+----------+------------------+---------------+--------------+ -; 1 ; 2 / 32 ( 6 % ) ; 3.3V ; -- ; -; 2 ; 0 / 35 ( 0 % ) ; 3.3V ; -- ; -; 3 ; 9 / 35 ( 26 % ) ; 3.3V ; -- ; -; 4 ; 13 / 36 ( 36 % ) ; 3.3V ; -- ; -+----------+------------------+---------------+--------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; All Package Pins ; -+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; -+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -; 1 ; 0 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; -; 2 ; 1 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; -; 3 ; 2 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 4 ; 3 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 5 ; 4 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 6 ; 5 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 8 ; 6 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 10 ; 7 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 11 ; 8 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 12 ; 9 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 13 ; 10 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 14 ; 18 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 15 ; 19 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; -; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; -; 18 ; 22 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; -; 19 ; 23 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; -; 20 ; 24 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ; -; 21 ; 25 ; 1 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ; -; 22 ; 26 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; -; 23 ; 27 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 24 ; 28 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 26 ; 29 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; -; 27 ; 30 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 28 ; 31 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 30 ; 32 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 31 ; 33 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 33 ; 35 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 34 ; 36 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 35 ; 37 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 37 ; 39 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 39 ; 43 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 40 ; 44 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 41 ; 45 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 42 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 43 ; 48 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 44 ; 49 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 45 ; 50 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 46 ; 51 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 47 ; 52 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 48 ; 53 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 49 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 50 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; -; 51 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 52 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; -; 53 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 54 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; -; 55 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 56 ; 54 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 57 ; 55 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 58 ; 56 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 59 ; 57 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 60 ; 58 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 61 ; 59 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 63 ; 60 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 64 ; 61 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 67 ; 69 ; 4 ; RM ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 68 ; 70 ; 4 ; DM ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 69 ; 71 ; 4 ; LM ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 70 ; 74 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 71 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 72 ; 75 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 74 ; 76 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 75 ; 77 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 76 ; 78 ; 4 ; R ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 77 ; 79 ; 4 ; A0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 80 ; 82 ; 4 ; A1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 81 ; 83 ; 4 ; A2 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 82 ; 84 ; 4 ; A3 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 83 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 84 ; 85 ; 4 ; A4 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 85 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 86 ; 86 ; 4 ; A5 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 87 ; 87 ; 4 ; A6 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 88 ; 88 ; 4 ; A7 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 89 ; 89 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 90 ; 90 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 91 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 92 ; 91 ; 4 ; L ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 94 ; 92 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 95 ; 93 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 96 ; 94 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 97 ; 95 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 98 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 99 ; 96 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 100 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 101 ; 97 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 102 ; 98 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 103 ; 99 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 104 ; 100 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 105 ; 101 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 106 ; 102 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 107 ; 105 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 108 ; 106 ; 3 ; ~LVDS54p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 109 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 110 ; 107 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 111 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 112 ; 108 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 113 ; 109 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 114 ; 110 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 115 ; 112 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 116 ; 113 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 117 ; 114 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 118 ; 117 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 119 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 120 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 121 ; 121 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; -; 122 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 123 ; 122 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; -; 124 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 125 ; 123 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; -; 126 ; 124 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; -; 127 ; 125 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 128 ; 126 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 129 ; 127 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 130 ; 128 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 131 ; 129 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 132 ; 130 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 133 ; 131 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 134 ; 132 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 135 ; 133 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 136 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 137 ; 134 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 138 ; 135 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 139 ; 136 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 141 ; 137 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 142 ; 138 ; 3 ; Y0 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 143 ; 141 ; 3 ; Y1 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 144 ; 142 ; 3 ; Y2 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 145 ; 143 ; 3 ; Y3 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 146 ; 149 ; 3 ; Y4 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 147 ; 150 ; 3 ; Y5 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 148 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 149 ; 151 ; 3 ; Y6 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 150 ; 152 ; 3 ; Y7 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 151 ; 153 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 152 ; 154 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 153 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 154 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; -; 155 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 156 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; -; 157 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 158 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; -; 159 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 160 ; 155 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 161 ; 156 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 162 ; 157 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 163 ; 158 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 164 ; 159 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 165 ; 160 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 166 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 167 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 168 ; 161 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 169 ; 162 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 170 ; 163 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 171 ; 164 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 172 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 173 ; 165 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 174 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 175 ; 168 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 176 ; 169 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 177 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 178 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 179 ; 173 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 180 ; 174 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 181 ; 175 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 182 ; 176 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 183 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 184 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 185 ; 180 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 186 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 187 ; 181 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 188 ; 182 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 189 ; 183 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 190 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 191 ; 184 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 192 ; 185 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 193 ; 186 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 194 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 195 ; 187 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 196 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 197 ; 191 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 198 ; 192 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 199 ; 195 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 200 ; 196 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 201 ; 197 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 202 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 203 ; 198 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 204 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 205 ; 199 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 206 ; 200 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 207 ; 201 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 208 ; 202 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -Note: Pin directions (input, output or bidir) are based on device operating in user mode. - - -+-------------------------------------------------------------------------------+ -; Output Pin Default Load For Reported TCO ; -+----------------------------------+-------+------------------------------------+ -; I/O Standard ; Load ; Termination Resistance ; -+----------------------------------+-------+------------------------------------+ -; 3.3-V LVTTL ; 0 pF ; Not Available ; -; 3.3-V LVCMOS ; 0 pF ; Not Available ; -; 2.5 V ; 0 pF ; Not Available ; -; 1.8 V ; 0 pF ; Not Available ; -; 1.5 V ; 0 pF ; Not Available ; -; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ; -; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ; -; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; -; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; -; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; -; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; -; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; -; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; -; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; -; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; -; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ; -; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ; -; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ; -; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ; -; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ; -; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ; -; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ; -; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ; -; LVDS ; 0 pF ; 100 Ohm (Differential) ; -; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ; -; RSDS ; 0 pF ; 100 Ohm (Differential) ; -; Simple RSDS ; 0 pF ; Not Available ; -; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ; -+----------------------------------+-------+------------------------------------+ -Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Resource Utilization by Entity ; -+------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------+--------------+ -; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; -+------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------+--------------+ -; |shifter_8b ; 16 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 21 ; 0 ; 16 (0) ; 0 (0) ; 0 (0) ; |shifter_8b ; work ; -; |triple_selector_8b:inst| ; 16 (16) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (16) ; 0 (0) ; 0 (0) ; |shifter_8b|triple_selector_8b:inst ; work ; -+------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------+--------------+ -Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. - - -+-------------------------------------------------------------------------------+ -; Delay Chain Summary ; -+------+----------+---------------+---------------+-----------------------+-----+ -; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; -+------+----------+---------------+---------------+-----------------------+-----+ -; Y0 ; Output ; -- ; -- ; -- ; -- ; -; Y1 ; Output ; -- ; -- ; -- ; -- ; -; Y2 ; Output ; -- ; -- ; -- ; -- ; -; Y3 ; Output ; -- ; -- ; -- ; -- ; -; Y4 ; Output ; -- ; -- ; -- ; -- ; -; Y5 ; Output ; -- ; -- ; -- ; -- ; -; Y6 ; Output ; -- ; -- ; -- ; -- ; -; Y7 ; Output ; -- ; -- ; -- ; -- ; -; A0 ; Input ; 6 ; 6 ; -- ; -- ; -; L ; Input ; 6 ; 6 ; -- ; -- ; -; LM ; Input ; 6 ; 6 ; -- ; -- ; -; DM ; Input ; 6 ; 6 ; -- ; -- ; -; A1 ; Input ; 6 ; 6 ; -- ; -- ; -; RM ; Input ; 6 ; 6 ; -- ; -- ; -; A2 ; Input ; 6 ; 6 ; -- ; -- ; -; A3 ; Input ; 6 ; 6 ; -- ; -- ; -; A4 ; Input ; 6 ; 6 ; -- ; -- ; -; A5 ; Input ; 6 ; 6 ; -- ; -- ; -; A6 ; Input ; 6 ; 6 ; -- ; -- ; -; A7 ; Input ; 6 ; 6 ; -- ; -- ; -; R ; Input ; 6 ; 6 ; -- ; -- ; -+------+----------+---------------+---------------+-----------------------+-----+ - - -+-----------------------------------------------------------------------+ -; Pad To Core Delay Chain Fanout ; -+-----------------------------------------+-------------------+---------+ -; Source Pin / Fanout ; Pad To Core Index ; Setting ; -+-----------------------------------------+-------------------+---------+ -; A0 ; ; ; -; - triple_selector_8b:inst|inst3~0 ; 1 ; 6 ; -; - triple_selector_8b:inst|inst7~0 ; 1 ; 6 ; -; L ; ; ; -; - triple_selector_8b:inst|inst3~0 ; 0 ; 6 ; -; LM ; ; ; -; - triple_selector_8b:inst|inst3~0 ; 1 ; 6 ; -; - triple_selector_8b:inst|inst7~0 ; 1 ; 6 ; -; - triple_selector_8b:inst|inst11~0 ; 1 ; 6 ; -; - triple_selector_8b:inst|inst15~0 ; 1 ; 6 ; -; - triple_selector_8b:inst|inst19~0 ; 1 ; 6 ; -; - triple_selector_8b:inst|inst23~0 ; 1 ; 6 ; -; - triple_selector_8b:inst|inst27~0 ; 1 ; 6 ; -; - triple_selector_8b:inst|inst31~0 ; 1 ; 6 ; -; DM ; ; ; -; - triple_selector_8b:inst|inst3~0 ; 0 ; 6 ; -; - triple_selector_8b:inst|inst7~0 ; 0 ; 6 ; -; - triple_selector_8b:inst|inst11~0 ; 0 ; 6 ; -; - triple_selector_8b:inst|inst15~0 ; 0 ; 6 ; -; - triple_selector_8b:inst|inst19~0 ; 0 ; 6 ; -; - triple_selector_8b:inst|inst23~0 ; 0 ; 6 ; -; - triple_selector_8b:inst|inst27~0 ; 0 ; 6 ; -; - triple_selector_8b:inst|inst31~0 ; 0 ; 6 ; -; A1 ; ; ; -; - triple_selector_8b:inst|inst3 ; 0 ; 6 ; -; - triple_selector_8b:inst|inst7~0 ; 0 ; 6 ; -; - triple_selector_8b:inst|inst11~0 ; 0 ; 6 ; -; RM ; ; ; -; - triple_selector_8b:inst|inst3 ; 0 ; 6 ; -; - triple_selector_8b:inst|inst7 ; 0 ; 6 ; -; - triple_selector_8b:inst|inst11 ; 0 ; 6 ; -; - triple_selector_8b:inst|inst15 ; 0 ; 6 ; -; - triple_selector_8b:inst|inst19 ; 0 ; 6 ; -; - triple_selector_8b:inst|inst23 ; 0 ; 6 ; -; - triple_selector_8b:inst|inst27 ; 0 ; 6 ; -; - triple_selector_8b:inst|inst31 ; 0 ; 6 ; -; A2 ; ; ; -; - triple_selector_8b:inst|inst7 ; 0 ; 6 ; -; - triple_selector_8b:inst|inst11~0 ; 0 ; 6 ; -; - triple_selector_8b:inst|inst15~0 ; 0 ; 6 ; -; A3 ; ; ; -; - triple_selector_8b:inst|inst11 ; 0 ; 6 ; -; - triple_selector_8b:inst|inst15~0 ; 0 ; 6 ; -; - triple_selector_8b:inst|inst19~0 ; 0 ; 6 ; -; A4 ; ; ; -; - triple_selector_8b:inst|inst15 ; 0 ; 6 ; -; - triple_selector_8b:inst|inst19~0 ; 0 ; 6 ; -; - triple_selector_8b:inst|inst23~0 ; 0 ; 6 ; -; A5 ; ; ; -; - triple_selector_8b:inst|inst19 ; 1 ; 6 ; -; - triple_selector_8b:inst|inst23~0 ; 1 ; 6 ; -; - triple_selector_8b:inst|inst27~0 ; 1 ; 6 ; -; A6 ; ; ; -; - triple_selector_8b:inst|inst23 ; 0 ; 6 ; -; - triple_selector_8b:inst|inst27~0 ; 0 ; 6 ; -; - triple_selector_8b:inst|inst31~0 ; 0 ; 6 ; -; A7 ; ; ; -; - triple_selector_8b:inst|inst27 ; 1 ; 6 ; -; - triple_selector_8b:inst|inst31~0 ; 1 ; 6 ; -; R ; ; ; -; - triple_selector_8b:inst|inst31 ; 0 ; 6 ; -+-----------------------------------------+-------------------+---------+ - - -+--------------------------------------------+ -; Non-Global High Fan-Out Signals ; -+----------------------------------+---------+ -; Name ; Fan-Out ; -+----------------------------------+---------+ -; RM ; 8 ; -; DM ; 8 ; -; LM ; 8 ; -; A6 ; 3 ; -; A5 ; 3 ; -; A4 ; 3 ; -; A3 ; 3 ; -; A2 ; 3 ; -; A1 ; 3 ; -; A7 ; 2 ; -; A0 ; 2 ; -; R ; 1 ; -; L ; 1 ; -; triple_selector_8b:inst|inst31 ; 1 ; -; triple_selector_8b:inst|inst31~0 ; 1 ; -; triple_selector_8b:inst|inst27 ; 1 ; -; triple_selector_8b:inst|inst27~0 ; 1 ; -; triple_selector_8b:inst|inst23 ; 1 ; -; triple_selector_8b:inst|inst23~0 ; 1 ; -; triple_selector_8b:inst|inst19 ; 1 ; -; triple_selector_8b:inst|inst19~0 ; 1 ; -; triple_selector_8b:inst|inst15 ; 1 ; -; triple_selector_8b:inst|inst15~0 ; 1 ; -; triple_selector_8b:inst|inst11 ; 1 ; -; triple_selector_8b:inst|inst11~0 ; 1 ; -; triple_selector_8b:inst|inst7 ; 1 ; -; triple_selector_8b:inst|inst7~0 ; 1 ; -; triple_selector_8b:inst|inst3 ; 1 ; -; triple_selector_8b:inst|inst3~0 ; 1 ; -+----------------------------------+---------+ - - -+----------------------------------------------------+ -; Interconnect Usage Summary ; -+----------------------------+-----------------------+ -; Interconnect Resource Type ; Usage ; -+----------------------------+-----------------------+ -; Block interconnects ; 23 / 26,052 ( < 1 % ) ; -; C16 interconnects ; 16 / 1,156 ( 1 % ) ; -; C4 interconnects ; 21 / 17,952 ( < 1 % ) ; -; Direct links ; 0 / 26,052 ( 0 % ) ; -; Global clocks ; 0 / 8 ( 0 % ) ; -; Local interconnects ; 8 / 8,256 ( < 1 % ) ; -; R24 interconnects ; 6 / 1,020 ( < 1 % ) ; -; R4 interconnects ; 37 / 22,440 ( < 1 % ) ; -+----------------------------+-----------------------+ - - -+---------------------------------------------------------------------------+ -; LAB Logic Elements ; -+---------------------------------------------+-----------------------------+ -; Number of Logic Elements (Average = 16.00) ; Number of LABs (Total = 1) ; -+---------------------------------------------+-----------------------------+ -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 0 ; -; 9 ; 0 ; -; 10 ; 0 ; -; 11 ; 0 ; -; 12 ; 0 ; -; 13 ; 0 ; -; 14 ; 0 ; -; 15 ; 0 ; -; 16 ; 1 ; -+---------------------------------------------+-----------------------------+ - - -+----------------------------------------------------------------------------+ -; LAB Signals Sourced ; -+----------------------------------------------+-----------------------------+ -; Number of Signals Sourced (Average = 16.00) ; Number of LABs (Total = 1) ; -+----------------------------------------------+-----------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 0 ; -; 9 ; 0 ; -; 10 ; 0 ; -; 11 ; 0 ; -; 12 ; 0 ; -; 13 ; 0 ; -; 14 ; 0 ; -; 15 ; 0 ; -; 16 ; 1 ; -+----------------------------------------------+-----------------------------+ - - -+-------------------------------------------------------------------------------+ -; LAB Signals Sourced Out ; -+-------------------------------------------------+-----------------------------+ -; Number of Signals Sourced Out (Average = 8.00) ; Number of LABs (Total = 1) ; -+-------------------------------------------------+-----------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 1 ; -+-------------------------------------------------+-----------------------------+ - - -+----------------------------------------------------------------------------+ -; LAB Distinct Inputs ; -+----------------------------------------------+-----------------------------+ -; Number of Distinct Inputs (Average = 13.00) ; Number of LABs (Total = 1) ; -+----------------------------------------------+-----------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 0 ; -; 9 ; 0 ; -; 10 ; 0 ; -; 11 ; 0 ; -; 12 ; 0 ; -; 13 ; 1 ; -+----------------------------------------------+-----------------------------+ - - -+-------------------------------------------------------------------------+ -; Fitter Device Options ; -+----------------------------------------------+--------------------------+ -; Option ; Setting ; -+----------------------------------------------+--------------------------+ -; Enable user-supplied start-up clock (CLKUSR) ; Off ; -; Enable device-wide reset (DEV_CLRn) ; Off ; -; Enable device-wide output enable (DEV_OE) ; Off ; -; Enable INIT_DONE output ; Off ; -; Configuration scheme ; Active Serial ; -; Error detection CRC ; Off ; -; nCEO ; As output driving ground ; -; ASDO,nCSO ; As input tri-stated ; -; Reserve all unused pins ; As input tri-stated ; -; Base pin-out file on sameframe device ; Off ; -+----------------------------------------------+--------------------------+ - - -+------------------------------------+ -; Operating Settings and Conditions ; -+---------------------------+--------+ -; Setting ; Value ; -+---------------------------+--------+ -; Nominal Core Voltage ; 1.20 V ; -; Low Junction Temperature ; 0 °C ; -; High Junction Temperature ; 85 °C ; -+---------------------------+--------+ - - -+------------------------------------------------------------+ -; Estimated Delay Added for Hold Timing ; -+-----------------+----------------------+-------------------+ -; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; -+-----------------+----------------------+-------------------+ - - -+----------------------------+ -; Advanced Data - General ; -+--------------------+-------+ -; Name ; Value ; -+--------------------+-------+ -; Status Code ; 0 ; -; Desired User Slack ; 0 ; -; Fit Attempts ; 1 ; -+--------------------+-------+ - - -+-------------------------------------------------------------------------------+ -; Advanced Data - Placement Preparation ; -+------------------------------------------------------------------+------------+ -; Name ; Value ; -+------------------------------------------------------------------+------------+ -; Auto Fit Point 1 - Fit Attempt 1 ; ff ; -; Mid Wire Use - Fit Attempt 1 ; 0 ; -; Mid Slack - Fit Attempt 1 ; 2147483639 ; -; Internal Atom Count - Fit Attempt 1 ; 17 ; -; LE/ALM Count - Fit Attempt 1 ; 17 ; -; LAB Count - Fit Attempt 1 ; 2 ; -; Outputs per Lab - Fit Attempt 1 ; 4.000 ; -; Inputs per LAB - Fit Attempt 1 ; 6.500 ; -; Global Inputs per LAB - Fit Attempt 1 ; 0.000 ; -; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:1 ; -; LEs in Chains - Fit Attempt 1 ; 0 ; -; LEs in Long Chains - Fit Attempt 1 ; 0 ; -; LABs with Chains - Fit Attempt 1 ; 0 ; -; LABs with Multiple Chains - Fit Attempt 1 ; 0 ; -; Time - Fit Attempt 1 ; 0 ; -+------------------------------------------------------------------+------------+ - - -+-------------------------------------------------+ -; Advanced Data - Placement ; -+------------------------------------+------------+ -; Name ; Value ; -+------------------------------------+------------+ -; Auto Fit Point 2 - Fit Attempt 1 ; ff ; -; Early Wire Use - Fit Attempt 1 ; 0 ; -; Early Slack - Fit Attempt 1 ; 2147483639 ; -; Auto Fit Point 5 - Fit Attempt 1 ; ff ; -; Mid Wire Use - Fit Attempt 1 ; 0 ; -; Mid Slack - Fit Attempt 1 ; 2147483639 ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 5 - Fit Attempt 1 ; ff ; -; Mid Wire Use - Fit Attempt 1 ; 0 ; -; Mid Slack - Fit Attempt 1 ; 2147483639 ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Late Wire Use - Fit Attempt 1 ; 0 ; -; Late Slack - Fit Attempt 1 ; 2147483639 ; -; Peak Regional Wire - Fit Attempt 1 ; 0.000 ; -; Auto Fit Point 7 - Fit Attempt 1 ; ff ; -; Time - Fit Attempt 1 ; 0 ; -+------------------------------------+------------+ - - -+--------------------------------------------------+ -; Advanced Data - Routing ; -+------------------------------------+-------------+ -; Name ; Value ; -+------------------------------------+-------------+ -; Early Slack - Fit Attempt 1 ; 2147483639 ; -; Early Wire Use - Fit Attempt 1 ; 0 ; -; Peak Regional Wire - Fit Attempt 1 ; 1 ; -; Mid Slack - Fit Attempt 1 ; 2147483639 ; -; Late Slack - Fit Attempt 1 ; -2147483648 ; -; Late Wire Use - Fit Attempt 1 ; 0 ; -; Time - Fit Attempt 1 ; 0 ; -+------------------------------------+-------------+ - - -+-----------------+ -; Fitter Messages ; -+-----------------+ -Info: ******************************************************************* -Info: Running Quartus II Fitter - Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Thu Mar 10 14:51:52 2022 -Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b -Info: Parallel compilation is enabled and will use 4 of the 6 processors detected -Info: Selected device EP2C8Q208C8 for design "shifter_8b" -Info: Low junction temperature is 0 degrees C -Info: High junction temperature is 85 degrees C -Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time -Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices - Info: Device EP2C5Q208C8 is compatible - Info: Device EP2C5Q208I8 is compatible - Info: Device EP2C8Q208I8 is compatible -Info: Fitter converted 3 user pins into dedicated programming pins - Info: Pin ~ASDO~ is reserved at location 1 - Info: Pin ~nCSO~ is reserved at location 2 - Info: Pin ~LVDS54p/nCEO~ is reserved at location 108 -Warning: No exact pin location assignment(s) for 2 pins of 21 total pins - Info: Pin L not assigned to an exact location on the device - Info: Pin R not assigned to an exact location on the device -Info: Fitter is using the Classic Timing Analyzer -Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time. -Info: Starting register packing -Info: Finished register packing - Extra Info: No registers were packed into other blocks -Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement - Info: Number of I/O pins in group: 2 (unused VREF, 3.3V VCCIO, 2 input, 0 output, 0 bidirectional) - Info: I/O standards used: 3.3-V LVTTL. -Info: I/O bank details before I/O pin placement - Info: Statistics of I/O banks - Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available - Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available - Info: I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 9 total pin(s) used -- 26 pins available - Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 11 total pin(s) used -- 25 pins available -Info: Fitter preparation operations ending: elapsed time is 00:00:00 -Info: Fitter placement preparation operations beginning -Info: Fitter placement preparation operations ending: elapsed time is 00:00:00 -Info: Fitter placement operations beginning -Info: Fitter placement was successful -Info: Fitter placement operations ending: elapsed time is 00:00:00 -Info: Fitter routing operations beginning -Info: Average interconnect usage is 0% of the available device resources - Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y10 to location X34_Y19 -Info: Fitter routing operations ending: elapsed time is 00:00:00 -Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. - Info: Optimizations that may affect the design's routability were skipped - Info: Optimizations that may affect the design's timing were skipped -Info: Started post-fitting delay annotation -Warning: Found 8 output pins without output pin load capacitance assignment - Info: Pin "Y0" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Y1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Y2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Y3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Y4" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Y5" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Y6" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Y7" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis -Info: Delay annotation completed successfully -Info: Generated suppressed messages file D:/dev/quartus/shifter_8b/shifter_8b.fit.smsg -Info: Quartus II Fitter was successful. 0 errors, 2 warnings - Info: Peak virtual memory: 285 megabytes - Info: Processing ended: Thu Mar 10 14:51:54 2022 - Info: Elapsed time: 00:00:02 - Info: Total CPU time (on all processors): 00:00:01 - - -+----------------------------+ -; Fitter Suppressed Messages ; -+----------------------------+ -The suppressed messages can be found in D:/dev/quartus/shifter_8b/shifter_8b.fit.smsg. - - diff --git a/shifter_8b/shifter_8b.fit.smsg b/shifter_8b/shifter_8b.fit.smsg deleted file mode 100644 index 14764e7..0000000 --- a/shifter_8b/shifter_8b.fit.smsg +++ /dev/null @@ -1,6 +0,0 @@ -Extra Info: Performing register packing on registers with non-logic cell location assignments -Extra Info: Completed register packing on registers with non-logic cell location assignments -Extra Info: Started Fast Input/Output/OE register processing -Extra Info: Finished Fast Input/Output/OE register processing -Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density -Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/shifter_8b/shifter_8b.fit.summary b/shifter_8b/shifter_8b.fit.summary deleted file mode 100644 index a05c9a6..0000000 --- a/shifter_8b/shifter_8b.fit.summary +++ /dev/null @@ -1,16 +0,0 @@ -Fitter Status : Successful - Thu Mar 10 14:51:54 2022 -Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition -Revision Name : shifter_8b -Top-level Entity Name : shifter_8b -Family : Cyclone II -Device : EP2C8Q208C8 -Timing Models : Final -Total logic elements : 16 / 8,256 ( < 1 % ) - Total combinational functions : 16 / 8,256 ( < 1 % ) - Dedicated logic registers : 0 / 8,256 ( 0 % ) -Total registers : 0 -Total pins : 21 / 138 ( 15 % ) -Total virtual pins : 0 -Total memory bits : 0 / 165,888 ( 0 % ) -Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % ) -Total PLLs : 0 / 2 ( 0 % ) diff --git a/shifter_8b/shifter_8b.flow.rpt b/shifter_8b/shifter_8b.flow.rpt deleted file mode 100644 index fd3de16..0000000 --- a/shifter_8b/shifter_8b.flow.rpt +++ /dev/null @@ -1,122 +0,0 @@ -Flow report for shifter_8b -Thu Mar 10 14:51:56 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Flow Summary - 3. Flow Settings - 4. Flow Non-Default Global Settings - 5. Flow Elapsed Time - 6. Flow OS Summary - 7. Flow Log - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------------+ -; Flow Summary ; -+------------------------------------+----------------------------------------------+ -; Flow Status ; Successful - Thu Mar 10 14:51:56 2022 ; -; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; -; Revision Name ; shifter_8b ; -; Top-level Entity Name ; shifter_8b ; -; Family ; Cyclone II ; -; Device ; EP2C8Q208C8 ; -; Timing Models ; Final ; -; Met timing requirements ; Yes ; -; Total logic elements ; 16 / 8,256 ( < 1 % ) ; -; Total combinational functions ; 16 / 8,256 ( < 1 % ) ; -; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ; -; Total registers ; 0 ; -; Total pins ; 21 / 138 ( 15 % ) ; -; Total virtual pins ; 0 ; -; Total memory bits ; 0 / 165,888 ( 0 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; -; Total PLLs ; 0 / 2 ( 0 % ) ; -+------------------------------------+----------------------------------------------+ - - -+-----------------------------------------+ -; Flow Settings ; -+-------------------+---------------------+ -; Option ; Setting ; -+-------------------+---------------------+ -; Start date & time ; 03/10/2022 14:51:51 ; -; Main task ; Compilation ; -; Revision Name ; shifter_8b ; -+-------------------+---------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------+ -; Flow Non-Default Global Settings ; -+------------------------------------+-----------------------------------------------+---------------+-------------+----------------+ -; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; -+------------------------------------+-----------------------------------------------+---------------+-------------+----------------+ -; COMPILER_SIGNATURE_ID ; 136411542855513.164689511129872 ; -- ; -- ; -- ; -; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; -; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; -; MISC_FILE ; D:/dev/quartus/shifter_8b/shifter_8b.dpf ; -- ; -- ; -- ; -; MISC_FILE ; D:/projects/quartus/shifter_8b/shifter_8b.dpf ; -- ; -- ; -- ; -; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; -; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; -; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ; -+------------------------------------+-----------------------------------------------+---------------+-------------+----------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Flow Elapsed Time ; -+-------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; -+-------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 226 MB ; 00:00:01 ; -; Fitter ; 00:00:02 ; 1.0 ; 285 MB ; 00:00:01 ; -; Assembler ; 00:00:00 ; 1.0 ; 221 MB ; 00:00:01 ; -; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 177 MB ; 00:00:00 ; -; Total ; 00:00:03 ; -- ; -- ; 00:00:03 ; -+-------------------------+--------------+-------------------------+---------------------+------------------------------------+ - - -+------------------------------------------------------------------------------------------+ -; Flow OS Summary ; -+-------------------------+------------------+---------------+------------+----------------+ -; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; -+-------------------------+------------------+---------------+------------+----------------+ -; Analysis & Synthesis ; DESKTOP-G0CBSMT ; Windows Vista ; 6.2 ; x86_64 ; -; Fitter ; DESKTOP-G0CBSMT ; Windows Vista ; 6.2 ; x86_64 ; -; Assembler ; DESKTOP-G0CBSMT ; Windows Vista ; 6.2 ; x86_64 ; -; Classic Timing Analyzer ; DESKTOP-G0CBSMT ; Windows Vista ; 6.2 ; x86_64 ; -+-------------------------+------------------+---------------+------------+----------------+ - - ------------- -; Flow Log ; ------------- -quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b -quartus_fit --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b -quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b -quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only - - - diff --git a/shifter_8b/shifter_8b.map.rpt b/shifter_8b/shifter_8b.map.rpt deleted file mode 100644 index 93ddb42..0000000 --- a/shifter_8b/shifter_8b.map.rpt +++ /dev/null @@ -1,223 +0,0 @@ -Analysis & Synthesis report for shifter_8b -Thu Mar 10 14:51:51 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Analysis & Synthesis Summary - 3. Analysis & Synthesis Settings - 4. Analysis & Synthesis Source Files Read - 5. Analysis & Synthesis Resource Usage Summary - 6. Analysis & Synthesis Resource Utilization by Entity - 7. General Register Statistics - 8. Analysis & Synthesis Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------------+ -; Analysis & Synthesis Summary ; -+------------------------------------+----------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Thu Mar 10 14:51:51 2022 ; -; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; -; Revision Name ; shifter_8b ; -; Top-level Entity Name ; shifter_8b ; -; Family ; Cyclone II ; -; Total logic elements ; 16 ; -; Total combinational functions ; 16 ; -; Dedicated logic registers ; 0 ; -; Total registers ; 0 ; -; Total pins ; 21 ; -; Total virtual pins ; 0 ; -; Total memory bits ; 0 ; -; Embedded Multiplier 9-bit elements ; 0 ; -; Total PLLs ; 0 ; -+------------------------------------+----------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Settings ; -+--------------------------------------------------------------+--------------------+--------------------+ -; Option ; Setting ; Default Value ; -+--------------------------------------------------------------+--------------------+--------------------+ -; Device ; EP2C8Q208C8 ; ; -; Top-level entity name ; shifter_8b ; shifter_8b ; -; Family name ; Cyclone II ; Stratix II ; -; Use Generated Physical Constraints File ; Off ; ; -; Use smart compilation ; Off ; Off ; -; Restructure Multiplexers ; Auto ; Auto ; -; Create Debugging Nodes for IP Cores ; Off ; Off ; -; Preserve fewer node names ; On ; On ; -; Disable OpenCore Plus hardware evaluation ; Off ; Off ; -; Verilog Version ; Verilog_2001 ; Verilog_2001 ; -; VHDL Version ; VHDL93 ; VHDL93 ; -; State Machine Processing ; Auto ; Auto ; -; Safe State Machine ; Off ; Off ; -; Extract Verilog State Machines ; On ; On ; -; Extract VHDL State Machines ; On ; On ; -; Ignore Verilog initial constructs ; Off ; Off ; -; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; -; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; -; Add Pass-Through Logic to Inferred RAMs ; On ; On ; -; Parallel Synthesis ; Off ; Off ; -; DSP Block Balancing ; Auto ; Auto ; -; NOT Gate Push-Back ; On ; On ; -; Power-Up Don't Care ; On ; On ; -; Remove Redundant Logic Cells ; Off ; Off ; -; Remove Duplicate Registers ; On ; On ; -; Ignore CARRY Buffers ; Off ; Off ; -; Ignore CASCADE Buffers ; Off ; Off ; -; Ignore GLOBAL Buffers ; Off ; Off ; -; Ignore ROW GLOBAL Buffers ; Off ; Off ; -; Ignore LCELL Buffers ; Off ; Off ; -; Ignore SOFT Buffers ; On ; On ; -; Limit AHDL Integers to 32 Bits ; Off ; Off ; -; Optimization Technique ; Balanced ; Balanced ; -; Carry Chain Length ; 70 ; 70 ; -; Auto Carry Chains ; On ; On ; -; Auto Open-Drain Pins ; On ; On ; -; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; -; Auto ROM Replacement ; On ; On ; -; Auto RAM Replacement ; On ; On ; -; Auto Shift Register Replacement ; Auto ; Auto ; -; Auto Clock Enable Replacement ; On ; On ; -; Strict RAM Replacement ; Off ; Off ; -; Allow Synchronous Control Signals ; On ; On ; -; Force Use of Synchronous Clear Signals ; Off ; Off ; -; Auto RAM to Logic Cell Conversion ; Off ; Off ; -; Auto Resource Sharing ; Off ; Off ; -; Allow Any RAM Size For Recognition ; Off ; Off ; -; Allow Any ROM Size For Recognition ; Off ; Off ; -; Allow Any Shift Register Size For Recognition ; Off ; Off ; -; Use LogicLock Constraints during Resource Balancing ; On ; On ; -; Ignore translate_off and synthesis_off directives ; Off ; Off ; -; Timing-Driven Synthesis ; Off ; Off ; -; Show Parameter Settings Tables in Synthesis Report ; On ; On ; -; Ignore Maximum Fan-Out Assignments ; Off ; Off ; -; Synchronization Register Chain Length ; 2 ; 2 ; -; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; -; HDL message level ; Level2 ; Level2 ; -; Suppress Register Optimization Related Messages ; Off ; Off ; -; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ; -; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; -; Clock MUX Protection ; On ; On ; -; Auto Gated Clock Conversion ; Off ; Off ; -; Block Design Naming ; Auto ; Auto ; -; SDC constraint protection ; Off ; Off ; -; Synthesis Effort ; Auto ; Auto ; -; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; -; Analysis & Synthesis Message Level ; Medium ; Medium ; -+--------------------------------------------------------------+--------------------+--------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+----------------------------------+-----------------+------------------------------------------+--------------------------------------------------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; -+----------------------------------+-----------------+------------------------------------------+--------------------------------------------------+ -; shifter_8b.bdf ; yes ; User Block Diagram/Schematic File ; D:/dev/quartus/shifter_8b/shifter_8b.bdf ; -; triple_selector_8b.bdf ; yes ; Auto-Found Block Diagram/Schematic File ; D:/dev/quartus/shifter_8b/triple_selector_8b.bdf ; -+----------------------------------+-----------------+------------------------------------------+--------------------------------------------------+ - - -+-----------------------------------------------------+ -; Analysis & Synthesis Resource Usage Summary ; -+---------------------------------------------+-------+ -; Resource ; Usage ; -+---------------------------------------------+-------+ -; Estimated Total logic elements ; 16 ; -; ; ; -; Total combinational functions ; 16 ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 8 ; -; -- 3 input functions ; 8 ; -; -- <=2 input functions ; 0 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 16 ; -; -- arithmetic mode ; 0 ; -; ; ; -; Total registers ; 0 ; -; -- Dedicated logic registers ; 0 ; -; -- I/O registers ; 0 ; -; ; ; -; I/O pins ; 21 ; -; Maximum fan-out node ; LM ; -; Maximum fan-out ; 8 ; -; Total fan-out ; 64 ; -; Average fan-out ; 1.73 ; -+---------------------------------------------+-------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Resource Utilization by Entity ; -+------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------+--------------+ -; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; -+------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------+--------------+ -; |shifter_8b ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 21 ; 0 ; |shifter_8b ; work ; -; |triple_selector_8b:inst| ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |shifter_8b|triple_selector_8b:inst ; work ; -+------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------+--------------+ -Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. - - -+------------------------------------------------------+ -; General Register Statistics ; -+----------------------------------------------+-------+ -; Statistic ; Value ; -+----------------------------------------------+-------+ -; Total registers ; 0 ; -; Number of registers using Synchronous Clear ; 0 ; -; Number of registers using Synchronous Load ; 0 ; -; Number of registers using Asynchronous Clear ; 0 ; -; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 0 ; -; Number of registers using Preset ; 0 ; -+----------------------------------------------+-------+ - - -+-------------------------------+ -; Analysis & Synthesis Messages ; -+-------------------------------+ -Info: ******************************************************************* -Info: Running Quartus II Analysis & Synthesis - Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Thu Mar 10 14:51:50 2022 -Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b -Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf - Info: Found entity 1: shifter_8b -Info: Elaborating entity "shifter_8b" for the top level hierarchy -Warning: Using design file triple_selector_8b.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project - Info: Found entity 1: triple_selector_8b -Info: Elaborating entity "triple_selector_8b" for hierarchy "triple_selector_8b:inst" -Info: Implemented 37 device resources after synthesis - the final resource count might be different - Info: Implemented 13 input pins - Info: Implemented 8 output pins - Info: Implemented 16 logic cells -Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning - Info: Peak virtual memory: 229 megabytes - Info: Processing ended: Thu Mar 10 14:51:52 2022 - Info: Elapsed time: 00:00:02 - Info: Total CPU time (on all processors): 00:00:01 - - diff --git a/shifter_8b/shifter_8b.map.summary b/shifter_8b/shifter_8b.map.summary deleted file mode 100644 index 8aed699..0000000 --- a/shifter_8b/shifter_8b.map.summary +++ /dev/null @@ -1,14 +0,0 @@ -Analysis & Synthesis Status : Successful - Thu Mar 10 14:51:51 2022 -Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition -Revision Name : shifter_8b -Top-level Entity Name : shifter_8b -Family : Cyclone II -Total logic elements : 16 - Total combinational functions : 16 - Dedicated logic registers : 0 -Total registers : 0 -Total pins : 21 -Total virtual pins : 0 -Total memory bits : 0 -Embedded Multiplier 9-bit elements : 0 -Total PLLs : 0 diff --git a/shifter_8b/shifter_8b.pin b/shifter_8b/shifter_8b.pin deleted file mode 100644 index 0b000e4..0000000 --- a/shifter_8b/shifter_8b.pin +++ /dev/null @@ -1,278 +0,0 @@ - -- Copyright (C) 1991-2009 Altera Corporation - -- Your use of Altera Corporation's design tools, logic functions - -- and other software and tools, and its AMPP partner logic - -- functions, and any output files from any of the foregoing - -- (including device programming or simulation files), and any - -- associated documentation or information are expressly subject - -- to the terms and conditions of the Altera Program License - -- Subscription Agreement, Altera MegaCore Function License - -- Agreement, or other applicable license agreement, including, - -- without limitation, that your use is for the sole purpose of - -- programming logic devices manufactured by Altera and sold by - -- Altera or its authorized distributors. Please refer to the - -- applicable agreement for further details. - -- - -- This is a Quartus II output file. It is for reporting purposes only, and is - -- not intended for use as a Quartus II input file. This file cannot be used - -- to make Quartus II pin assignments - for instructions on how to make pin - -- assignments, please see Quartus II help. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- NC : No Connect. This pin has no internal connection to the device. - -- DNU : Do Not Use. This pin MUST NOT be connected. - -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). - -- VCCIO : Dedicated power pin, which MUST be connected to VCC - -- of its bank. - -- Bank 1: 3.3V - -- Bank 2: 3.3V - -- Bank 3: 3.3V - -- Bank 4: 3.3V - -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. - -- It can also be used to report unused dedicated pins. The connection - -- on the board for unused dedicated pins depends on whether this will - -- be used in a future design. One example is device migration. When - -- using device migration, refer to the device pin-tables. If it is a - -- GND pin in the pin table or if it will not be used in a future design - -- for another purpose the it MUST be connected to GND. If it is an unused - -- dedicated pin, then it can be connected to a valid signal on the board - -- (low, high, or toggling) if that signal is required for a different - -- revision of the design. - -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. - -- This pin should be connected to GND. It may also be connected to a - -- valid signal on the board (low, high, or toggling) if that signal - -- is required for a different revision of the design. - -- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17), - -- connect each pin marked GND* either individually through a 10k Ohm resistor - -- to GND or tie all pins together and connect through a single 10k Ohm resistor - -- to GND. - -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND - -- or leave it unconnected. - -- RESERVED : Unused I/O pin, which MUST be left unconnected. - -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. - -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. - -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. - -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- Pin directions (input, output or bidir) are based on device operating in user mode. - --------------------------------------------------------------------------------- - -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition -CHIP "shifter_8b" ASSIGNED TO AN: EP2C8Q208C8 - -Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment -------------------------------------------------------------------------------------------------------------- -~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVTTL : : 1 : N -~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVTTL : : 1 : N -RESERVED_INPUT : 3 : : : : 1 : -RESERVED_INPUT : 4 : : : : 1 : -RESERVED_INPUT : 5 : : : : 1 : -RESERVED_INPUT : 6 : : : : 1 : -VCCIO1 : 7 : power : : 3.3V : 1 : -RESERVED_INPUT : 8 : : : : 1 : -GND : 9 : gnd : : : : -RESERVED_INPUT : 10 : : : : 1 : -RESERVED_INPUT : 11 : : : : 1 : -RESERVED_INPUT : 12 : : : : 1 : -RESERVED_INPUT : 13 : : : : 1 : -RESERVED_INPUT : 14 : : : : 1 : -RESERVED_INPUT : 15 : : : : 1 : -TDO : 16 : output : : : 1 : -TMS : 17 : input : : : 1 : -TCK : 18 : input : : : 1 : -TDI : 19 : input : : : 1 : -DATA0 : 20 : input : : : 1 : -DCLK : 21 : : : : 1 : -nCE : 22 : : : : 1 : -GND+ : 23 : : : : 1 : -GND+ : 24 : : : : 1 : -GND : 25 : gnd : : : : -nCONFIG : 26 : : : : 1 : -GND+ : 27 : : : : 1 : -GND+ : 28 : : : : 1 : -VCCIO1 : 29 : power : : 3.3V : 1 : -RESERVED_INPUT : 30 : : : : 1 : -RESERVED_INPUT : 31 : : : : 1 : -VCCINT : 32 : power : : 1.2V : : -RESERVED_INPUT : 33 : : : : 1 : -RESERVED_INPUT : 34 : : : : 1 : -RESERVED_INPUT : 35 : : : : 1 : -GND : 36 : gnd : : : : -RESERVED_INPUT : 37 : : : : 1 : -GND : 38 : gnd : : : : -RESERVED_INPUT : 39 : : : : 1 : -RESERVED_INPUT : 40 : : : : 1 : -RESERVED_INPUT : 41 : : : : 1 : -VCCIO1 : 42 : power : : 3.3V : 1 : -RESERVED_INPUT : 43 : : : : 1 : -RESERVED_INPUT : 44 : : : : 1 : -RESERVED_INPUT : 45 : : : : 1 : -RESERVED_INPUT : 46 : : : : 1 : -RESERVED_INPUT : 47 : : : : 1 : -RESERVED_INPUT : 48 : : : : 1 : -GND : 49 : gnd : : : : -GND_PLL1 : 50 : gnd : : : : -VCCD_PLL1 : 51 : power : : 1.2V : : -GND_PLL1 : 52 : gnd : : : : -VCCA_PLL1 : 53 : power : : 1.2V : : -GNDA_PLL1 : 54 : gnd : : : : -GND : 55 : gnd : : : : -RESERVED_INPUT : 56 : : : : 4 : -RESERVED_INPUT : 57 : : : : 4 : -RESERVED_INPUT : 58 : : : : 4 : -RESERVED_INPUT : 59 : : : : 4 : -RESERVED_INPUT : 60 : : : : 4 : -RESERVED_INPUT : 61 : : : : 4 : -VCCIO4 : 62 : power : : 3.3V : 4 : -RESERVED_INPUT : 63 : : : : 4 : -RESERVED_INPUT : 64 : : : : 4 : -GND : 65 : gnd : : : : -VCCINT : 66 : power : : 1.2V : : -RM : 67 : input : 3.3-V LVTTL : : 4 : Y -DM : 68 : input : 3.3-V LVTTL : : 4 : Y -LM : 69 : input : 3.3-V LVTTL : : 4 : Y -RESERVED_INPUT : 70 : : : : 4 : -VCCIO4 : 71 : power : : 3.3V : 4 : -RESERVED_INPUT : 72 : : : : 4 : -GND : 73 : gnd : : : : -RESERVED_INPUT : 74 : : : : 4 : -RESERVED_INPUT : 75 : : : : 4 : -R : 76 : input : 3.3-V LVTTL : : 4 : N -A0 : 77 : input : 3.3-V LVTTL : : 4 : Y -GND : 78 : gnd : : : : -VCCINT : 79 : power : : 1.2V : : -A1 : 80 : input : 3.3-V LVTTL : : 4 : Y -A2 : 81 : input : 3.3-V LVTTL : : 4 : Y -A3 : 82 : input : 3.3-V LVTTL : : 4 : Y -VCCIO4 : 83 : power : : 3.3V : 4 : -A4 : 84 : input : 3.3-V LVTTL : : 4 : Y -GND : 85 : gnd : : : : -A5 : 86 : input : 3.3-V LVTTL : : 4 : Y -A6 : 87 : input : 3.3-V LVTTL : : 4 : Y -A7 : 88 : input : 3.3-V LVTTL : : 4 : Y -RESERVED_INPUT : 89 : : : : 4 : -RESERVED_INPUT : 90 : : : : 4 : -VCCIO4 : 91 : power : : 3.3V : 4 : -L : 92 : input : 3.3-V LVTTL : : 4 : N -GND : 93 : gnd : : : : -RESERVED_INPUT : 94 : : : : 4 : -RESERVED_INPUT : 95 : : : : 4 : -RESERVED_INPUT : 96 : : : : 4 : -RESERVED_INPUT : 97 : : : : 4 : -VCCIO4 : 98 : power : : 3.3V : 4 : -RESERVED_INPUT : 99 : : : : 4 : -GND : 100 : gnd : : : : -RESERVED_INPUT : 101 : : : : 4 : -RESERVED_INPUT : 102 : : : : 4 : -RESERVED_INPUT : 103 : : : : 4 : -RESERVED_INPUT : 104 : : : : 4 : -RESERVED_INPUT : 105 : : : : 3 : -RESERVED_INPUT : 106 : : : : 3 : -RESERVED_INPUT : 107 : : : : 3 : -~LVDS54p/nCEO~ : 108 : output : 3.3-V LVTTL : : 3 : N -VCCIO3 : 109 : power : : 3.3V : 3 : -RESERVED_INPUT : 110 : : : : 3 : -GND : 111 : gnd : : : : -RESERVED_INPUT : 112 : : : : 3 : -RESERVED_INPUT : 113 : : : : 3 : -RESERVED_INPUT : 114 : : : : 3 : -RESERVED_INPUT : 115 : : : : 3 : -RESERVED_INPUT : 116 : : : : 3 : -RESERVED_INPUT : 117 : : : : 3 : -RESERVED_INPUT : 118 : : : : 3 : -GND : 119 : gnd : : : : -VCCINT : 120 : power : : 1.2V : : -nSTATUS : 121 : : : : 3 : -VCCIO3 : 122 : power : : 3.3V : 3 : -CONF_DONE : 123 : : : : 3 : -GND : 124 : gnd : : : : -MSEL1 : 125 : : : : 3 : -MSEL0 : 126 : : : : 3 : -RESERVED_INPUT : 127 : : : : 3 : -RESERVED_INPUT : 128 : : : : 3 : -GND+ : 129 : : : : 3 : -GND+ : 130 : : : : 3 : -GND+ : 131 : : : : 3 : -GND+ : 132 : : : : 3 : -RESERVED_INPUT : 133 : : : : 3 : -RESERVED_INPUT : 134 : : : : 3 : -RESERVED_INPUT : 135 : : : : 3 : -VCCIO3 : 136 : power : : 3.3V : 3 : -RESERVED_INPUT : 137 : : : : 3 : -RESERVED_INPUT : 138 : : : : 3 : -RESERVED_INPUT : 139 : : : : 3 : -GND : 140 : gnd : : : : -RESERVED_INPUT : 141 : : : : 3 : -Y0 : 142 : output : 3.3-V LVTTL : : 3 : Y -Y1 : 143 : output : 3.3-V LVTTL : : 3 : Y -Y2 : 144 : output : 3.3-V LVTTL : : 3 : Y -Y3 : 145 : output : 3.3-V LVTTL : : 3 : Y -Y4 : 146 : output : 3.3-V LVTTL : : 3 : Y -Y5 : 147 : output : 3.3-V LVTTL : : 3 : Y -VCCIO3 : 148 : power : : 3.3V : 3 : -Y6 : 149 : output : 3.3-V LVTTL : : 3 : Y -Y7 : 150 : output : 3.3-V LVTTL : : 3 : Y -RESERVED_INPUT : 151 : : : : 3 : -RESERVED_INPUT : 152 : : : : 3 : -GND : 153 : gnd : : : : -GND_PLL2 : 154 : gnd : : : : -VCCD_PLL2 : 155 : power : : 1.2V : : -GND_PLL2 : 156 : gnd : : : : -VCCA_PLL2 : 157 : power : : 1.2V : : -GNDA_PLL2 : 158 : gnd : : : : -GND : 159 : gnd : : : : -RESERVED_INPUT : 160 : : : : 2 : -RESERVED_INPUT : 161 : : : : 2 : -RESERVED_INPUT : 162 : : : : 2 : -RESERVED_INPUT : 163 : : : : 2 : -RESERVED_INPUT : 164 : : : : 2 : -RESERVED_INPUT : 165 : : : : 2 : -VCCIO2 : 166 : power : : 3.3V : 2 : -GND : 167 : gnd : : : : -RESERVED_INPUT : 168 : : : : 2 : -RESERVED_INPUT : 169 : : : : 2 : -RESERVED_INPUT : 170 : : : : 2 : -RESERVED_INPUT : 171 : : : : 2 : -VCCIO2 : 172 : power : : 3.3V : 2 : -RESERVED_INPUT : 173 : : : : 2 : -GND : 174 : gnd : : : : -RESERVED_INPUT : 175 : : : : 2 : -RESERVED_INPUT : 176 : : : : 2 : -GND : 177 : gnd : : : : -VCCINT : 178 : power : : 1.2V : : -RESERVED_INPUT : 179 : : : : 2 : -RESERVED_INPUT : 180 : : : : 2 : -RESERVED_INPUT : 181 : : : : 2 : -RESERVED_INPUT : 182 : : : : 2 : -VCCIO2 : 183 : power : : 3.3V : 2 : -GND : 184 : gnd : : : : -RESERVED_INPUT : 185 : : : : 2 : -GND : 186 : gnd : : : : -RESERVED_INPUT : 187 : : : : 2 : -RESERVED_INPUT : 188 : : : : 2 : -RESERVED_INPUT : 189 : : : : 2 : -VCCINT : 190 : power : : 1.2V : : -RESERVED_INPUT : 191 : : : : 2 : -RESERVED_INPUT : 192 : : : : 2 : -RESERVED_INPUT : 193 : : : : 2 : -VCCIO2 : 194 : power : : 3.3V : 2 : -RESERVED_INPUT : 195 : : : : 2 : -GND : 196 : gnd : : : : -RESERVED_INPUT : 197 : : : : 2 : -RESERVED_INPUT : 198 : : : : 2 : -RESERVED_INPUT : 199 : : : : 2 : -RESERVED_INPUT : 200 : : : : 2 : -RESERVED_INPUT : 201 : : : : 2 : -VCCIO2 : 202 : power : : 3.3V : 2 : -RESERVED_INPUT : 203 : : : : 2 : -GND : 204 : gnd : : : : -RESERVED_INPUT : 205 : : : : 2 : -RESERVED_INPUT : 206 : : : : 2 : -RESERVED_INPUT : 207 : : : : 2 : -RESERVED_INPUT : 208 : : : : 2 : diff --git a/shifter_8b/shifter_8b.pof b/shifter_8b/shifter_8b.pof deleted file mode 100644 index 34633c1..0000000 Binary files a/shifter_8b/shifter_8b.pof and /dev/null differ diff --git a/shifter_8b/shifter_8b.qws b/shifter_8b/shifter_8b.qws deleted file mode 100644 index 4d068ed..0000000 --- a/shifter_8b/shifter_8b.qws +++ /dev/null @@ -1,34 +0,0 @@ -[ProjectWorkspace] -ptn_Child1=Frames -[ProjectWorkspace.Frames] -ptn_Child1=ChildFrames -[ProjectWorkspace.Frames.ChildFrames] -ptn_Child1=Document-0 -ptn_Child2=Document-1 -ptn_Child3=Document-2 -ptn_Child4=Document-3 -ptn_Child5=Document-4 -[ProjectWorkspace.Frames.ChildFrames.Document-0] -ptn_Child1=ViewFrame-0 -[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0] -DocPathName=shifter_8b.bdf -DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde} -IsChildFrameDetached=False -IsActiveChildFrame=True -ptn_Child1=StateMap -[ProjectWorkspace.Frames.ChildFrames.Document-1] -ptn_Child1=ViewFrame-0 -[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0] -DocPathName=triple_selector_8b.bdf -DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde} -IsChildFrameDetached=False -IsActiveChildFrame=False -ptn_Child1=StateMap -[ProjectWorkspace.Frames.ChildFrames.Document-2] -ptn_Child1=ViewFrame-0 -[ProjectWorkspace.Frames.ChildFrames.Document-2.ViewFrame-0] -DocPathName=shifter_8b.bsf -DocumentCLSID={7b19e8f4-2bbe-11d1-a082-0020affa5bde} -IsChildFrameDetached=False -IsActiveChildFrame=False -ptn_Child1=StateMap diff --git a/shifter_8b/shifter_8b.sof b/shifter_8b/shifter_8b.sof deleted file mode 100644 index 2168f65..0000000 Binary files a/shifter_8b/shifter_8b.sof and /dev/null differ diff --git a/shifter_8b/shifter_8b.tan.rpt b/shifter_8b/shifter_8b.tan.rpt deleted file mode 100644 index 782a763..0000000 --- a/shifter_8b/shifter_8b.tan.rpt +++ /dev/null @@ -1,174 +0,0 @@ -Classic Timing Analyzer report for shifter_8b -Thu Mar 10 14:51:56 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Timing Analyzer Summary - 3. Timing Analyzer Settings - 4. Parallel Compilation - 5. tpd - 6. Timing Analyzer Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------------------------------------------------+ -; Timing Analyzer Summary ; -+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ -; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; -+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ -; Worst-case tpd ; N/A ; None ; 15.646 ns ; LM ; Y6 ; -- ; -- ; 0 ; -; Total number of failed paths ; ; ; ; ; ; ; ; 0 ; -+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ - - -+--------------------------------------------------------------------------------------------------------------------+ -; Timing Analyzer Settings ; -+---------------------------------------------------------------------+--------------------+------+----+-------------+ -; Option ; Setting ; From ; To ; Entity Name ; -+---------------------------------------------------------------------+--------------------+------+----+-------------+ -; Device Name ; EP2C8Q208C8 ; ; ; ; -; Timing Models ; Final ; ; ; ; -; Default hold multicycle ; Same as Multicycle ; ; ; ; -; Cut paths between unrelated clock domains ; On ; ; ; ; -; Cut off read during write signal paths ; On ; ; ; ; -; Cut off feedback from I/O pins ; On ; ; ; ; -; Report Combined Fast/Slow Timing ; Off ; ; ; ; -; Ignore Clock Settings ; Off ; ; ; ; -; Analyze latches as synchronous elements ; On ; ; ; ; -; Enable Recovery/Removal analysis ; Off ; ; ; ; -; Enable Clock Latency ; Off ; ; ; ; -; Use TimeQuest Timing Analyzer ; Off ; ; ; ; -; Minimum Core Junction Temperature ; 0 ; ; ; ; -; Maximum Core Junction Temperature ; 85 ; ; ; ; -; Number of source nodes to report per destination node ; 10 ; ; ; ; -; Number of destination nodes to report ; 10 ; ; ; ; -; Number of paths to report ; 200 ; ; ; ; -; Report Minimum Timing Checks ; Off ; ; ; ; -; Use Fast Timing Models ; Off ; ; ; ; -; Report IO Paths Separately ; Off ; ; ; ; -; Perform Multicorner Analysis ; On ; ; ; ; -; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ; -; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ; -; Output I/O Timing Endpoint ; Near End ; ; ; ; -+---------------------------------------------------------------------+--------------------+------+----+-------------+ - - -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 6 ; -; Maximum allowed ; 4 ; -; ; ; -; Average used ; 1.00 ; -; Maximum used ; 1 ; -; ; ; -; Usage by Processor ; % Time Used ; -; 1 processor ; 100.0% ; -; 2-6 processors ; 0.0% ; -+----------------------------+-------------+ - - -+---------------------------------------------------------+ -; tpd ; -+-------+-------------------+-----------------+------+----+ -; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ; -+-------+-------------------+-----------------+------+----+ -; N/A ; None ; 15.646 ns ; LM ; Y6 ; -; N/A ; None ; 15.635 ns ; DM ; Y4 ; -; N/A ; None ; 15.562 ns ; LM ; Y4 ; -; N/A ; None ; 15.337 ns ; A6 ; Y6 ; -; N/A ; None ; 15.239 ns ; DM ; Y6 ; -; N/A ; None ; 15.230 ns ; DM ; Y0 ; -; N/A ; None ; 15.217 ns ; DM ; Y5 ; -; N/A ; None ; 15.211 ns ; DM ; Y1 ; -; N/A ; None ; 15.186 ns ; DM ; Y2 ; -; N/A ; None ; 15.161 ns ; LM ; Y0 ; -; N/A ; None ; 15.148 ns ; LM ; Y5 ; -; N/A ; None ; 15.141 ns ; LM ; Y1 ; -; N/A ; None ; 15.115 ns ; LM ; Y2 ; -; N/A ; None ; 14.955 ns ; L ; Y0 ; -; N/A ; None ; 14.954 ns ; A3 ; Y4 ; -; N/A ; None ; 14.878 ns ; LM ; Y7 ; -; N/A ; None ; 14.829 ns ; A6 ; Y7 ; -; N/A ; None ; 14.828 ns ; A7 ; Y7 ; -; N/A ; None ; 14.763 ns ; A4 ; Y4 ; -; N/A ; None ; 14.737 ns ; A0 ; Y0 ; -; N/A ; None ; 14.726 ns ; DM ; Y7 ; -; N/A ; None ; 14.719 ns ; A0 ; Y1 ; -; N/A ; None ; 14.714 ns ; A5 ; Y6 ; -; N/A ; None ; 14.704 ns ; DM ; Y3 ; -; N/A ; None ; 14.631 ns ; LM ; Y3 ; -; N/A ; None ; 14.548 ns ; A2 ; Y2 ; -; N/A ; None ; 14.509 ns ; A1 ; Y1 ; -; N/A ; None ; 14.487 ns ; A1 ; Y2 ; -; N/A ; None ; 14.397 ns ; R ; Y7 ; -; N/A ; None ; 14.391 ns ; RM ; Y6 ; -; N/A ; None ; 14.373 ns ; RM ; Y4 ; -; N/A ; None ; 14.365 ns ; RM ; Y7 ; -; N/A ; None ; 14.346 ns ; A4 ; Y5 ; -; N/A ; None ; 14.300 ns ; A7 ; Y6 ; -; N/A ; None ; 14.259 ns ; RM ; Y1 ; -; N/A ; None ; 14.215 ns ; A5 ; Y5 ; -; N/A ; None ; 14.066 ns ; A2 ; Y3 ; -; N/A ; None ; 14.002 ns ; RM ; Y5 ; -; N/A ; None ; 13.950 ns ; A5 ; Y4 ; -; N/A ; None ; 13.923 ns ; RM ; Y2 ; -; N/A ; None ; 13.902 ns ; RM ; Y0 ; -; N/A ; None ; 13.836 ns ; A3 ; Y3 ; -; N/A ; None ; 13.818 ns ; A3 ; Y2 ; -; N/A ; None ; 13.589 ns ; A2 ; Y1 ; -; N/A ; None ; 13.485 ns ; A6 ; Y5 ; -; N/A ; None ; 13.479 ns ; A1 ; Y0 ; -; N/A ; None ; 13.437 ns ; RM ; Y3 ; -; N/A ; None ; 12.844 ns ; A4 ; Y3 ; -+-------+-------------------+-----------------+------+----+ - - -+--------------------------+ -; Timing Analyzer Messages ; -+--------------------------+ -Info: ******************************************************************* -Info: Running Quartus II Classic Timing Analyzer - Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Thu Mar 10 14:51:56 2022 -Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only -Info: Parallel compilation is enabled and will use 4 of the 6 processors detected -Info: Longest tpd from source pin "LM" to destination pin "Y6" is 15.646 ns - Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_69; Fanout = 8; PIN Node = 'LM' - Info: 2: + IC(6.993 ns) + CELL(0.624 ns) = 8.611 ns; Loc. = LCCOMB_X21_Y10_N24; Fanout = 1; COMB Node = 'triple_selector_8b:inst|inst27~0' - Info: 3: + IC(0.395 ns) + CELL(0.651 ns) = 9.657 ns; Loc. = LCCOMB_X21_Y10_N18; Fanout = 1; COMB Node = 'triple_selector_8b:inst|inst27' - Info: 4: + IC(2.873 ns) + CELL(3.116 ns) = 15.646 ns; Loc. = PIN_149; Fanout = 0; PIN Node = 'Y6' - Info: Total cell delay = 5.385 ns ( 34.42 % ) - Info: Total interconnect delay = 10.261 ns ( 65.58 % ) -Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 191 megabytes - Info: Processing ended: Thu Mar 10 14:51:56 2022 - Info: Elapsed time: 00:00:00 - Info: Total CPU time (on all processors): 00:00:00 - - diff --git a/shifter_8b/shifter_8b.tan.summary b/shifter_8b/shifter_8b.tan.summary deleted file mode 100644 index 4c457e6..0000000 --- a/shifter_8b/shifter_8b.tan.summary +++ /dev/null @@ -1,26 +0,0 @@ --------------------------------------------------------------------------------------- -Timing Analyzer Summary --------------------------------------------------------------------------------------- - -Type : Worst-case tpd -Slack : N/A -Required Time : None -Actual Time : 15.646 ns -From : LM -To : Y6 -From Clock : -- -To Clock : -- -Failed Paths : 0 - -Type : Total number of failed paths -Slack : -Required Time : -Actual Time : -From : -To : -From Clock : -To Clock : -Failed Paths : 0 - --------------------------------------------------------------------------------------- - diff --git a/triple_selector_8b/db/triple_selector_8b.(0).cnf.cdb b/triple_selector_8b/db/triple_selector_8b.(0).cnf.cdb deleted file mode 100644 index 86e6b67..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.(0).cnf.cdb and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.(0).cnf.hdb b/triple_selector_8b/db/triple_selector_8b.(0).cnf.hdb deleted file mode 100644 index 43a3f60..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.(0).cnf.hdb and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.asm.qmsg b/triple_selector_8b/db/triple_selector_8b.asm.qmsg deleted file mode 100644 index e413754..0000000 --- a/triple_selector_8b/db/triple_selector_8b.asm.qmsg +++ /dev/null @@ -1,7 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:24:28 2022 " "Info: Processing started: Mon Mar 07 10:24:28 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off triple_selector_8b -c triple_selector_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off triple_selector_8b -c triple_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1} -{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "242 " "Info: Peak virtual memory: 242 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 10:24:29 2022 " "Info: Processing ended: Mon Mar 07 10:24:29 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/triple_selector_8b/db/triple_selector_8b.asm_labs.ddb b/triple_selector_8b/db/triple_selector_8b.asm_labs.ddb deleted file mode 100644 index eb5d72a..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.asm_labs.ddb and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.cbx.xml b/triple_selector_8b/db/triple_selector_8b.cbx.xml deleted file mode 100644 index 82f3638..0000000 --- a/triple_selector_8b/db/triple_selector_8b.cbx.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/triple_selector_8b/db/triple_selector_8b.cmp.bpm b/triple_selector_8b/db/triple_selector_8b.cmp.bpm deleted file mode 100644 index b585851..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.cmp.bpm and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.cmp.cdb b/triple_selector_8b/db/triple_selector_8b.cmp.cdb deleted file mode 100644 index efb08bc..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.cmp.cdb and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.cmp.ecobp b/triple_selector_8b/db/triple_selector_8b.cmp.ecobp deleted file mode 100644 index e05efff..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.cmp.ecobp and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.cmp.hdb b/triple_selector_8b/db/triple_selector_8b.cmp.hdb deleted file mode 100644 index 7f833d1..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.cmp.hdb and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.cmp.kpt b/triple_selector_8b/db/triple_selector_8b.cmp.kpt deleted file mode 100644 index 1ed88b6..0000000 --- a/triple_selector_8b/db/triple_selector_8b.cmp.kpt +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/triple_selector_8b/db/triple_selector_8b.cmp.logdb b/triple_selector_8b/db/triple_selector_8b.cmp.logdb deleted file mode 100644 index 626799f..0000000 --- a/triple_selector_8b/db/triple_selector_8b.cmp.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/triple_selector_8b/db/triple_selector_8b.cmp.rdb b/triple_selector_8b/db/triple_selector_8b.cmp.rdb deleted file mode 100644 index 689a39c..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.cmp.rdb and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.cmp.tdb b/triple_selector_8b/db/triple_selector_8b.cmp.tdb deleted file mode 100644 index 761dff4..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.cmp.tdb and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.cmp0.ddb b/triple_selector_8b/db/triple_selector_8b.cmp0.ddb deleted file mode 100644 index b4946cd..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.cmp0.ddb and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.cmp2.ddb b/triple_selector_8b/db/triple_selector_8b.cmp2.ddb deleted file mode 100644 index d4633db..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.cmp2.ddb and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.cmp_merge.kpt b/triple_selector_8b/db/triple_selector_8b.cmp_merge.kpt deleted file mode 100644 index 8364adc..0000000 --- a/triple_selector_8b/db/triple_selector_8b.cmp_merge.kpt +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/triple_selector_8b/db/triple_selector_8b.db_info b/triple_selector_8b/db/triple_selector_8b.db_info deleted file mode 100644 index a1982c9..0000000 --- a/triple_selector_8b/db/triple_selector_8b.db_info +++ /dev/null @@ -1,3 +0,0 @@ -Quartus_Version = Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition -Version_Index = 167832322 -Creation_Time = Mon Mar 07 10:23:46 2022 diff --git a/triple_selector_8b/db/triple_selector_8b.eco.cdb b/triple_selector_8b/db/triple_selector_8b.eco.cdb deleted file mode 100644 index 6612017..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.eco.cdb and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.fit.qmsg b/triple_selector_8b/db/triple_selector_8b.fit.qmsg deleted file mode 100644 index a8fa121..0000000 --- a/triple_selector_8b/db/triple_selector_8b.fit.qmsg +++ /dev/null @@ -1,39 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:24:26 2022 " "Info: Processing started: Mon Mar 07 10:24:26 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off triple_selector_8b -c triple_selector_8b " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off triple_selector_8b -c triple_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "IMPP_MPP_USER_DEVICE" "triple_selector_8b EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"triple_selector_8b\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1} -{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "35 35 " "Warning: No exact pin location assignment(s) for 35 pins of 35 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y0 " "Info: Pin Y0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y0 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 1088 600 776 1104 "Y0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y1 " "Info: Pin Y1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y1 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 944 600 776 960 "Y1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y2 " "Info: Pin Y2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y2 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 800 600 776 816 "Y2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y3 " "Info: Pin Y3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y3 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 656 600 776 672 "Y3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y4 " "Info: Pin Y4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y4 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 512 600 776 528 "Y4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y5 " "Info: Pin Y5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y5 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 368 600 776 384 "Y5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y6 " "Info: Pin Y6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y6 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 224 600 776 240 "Y6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y7 " "Info: Pin Y7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y7 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 80 600 776 96 "Y7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B0 " "Info: Pin B0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B0 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 1080 16 184 1096 "B0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A0 " "Info: Pin A0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A0 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 1032 16 184 1048 "A0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "AY " "Info: Pin AY not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { AY } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 1272 16 184 1288 "AY" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AY } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "BY " "Info: Pin BY not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { BY } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 1320 16 184 1336 "BY" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { BY } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "C0 " "Info: Pin C0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { C0 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 1128 16 184 1144 "C0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { C0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CY " "Info: Pin CY not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { CY } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 1360 16 184 1376 "CY" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CY } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A1 " "Info: Pin A1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A1 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 888 16 184 904 "A1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B1 " "Info: Pin B1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B1 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 936 16 184 952 "B1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "C1 " "Info: Pin C1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { C1 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 984 16 184 1000 "C1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { C1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A2 " "Info: Pin A2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A2 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 744 16 184 760 "A2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B2 " "Info: Pin B2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B2 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 792 16 184 808 "B2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "C2 " "Info: Pin C2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { C2 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 840 16 184 856 "C2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { C2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A3 " "Info: Pin A3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A3 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 600 16 184 616 "A3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B3 " "Info: Pin B3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B3 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 648 16 184 664 "B3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "C3 " "Info: Pin C3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { C3 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 696 16 184 712 "C3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { C3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A4 " "Info: Pin A4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A4 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 456 16 184 472 "A4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B4 " "Info: Pin B4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B4 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 504 16 184 520 "B4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "C4 " "Info: Pin C4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { C4 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 552 16 184 568 "C4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { C4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A5 " "Info: Pin A5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A5 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 312 16 184 328 "A5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B5 " "Info: Pin B5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B5 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 360 16 184 376 "B5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "C5 " "Info: Pin C5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { C5 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 408 16 184 424 "C5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { C5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A6 " "Info: Pin A6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A6 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 168 16 184 184 "A6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B6 " "Info: Pin B6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B6 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 216 16 184 232 "B6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "C6 " "Info: Pin C6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { C6 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 264 16 184 280 "C6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { C6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A7 " "Info: Pin A7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A7 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 24 16 184 40 "A7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B7 " "Info: Pin B7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B7 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 72 16 184 88 "B7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "C7 " "Info: Pin C7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { C7 } } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 120 16 184 136 "C7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { C7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1} -{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1} -{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "35 unused 3.3V 27 8 0 " "Info: Number of I/O pins in group: 35 (unused VREF, 3.3V VCCIO, 27 input, 8 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 2 30 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 35 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 34 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 36 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y10 X34_Y19 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y10 to location X34_Y19" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} -{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y0 0 " "Info: Pin \"Y0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y1 0 " "Info: Pin \"Y1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y2 0 " "Info: Pin \"Y2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y3 0 " "Info: Pin \"Y3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y4 0 " "Info: Pin \"Y4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y5 0 " "Info: Pin \"Y5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y6 0 " "Info: Pin \"Y6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y7 0 " "Info: Pin \"Y7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/triple_selector_8b/triple_selector_8b.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/triple_selector_8b/triple_selector_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "306 " "Info: Peak virtual memory: 306 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 10:24:27 2022 " "Info: Processing ended: Mon Mar 07 10:24:27 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/triple_selector_8b/db/triple_selector_8b.hier_info b/triple_selector_8b/db/triple_selector_8b.hier_info deleted file mode 100644 index 6e018d3..0000000 --- a/triple_selector_8b/db/triple_selector_8b.hier_info +++ /dev/null @@ -1,59 +0,0 @@ -|triple_selector_8b -Y0 <= inst3.DB_MAX_OUTPUT_PORT_TYPE -B0 => inst1.IN0 -BY => inst1.IN1 -BY => inst5.IN1 -BY => inst9.IN1 -BY => inst13.IN1 -BY => inst16.IN1 -BY => inst21.IN1 -BY => inst24.IN1 -BY => inst29.IN1 -C0 => inst2.IN0 -CY => inst2.IN1 -CY => inst6.IN1 -CY => inst10.IN1 -CY => inst14.IN1 -CY => inst18.IN1 -CY => inst22.IN1 -CY => inst26.IN1 -CY => inst30.IN1 -A0 => inst.IN0 -AY => inst.IN1 -AY => inst4.IN1 -AY => inst8.IN1 -AY => inst12.IN1 -AY => inst17.IN1 -AY => inst20.IN1 -AY => inst25.IN1 -AY => inst28.IN1 -Y1 <= inst7.DB_MAX_OUTPUT_PORT_TYPE -B1 => inst5.IN0 -C1 => inst6.IN0 -A1 => inst4.IN0 -Y2 <= inst11.DB_MAX_OUTPUT_PORT_TYPE -B2 => inst9.IN0 -C2 => inst10.IN0 -A2 => inst8.IN0 -Y3 <= inst15.DB_MAX_OUTPUT_PORT_TYPE -B3 => inst13.IN0 -C3 => inst14.IN0 -A3 => inst12.IN0 -Y4 <= inst19.DB_MAX_OUTPUT_PORT_TYPE -B4 => inst16.IN0 -C4 => inst18.IN0 -A4 => inst17.IN0 -Y5 <= inst23.DB_MAX_OUTPUT_PORT_TYPE -B5 => inst21.IN0 -C5 => inst22.IN0 -A5 => inst20.IN0 -Y6 <= inst27.DB_MAX_OUTPUT_PORT_TYPE -B6 => inst24.IN0 -C6 => inst26.IN0 -A6 => inst25.IN0 -Y7 <= inst31.DB_MAX_OUTPUT_PORT_TYPE -B7 => inst29.IN0 -C7 => inst30.IN0 -A7 => inst28.IN0 - - diff --git a/triple_selector_8b/db/triple_selector_8b.hif b/triple_selector_8b/db/triple_selector_8b.hif deleted file mode 100644 index 096c9ff..0000000 --- a/triple_selector_8b/db/triple_selector_8b.hif +++ /dev/null @@ -1,42 +0,0 @@ -Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition -11 -936 -OFF -OFF -OFF -ON -ON -ON -FV_OFF -Level2 -0 -0 -VRSM_ON -VHSM_ON -0 --- Start Library Paths -- --- End Library Paths -- --- Start VHDL Libraries -- --- End VHDL Libraries -- -# entity -triple_selector_8b -# storage -db|triple_selector_8b.(0).cnf -db|triple_selector_8b.(0).cnf -# case_insensitive -# source_file -triple_selector_8b.bdf -91b7a41e9ebd47591ce44c4793a9f2e -26 -# internal_option { -BLOCK_DESIGN_NAMING -AUTO -} -# hierarchies { -| -} -# macro_sequence - -# end -# complete - \ No newline at end of file diff --git a/triple_selector_8b/db/triple_selector_8b.lpc.html b/triple_selector_8b/db/triple_selector_8b.lpc.html deleted file mode 100644 index fd4875d..0000000 --- a/triple_selector_8b/db/triple_selector_8b.lpc.html +++ /dev/null @@ -1,18 +0,0 @@ - - - - - - - - - - - - - - - - - -
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
diff --git a/triple_selector_8b/db/triple_selector_8b.lpc.rdb b/triple_selector_8b/db/triple_selector_8b.lpc.rdb deleted file mode 100644 index 8bd163a..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.lpc.rdb and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.lpc.txt b/triple_selector_8b/db/triple_selector_8b.lpc.txt deleted file mode 100644 index a463804..0000000 --- a/triple_selector_8b/db/triple_selector_8b.lpc.txt +++ /dev/null @@ -1,5 +0,0 @@ -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Legal Partition Candidates ; -+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ -; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; -+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/triple_selector_8b/db/triple_selector_8b.map.bpm b/triple_selector_8b/db/triple_selector_8b.map.bpm deleted file mode 100644 index 35e96e9..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.map.bpm and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.map.cdb b/triple_selector_8b/db/triple_selector_8b.map.cdb deleted file mode 100644 index 238609f..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.map.cdb and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.map.ecobp b/triple_selector_8b/db/triple_selector_8b.map.ecobp deleted file mode 100644 index e05efff..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.map.ecobp and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.map.hdb b/triple_selector_8b/db/triple_selector_8b.map.hdb deleted file mode 100644 index ef5ae30..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.map.hdb and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.map.kpt b/triple_selector_8b/db/triple_selector_8b.map.kpt deleted file mode 100644 index 03a3968..0000000 --- a/triple_selector_8b/db/triple_selector_8b.map.kpt +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/triple_selector_8b/db/triple_selector_8b.map.logdb b/triple_selector_8b/db/triple_selector_8b.map.logdb deleted file mode 100644 index 626799f..0000000 --- a/triple_selector_8b/db/triple_selector_8b.map.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/triple_selector_8b/db/triple_selector_8b.map.qmsg b/triple_selector_8b/db/triple_selector_8b.map.qmsg deleted file mode 100644 index 67830c6..0000000 --- a/triple_selector_8b/db/triple_selector_8b.map.qmsg +++ /dev/null @@ -1,7 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:24:25 2022 " "Info: Processing started: Mon Mar 07 10:24:25 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off triple_selector_8b -c triple_selector_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off triple_selector_8b -c triple_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "triple_selector_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file triple_selector_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 triple_selector_8b " "Info: Found entity 1: triple_selector_8b" { } { { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_START_ELABORATION_TOP" "triple_selector_8b " "Info: Elaborating entity \"triple_selector_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_TM_SUMMARY" "51 " "Info: Implemented 51 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Info: Implemented 27 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "16 " "Info: Implemented 16 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "249 " "Info: Peak virtual memory: 249 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 10:24:26 2022 " "Info: Processing ended: Mon Mar 07 10:24:26 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/triple_selector_8b/db/triple_selector_8b.map_bb.cdb b/triple_selector_8b/db/triple_selector_8b.map_bb.cdb deleted file mode 100644 index ff17d9a..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.map_bb.cdb and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.map_bb.hdb b/triple_selector_8b/db/triple_selector_8b.map_bb.hdb deleted file mode 100644 index 7df4379..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.map_bb.hdb and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.map_bb.logdb b/triple_selector_8b/db/triple_selector_8b.map_bb.logdb deleted file mode 100644 index 626799f..0000000 --- a/triple_selector_8b/db/triple_selector_8b.map_bb.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/triple_selector_8b/db/triple_selector_8b.pre_map.cdb b/triple_selector_8b/db/triple_selector_8b.pre_map.cdb deleted file mode 100644 index 2138e19..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.pre_map.cdb and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.pre_map.hdb b/triple_selector_8b/db/triple_selector_8b.pre_map.hdb deleted file mode 100644 index 4c19e86..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.pre_map.hdb and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.rtlv.hdb b/triple_selector_8b/db/triple_selector_8b.rtlv.hdb deleted file mode 100644 index 264ab31..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.rtlv.hdb and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.rtlv_sg.cdb b/triple_selector_8b/db/triple_selector_8b.rtlv_sg.cdb deleted file mode 100644 index 943e1ca..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.rtlv_sg.cdb and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.rtlv_sg_swap.cdb b/triple_selector_8b/db/triple_selector_8b.rtlv_sg_swap.cdb deleted file mode 100644 index bccc94e..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.rtlv_sg_swap.cdb and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.sgdiff.cdb b/triple_selector_8b/db/triple_selector_8b.sgdiff.cdb deleted file mode 100644 index e3795e6..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.sgdiff.cdb and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.sgdiff.hdb b/triple_selector_8b/db/triple_selector_8b.sgdiff.hdb deleted file mode 100644 index c9b62a5..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.sgdiff.hdb and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.sld_design_entry.sci b/triple_selector_8b/db/triple_selector_8b.sld_design_entry.sci deleted file mode 100644 index 904d003..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.sld_design_entry.sci and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.sld_design_entry_dsc.sci b/triple_selector_8b/db/triple_selector_8b.sld_design_entry_dsc.sci deleted file mode 100644 index 2000bdc..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.sld_design_entry_dsc.sci and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.syn_hier_info b/triple_selector_8b/db/triple_selector_8b.syn_hier_info deleted file mode 100644 index e69de29..0000000 diff --git a/triple_selector_8b/db/triple_selector_8b.tan.qmsg b/triple_selector_8b/db/triple_selector_8b.tan.qmsg deleted file mode 100644 index 9e03ccb..0000000 --- a/triple_selector_8b/db/triple_selector_8b.tan.qmsg +++ /dev/null @@ -1,6 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:24:29 2022 " "Info: Processing started: Mon Mar 07 10:24:29 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off triple_selector_8b -c triple_selector_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off triple_selector_8b -c triple_selector_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "ITDB_FULL_TPD_RESULT" "BY Y6 16.101 ns Longest " "Info: Longest tpd from source pin \"BY\" to destination pin \"Y6\" is 16.101 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.985 ns) 0.985 ns BY 1 PIN PIN_31 8 " "Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_31; Fanout = 8; PIN Node = 'BY'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { BY } "NODE_NAME" } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 1320 16 184 1336 "BY" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.949 ns) + CELL(0.651 ns) 8.585 ns inst27~0 2 COMB LCCOMB_X33_Y11_N0 1 " "Info: 2: + IC(6.949 ns) + CELL(0.651 ns) = 8.585 ns; Loc. = LCCOMB_X33_Y11_N0; Fanout = 1; COMB Node = 'inst27~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.600 ns" { BY inst27~0 } "NODE_NAME" } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 208 488 552 256 "inst27" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.366 ns) + CELL(0.624 ns) 9.575 ns inst27 3 COMB LCCOMB_X33_Y11_N10 1 " "Info: 3: + IC(0.366 ns) + CELL(0.624 ns) = 9.575 ns; Loc. = LCCOMB_X33_Y11_N10; Fanout = 1; COMB Node = 'inst27'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.990 ns" { inst27~0 inst27 } "NODE_NAME" } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 208 488 552 256 "inst27" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.430 ns) + CELL(3.096 ns) 16.101 ns Y6 4 PIN PIN_30 0 " "Info: 4: + IC(3.430 ns) + CELL(3.096 ns) = 16.101 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'Y6'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.526 ns" { inst27 Y6 } "NODE_NAME" } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf" { { 224 600 776 240 "Y6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.356 ns ( 33.27 % ) " "Info: Total cell delay = 5.356 ns ( 33.27 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "10.745 ns ( 66.73 % ) " "Info: Total interconnect delay = 10.745 ns ( 66.73 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "16.101 ns" { BY inst27~0 inst27 Y6 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "16.101 ns" { BY {} BY~combout {} inst27~0 {} inst27 {} Y6 {} } { 0.000ns 0.000ns 6.949ns 0.366ns 3.430ns } { 0.000ns 0.985ns 0.651ns 0.624ns 3.096ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 10:24:29 2022 " "Info: Processing ended: Mon Mar 07 10:24:29 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/triple_selector_8b/db/triple_selector_8b.tis_db_list.ddb b/triple_selector_8b/db/triple_selector_8b.tis_db_list.ddb deleted file mode 100644 index 2a9a6ed..0000000 Binary files a/triple_selector_8b/db/triple_selector_8b.tis_db_list.ddb and /dev/null differ diff --git a/triple_selector_8b/db/triple_selector_8b.tmw_info b/triple_selector_8b/db/triple_selector_8b.tmw_info deleted file mode 100644 index 15a6255..0000000 --- a/triple_selector_8b/db/triple_selector_8b.tmw_info +++ /dev/null @@ -1,6 +0,0 @@ -start_full_compilation:s:00:00:05 -start_analysis_synthesis:s:00:00:01-start_full_compilation -start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:02-start_full_compilation -start_assembler:s:00:00:01-start_full_compilation -start_timing_analyzer:s:00:00:01-start_full_compilation diff --git a/triple_selector_8b/incremental_db/README b/triple_selector_8b/incremental_db/README deleted file mode 100644 index 9f62dcd..0000000 --- a/triple_selector_8b/incremental_db/README +++ /dev/null @@ -1,11 +0,0 @@ -This folder contains data for incremental compilation. - -The compiled_partitions sub-folder contains previous compilation results for each partition. -As long as this folder is preserved, incremental compilation results from earlier compiles -can be re-used. To perform a clean compilation from source files for all partitions, both -the db and incremental_db folder should be removed. - -The imported_partitions sub-folder contains the last imported QXP for each imported partition. -As long as this folder is preserved, imported partitions will be automatically re-imported -when the db or incremental_db/compiled_partitions folders are removed. - diff --git a/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.cmp.atm b/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.cmp.atm deleted file mode 100644 index 1f85076..0000000 Binary files a/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.cmp.atm and /dev/null differ diff --git a/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.cmp.dfp b/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.cmp.dfp deleted file mode 100644 index b1c67d6..0000000 Binary files a/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.cmp.dfp and /dev/null differ diff --git a/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.cmp.hdbx b/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.cmp.hdbx deleted file mode 100644 index 30c8a44..0000000 Binary files a/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.cmp.hdbx and /dev/null differ diff --git a/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.cmp.kpt b/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.cmp.kpt deleted file mode 100644 index c1e72d7..0000000 --- a/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.cmp.kpt +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.cmp.logdb b/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.cmp.logdb deleted file mode 100644 index 626799f..0000000 --- a/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.cmp.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.cmp.rcf b/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.cmp.rcf deleted file mode 100644 index 479b7f5..0000000 Binary files a/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.cmp.rcf and /dev/null differ diff --git a/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.map.atm b/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.map.atm deleted file mode 100644 index 13e991c..0000000 Binary files a/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.map.atm and /dev/null differ diff --git a/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.map.dpi b/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.map.dpi deleted file mode 100644 index 1d82483..0000000 Binary files a/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.map.dpi and /dev/null differ diff --git a/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.map.hdbx b/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.map.hdbx deleted file mode 100644 index 5fac0a1..0000000 Binary files a/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.map.hdbx and /dev/null differ diff --git a/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.map.kpt b/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.map.kpt deleted file mode 100644 index eaf76eb..0000000 --- a/triple_selector_8b/incremental_db/compiled_partitions/triple_selector_8b.root_partition.map.kpt +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/triple_selector_8b/triple_selector_8b.asm.rpt b/triple_selector_8b/triple_selector_8b.asm.rpt deleted file mode 100644 index b79809e..0000000 --- a/triple_selector_8b/triple_selector_8b.asm.rpt +++ /dev/null @@ -1,129 +0,0 @@ -Assembler report for triple_selector_8b -Mon Mar 07 10:24:29 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Assembler Summary - 3. Assembler Settings - 4. Assembler Generated Files - 5. Assembler Device Options: D:/projects/quartus/triple_selector_8b/triple_selector_8b.sof - 6. Assembler Device Options: D:/projects/quartus/triple_selector_8b/triple_selector_8b.pof - 7. Assembler Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+---------------------------------------------------------------+ -; Assembler Summary ; -+-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Mon Mar 07 10:24:29 2022 ; -; Revision Name ; triple_selector_8b ; -; Top-level Entity Name ; triple_selector_8b ; -; Family ; Cyclone II ; -; Device ; EP2C8Q208C8 ; -+-----------------------+---------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------+ -; Assembler Settings ; -+-----------------------------------------------------------------------------+----------+---------------+ -; Option ; Setting ; Default Value ; -+-----------------------------------------------------------------------------+----------+---------------+ -; Use smart compilation ; Off ; Off ; -; Generate compressed bitstreams ; On ; On ; -; Compression mode ; Off ; Off ; -; Clock source for configuration device ; Internal ; Internal ; -; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; -; Divide clock frequency by ; 1 ; 1 ; -; Auto user code ; Off ; Off ; -; Use configuration device ; On ; On ; -; Configuration device ; Auto ; Auto ; -; Configuration device auto user code ; Off ; Off ; -; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; -; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; -; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; -; Hexadecimal Output File start address ; 0 ; 0 ; -; Hexadecimal Output File count direction ; Up ; Up ; -; Release clears before tri-states ; Off ; Off ; -; Auto-restart configuration after error ; On ; On ; -; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ; -; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; -; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; -; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; -; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; -+-----------------------------------------------------------------------------+----------+---------------+ - - -+---------------------------------------------------------------+ -; Assembler Generated Files ; -+---------------------------------------------------------------+ -; File Name ; -+---------------------------------------------------------------+ -; D:/projects/quartus/triple_selector_8b/triple_selector_8b.sof ; -; D:/projects/quartus/triple_selector_8b/triple_selector_8b.pof ; -+---------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------+ -; Assembler Device Options: D:/projects/quartus/triple_selector_8b/triple_selector_8b.sof ; -+----------------+------------------------------------------------------------------------+ -; Option ; Setting ; -+----------------+------------------------------------------------------------------------+ -; Device ; EP2C8Q208C8 ; -; JTAG usercode ; 0xFFFFFFFF ; -; Checksum ; 0x000C82A8 ; -+----------------+------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------+ -; Assembler Device Options: D:/projects/quartus/triple_selector_8b/triple_selector_8b.pof ; -+--------------------+--------------------------------------------------------------------+ -; Option ; Setting ; -+--------------------+--------------------------------------------------------------------+ -; Device ; EPCS4 ; -; JTAG usercode ; 0x00000000 ; -; Checksum ; 0x06F0BC42 ; -; Compression Ratio ; 3 ; -+--------------------+--------------------------------------------------------------------+ - - -+--------------------+ -; Assembler Messages ; -+--------------------+ -Info: ******************************************************************* -Info: Running Quartus II Assembler - Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Mon Mar 07 10:24:28 2022 -Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off triple_selector_8b -c triple_selector_8b -Info: Writing out detailed assembly data for power analysis -Info: Assembler is generating device programming files -Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled -Info: Quartus II Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 242 megabytes - Info: Processing ended: Mon Mar 07 10:24:29 2022 - Info: Elapsed time: 00:00:01 - Info: Total CPU time (on all processors): 00:00:01 - - diff --git a/triple_selector_8b/triple_selector_8b.done b/triple_selector_8b/triple_selector_8b.done deleted file mode 100644 index ee9a0af..0000000 --- a/triple_selector_8b/triple_selector_8b.done +++ /dev/null @@ -1 +0,0 @@ -Mon Mar 07 10:24:30 2022 diff --git a/triple_selector_8b/triple_selector_8b.fit.rpt b/triple_selector_8b/triple_selector_8b.fit.rpt deleted file mode 100644 index 3137a73..0000000 --- a/triple_selector_8b/triple_selector_8b.fit.rpt +++ /dev/null @@ -1,1094 +0,0 @@ -Fitter report for triple_selector_8b -Mon Mar 07 10:24:27 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Fitter Summary - 3. Fitter Settings - 4. Parallel Compilation - 5. Incremental Compilation Preservation Summary - 6. Incremental Compilation Partition Settings - 7. Incremental Compilation Placement Preservation - 8. Pin-Out File - 9. Fitter Resource Usage Summary - 10. Input Pins - 11. Output Pins - 12. I/O Bank Usage - 13. All Package Pins - 14. Output Pin Default Load For Reported TCO - 15. Fitter Resource Utilization by Entity - 16. Delay Chain Summary - 17. Pad To Core Delay Chain Fanout - 18. Non-Global High Fan-Out Signals - 19. Interconnect Usage Summary - 20. LAB Logic Elements - 21. LAB Signals Sourced - 22. LAB Signals Sourced Out - 23. LAB Distinct Inputs - 24. Fitter Device Options - 25. Operating Settings and Conditions - 26. Estimated Delay Added for Hold Timing - 27. Advanced Data - General - 28. Advanced Data - Placement Preparation - 29. Advanced Data - Placement - 30. Advanced Data - Routing - 31. Fitter Messages - 32. Fitter Suppressed Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------------+ -; Fitter Summary ; -+------------------------------------+----------------------------------------------+ -; Fitter Status ; Successful - Mon Mar 07 10:24:27 2022 ; -; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; -; Revision Name ; triple_selector_8b ; -; Top-level Entity Name ; triple_selector_8b ; -; Family ; Cyclone II ; -; Device ; EP2C8Q208C8 ; -; Timing Models ; Final ; -; Total logic elements ; 16 / 8,256 ( < 1 % ) ; -; Total combinational functions ; 16 / 8,256 ( < 1 % ) ; -; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ; -; Total registers ; 0 ; -; Total pins ; 35 / 138 ( 25 % ) ; -; Total virtual pins ; 0 ; -; Total memory bits ; 0 / 165,888 ( 0 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; -; Total PLLs ; 0 / 2 ( 0 % ) ; -+------------------------------------+----------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Settings ; -+--------------------------------------------------------------------+--------------------------------+--------------------------------+ -; Option ; Setting ; Default Value ; -+--------------------------------------------------------------------+--------------------------------+--------------------------------+ -; Device ; EP2C8Q208C8 ; ; -; Minimum Core Junction Temperature ; 0 ; ; -; Maximum Core Junction Temperature ; 85 ; ; -; Fit Attempts to Skip ; 0 ; 0.0 ; -; Use smart compilation ; Off ; Off ; -; Use TimeQuest Timing Analyzer ; Off ; Off ; -; Router Timing Optimization Level ; Normal ; Normal ; -; Placement Effort Multiplier ; 1.0 ; 1.0 ; -; Router Effort Multiplier ; 1.0 ; 1.0 ; -; Always Enable Input Buffers ; Off ; Off ; -; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; -; Optimize Multi-Corner Timing ; Off ; Off ; -; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; -; Optimize Timing ; Normal compilation ; Normal compilation ; -; Optimize Timing for ECOs ; Off ; Off ; -; Regenerate full fit report during ECO compiles ; Off ; Off ; -; Optimize IOC Register Placement for Timing ; On ; On ; -; Limit to One Fitting Attempt ; Off ; Off ; -; Final Placement Optimizations ; Automatically ; Automatically ; -; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; -; Fitter Initial Placement Seed ; 1 ; 1 ; -; PCI I/O ; Off ; Off ; -; Weak Pull-Up Resistor ; Off ; Off ; -; Enable Bus-Hold Circuitry ; Off ; Off ; -; Auto Global Memory Control Signals ; Off ; Off ; -; Auto Packed Registers ; Auto ; Auto ; -; Auto Delay Chains ; On ; On ; -; Auto Merge PLLs ; On ; On ; -; Ignore PLL Mode When Merging PLLs ; Off ; Off ; -; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; -; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; -; Perform Register Duplication for Performance ; Off ; Off ; -; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; -; Perform Register Retiming for Performance ; Off ; Off ; -; Perform Asynchronous Signal Pipelining ; Off ; Off ; -; Fitter Effort ; Auto Fit ; Auto Fit ; -; Physical Synthesis Effort Level ; Normal ; Normal ; -; Auto Global Clock ; On ; On ; -; Auto Global Register Control Signals ; On ; On ; -; Stop After Congestion Map Generation ; Off ; Off ; -; Save Intermediate Fitting Results ; Off ; Off ; -; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; -+--------------------------------------------------------------------+--------------------------------+--------------------------------+ - - -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 4 ; -; Maximum allowed ; 4 ; -; ; ; -; Average used ; 1.00 ; -; Maximum used ; 4 ; -; ; ; -; Usage by Processor ; % Time Used ; -; 1 processor ; 100.0% ; -; 2-4 processors ; < 0.1% ; -+----------------------------+-------------+ - - -+----------------------------------------------+ -; Incremental Compilation Preservation Summary ; -+-------------------------+--------------------+ -; Type ; Value ; -+-------------------------+--------------------+ -; Placement ; ; -; -- Requested ; 0 / 51 ( 0.00 % ) ; -; -- Achieved ; 0 / 51 ( 0.00 % ) ; -; ; ; -; Routing (by Connection) ; ; -; -- Requested ; 0 / 0 ( 0.00 % ) ; -; -- Achieved ; 0 / 0 ( 0.00 % ) ; -+-------------------------+--------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Incremental Compilation Partition Settings ; -+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ -; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; -+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ -; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; -+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ - - -+--------------------------------------------------------------------------------------------+ -; Incremental Compilation Placement Preservation ; -+----------------+---------+-------------------+-------------------------+-------------------+ -; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; -+----------------+---------+-------------------+-------------------------+-------------------+ -; Top ; 51 ; 0 ; N/A ; Source File ; -+----------------+---------+-------------------+-------------------------+-------------------+ - - -+--------------+ -; Pin-Out File ; -+--------------+ -The pin-out file can be found in D:/projects/quartus/triple_selector_8b/triple_selector_8b.pin. - - -+--------------------------------------------------------------------+ -; Fitter Resource Usage Summary ; -+---------------------------------------------+----------------------+ -; Resource ; Usage ; -+---------------------------------------------+----------------------+ -; Total logic elements ; 16 / 8,256 ( < 1 % ) ; -; -- Combinational with no register ; 16 ; -; -- Register only ; 0 ; -; -- Combinational with a register ; 0 ; -; ; ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 8 ; -; -- 3 input functions ; 8 ; -; -- <=2 input functions ; 0 ; -; -- Register only ; 0 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 16 ; -; -- arithmetic mode ; 0 ; -; ; ; -; Total registers* ; 0 / 8,646 ( 0 % ) ; -; -- Dedicated logic registers ; 0 / 8,256 ( 0 % ) ; -; -- I/O registers ; 0 / 390 ( 0 % ) ; -; ; ; -; Total LABs: partially or completely used ; 1 / 516 ( < 1 % ) ; -; User inserted logic elements ; 0 ; -; Virtual pins ; 0 ; -; I/O pins ; 35 / 138 ( 25 % ) ; -; -- Clock pins ; 2 / 4 ( 50 % ) ; -; Global signals ; 0 ; -; M4Ks ; 0 / 36 ( 0 % ) ; -; Total block memory bits ; 0 / 165,888 ( 0 % ) ; -; Total block memory implementation bits ; 0 / 165,888 ( 0 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; -; PLLs ; 0 / 2 ( 0 % ) ; -; Global clocks ; 0 / 8 ( 0 % ) ; -; JTAGs ; 0 / 1 ( 0 % ) ; -; ASMI blocks ; 0 / 1 ( 0 % ) ; -; CRC blocks ; 0 / 1 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; -; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ; -; Maximum fan-out node ; AY ; -; Maximum fan-out ; 8 ; -; Highest non-global fan-out signal ; AY ; -; Highest non-global fan-out ; 8 ; -; Total fan-out ; 64 ; -; Average fan-out ; 1.19 ; -+---------------------------------------------+----------------------+ -* Register count does not include registers inside RAM blocks or DSP blocks. - - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Input Pins ; -+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ; -+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ -; A0 ; 110 ; 3 ; 34 ; 3 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; A1 ; 103 ; 4 ; 32 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; A2 ; 141 ; 3 ; 34 ; 12 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; A3 ; 129 ; 3 ; 34 ; 10 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; A4 ; 132 ; 3 ; 34 ; 10 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; A5 ; 143 ; 3 ; 34 ; 13 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; A6 ; 137 ; 3 ; 34 ; 11 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; A7 ; 135 ; 3 ; 34 ; 11 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; AY ; 127 ; 3 ; 34 ; 9 ; 1 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; B0 ; 138 ; 3 ; 34 ; 12 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; B1 ; 134 ; 3 ; 34 ; 11 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; B2 ; 105 ; 3 ; 34 ; 1 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; B3 ; 130 ; 3 ; 34 ; 10 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; B4 ; 128 ; 3 ; 34 ; 9 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; B5 ; 144 ; 3 ; 34 ; 13 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; B6 ; 115 ; 3 ; 34 ; 4 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; B7 ; 133 ; 3 ; 34 ; 11 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; BY ; 31 ; 1 ; 0 ; 8 ; 1 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; C0 ; 116 ; 3 ; 34 ; 5 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; C1 ; 139 ; 3 ; 34 ; 12 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; C2 ; 113 ; 3 ; 34 ; 3 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; C3 ; 131 ; 3 ; 34 ; 10 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; C4 ; 114 ; 3 ; 34 ; 4 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; C5 ; 145 ; 3 ; 34 ; 14 ; 4 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; C6 ; 112 ; 3 ; 34 ; 3 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; C7 ; 118 ; 3 ; 34 ; 7 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -; CY ; 142 ; 3 ; 34 ; 12 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; -+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Output Pins ; -+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; -+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ -; Y0 ; 107 ; 3 ; 34 ; 2 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; -; Y1 ; 15 ; 1 ; 0 ; 14 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; -; Y2 ; 87 ; 4 ; 25 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; -; Y3 ; 102 ; 4 ; 32 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; -; Y4 ; 117 ; 3 ; 34 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; -; Y5 ; 34 ; 1 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; -; Y6 ; 30 ; 1 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; -; Y7 ; 171 ; 2 ; 28 ; 19 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; -+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+ - - -+------------------------------------------------------------+ -; I/O Bank Usage ; -+----------+------------------+---------------+--------------+ -; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; -+----------+------------------+---------------+--------------+ -; 1 ; 6 / 32 ( 19 % ) ; 3.3V ; -- ; -; 2 ; 1 / 35 ( 3 % ) ; 3.3V ; -- ; -; 3 ; 28 / 35 ( 80 % ) ; 3.3V ; -- ; -; 4 ; 3 / 36 ( 8 % ) ; 3.3V ; -- ; -+----------+------------------+---------------+--------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; All Package Pins ; -+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; -+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -; 1 ; 0 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; -; 2 ; 1 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; -; 3 ; 2 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 4 ; 3 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 5 ; 4 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 6 ; 5 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 8 ; 6 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 10 ; 7 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 11 ; 8 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 12 ; 9 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 13 ; 10 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 14 ; 18 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 15 ; 19 ; 1 ; Y1 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; -; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; -; 18 ; 22 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; -; 19 ; 23 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; -; 20 ; 24 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ; -; 21 ; 25 ; 1 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ; -; 22 ; 26 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; -; 23 ; 27 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 24 ; 28 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 26 ; 29 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; -; 27 ; 30 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 28 ; 31 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 30 ; 32 ; 1 ; Y6 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 31 ; 33 ; 1 ; BY ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 33 ; 35 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 34 ; 36 ; 1 ; Y5 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 35 ; 37 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 37 ; 39 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 39 ; 43 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 40 ; 44 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 41 ; 45 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 42 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 43 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 44 ; 49 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 45 ; 50 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 46 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 47 ; 52 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 48 ; 53 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 49 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 50 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; -; 51 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 52 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; -; 53 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 54 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; -; 55 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 56 ; 54 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 57 ; 55 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 58 ; 56 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 59 ; 57 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 60 ; 58 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 61 ; 59 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 63 ; 60 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 64 ; 61 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 67 ; 69 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 68 ; 70 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 69 ; 71 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 70 ; 74 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 71 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 72 ; 75 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 74 ; 76 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 75 ; 77 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 76 ; 78 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 77 ; 79 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 80 ; 82 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 81 ; 83 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 82 ; 84 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 83 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 84 ; 85 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 85 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 86 ; 86 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 87 ; 87 ; 4 ; Y2 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 88 ; 88 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 89 ; 89 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 90 ; 90 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 91 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 92 ; 91 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 94 ; 92 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 95 ; 93 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 96 ; 94 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 97 ; 95 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 98 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 99 ; 96 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 100 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 101 ; 97 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 102 ; 98 ; 4 ; Y3 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 103 ; 99 ; 4 ; A1 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 104 ; 100 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 105 ; 101 ; 3 ; B2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 106 ; 102 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 107 ; 105 ; 3 ; Y0 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 108 ; 106 ; 3 ; ~LVDS54p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 109 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 110 ; 107 ; 3 ; A0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 111 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 112 ; 108 ; 3 ; C6 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 113 ; 109 ; 3 ; C2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 114 ; 110 ; 3 ; C4 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 115 ; 112 ; 3 ; B6 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 116 ; 113 ; 3 ; C0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 117 ; 114 ; 3 ; Y4 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 118 ; 117 ; 3 ; C7 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 119 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 120 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 121 ; 121 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; -; 122 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 123 ; 122 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; -; 124 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 125 ; 123 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; -; 126 ; 124 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; -; 127 ; 125 ; 3 ; AY ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 128 ; 126 ; 3 ; B4 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 129 ; 127 ; 3 ; A3 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 130 ; 128 ; 3 ; B3 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 131 ; 129 ; 3 ; C3 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 132 ; 130 ; 3 ; A4 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 133 ; 131 ; 3 ; B7 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 134 ; 132 ; 3 ; B1 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 135 ; 133 ; 3 ; A7 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 136 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 137 ; 134 ; 3 ; A6 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 138 ; 135 ; 3 ; B0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 139 ; 136 ; 3 ; C1 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 141 ; 137 ; 3 ; A2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 142 ; 138 ; 3 ; CY ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 143 ; 141 ; 3 ; A5 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 144 ; 142 ; 3 ; B5 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 145 ; 143 ; 3 ; C5 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; 146 ; 149 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 147 ; 150 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 148 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 149 ; 151 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 150 ; 152 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 151 ; 153 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 152 ; 154 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 153 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 154 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; -; 155 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 156 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; -; 157 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 158 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; -; 159 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 160 ; 155 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 161 ; 156 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 162 ; 157 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 163 ; 158 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 164 ; 159 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 165 ; 160 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 166 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 167 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 168 ; 161 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 169 ; 162 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 170 ; 163 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 171 ; 164 ; 2 ; Y7 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; -; 172 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 173 ; 165 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 174 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 175 ; 168 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 176 ; 169 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 177 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 178 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 179 ; 173 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 180 ; 174 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 181 ; 175 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 182 ; 176 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 183 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 184 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 185 ; 180 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 186 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 187 ; 181 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 188 ; 182 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 189 ; 183 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 190 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; 191 ; 184 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 192 ; 185 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 193 ; 186 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 194 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 195 ; 187 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 196 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 197 ; 191 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 198 ; 192 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 199 ; 195 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 200 ; 196 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 201 ; 197 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 202 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 203 ; 198 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 204 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 205 ; 199 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 206 ; 200 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 207 ; 201 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 208 ; 202 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -Note: Pin directions (input, output or bidir) are based on device operating in user mode. - - -+-------------------------------------------------------------------------------+ -; Output Pin Default Load For Reported TCO ; -+----------------------------------+-------+------------------------------------+ -; I/O Standard ; Load ; Termination Resistance ; -+----------------------------------+-------+------------------------------------+ -; 3.3-V LVTTL ; 0 pF ; Not Available ; -; 3.3-V LVCMOS ; 0 pF ; Not Available ; -; 2.5 V ; 0 pF ; Not Available ; -; 1.8 V ; 0 pF ; Not Available ; -; 1.5 V ; 0 pF ; Not Available ; -; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ; -; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ; -; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; -; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; -; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; -; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; -; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; -; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; -; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; -; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; -; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ; -; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ; -; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ; -; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ; -; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ; -; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ; -; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ; -; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ; -; LVDS ; 0 pF ; 100 Ohm (Differential) ; -; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ; -; RSDS ; 0 pF ; 100 Ohm (Differential) ; -; Simple RSDS ; 0 pF ; Not Available ; -; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ; -+----------------------------------+-------+------------------------------------+ -Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Resource Utilization by Entity ; -+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ -; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; -+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ -; |triple_selector_8b ; 16 (16) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 35 ; 0 ; 16 (16) ; 0 (0) ; 0 (0) ; |triple_selector_8b ; work ; -+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ -Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. - - -+-------------------------------------------------------------------------------+ -; Delay Chain Summary ; -+------+----------+---------------+---------------+-----------------------+-----+ -; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; -+------+----------+---------------+---------------+-----------------------+-----+ -; Y0 ; Output ; -- ; -- ; -- ; -- ; -; Y1 ; Output ; -- ; -- ; -- ; -- ; -; Y2 ; Output ; -- ; -- ; -- ; -- ; -; Y3 ; Output ; -- ; -- ; -- ; -- ; -; Y4 ; Output ; -- ; -- ; -- ; -- ; -; Y5 ; Output ; -- ; -- ; -- ; -- ; -; Y6 ; Output ; -- ; -- ; -- ; -- ; -; Y7 ; Output ; -- ; -- ; -- ; -- ; -; B0 ; Input ; 6 ; 6 ; -- ; -- ; -; A0 ; Input ; 6 ; 6 ; -- ; -- ; -; AY ; Input ; 6 ; 6 ; -- ; -- ; -; BY ; Input ; 6 ; 6 ; -- ; -- ; -; C0 ; Input ; 6 ; 6 ; -- ; -- ; -; CY ; Input ; 6 ; 6 ; -- ; -- ; -; A1 ; Input ; 6 ; 6 ; -- ; -- ; -; B1 ; Input ; 6 ; 6 ; -- ; -- ; -; C1 ; Input ; 6 ; 6 ; -- ; -- ; -; A2 ; Input ; 6 ; 6 ; -- ; -- ; -; B2 ; Input ; 6 ; 6 ; -- ; -- ; -; C2 ; Input ; 6 ; 6 ; -- ; -- ; -; A3 ; Input ; 0 ; 0 ; -- ; -- ; -; B3 ; Input ; 0 ; 0 ; -- ; -- ; -; C3 ; Input ; 0 ; 0 ; -- ; -- ; -; A4 ; Input ; 0 ; 0 ; -- ; -- ; -; B4 ; Input ; 6 ; 6 ; -- ; -- ; -; C4 ; Input ; 6 ; 6 ; -- ; -- ; -; A5 ; Input ; 6 ; 6 ; -- ; -- ; -; B5 ; Input ; 6 ; 6 ; -- ; -- ; -; C5 ; Input ; 6 ; 6 ; -- ; -- ; -; A6 ; Input ; 6 ; 6 ; -- ; -- ; -; B6 ; Input ; 6 ; 6 ; -- ; -- ; -; C6 ; Input ; 6 ; 6 ; -- ; -- ; -; A7 ; Input ; 6 ; 6 ; -- ; -- ; -; B7 ; Input ; 6 ; 6 ; -- ; -- ; -; C7 ; Input ; 6 ; 6 ; -- ; -- ; -+------+----------+---------------+---------------+-----------------------+-----+ - - -+---------------------------------------------------+ -; Pad To Core Delay Chain Fanout ; -+---------------------+-------------------+---------+ -; Source Pin / Fanout ; Pad To Core Index ; Setting ; -+---------------------+-------------------+---------+ -; B0 ; ; ; -; - inst3~0 ; 1 ; 6 ; -; A0 ; ; ; -; - inst3~0 ; 0 ; 6 ; -; AY ; ; ; -; - inst3~0 ; 0 ; 6 ; -; - inst7~0 ; 0 ; 6 ; -; - inst11~0 ; 0 ; 6 ; -; - inst15~0 ; 0 ; 6 ; -; - inst19~0 ; 0 ; 6 ; -; - inst23~0 ; 0 ; 6 ; -; - inst27~0 ; 0 ; 6 ; -; - inst31~0 ; 0 ; 6 ; -; BY ; ; ; -; - inst3~0 ; 1 ; 6 ; -; - inst7~0 ; 1 ; 6 ; -; - inst11~0 ; 1 ; 6 ; -; - inst15~0 ; 1 ; 6 ; -; - inst19~0 ; 1 ; 6 ; -; - inst23~0 ; 1 ; 6 ; -; - inst27~0 ; 1 ; 6 ; -; - inst31~0 ; 1 ; 6 ; -; C0 ; ; ; -; - inst3 ; 0 ; 6 ; -; CY ; ; ; -; - inst3 ; 1 ; 6 ; -; - inst7 ; 1 ; 6 ; -; - inst11 ; 1 ; 6 ; -; - inst15 ; 1 ; 6 ; -; - inst19 ; 1 ; 6 ; -; - inst23 ; 1 ; 6 ; -; - inst27 ; 1 ; 6 ; -; - inst31 ; 1 ; 6 ; -; A1 ; ; ; -; - inst7~0 ; 0 ; 6 ; -; B1 ; ; ; -; - inst7~0 ; 1 ; 6 ; -; C1 ; ; ; -; - inst7 ; 0 ; 6 ; -; A2 ; ; ; -; - inst11~0 ; 1 ; 6 ; -; B2 ; ; ; -; - inst11~0 ; 0 ; 6 ; -; C2 ; ; ; -; - inst11 ; 0 ; 6 ; -; A3 ; ; ; -; B3 ; ; ; -; C3 ; ; ; -; A4 ; ; ; -; B4 ; ; ; -; - inst19~0 ; 1 ; 6 ; -; C4 ; ; ; -; - inst19 ; 1 ; 6 ; -; A5 ; ; ; -; - inst23~0 ; 1 ; 6 ; -; B5 ; ; ; -; - inst23~0 ; 0 ; 6 ; -; C5 ; ; ; -; - inst23 ; 0 ; 6 ; -; A6 ; ; ; -; - inst27~0 ; 1 ; 6 ; -; B6 ; ; ; -; - inst27~0 ; 0 ; 6 ; -; C6 ; ; ; -; - inst27 ; 1 ; 6 ; -; A7 ; ; ; -; - inst31~0 ; 1 ; 6 ; -; B7 ; ; ; -; - inst31~0 ; 1 ; 6 ; -; C7 ; ; ; -; - inst31 ; 0 ; 6 ; -+---------------------+-------------------+---------+ - - -+---------------------------------+ -; Non-Global High Fan-Out Signals ; -+----------+----------------------+ -; Name ; Fan-Out ; -+----------+----------------------+ -; CY ; 8 ; -; BY ; 8 ; -; AY ; 8 ; -; C7 ; 1 ; -; B7 ; 1 ; -; A7 ; 1 ; -; C6 ; 1 ; -; B6 ; 1 ; -; A6 ; 1 ; -; C5 ; 1 ; -; B5 ; 1 ; -; A5 ; 1 ; -; C4 ; 1 ; -; B4 ; 1 ; -; A4 ; 1 ; -; C3 ; 1 ; -; B3 ; 1 ; -; A3 ; 1 ; -; C2 ; 1 ; -; B2 ; 1 ; -; A2 ; 1 ; -; C1 ; 1 ; -; B1 ; 1 ; -; A1 ; 1 ; -; C0 ; 1 ; -; A0 ; 1 ; -; B0 ; 1 ; -; inst31 ; 1 ; -; inst31~0 ; 1 ; -; inst27 ; 1 ; -; inst27~0 ; 1 ; -; inst23 ; 1 ; -; inst23~0 ; 1 ; -; inst19 ; 1 ; -; inst19~0 ; 1 ; -; inst15 ; 1 ; -; inst15~0 ; 1 ; -; inst11 ; 1 ; -; inst11~0 ; 1 ; -; inst7 ; 1 ; -; inst7~0 ; 1 ; -; inst3 ; 1 ; -; inst3~0 ; 1 ; -+----------+----------------------+ - - -+----------------------------------------------------+ -; Interconnect Usage Summary ; -+----------------------------+-----------------------+ -; Interconnect Resource Type ; Usage ; -+----------------------------+-----------------------+ -; Block interconnects ; 36 / 26,052 ( < 1 % ) ; -; C16 interconnects ; 1 / 1,156 ( < 1 % ) ; -; C4 interconnects ; 47 / 17,952 ( < 1 % ) ; -; Direct links ; 0 / 26,052 ( 0 % ) ; -; Global clocks ; 0 / 8 ( 0 % ) ; -; Local interconnects ; 8 / 8,256 ( < 1 % ) ; -; R24 interconnects ; 5 / 1,020 ( < 1 % ) ; -; R4 interconnects ; 28 / 22,440 ( < 1 % ) ; -+----------------------------+-----------------------+ - - -+---------------------------------------------------------------------------+ -; LAB Logic Elements ; -+---------------------------------------------+-----------------------------+ -; Number of Logic Elements (Average = 16.00) ; Number of LABs (Total = 1) ; -+---------------------------------------------+-----------------------------+ -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 0 ; -; 9 ; 0 ; -; 10 ; 0 ; -; 11 ; 0 ; -; 12 ; 0 ; -; 13 ; 0 ; -; 14 ; 0 ; -; 15 ; 0 ; -; 16 ; 1 ; -+---------------------------------------------+-----------------------------+ - - -+----------------------------------------------------------------------------+ -; LAB Signals Sourced ; -+----------------------------------------------+-----------------------------+ -; Number of Signals Sourced (Average = 16.00) ; Number of LABs (Total = 1) ; -+----------------------------------------------+-----------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 0 ; -; 9 ; 0 ; -; 10 ; 0 ; -; 11 ; 0 ; -; 12 ; 0 ; -; 13 ; 0 ; -; 14 ; 0 ; -; 15 ; 0 ; -; 16 ; 1 ; -+----------------------------------------------+-----------------------------+ - - -+-------------------------------------------------------------------------------+ -; LAB Signals Sourced Out ; -+-------------------------------------------------+-----------------------------+ -; Number of Signals Sourced Out (Average = 8.00) ; Number of LABs (Total = 1) ; -+-------------------------------------------------+-----------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 1 ; -+-------------------------------------------------+-----------------------------+ - - -+----------------------------------------------------------------------------+ -; LAB Distinct Inputs ; -+----------------------------------------------+-----------------------------+ -; Number of Distinct Inputs (Average = 27.00) ; Number of LABs (Total = 1) ; -+----------------------------------------------+-----------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 0 ; -; 9 ; 0 ; -; 10 ; 0 ; -; 11 ; 0 ; -; 12 ; 0 ; -; 13 ; 0 ; -; 14 ; 0 ; -; 15 ; 0 ; -; 16 ; 0 ; -; 17 ; 0 ; -; 18 ; 0 ; -; 19 ; 0 ; -; 20 ; 0 ; -; 21 ; 0 ; -; 22 ; 0 ; -; 23 ; 0 ; -; 24 ; 0 ; -; 25 ; 0 ; -; 26 ; 0 ; -; 27 ; 1 ; -+----------------------------------------------+-----------------------------+ - - -+-------------------------------------------------------------------------+ -; Fitter Device Options ; -+----------------------------------------------+--------------------------+ -; Option ; Setting ; -+----------------------------------------------+--------------------------+ -; Enable user-supplied start-up clock (CLKUSR) ; Off ; -; Enable device-wide reset (DEV_CLRn) ; Off ; -; Enable device-wide output enable (DEV_OE) ; Off ; -; Enable INIT_DONE output ; Off ; -; Configuration scheme ; Active Serial ; -; Error detection CRC ; Off ; -; nCEO ; As output driving ground ; -; ASDO,nCSO ; As input tri-stated ; -; Reserve all unused pins ; As output driving ground ; -; Base pin-out file on sameframe device ; Off ; -+----------------------------------------------+--------------------------+ - - -+------------------------------------+ -; Operating Settings and Conditions ; -+---------------------------+--------+ -; Setting ; Value ; -+---------------------------+--------+ -; Nominal Core Voltage ; 1.20 V ; -; Low Junction Temperature ; 0 °C ; -; High Junction Temperature ; 85 °C ; -+---------------------------+--------+ - - -+------------------------------------------------------------+ -; Estimated Delay Added for Hold Timing ; -+-----------------+----------------------+-------------------+ -; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; -+-----------------+----------------------+-------------------+ - - -+----------------------------+ -; Advanced Data - General ; -+--------------------+-------+ -; Name ; Value ; -+--------------------+-------+ -; Status Code ; 0 ; -; Desired User Slack ; 0 ; -; Fit Attempts ; 1 ; -+--------------------+-------+ - - -+-------------------------------------------------------------------------------+ -; Advanced Data - Placement Preparation ; -+------------------------------------------------------------------+------------+ -; Name ; Value ; -+------------------------------------------------------------------+------------+ -; Auto Fit Point 1 - Fit Attempt 1 ; ff ; -; Mid Wire Use - Fit Attempt 1 ; 0 ; -; Mid Slack - Fit Attempt 1 ; 2147483639 ; -; Internal Atom Count - Fit Attempt 1 ; 17 ; -; LE/ALM Count - Fit Attempt 1 ; 17 ; -; LAB Count - Fit Attempt 1 ; 2 ; -; Outputs per Lab - Fit Attempt 1 ; 4.000 ; -; Inputs per LAB - Fit Attempt 1 ; 13.500 ; -; Global Inputs per LAB - Fit Attempt 1 ; 0.000 ; -; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:2 ; -; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:1 ; -; LEs in Chains - Fit Attempt 1 ; 0 ; -; LEs in Long Chains - Fit Attempt 1 ; 0 ; -; LABs with Chains - Fit Attempt 1 ; 0 ; -; LABs with Multiple Chains - Fit Attempt 1 ; 0 ; -; Time - Fit Attempt 1 ; 0 ; -+------------------------------------------------------------------+------------+ - - -+--------------------------------------------------+ -; Advanced Data - Placement ; -+-------------------------------------+------------+ -; Name ; Value ; -+-------------------------------------+------------+ -; Auto Fit Point 2 - Fit Attempt 1 ; ff ; -; Auto Fit Point 5 - Fit Attempt 1 ; ff ; -; Mid Wire Use - Fit Attempt 1 ; 0 ; -; Mid Slack - Fit Attempt 1 ; 2147483639 ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 5 - Fit Attempt 1 ; ff ; -; Mid Wire Use - Fit Attempt 1 ; 0 ; -; Mid Slack - Fit Attempt 1 ; 2147483639 ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Auto Fit Point 6 - Fit Attempt 1 ; ff ; -; Late Wire Use - Fit Attempt 1 ; 0 ; -; Late Slack - Fit Attempt 1 ; 2147483639 ; -; Peak Regional Wire - Fit Attempt 1 ; 0.000 ; -; Auto Fit Point 7 - Fit Attempt 1 ; ff ; -; Time - Fit Attempt 1 ; 0 ; -; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016 ; -+-------------------------------------+------------+ - - -+--------------------------------------------------+ -; Advanced Data - Routing ; -+------------------------------------+-------------+ -; Name ; Value ; -+------------------------------------+-------------+ -; Early Slack - Fit Attempt 1 ; 2147483639 ; -; Early Wire Use - Fit Attempt 1 ; 0 ; -; Peak Regional Wire - Fit Attempt 1 ; 1 ; -; Mid Slack - Fit Attempt 1 ; 2147483639 ; -; Late Slack - Fit Attempt 1 ; -2147483648 ; -; Late Wire Use - Fit Attempt 1 ; 0 ; -; Time - Fit Attempt 1 ; 0 ; -+------------------------------------+-------------+ - - -+-----------------+ -; Fitter Messages ; -+-----------------+ -Info: ******************************************************************* -Info: Running Quartus II Fitter - Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Mon Mar 07 10:24:26 2022 -Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off triple_selector_8b -c triple_selector_8b -Info: Parallel compilation is enabled and will use 4 of the 4 processors detected -Info: Selected device EP2C8Q208C8 for design "triple_selector_8b" -Info: Low junction temperature is 0 degrees C -Info: High junction temperature is 85 degrees C -Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time -Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices - Info: Device EP2C5Q208C8 is compatible - Info: Device EP2C5Q208I8 is compatible - Info: Device EP2C8Q208I8 is compatible -Info: Fitter converted 3 user pins into dedicated programming pins - Info: Pin ~ASDO~ is reserved at location 1 - Info: Pin ~nCSO~ is reserved at location 2 - Info: Pin ~LVDS54p/nCEO~ is reserved at location 108 -Warning: No exact pin location assignment(s) for 35 pins of 35 total pins - Info: Pin Y0 not assigned to an exact location on the device - Info: Pin Y1 not assigned to an exact location on the device - Info: Pin Y2 not assigned to an exact location on the device - Info: Pin Y3 not assigned to an exact location on the device - Info: Pin Y4 not assigned to an exact location on the device - Info: Pin Y5 not assigned to an exact location on the device - Info: Pin Y6 not assigned to an exact location on the device - Info: Pin Y7 not assigned to an exact location on the device - Info: Pin B0 not assigned to an exact location on the device - Info: Pin A0 not assigned to an exact location on the device - Info: Pin AY not assigned to an exact location on the device - Info: Pin BY not assigned to an exact location on the device - Info: Pin C0 not assigned to an exact location on the device - Info: Pin CY not assigned to an exact location on the device - Info: Pin A1 not assigned to an exact location on the device - Info: Pin B1 not assigned to an exact location on the device - Info: Pin C1 not assigned to an exact location on the device - Info: Pin A2 not assigned to an exact location on the device - Info: Pin B2 not assigned to an exact location on the device - Info: Pin C2 not assigned to an exact location on the device - Info: Pin A3 not assigned to an exact location on the device - Info: Pin B3 not assigned to an exact location on the device - Info: Pin C3 not assigned to an exact location on the device - Info: Pin A4 not assigned to an exact location on the device - Info: Pin B4 not assigned to an exact location on the device - Info: Pin C4 not assigned to an exact location on the device - Info: Pin A5 not assigned to an exact location on the device - Info: Pin B5 not assigned to an exact location on the device - Info: Pin C5 not assigned to an exact location on the device - Info: Pin A6 not assigned to an exact location on the device - Info: Pin B6 not assigned to an exact location on the device - Info: Pin C6 not assigned to an exact location on the device - Info: Pin A7 not assigned to an exact location on the device - Info: Pin B7 not assigned to an exact location on the device - Info: Pin C7 not assigned to an exact location on the device -Info: Fitter is using the Classic Timing Analyzer -Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time. -Info: Starting register packing -Info: Finished register packing - Extra Info: No registers were packed into other blocks -Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement - Info: Number of I/O pins in group: 35 (unused VREF, 3.3V VCCIO, 27 input, 8 output, 0 bidirectional) - Info: I/O standards used: 3.3-V LVTTL. -Info: I/O bank details before I/O pin placement - Info: Statistics of I/O banks - Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available - Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available - Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available - Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available -Info: Fitter preparation operations ending: elapsed time is 00:00:00 -Info: Fitter placement preparation operations beginning -Info: Fitter placement preparation operations ending: elapsed time is 00:00:00 -Info: Fitter placement operations beginning -Info: Fitter placement was successful -Info: Fitter placement operations ending: elapsed time is 00:00:00 -Info: Fitter routing operations beginning -Info: Average interconnect usage is 0% of the available device resources - Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y10 to location X34_Y19 -Info: Fitter routing operations ending: elapsed time is 00:00:00 -Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. - Info: Optimizations that may affect the design's routability were skipped - Info: Optimizations that may affect the design's timing were skipped -Info: Started post-fitting delay annotation -Warning: Found 8 output pins without output pin load capacitance assignment - Info: Pin "Y0" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Y1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Y2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Y3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Y4" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Y5" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Y6" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis - Info: Pin "Y7" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis -Info: Delay annotation completed successfully -Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. -Info: Generated suppressed messages file D:/projects/quartus/triple_selector_8b/triple_selector_8b.fit.smsg -Info: Quartus II Fitter was successful. 0 errors, 3 warnings - Info: Peak virtual memory: 306 megabytes - Info: Processing ended: Mon Mar 07 10:24:27 2022 - Info: Elapsed time: 00:00:01 - Info: Total CPU time (on all processors): 00:00:01 - - -+----------------------------+ -; Fitter Suppressed Messages ; -+----------------------------+ -The suppressed messages can be found in D:/projects/quartus/triple_selector_8b/triple_selector_8b.fit.smsg. - - diff --git a/triple_selector_8b/triple_selector_8b.fit.smsg b/triple_selector_8b/triple_selector_8b.fit.smsg deleted file mode 100644 index 14764e7..0000000 --- a/triple_selector_8b/triple_selector_8b.fit.smsg +++ /dev/null @@ -1,6 +0,0 @@ -Extra Info: Performing register packing on registers with non-logic cell location assignments -Extra Info: Completed register packing on registers with non-logic cell location assignments -Extra Info: Started Fast Input/Output/OE register processing -Extra Info: Finished Fast Input/Output/OE register processing -Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density -Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/triple_selector_8b/triple_selector_8b.fit.summary b/triple_selector_8b/triple_selector_8b.fit.summary deleted file mode 100644 index e668314..0000000 --- a/triple_selector_8b/triple_selector_8b.fit.summary +++ /dev/null @@ -1,16 +0,0 @@ -Fitter Status : Successful - Mon Mar 07 10:24:27 2022 -Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition -Revision Name : triple_selector_8b -Top-level Entity Name : triple_selector_8b -Family : Cyclone II -Device : EP2C8Q208C8 -Timing Models : Final -Total logic elements : 16 / 8,256 ( < 1 % ) - Total combinational functions : 16 / 8,256 ( < 1 % ) - Dedicated logic registers : 0 / 8,256 ( 0 % ) -Total registers : 0 -Total pins : 35 / 138 ( 25 % ) -Total virtual pins : 0 -Total memory bits : 0 / 165,888 ( 0 % ) -Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % ) -Total PLLs : 0 / 2 ( 0 % ) diff --git a/triple_selector_8b/triple_selector_8b.flow.rpt b/triple_selector_8b/triple_selector_8b.flow.rpt deleted file mode 100644 index 6342bf2..0000000 --- a/triple_selector_8b/triple_selector_8b.flow.rpt +++ /dev/null @@ -1,120 +0,0 @@ -Flow report for triple_selector_8b -Mon Mar 07 10:24:29 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Flow Summary - 3. Flow Settings - 4. Flow Non-Default Global Settings - 5. Flow Elapsed Time - 6. Flow OS Summary - 7. Flow Log - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------------+ -; Flow Summary ; -+------------------------------------+----------------------------------------------+ -; Flow Status ; Successful - Mon Mar 07 10:24:29 2022 ; -; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; -; Revision Name ; triple_selector_8b ; -; Top-level Entity Name ; triple_selector_8b ; -; Family ; Cyclone II ; -; Device ; EP2C8Q208C8 ; -; Timing Models ; Final ; -; Met timing requirements ; Yes ; -; Total logic elements ; 16 / 8,256 ( < 1 % ) ; -; Total combinational functions ; 16 / 8,256 ( < 1 % ) ; -; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ; -; Total registers ; 0 ; -; Total pins ; 35 / 138 ( 25 % ) ; -; Total virtual pins ; 0 ; -; Total memory bits ; 0 / 165,888 ( 0 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; -; Total PLLs ; 0 / 2 ( 0 % ) ; -+------------------------------------+----------------------------------------------+ - - -+-----------------------------------------+ -; Flow Settings ; -+-------------------+---------------------+ -; Option ; Setting ; -+-------------------+---------------------+ -; Start date & time ; 03/07/2022 10:24:25 ; -; Main task ; Compilation ; -; Revision Name ; triple_selector_8b ; -+-------------------+---------------------+ - - -+---------------------------------------------------------------------------------------------------------------------+ -; Flow Non-Default Global Settings ; -+------------------------------------+---------------------------------+---------------+-------------+----------------+ -; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; -+------------------------------------+---------------------------------+---------------+-------------+----------------+ -; COMPILER_SIGNATURE_ID ; 220283517943889.164661986528660 ; -- ; -- ; -- ; -; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; -; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; -; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; -; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; -; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ; -+------------------------------------+---------------------------------+---------------+-------------+----------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Flow Elapsed Time ; -+-------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; -+-------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 245 MB ; 00:00:00 ; -; Fitter ; 00:00:01 ; 1.0 ; 306 MB ; 00:00:01 ; -; Assembler ; 00:00:01 ; 1.0 ; 242 MB ; 00:00:00 ; -; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 198 MB ; 00:00:00 ; -; Total ; 00:00:02 ; -- ; -- ; 00:00:01 ; -+-------------------------+--------------+-------------------------+---------------------+------------------------------------+ - - -+------------------------------------------------------------------------------------------+ -; Flow OS Summary ; -+-------------------------+------------------+---------------+------------+----------------+ -; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; -+-------------------------+------------------+---------------+------------+----------------+ -; Analysis & Synthesis ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; -; Fitter ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; -; Assembler ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; -; Classic Timing Analyzer ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ; -+-------------------------+------------------+---------------+------------+----------------+ - - ------------- -; Flow Log ; ------------- -quartus_map --read_settings_files=on --write_settings_files=off triple_selector_8b -c triple_selector_8b -quartus_fit --read_settings_files=off --write_settings_files=off triple_selector_8b -c triple_selector_8b -quartus_asm --read_settings_files=off --write_settings_files=off triple_selector_8b -c triple_selector_8b -quartus_tan --read_settings_files=off --write_settings_files=off triple_selector_8b -c triple_selector_8b --timing_analysis_only - - - diff --git a/triple_selector_8b/triple_selector_8b.map.rpt b/triple_selector_8b/triple_selector_8b.map.rpt deleted file mode 100644 index f157c1b..0000000 --- a/triple_selector_8b/triple_selector_8b.map.rpt +++ /dev/null @@ -1,218 +0,0 @@ -Analysis & Synthesis report for triple_selector_8b -Mon Mar 07 10:24:26 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Analysis & Synthesis Summary - 3. Analysis & Synthesis Settings - 4. Analysis & Synthesis Source Files Read - 5. Analysis & Synthesis Resource Usage Summary - 6. Analysis & Synthesis Resource Utilization by Entity - 7. General Register Statistics - 8. Analysis & Synthesis Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------------+ -; Analysis & Synthesis Summary ; -+------------------------------------+----------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Mon Mar 07 10:24:25 2022 ; -; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; -; Revision Name ; triple_selector_8b ; -; Top-level Entity Name ; triple_selector_8b ; -; Family ; Cyclone II ; -; Total logic elements ; 16 ; -; Total combinational functions ; 16 ; -; Dedicated logic registers ; 0 ; -; Total registers ; 0 ; -; Total pins ; 35 ; -; Total virtual pins ; 0 ; -; Total memory bits ; 0 ; -; Embedded Multiplier 9-bit elements ; 0 ; -; Total PLLs ; 0 ; -+------------------------------------+----------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Settings ; -+--------------------------------------------------------------+--------------------+--------------------+ -; Option ; Setting ; Default Value ; -+--------------------------------------------------------------+--------------------+--------------------+ -; Device ; EP2C8Q208C8 ; ; -; Top-level entity name ; triple_selector_8b ; triple_selector_8b ; -; Family name ; Cyclone II ; Stratix II ; -; Use Generated Physical Constraints File ; Off ; ; -; Use smart compilation ; Off ; Off ; -; Restructure Multiplexers ; Auto ; Auto ; -; Create Debugging Nodes for IP Cores ; Off ; Off ; -; Preserve fewer node names ; On ; On ; -; Disable OpenCore Plus hardware evaluation ; Off ; Off ; -; Verilog Version ; Verilog_2001 ; Verilog_2001 ; -; VHDL Version ; VHDL93 ; VHDL93 ; -; State Machine Processing ; Auto ; Auto ; -; Safe State Machine ; Off ; Off ; -; Extract Verilog State Machines ; On ; On ; -; Extract VHDL State Machines ; On ; On ; -; Ignore Verilog initial constructs ; Off ; Off ; -; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; -; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; -; Add Pass-Through Logic to Inferred RAMs ; On ; On ; -; Parallel Synthesis ; Off ; Off ; -; DSP Block Balancing ; Auto ; Auto ; -; NOT Gate Push-Back ; On ; On ; -; Power-Up Don't Care ; On ; On ; -; Remove Redundant Logic Cells ; Off ; Off ; -; Remove Duplicate Registers ; On ; On ; -; Ignore CARRY Buffers ; Off ; Off ; -; Ignore CASCADE Buffers ; Off ; Off ; -; Ignore GLOBAL Buffers ; Off ; Off ; -; Ignore ROW GLOBAL Buffers ; Off ; Off ; -; Ignore LCELL Buffers ; Off ; Off ; -; Ignore SOFT Buffers ; On ; On ; -; Limit AHDL Integers to 32 Bits ; Off ; Off ; -; Optimization Technique ; Balanced ; Balanced ; -; Carry Chain Length ; 70 ; 70 ; -; Auto Carry Chains ; On ; On ; -; Auto Open-Drain Pins ; On ; On ; -; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; -; Auto ROM Replacement ; On ; On ; -; Auto RAM Replacement ; On ; On ; -; Auto Shift Register Replacement ; Auto ; Auto ; -; Auto Clock Enable Replacement ; On ; On ; -; Strict RAM Replacement ; Off ; Off ; -; Allow Synchronous Control Signals ; On ; On ; -; Force Use of Synchronous Clear Signals ; Off ; Off ; -; Auto RAM to Logic Cell Conversion ; Off ; Off ; -; Auto Resource Sharing ; Off ; Off ; -; Allow Any RAM Size For Recognition ; Off ; Off ; -; Allow Any ROM Size For Recognition ; Off ; Off ; -; Allow Any Shift Register Size For Recognition ; Off ; Off ; -; Use LogicLock Constraints during Resource Balancing ; On ; On ; -; Ignore translate_off and synthesis_off directives ; Off ; Off ; -; Timing-Driven Synthesis ; Off ; Off ; -; Show Parameter Settings Tables in Synthesis Report ; On ; On ; -; Ignore Maximum Fan-Out Assignments ; Off ; Off ; -; Synchronization Register Chain Length ; 2 ; 2 ; -; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; -; HDL message level ; Level2 ; Level2 ; -; Suppress Register Optimization Related Messages ; Off ; Off ; -; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ; -; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; -; Clock MUX Protection ; On ; On ; -; Auto Gated Clock Conversion ; Off ; Off ; -; Block Design Naming ; Auto ; Auto ; -; SDC constraint protection ; Off ; Off ; -; Synthesis Effort ; Auto ; Auto ; -; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; -; Analysis & Synthesis Message Level ; Medium ; Medium ; -+--------------------------------------------------------------+--------------------+--------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; -+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+ -; triple_selector_8b.bdf ; yes ; User Block Diagram/Schematic File ; D:/projects/quartus/triple_selector_8b/triple_selector_8b.bdf ; -+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+ - - -+-----------------------------------------------------+ -; Analysis & Synthesis Resource Usage Summary ; -+---------------------------------------------+-------+ -; Resource ; Usage ; -+---------------------------------------------+-------+ -; Estimated Total logic elements ; 16 ; -; ; ; -; Total combinational functions ; 16 ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 8 ; -; -- 3 input functions ; 8 ; -; -- <=2 input functions ; 0 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 16 ; -; -- arithmetic mode ; 0 ; -; ; ; -; Total registers ; 0 ; -; -- Dedicated logic registers ; 0 ; -; -- I/O registers ; 0 ; -; ; ; -; I/O pins ; 35 ; -; Maximum fan-out node ; AY ; -; Maximum fan-out ; 8 ; -; Total fan-out ; 64 ; -; Average fan-out ; 1.25 ; -+---------------------------------------------+-------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Resource Utilization by Entity ; -+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ -; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; -+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ -; |triple_selector_8b ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 35 ; 0 ; |triple_selector_8b ; work ; -+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ -Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. - - -+------------------------------------------------------+ -; General Register Statistics ; -+----------------------------------------------+-------+ -; Statistic ; Value ; -+----------------------------------------------+-------+ -; Total registers ; 0 ; -; Number of registers using Synchronous Clear ; 0 ; -; Number of registers using Synchronous Load ; 0 ; -; Number of registers using Asynchronous Clear ; 0 ; -; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 0 ; -; Number of registers using Preset ; 0 ; -+----------------------------------------------+-------+ - - -+-------------------------------+ -; Analysis & Synthesis Messages ; -+-------------------------------+ -Info: ******************************************************************* -Info: Running Quartus II Analysis & Synthesis - Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Mon Mar 07 10:24:25 2022 -Info: Command: quartus_map --read_settings_files=on --write_settings_files=off triple_selector_8b -c triple_selector_8b -Info: Found 1 design units, including 1 entities, in source file triple_selector_8b.bdf - Info: Found entity 1: triple_selector_8b -Info: Elaborating entity "triple_selector_8b" for the top level hierarchy -Info: Implemented 51 device resources after synthesis - the final resource count might be different - Info: Implemented 27 input pins - Info: Implemented 8 output pins - Info: Implemented 16 logic cells -Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 249 megabytes - Info: Processing ended: Mon Mar 07 10:24:26 2022 - Info: Elapsed time: 00:00:01 - Info: Total CPU time (on all processors): 00:00:00 - - diff --git a/triple_selector_8b/triple_selector_8b.map.summary b/triple_selector_8b/triple_selector_8b.map.summary deleted file mode 100644 index 1508710..0000000 --- a/triple_selector_8b/triple_selector_8b.map.summary +++ /dev/null @@ -1,14 +0,0 @@ -Analysis & Synthesis Status : Successful - Mon Mar 07 10:24:25 2022 -Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition -Revision Name : triple_selector_8b -Top-level Entity Name : triple_selector_8b -Family : Cyclone II -Total logic elements : 16 - Total combinational functions : 16 - Dedicated logic registers : 0 -Total registers : 0 -Total pins : 35 -Total virtual pins : 0 -Total memory bits : 0 -Embedded Multiplier 9-bit elements : 0 -Total PLLs : 0 diff --git a/triple_selector_8b/triple_selector_8b.pin b/triple_selector_8b/triple_selector_8b.pin deleted file mode 100644 index 232228d..0000000 --- a/triple_selector_8b/triple_selector_8b.pin +++ /dev/null @@ -1,278 +0,0 @@ - -- Copyright (C) 1991-2009 Altera Corporation - -- Your use of Altera Corporation's design tools, logic functions - -- and other software and tools, and its AMPP partner logic - -- functions, and any output files from any of the foregoing - -- (including device programming or simulation files), and any - -- associated documentation or information are expressly subject - -- to the terms and conditions of the Altera Program License - -- Subscription Agreement, Altera MegaCore Function License - -- Agreement, or other applicable license agreement, including, - -- without limitation, that your use is for the sole purpose of - -- programming logic devices manufactured by Altera and sold by - -- Altera or its authorized distributors. Please refer to the - -- applicable agreement for further details. - -- - -- This is a Quartus II output file. It is for reporting purposes only, and is - -- not intended for use as a Quartus II input file. This file cannot be used - -- to make Quartus II pin assignments - for instructions on how to make pin - -- assignments, please see Quartus II help. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- NC : No Connect. This pin has no internal connection to the device. - -- DNU : Do Not Use. This pin MUST NOT be connected. - -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). - -- VCCIO : Dedicated power pin, which MUST be connected to VCC - -- of its bank. - -- Bank 1: 3.3V - -- Bank 2: 3.3V - -- Bank 3: 3.3V - -- Bank 4: 3.3V - -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. - -- It can also be used to report unused dedicated pins. The connection - -- on the board for unused dedicated pins depends on whether this will - -- be used in a future design. One example is device migration. When - -- using device migration, refer to the device pin-tables. If it is a - -- GND pin in the pin table or if it will not be used in a future design - -- for another purpose the it MUST be connected to GND. If it is an unused - -- dedicated pin, then it can be connected to a valid signal on the board - -- (low, high, or toggling) if that signal is required for a different - -- revision of the design. - -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. - -- This pin should be connected to GND. It may also be connected to a - -- valid signal on the board (low, high, or toggling) if that signal - -- is required for a different revision of the design. - -- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17), - -- connect each pin marked GND* either individually through a 10k Ohm resistor - -- to GND or tie all pins together and connect through a single 10k Ohm resistor - -- to GND. - -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND - -- or leave it unconnected. - -- RESERVED : Unused I/O pin, which MUST be left unconnected. - -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. - -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. - -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. - -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- Pin directions (input, output or bidir) are based on device operating in user mode. - --------------------------------------------------------------------------------- - -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition -CHIP "triple_selector_8b" ASSIGNED TO AN: EP2C8Q208C8 - -Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment -------------------------------------------------------------------------------------------------------------- -~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVTTL : : 1 : N -~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVTTL : : 1 : N -GND* : 3 : : : : 1 : -GND* : 4 : : : : 1 : -GND* : 5 : : : : 1 : -GND* : 6 : : : : 1 : -VCCIO1 : 7 : power : : 3.3V : 1 : -GND* : 8 : : : : 1 : -GND : 9 : gnd : : : : -GND* : 10 : : : : 1 : -GND* : 11 : : : : 1 : -GND* : 12 : : : : 1 : -GND* : 13 : : : : 1 : -GND* : 14 : : : : 1 : -Y1 : 15 : output : 3.3-V LVTTL : : 1 : N -TDO : 16 : output : : : 1 : -TMS : 17 : input : : : 1 : -TCK : 18 : input : : : 1 : -TDI : 19 : input : : : 1 : -DATA0 : 20 : input : : : 1 : -DCLK : 21 : : : : 1 : -nCE : 22 : : : : 1 : -GND+ : 23 : : : : 1 : -GND+ : 24 : : : : 1 : -GND : 25 : gnd : : : : -nCONFIG : 26 : : : : 1 : -GND+ : 27 : : : : 1 : -GND+ : 28 : : : : 1 : -VCCIO1 : 29 : power : : 3.3V : 1 : -Y6 : 30 : output : 3.3-V LVTTL : : 1 : N -BY : 31 : input : 3.3-V LVTTL : : 1 : N -VCCINT : 32 : power : : 1.2V : : -GND* : 33 : : : : 1 : -Y5 : 34 : output : 3.3-V LVTTL : : 1 : N -GND* : 35 : : : : 1 : -GND : 36 : gnd : : : : -GND* : 37 : : : : 1 : -GND : 38 : gnd : : : : -GND* : 39 : : : : 1 : -GND* : 40 : : : : 1 : -GND* : 41 : : : : 1 : -VCCIO1 : 42 : power : : 3.3V : 1 : -GND* : 43 : : : : 1 : -GND* : 44 : : : : 1 : -GND* : 45 : : : : 1 : -GND* : 46 : : : : 1 : -GND* : 47 : : : : 1 : -GND* : 48 : : : : 1 : -GND : 49 : gnd : : : : -GND_PLL1 : 50 : gnd : : : : -VCCD_PLL1 : 51 : power : : 1.2V : : -GND_PLL1 : 52 : gnd : : : : -VCCA_PLL1 : 53 : power : : 1.2V : : -GNDA_PLL1 : 54 : gnd : : : : -GND : 55 : gnd : : : : -GND* : 56 : : : : 4 : -GND* : 57 : : : : 4 : -GND* : 58 : : : : 4 : -GND* : 59 : : : : 4 : -GND* : 60 : : : : 4 : -GND* : 61 : : : : 4 : -VCCIO4 : 62 : power : : 3.3V : 4 : -GND* : 63 : : : : 4 : -GND* : 64 : : : : 4 : -GND : 65 : gnd : : : : -VCCINT : 66 : power : : 1.2V : : -GND* : 67 : : : : 4 : -GND* : 68 : : : : 4 : -GND* : 69 : : : : 4 : -GND* : 70 : : : : 4 : -VCCIO4 : 71 : power : : 3.3V : 4 : -GND* : 72 : : : : 4 : -GND : 73 : gnd : : : : -GND* : 74 : : : : 4 : -GND* : 75 : : : : 4 : -GND* : 76 : : : : 4 : -GND* : 77 : : : : 4 : -GND : 78 : gnd : : : : -VCCINT : 79 : power : : 1.2V : : -GND* : 80 : : : : 4 : -GND* : 81 : : : : 4 : -GND* : 82 : : : : 4 : -VCCIO4 : 83 : power : : 3.3V : 4 : -GND* : 84 : : : : 4 : -GND : 85 : gnd : : : : -GND* : 86 : : : : 4 : -Y2 : 87 : output : 3.3-V LVTTL : : 4 : N -GND* : 88 : : : : 4 : -GND* : 89 : : : : 4 : -GND* : 90 : : : : 4 : -VCCIO4 : 91 : power : : 3.3V : 4 : -GND* : 92 : : : : 4 : -GND : 93 : gnd : : : : -GND* : 94 : : : : 4 : -GND* : 95 : : : : 4 : -GND* : 96 : : : : 4 : -GND* : 97 : : : : 4 : -VCCIO4 : 98 : power : : 3.3V : 4 : -GND* : 99 : : : : 4 : -GND : 100 : gnd : : : : -GND* : 101 : : : : 4 : -Y3 : 102 : output : 3.3-V LVTTL : : 4 : N -A1 : 103 : input : 3.3-V LVTTL : : 4 : N -GND* : 104 : : : : 4 : -B2 : 105 : input : 3.3-V LVTTL : : 3 : N -GND* : 106 : : : : 3 : -Y0 : 107 : output : 3.3-V LVTTL : : 3 : N -~LVDS54p/nCEO~ : 108 : output : 3.3-V LVTTL : : 3 : N -VCCIO3 : 109 : power : : 3.3V : 3 : -A0 : 110 : input : 3.3-V LVTTL : : 3 : N -GND : 111 : gnd : : : : -C6 : 112 : input : 3.3-V LVTTL : : 3 : N -C2 : 113 : input : 3.3-V LVTTL : : 3 : N -C4 : 114 : input : 3.3-V LVTTL : : 3 : N -B6 : 115 : input : 3.3-V LVTTL : : 3 : N -C0 : 116 : input : 3.3-V LVTTL : : 3 : N -Y4 : 117 : output : 3.3-V LVTTL : : 3 : N -C7 : 118 : input : 3.3-V LVTTL : : 3 : N -GND : 119 : gnd : : : : -VCCINT : 120 : power : : 1.2V : : -nSTATUS : 121 : : : : 3 : -VCCIO3 : 122 : power : : 3.3V : 3 : -CONF_DONE : 123 : : : : 3 : -GND : 124 : gnd : : : : -MSEL1 : 125 : : : : 3 : -MSEL0 : 126 : : : : 3 : -AY : 127 : input : 3.3-V LVTTL : : 3 : N -B4 : 128 : input : 3.3-V LVTTL : : 3 : N -A3 : 129 : input : 3.3-V LVTTL : : 3 : N -B3 : 130 : input : 3.3-V LVTTL : : 3 : N -C3 : 131 : input : 3.3-V LVTTL : : 3 : N -A4 : 132 : input : 3.3-V LVTTL : : 3 : N -B7 : 133 : input : 3.3-V LVTTL : : 3 : N -B1 : 134 : input : 3.3-V LVTTL : : 3 : N -A7 : 135 : input : 3.3-V LVTTL : : 3 : N -VCCIO3 : 136 : power : : 3.3V : 3 : -A6 : 137 : input : 3.3-V LVTTL : : 3 : N -B0 : 138 : input : 3.3-V LVTTL : : 3 : N -C1 : 139 : input : 3.3-V LVTTL : : 3 : N -GND : 140 : gnd : : : : -A2 : 141 : input : 3.3-V LVTTL : : 3 : N -CY : 142 : input : 3.3-V LVTTL : : 3 : N -A5 : 143 : input : 3.3-V LVTTL : : 3 : N -B5 : 144 : input : 3.3-V LVTTL : : 3 : N -C5 : 145 : input : 3.3-V LVTTL : : 3 : N -GND* : 146 : : : : 3 : -GND* : 147 : : : : 3 : -VCCIO3 : 148 : power : : 3.3V : 3 : -GND* : 149 : : : : 3 : -GND* : 150 : : : : 3 : -GND* : 151 : : : : 3 : -GND* : 152 : : : : 3 : -GND : 153 : gnd : : : : -GND_PLL2 : 154 : gnd : : : : -VCCD_PLL2 : 155 : power : : 1.2V : : -GND_PLL2 : 156 : gnd : : : : -VCCA_PLL2 : 157 : power : : 1.2V : : -GNDA_PLL2 : 158 : gnd : : : : -GND : 159 : gnd : : : : -GND* : 160 : : : : 2 : -GND* : 161 : : : : 2 : -GND* : 162 : : : : 2 : -GND* : 163 : : : : 2 : -GND* : 164 : : : : 2 : -GND* : 165 : : : : 2 : -VCCIO2 : 166 : power : : 3.3V : 2 : -GND : 167 : gnd : : : : -GND* : 168 : : : : 2 : -GND* : 169 : : : : 2 : -GND* : 170 : : : : 2 : -Y7 : 171 : output : 3.3-V LVTTL : : 2 : N -VCCIO2 : 172 : power : : 3.3V : 2 : -GND* : 173 : : : : 2 : -GND : 174 : gnd : : : : -GND* : 175 : : : : 2 : -GND* : 176 : : : : 2 : -GND : 177 : gnd : : : : -VCCINT : 178 : power : : 1.2V : : -GND* : 179 : : : : 2 : -GND* : 180 : : : : 2 : -GND* : 181 : : : : 2 : -GND* : 182 : : : : 2 : -VCCIO2 : 183 : power : : 3.3V : 2 : -GND : 184 : gnd : : : : -GND* : 185 : : : : 2 : -GND : 186 : gnd : : : : -GND* : 187 : : : : 2 : -GND* : 188 : : : : 2 : -GND* : 189 : : : : 2 : -VCCINT : 190 : power : : 1.2V : : -GND* : 191 : : : : 2 : -GND* : 192 : : : : 2 : -GND* : 193 : : : : 2 : -VCCIO2 : 194 : power : : 3.3V : 2 : -GND* : 195 : : : : 2 : -GND : 196 : gnd : : : : -GND* : 197 : : : : 2 : -GND* : 198 : : : : 2 : -GND* : 199 : : : : 2 : -GND* : 200 : : : : 2 : -GND* : 201 : : : : 2 : -VCCIO2 : 202 : power : : 3.3V : 2 : -GND* : 203 : : : : 2 : -GND : 204 : gnd : : : : -GND* : 205 : : : : 2 : -GND* : 206 : : : : 2 : -GND* : 207 : : : : 2 : -GND* : 208 : : : : 2 : diff --git a/triple_selector_8b/triple_selector_8b.pof b/triple_selector_8b/triple_selector_8b.pof deleted file mode 100644 index 1be1781..0000000 Binary files a/triple_selector_8b/triple_selector_8b.pof and /dev/null differ diff --git a/triple_selector_8b/triple_selector_8b.qws b/triple_selector_8b/triple_selector_8b.qws deleted file mode 100644 index 7891c27..0000000 --- a/triple_selector_8b/triple_selector_8b.qws +++ /dev/null @@ -1,14 +0,0 @@ -[ProjectWorkspace] -ptn_Child1=Frames -[ProjectWorkspace.Frames] -ptn_Child1=ChildFrames -[ProjectWorkspace.Frames.ChildFrames] -ptn_Child1=Document-0 -[ProjectWorkspace.Frames.ChildFrames.Document-0] -ptn_Child1=ViewFrame-0 -[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0] -DocPathName=triple_selector_8b.bdf -DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde} -IsChildFrameDetached=False -IsActiveChildFrame=True -ptn_Child1=StateMap diff --git a/triple_selector_8b/triple_selector_8b.sof b/triple_selector_8b/triple_selector_8b.sof deleted file mode 100644 index 17bc883..0000000 Binary files a/triple_selector_8b/triple_selector_8b.sof and /dev/null differ diff --git a/triple_selector_8b/triple_selector_8b.tan.rpt b/triple_selector_8b/triple_selector_8b.tan.rpt deleted file mode 100644 index 855cc3e..0000000 --- a/triple_selector_8b/triple_selector_8b.tan.rpt +++ /dev/null @@ -1,174 +0,0 @@ -Classic Timing Analyzer report for triple_selector_8b -Mon Mar 07 10:24:29 2022 -Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Timing Analyzer Summary - 3. Timing Analyzer Settings - 4. Parallel Compilation - 5. tpd - 6. Timing Analyzer Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------------------------------------------------+ -; Timing Analyzer Summary ; -+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ -; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; -+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ -; Worst-case tpd ; N/A ; None ; 16.101 ns ; BY ; Y6 ; -- ; -- ; 0 ; -; Total number of failed paths ; ; ; ; ; ; ; ; 0 ; -+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ - - -+--------------------------------------------------------------------------------------------------------------------+ -; Timing Analyzer Settings ; -+---------------------------------------------------------------------+--------------------+------+----+-------------+ -; Option ; Setting ; From ; To ; Entity Name ; -+---------------------------------------------------------------------+--------------------+------+----+-------------+ -; Device Name ; EP2C8Q208C8 ; ; ; ; -; Timing Models ; Final ; ; ; ; -; Default hold multicycle ; Same as Multicycle ; ; ; ; -; Cut paths between unrelated clock domains ; On ; ; ; ; -; Cut off read during write signal paths ; On ; ; ; ; -; Cut off feedback from I/O pins ; On ; ; ; ; -; Report Combined Fast/Slow Timing ; Off ; ; ; ; -; Ignore Clock Settings ; Off ; ; ; ; -; Analyze latches as synchronous elements ; On ; ; ; ; -; Enable Recovery/Removal analysis ; Off ; ; ; ; -; Enable Clock Latency ; Off ; ; ; ; -; Use TimeQuest Timing Analyzer ; Off ; ; ; ; -; Minimum Core Junction Temperature ; 0 ; ; ; ; -; Maximum Core Junction Temperature ; 85 ; ; ; ; -; Number of source nodes to report per destination node ; 10 ; ; ; ; -; Number of destination nodes to report ; 10 ; ; ; ; -; Number of paths to report ; 200 ; ; ; ; -; Report Minimum Timing Checks ; Off ; ; ; ; -; Use Fast Timing Models ; Off ; ; ; ; -; Report IO Paths Separately ; Off ; ; ; ; -; Perform Multicorner Analysis ; On ; ; ; ; -; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ; -; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ; -; Output I/O Timing Endpoint ; Near End ; ; ; ; -+---------------------------------------------------------------------+--------------------+------+----+-------------+ - - -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 4 ; -; Maximum allowed ; 4 ; -; ; ; -; Average used ; 1.00 ; -; Maximum used ; 1 ; -; ; ; -; Usage by Processor ; % Time Used ; -; 1 processor ; 100.0% ; -; 2-4 processors ; 0.0% ; -+----------------------------+-------------+ - - -+---------------------------------------------------------+ -; tpd ; -+-------+-------------------+-----------------+------+----+ -; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ; -+-------+-------------------+-----------------+------+----+ -; N/A ; None ; 16.101 ns ; BY ; Y6 ; -; N/A ; None ; 15.802 ns ; AY ; Y6 ; -; N/A ; None ; 15.533 ns ; BY ; Y5 ; -; N/A ; None ; 15.448 ns ; BY ; Y1 ; -; N/A ; None ; 15.059 ns ; BY ; Y2 ; -; N/A ; None ; 15.018 ns ; B6 ; Y6 ; -; N/A ; None ; 14.809 ns ; A1 ; Y1 ; -; N/A ; None ; 14.793 ns ; B2 ; Y2 ; -; N/A ; None ; 14.673 ns ; BY ; Y3 ; -; N/A ; None ; 14.653 ns ; BY ; Y0 ; -; N/A ; None ; 14.271 ns ; BY ; Y7 ; -; N/A ; None ; 14.263 ns ; B5 ; Y5 ; -; N/A ; None ; 14.243 ns ; C6 ; Y6 ; -; N/A ; None ; 14.234 ns ; AY ; Y5 ; -; N/A ; None ; 14.152 ns ; AY ; Y1 ; -; N/A ; None ; 14.062 ns ; A5 ; Y5 ; -; N/A ; None ; 13.973 ns ; A6 ; Y6 ; -; N/A ; None ; 13.949 ns ; CY ; Y6 ; -; N/A ; None ; 13.897 ns ; A0 ; Y0 ; -; N/A ; None ; 13.829 ns ; BY ; Y4 ; -; N/A ; None ; 13.768 ns ; AY ; Y2 ; -; N/A ; None ; 13.685 ns ; CY ; Y5 ; -; N/A ; None ; 13.662 ns ; A2 ; Y2 ; -; N/A ; None ; 13.484 ns ; C2 ; Y2 ; -; N/A ; None ; 13.409 ns ; B1 ; Y1 ; -; N/A ; None ; 13.376 ns ; AY ; Y3 ; -; N/A ; None ; 13.362 ns ; AY ; Y0 ; -; N/A ; None ; 13.348 ns ; B0 ; Y0 ; -; N/A ; None ; 13.191 ns ; CY ; Y2 ; -; N/A ; None ; 13.149 ns ; C5 ; Y5 ; -; N/A ; None ; 12.995 ns ; CY ; Y1 ; -; N/A ; None ; 12.981 ns ; AY ; Y7 ; -; N/A ; None ; 12.730 ns ; C1 ; Y1 ; -; N/A ; None ; 12.665 ns ; C7 ; Y7 ; -; N/A ; None ; 12.656 ns ; A7 ; Y7 ; -; N/A ; None ; 12.630 ns ; B4 ; Y4 ; -; N/A ; None ; 12.565 ns ; B7 ; Y7 ; -; N/A ; None ; 12.532 ns ; AY ; Y4 ; -; N/A ; None ; 12.414 ns ; CY ; Y7 ; -; N/A ; None ; 12.344 ns ; C0 ; Y0 ; -; N/A ; None ; 12.325 ns ; C4 ; Y4 ; -; N/A ; None ; 12.158 ns ; CY ; Y3 ; -; N/A ; None ; 12.140 ns ; CY ; Y0 ; -; N/A ; None ; 11.975 ns ; CY ; Y4 ; -; N/A ; None ; 9.351 ns ; A3 ; Y3 ; -; N/A ; None ; 8.853 ns ; B3 ; Y3 ; -; N/A ; None ; 8.008 ns ; A4 ; Y4 ; -; N/A ; None ; 7.755 ns ; C3 ; Y3 ; -+-------+-------------------+-----------------+------+----+ - - -+--------------------------+ -; Timing Analyzer Messages ; -+--------------------------+ -Info: ******************************************************************* -Info: Running Quartus II Classic Timing Analyzer - Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition - Info: Processing started: Mon Mar 07 10:24:29 2022 -Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off triple_selector_8b -c triple_selector_8b --timing_analysis_only -Info: Parallel compilation is enabled and will use 4 of the 4 processors detected -Info: Longest tpd from source pin "BY" to destination pin "Y6" is 16.101 ns - Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_31; Fanout = 8; PIN Node = 'BY' - Info: 2: + IC(6.949 ns) + CELL(0.651 ns) = 8.585 ns; Loc. = LCCOMB_X33_Y11_N0; Fanout = 1; COMB Node = 'inst27~0' - Info: 3: + IC(0.366 ns) + CELL(0.624 ns) = 9.575 ns; Loc. = LCCOMB_X33_Y11_N10; Fanout = 1; COMB Node = 'inst27' - Info: 4: + IC(3.430 ns) + CELL(3.096 ns) = 16.101 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'Y6' - Info: Total cell delay = 5.356 ns ( 33.27 % ) - Info: Total interconnect delay = 10.745 ns ( 66.73 % ) -Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 212 megabytes - Info: Processing ended: Mon Mar 07 10:24:29 2022 - Info: Elapsed time: 00:00:00 - Info: Total CPU time (on all processors): 00:00:00 - - diff --git a/triple_selector_8b/triple_selector_8b.tan.summary b/triple_selector_8b/triple_selector_8b.tan.summary deleted file mode 100644 index 2cad432..0000000 --- a/triple_selector_8b/triple_selector_8b.tan.summary +++ /dev/null @@ -1,26 +0,0 @@ --------------------------------------------------------------------------------------- -Timing Analyzer Summary --------------------------------------------------------------------------------------- - -Type : Worst-case tpd -Slack : N/A -Required Time : None -Actual Time : 16.101 ns -From : BY -To : Y6 -From Clock : -- -To Clock : -- -Failed Paths : 0 - -Type : Total number of failed paths -Slack : -Required Time : -Actual Time : -From : -To : -From Clock : -To Clock : -Failed Paths : 0 - --------------------------------------------------------------------------------------- -