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add test_ALU

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juzeon
2022-05-17 16:23:11 +08:00
parent a03243f73f
commit c2af9395e3
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test_ALU/38_decoder.bdf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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106
test_ALU/38_decoder.bsf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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3658
test_ALU/ALU_3_in_1.bdf Normal file
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274
test_ALU/ALU_3_in_1.bsf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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2046
test_ALU/ALU_parallel_8b.bdf Normal file
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246
test_ALU/ALU_parallel_8b.bsf Normal file
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@@ -0,0 +1,246 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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(line (pt 192 88)(pt 192 72)(line_width 1))
)
(port
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)
)

1791
test_ALU/double_selector_8b.bdf Normal file
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211
test_ALU/double_selector_8b.bsf Normal file
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@@ -0,0 +1,211 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
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(text "double_selector_8b" (rect 5 0 117 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 336 25 348)(font "Arial" ))
(port
(pt 0 144)
(input)
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(text "a0" (rect 21 136 35 150)(font "Arial" (font_size 8)))
(line (pt 0 144)(pt 16 144)(line_width 1))
)
(port
(pt 0 128)
(input)
(text "a1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "a1" (rect 21 120 35 134)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 16 128)(line_width 1))
)
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(text "a2" (rect 21 104 35 118)(font "Arial" (font_size 8)))
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)
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)
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(text "a4" (rect 21 72 35 86)(font "Arial" (font_size 8)))
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)
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)
)

273
test_ALU/nano_selector.bdf Normal file
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@@ -0,0 +1,273 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
//#pragma file_not_in_maxplusii_format
(header "graphic" (version "1.3"))
(pin
(input)
(rect 360 176 528 192)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "A" (rect 5 0 12 12)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 92 12)(pt 117 12)(line_width 1))
(line (pt 92 4)(pt 117 4)(line_width 1))
(line (pt 121 8)(pt 168 8)(line_width 1))
(line (pt 92 12)(pt 92 4)(line_width 1))
(line (pt 117 4)(pt 121 8)(line_width 1))
(line (pt 117 12)(pt 121 8)(line_width 1))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
)
(pin
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(rect 360 208 528 224)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
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(pt 168 8)
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(line (pt 117 12)(pt 121 8)(line_width 1))
)
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)
(pin
(input)
(rect 360 240 528 256)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "A_EN" (rect 5 0 33 12)(font "Arial" ))
(pt 168 8)
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(line (pt 92 12)(pt 117 12)(line_width 1))
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(line (pt 117 12)(pt 121 8)(line_width 1))
)
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
)
(pin
(output)
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(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "Q" (rect 90 0 98 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8)(line_width 1))
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(line (pt 82 8)(pt 78 12)(line_width 1))
(line (pt 78 12)(pt 82 8)(line_width 1))
)
)
(symbol
(rect 560 232 608 264)
(text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6)))
(text "inst" (rect 3 21 20 33)(font "Arial" ))
(port
(pt 0 16)
(input)
(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 13 16)(line_width 1))
)
(port
(pt 48 16)
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(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
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)
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(line (pt 13 7)(pt 31 16)(line_width 1))
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(circle (rect 31 12 39 20)(line_width 1))
)
)
(symbol
(rect 640 128 704 176)
(text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
(text "inst3" (rect 3 37 26 49)(font "Arial" ))
(port
(pt 0 16)
(input)
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
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(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
(line (pt 0 32)(pt 14 32)(line_width 1))
)
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)
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(line (pt 14 37)(pt 31 37)(line_width 1))
(line (pt 14 12)(pt 14 37)(line_width 1))
(arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)(line_width 1))
)
)
(symbol
(rect 640 184 704 232)
(text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
(text "inst4" (rect 3 37 26 49)(font "Arial" ))
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(line (pt 0 16)(pt 14 16)(line_width 1))
)
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)
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(rect 736 136 800 184)
(text "OR2" (rect 1 0 19 10)(font "Arial" (font_size 6)))
(text "inst5" (rect 3 37 26 49)(font "Arial" ))
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)
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)
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)
)
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(pt 528 216)
(pt 640 216)
)
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)
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)
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57
test_ALU/nano_selector.bsf Normal file
View File

@@ -0,0 +1,57 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 112 112)
(text "nano_selector" (rect 5 0 86 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 80 25 92)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "A" (rect 0 0 9 14)(font "Arial" (font_size 8)))
(text "A" (rect 21 27 30 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "B" (rect 0 0 8 14)(font "Arial" (font_size 8)))
(text "B" (rect 21 43 29 57)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "A_EN" (rect 0 0 31 14)(font "Arial" (font_size 8)))
(text "A_EN" (rect 21 59 52 73)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 96 32)
(output)
(text "Q" (rect 0 0 9 14)(font "Arial" (font_size 8)))
(text "Q" (rect 66 27 75 41)(font "Arial" (font_size 8)))
(line (pt 96 32)(pt 80 32)(line_width 1))
)
(drawing
(rectangle (rect 16 16 80 80)(line_width 1))
)
)

1004
test_ALU/register_8b.bdf Normal file
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155
test_ALU/register_8b.bsf Normal file
View File

@@ -0,0 +1,155 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
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1077
test_ALU/shifter_8b.bdf Normal file
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183
test_ALU/shifter_8b.bsf Normal file
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@@ -0,0 +1,183 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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975
test_ALU/test_ALU.bdf Normal file
View File

@@ -0,0 +1,975 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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12
test_ALU/test_ALU.dpf Normal file
View File

@@ -0,0 +1,12 @@
<?xml version="1.0" encoding="UTF-8"?>
<pin_planner>
<pin_info>
</pin_info>
<buses>
</buses>
<group_file_association>
</group_file_association>
<pin_planner_file_specifies>
</pin_planner_file_specifies>
</pin_planner>

30
test_ALU/test_ALU.qpf Normal file
View File

@@ -0,0 +1,30 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 16:09:17 May 17, 2022
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "9.0"
DATE = "16:09:17 May 17, 2022"
# Revisions
PROJECT_REVISION = "test_ALU"

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test_ALU/test_ALU.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 16:09:17 May 17, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# test_ALU_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C8Q208C8
set_global_assignment -name TOP_LEVEL_ENTITY test_ALU
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:09:17 MAY 17, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name BDF_FILE test_ALU.bdf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_67 -to A0
set_location_assignment PIN_68 -to A1
set_location_assignment PIN_69 -to A2
set_location_assignment PIN_70 -to A3
set_location_assignment PIN_72 -to A4
set_location_assignment PIN_74 -to A5
set_location_assignment PIN_75 -to A6
set_location_assignment PIN_76 -to A7
set_location_assignment PIN_23 -to B0
set_location_assignment PIN_24 -to B1
set_location_assignment PIN_27 -to B2
set_location_assignment PIN_28 -to B3
set_location_assignment PIN_208 -to B4
set_location_assignment PIN_129 -to B5
set_location_assignment PIN_130 -to B6
set_location_assignment PIN_107 -to B7
set_location_assignment PIN_77 -to CP_A
set_location_assignment PIN_80 -to CP_B
set_location_assignment PIN_81 -to CP_Z
set_location_assignment PIN_82 -to CLR
set_location_assignment PIN_142 -to FLG_C
set_location_assignment PIN_143 -to FLG_V
set_location_assignment PIN_144 -to FLG_N
set_location_assignment PIN_145 -to FLG_Z
set_location_assignment PIN_151 -to Q0
set_location_assignment PIN_152 -to Q1
set_location_assignment PIN_160 -to Q2
set_location_assignment PIN_161 -to Q3
set_location_assignment PIN_162 -to Q4
set_location_assignment PIN_163 -to Q5
set_location_assignment PIN_164 -to Q6
set_location_assignment PIN_165 -to Q7
set_location_assignment PIN_84 -to S0
set_location_assignment PIN_86 -to S1
set_location_assignment PIN_87 -to S2

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test_ALU/triple_selector_8b.bdf Normal file
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test_ALU/triple_selector_8b.bsf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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