diff --git a/README.md b/README.md
index 57d4cc8..5aa7cad 100644
--- a/README.md
+++ b/README.md
@@ -6,10 +6,28 @@
8位加法计算器。
-### data_selector
+```
+K0~K7: A0~A7
+K8~K15: B0~B7
+K16: CI
+LR0~LR7: S0~S7
+LR8: CO
+```
+
+### double_selector_8b
8位数据选择器（二选一）。
+引脚分配：
+
+```
+K0~K7: a0~a7
+K8~K15: b0~b7
+K16: AY
+K17: BY
+LR0~LR7: Y0~Y7
+```
+
### register_8b
8位寄存器。
diff --git a/adder_8b/adder_8b.asm.rpt b/adder_8b/adder_8b.asm.rpt
index 5f7ceaf..0389a29 100644
--- a/adder_8b/adder_8b.asm.rpt
+++ b/adder_8b/adder_8b.asm.rpt
@@ -1,5 +1,5 @@
Assembler report for adder_8b
-Mon Mar 07 10:22:24 2022
+Mon Mar 07 11:28:58 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@@ -38,7 +38,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Mon Mar 07 10:22:24 2022 ;
+; Assembler Status ; Successful - Mon Mar 07 11:28:58 2022 ;
; Revision Name ; adder_8b ;
; Top-level Entity Name ; adder_8b ;
; Family ; Cyclone II ;
@@ -93,7 +93,7 @@ applicable agreement for further details.
+----------------+----------------------------------------------------+
; Device ; EP2C8Q208C8 ;
; JTAG usercode ; 0xFFFFFFFF ;
-; Checksum ; 0x000C8655 ;
+; Checksum ; 0x000C3C8E ;
+----------------+----------------------------------------------------+
@@ -104,7 +104,7 @@ applicable agreement for further details.
+--------------------+------------------------------------------------+
; Device ; EPCS4 ;
; JTAG usercode ; 0x00000000 ;
-; Checksum ; 0x06F061B0 ;
+; Checksum ; 0x06EFBA32 ;
; Compression Ratio ; 3 ;
+--------------------+------------------------------------------------+
@@ -115,14 +115,14 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
- Info: Processing started: Mon Mar 07 10:22:24 2022
+ Info: Processing started: Mon Mar 07 11:28:58 2022
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b
Info: Writing out detailed assembly data for power analysis
Info: Assembler is generating device programming files
Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 242 megabytes
- Info: Processing ended: Mon Mar 07 10:22:24 2022
+ Info: Processing ended: Mon Mar 07 11:28:58 2022
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00
diff --git a/adder_8b/adder_8b.done b/adder_8b/adder_8b.done
index 13ed4d3..c3c07d5 100644
--- a/adder_8b/adder_8b.done
+++ b/adder_8b/adder_8b.done
@@ -1 +1 @@
-Mon Mar 07 10:22:26 2022
+Mon Mar 07 11:29:00 2022
diff --git a/data_selector/data_selector.dpf b/adder_8b/adder_8b.dpf
similarity index 100%
rename from data_selector/data_selector.dpf
rename to adder_8b/adder_8b.dpf
diff --git a/adder_8b/adder_8b.fit.rpt b/adder_8b/adder_8b.fit.rpt
index 5b7f598..c079c15 100644
--- a/adder_8b/adder_8b.fit.rpt
+++ b/adder_8b/adder_8b.fit.rpt
@@ -1,5 +1,5 @@
Fitter report for adder_8b
-Mon Mar 07 10:22:23 2022
+Mon Mar 07 11:28:57 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@@ -63,7 +63,7 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+----------------------------------------------+
-; Fitter Status ; Successful - Mon Mar 07 10:22:23 2022 ;
+; Fitter Status ; Successful - Mon Mar 07 11:28:57 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; adder_8b ;
; Top-level Entity Name ; adder_8b ;
@@ -91,6 +91,7 @@ applicable agreement for further details.
; Minimum Core Junction Temperature ; 0 ; ;
; Maximum Core Junction Temperature ; 85 ; ;
; Fit Attempts to Skip ; 0 ; 0.0 ;
+; Device I/O Standard ; 3.3-V LVTTL ; ;
; Use smart compilation ; Off ; Off ;
; Use TimeQuest Timing Analyzer ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
@@ -216,7 +217,7 @@ The pin-out file can be found in D:/projects/quartus/adder_8b/adder_8b.pin.
; User inserted logic elements ; 0 ;
; Virtual pins ; 0 ;
; I/O pins ; 26 / 138 ( 19 % ) ;
-; -- Clock pins ; 2 / 4 ( 50 % ) ;
+; -- Clock pins ; 1 / 4 ( 25 % ) ;
; Global signals ; 0 ;
; M4Ks ; 0 / 36 ( 0 % ) ;
; Total block memory bits ; 0 / 165,888 ( 0 % ) ;
@@ -245,23 +246,23 @@ The pin-out file can be found in D:/projects/quartus/adder_8b/adder_8b.pin.
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
-; A0 ; 24 ; 1 ; 0 ; 9 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; A1 ; 57 ; 4 ; 1 ; 0 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; A2 ; 23 ; 1 ; 0 ; 9 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; A3 ; 40 ; 1 ; 0 ; 5 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; A4 ; 41 ; 1 ; 0 ; 4 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; A5 ; 150 ; 3 ; 34 ; 16 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; A6 ; 13 ; 1 ; 0 ; 16 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; A7 ; 5 ; 1 ; 0 ; 17 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; B0 ; 28 ; 1 ; 0 ; 9 ; 3 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; B1 ; 60 ; 4 ; 3 ; 0 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; B2 ; 30 ; 1 ; 0 ; 8 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; B3 ; 39 ; 1 ; 0 ; 5 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; B4 ; 207 ; 2 ; 1 ; 19 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; B5 ; 14 ; 1 ; 0 ; 14 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; B6 ; 10 ; 1 ; 0 ; 17 ; 3 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; B7 ; 11 ; 1 ; 0 ; 16 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; CI ; 27 ; 1 ; 0 ; 9 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; A0 ; 77 ; 4 ; 18 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; A1 ; 80 ; 4 ; 23 ; 0 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; A2 ; 81 ; 4 ; 23 ; 0 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; A3 ; 82 ; 4 ; 23 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; A4 ; 84 ; 4 ; 25 ; 0 ; 3 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; A5 ; 86 ; 4 ; 25 ; 0 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; A6 ; 87 ; 4 ; 25 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; A7 ; 88 ; 4 ; 25 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; B0 ; 67 ; 4 ; 9 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; B1 ; 68 ; 4 ; 12 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; B2 ; 69 ; 4 ; 12 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; B3 ; 70 ; 4 ; 14 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; B4 ; 72 ; 4 ; 16 ; 0 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; B5 ; 74 ; 4 ; 16 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; B6 ; 75 ; 4 ; 16 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; B7 ; 76 ; 4 ; 18 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; CI ; 23 ; 1 ; 0 ; 9 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
@@ -270,15 +271,15 @@ The pin-out file can be found in D:/projects/quartus/adder_8b/adder_8b.pin.
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
-; CO ; 58 ; 4 ; 1 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; S0 ; 102 ; 4 ; 32 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; S1 ; 34 ; 1 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; S2 ; 118 ; 3 ; 34 ; 7 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; S3 ; 31 ; 1 ; 0 ; 8 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; S4 ; 37 ; 1 ; 0 ; 6 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; S5 ; 35 ; 1 ; 0 ; 7 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; S6 ; 12 ; 1 ; 0 ; 16 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; S7 ; 6 ; 1 ; 0 ; 17 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; CO ; 151 ; 3 ; 34 ; 17 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; S0 ; 142 ; 3 ; 34 ; 12 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; S1 ; 143 ; 3 ; 34 ; 13 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; S2 ; 144 ; 3 ; 34 ; 13 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; S3 ; 145 ; 3 ; 34 ; 14 ; 4 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; S4 ; 146 ; 3 ; 34 ; 15 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; S5 ; 147 ; 3 ; 34 ; 15 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; S6 ; 149 ; 3 ; 34 ; 16 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; S7 ; 150 ; 3 ; 34 ; 16 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
@@ -287,10 +288,10 @@ The pin-out file can be found in D:/projects/quartus/adder_8b/adder_8b.pin.
+----------+------------------+---------------+--------------+
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
+----------+------------------+---------------+--------------+
-; 1 ; 21 / 32 ( 66 % ) ; 3.3V ; -- ;
-; 2 ; 1 / 35 ( 3 % ) ; 3.3V ; -- ;
-; 3 ; 3 / 35 ( 9 % ) ; 3.3V ; -- ;
-; 4 ; 4 / 36 ( 11 % ) ; 3.3V ; -- ;
+; 1 ; 3 / 32 ( 9 % ) ; 3.3V ; -- ;
+; 2 ; 0 / 35 ( 0 % ) ; 3.3V ; -- ;
+; 3 ; 10 / 35 ( 29 % ) ; 3.3V ; -- ;
+; 4 ; 16 / 36 ( 44 % ) ; 3.3V ; -- ;
+----------+------------------+---------------+--------------+
@@ -301,19 +302,19 @@ The pin-out file can be found in D:/projects/quartus/adder_8b/adder_8b.pin.
+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; 1 ; 0 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
; 2 ; 1 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
-; 3 ; 2 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 4 ; 3 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 5 ; 4 ; 1 ; A7 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 6 ; 5 ; 1 ; S7 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 3 ; 2 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 4 ; 3 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 5 ; 4 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 6 ; 5 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 8 ; 6 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 8 ; 6 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 10 ; 7 ; 1 ; B6 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 11 ; 8 ; 1 ; B7 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 12 ; 9 ; 1 ; S6 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 13 ; 10 ; 1 ; A6 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 14 ; 18 ; 1 ; B5 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 15 ; 19 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 10 ; 7 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 11 ; 8 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 12 ; 9 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 13 ; 10 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 14 ; 18 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 15 ; 19 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
; 18 ; 22 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
@@ -321,32 +322,32 @@ The pin-out file can be found in D:/projects/quartus/adder_8b/adder_8b.pin.
; 20 ; 24 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ;
; 21 ; 25 ; 1 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ;
; 22 ; 26 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
-; 23 ; 27 ; 1 ; A2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 24 ; 28 ; 1 ; A0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 23 ; 27 ; 1 ; CI ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 24 ; 28 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 26 ; 29 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
-; 27 ; 30 ; 1 ; CI ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 28 ; 31 ; 1 ; B0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 27 ; 30 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; 28 ; 31 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 30 ; 32 ; 1 ; B2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 31 ; 33 ; 1 ; S3 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 30 ; 32 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 31 ; 33 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 33 ; 35 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 34 ; 36 ; 1 ; S1 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 35 ; 37 ; 1 ; S5 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 33 ; 35 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 34 ; 36 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 35 ; 37 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 37 ; 39 ; 1 ; S4 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 37 ; 39 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 39 ; 43 ; 1 ; B3 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 40 ; 44 ; 1 ; A3 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 41 ; 45 ; 1 ; A4 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 39 ; 43 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 40 ; 44 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 41 ; 45 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 42 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 43 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 44 ; 49 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 45 ; 50 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 46 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 47 ; 52 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 48 ; 53 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 43 ; 48 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 44 ; 49 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 45 ; 50 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 46 ; 51 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 47 ; 52 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 48 ; 53 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 49 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 50 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
; 51 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
@@ -354,69 +355,69 @@ The pin-out file can be found in D:/projects/quartus/adder_8b/adder_8b.pin.
; 53 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 54 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
; 55 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 56 ; 54 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 57 ; 55 ; 4 ; A1 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
-; 58 ; 56 ; 4 ; CO ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
-; 59 ; 57 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 60 ; 58 ; 4 ; B1 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
-; 61 ; 59 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 56 ; 54 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 57 ; 55 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 58 ; 56 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 59 ; 57 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 60 ; 58 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 61 ; 59 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 63 ; 60 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 64 ; 61 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 63 ; 60 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 64 ; 61 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 67 ; 69 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 68 ; 70 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 69 ; 71 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 70 ; 74 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 67 ; 69 ; 4 ; B0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 68 ; 70 ; 4 ; B1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 69 ; 71 ; 4 ; B2 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 70 ; 74 ; 4 ; B3 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 71 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 72 ; 75 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 72 ; 75 ; 4 ; B4 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 74 ; 76 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 75 ; 77 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 76 ; 78 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 77 ; 79 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 74 ; 76 ; 4 ; B5 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 75 ; 77 ; 4 ; B6 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 76 ; 78 ; 4 ; B7 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 77 ; 79 ; 4 ; A0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 80 ; 82 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 81 ; 83 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 82 ; 84 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 80 ; 82 ; 4 ; A1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 81 ; 83 ; 4 ; A2 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 82 ; 84 ; 4 ; A3 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 83 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 84 ; 85 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 84 ; 85 ; 4 ; A4 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 85 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 86 ; 86 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 87 ; 87 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 88 ; 88 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 89 ; 89 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 90 ; 90 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 86 ; 86 ; 4 ; A5 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 87 ; 87 ; 4 ; A6 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 88 ; 88 ; 4 ; A7 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 89 ; 89 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 90 ; 90 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 91 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 92 ; 91 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 92 ; 91 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 94 ; 92 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 95 ; 93 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 96 ; 94 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 97 ; 95 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 94 ; 92 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 95 ; 93 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 96 ; 94 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 97 ; 95 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 98 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 99 ; 96 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 99 ; 96 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 100 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 101 ; 97 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 102 ; 98 ; 4 ; S0 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
-; 103 ; 99 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 104 ; 100 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 105 ; 101 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 106 ; 102 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 107 ; 105 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 101 ; 97 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 102 ; 98 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 103 ; 99 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 104 ; 100 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 105 ; 101 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 106 ; 102 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 107 ; 105 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 108 ; 106 ; 3 ; ~LVDS54p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 109 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 110 ; 107 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 110 ; 107 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 111 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 112 ; 108 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 113 ; 109 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 114 ; 110 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 115 ; 112 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 116 ; 113 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 117 ; 114 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 118 ; 117 ; 3 ; S2 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 112 ; 108 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 113 ; 109 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 114 ; 110 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 115 ; 112 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 116 ; 113 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 117 ; 114 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 118 ; 117 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 119 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 120 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 121 ; 121 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
@@ -425,32 +426,32 @@ The pin-out file can be found in D:/projects/quartus/adder_8b/adder_8b.pin.
; 124 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 125 ; 123 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
; 126 ; 124 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
-; 127 ; 125 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 128 ; 126 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 127 ; 125 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 128 ; 126 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 129 ; 127 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 130 ; 128 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 131 ; 129 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 132 ; 130 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; 133 ; 131 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 134 ; 132 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 135 ; 133 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 133 ; 131 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 134 ; 132 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 135 ; 133 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 136 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 137 ; 134 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 138 ; 135 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 139 ; 136 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 137 ; 134 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 138 ; 135 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 139 ; 136 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 141 ; 137 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 142 ; 138 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 143 ; 141 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 144 ; 142 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 145 ; 143 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 146 ; 149 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 147 ; 150 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 141 ; 137 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 142 ; 138 ; 3 ; S0 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 143 ; 141 ; 3 ; S1 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 144 ; 142 ; 3 ; S2 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 145 ; 143 ; 3 ; S3 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 146 ; 149 ; 3 ; S4 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 147 ; 150 ; 3 ; S5 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 148 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 149 ; 151 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 150 ; 152 ; 3 ; A5 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 151 ; 153 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 152 ; 154 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 149 ; 151 ; 3 ; S6 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 150 ; 152 ; 3 ; S7 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 151 ; 153 ; 3 ; CO ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 152 ; 154 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 153 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 154 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
; 155 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
@@ -458,55 +459,55 @@ The pin-out file can be found in D:/projects/quartus/adder_8b/adder_8b.pin.
; 157 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 158 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
; 159 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 160 ; 155 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 161 ; 156 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 162 ; 157 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 163 ; 158 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 164 ; 159 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 165 ; 160 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 160 ; 155 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 161 ; 156 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 162 ; 157 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 163 ; 158 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 164 ; 159 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 165 ; 160 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 166 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 167 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 168 ; 161 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 169 ; 162 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 170 ; 163 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 171 ; 164 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 168 ; 161 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 169 ; 162 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 170 ; 163 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 171 ; 164 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 172 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 173 ; 165 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 173 ; 165 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 174 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 175 ; 168 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 176 ; 169 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 175 ; 168 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 176 ; 169 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 177 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 178 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 179 ; 173 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 180 ; 174 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 181 ; 175 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 182 ; 176 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 179 ; 173 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 180 ; 174 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 181 ; 175 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 182 ; 176 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 183 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 184 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 185 ; 180 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 185 ; 180 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 186 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 187 ; 181 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 188 ; 182 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 189 ; 183 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 187 ; 181 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 188 ; 182 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 189 ; 183 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 190 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 191 ; 184 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 192 ; 185 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 193 ; 186 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 191 ; 184 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 192 ; 185 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 193 ; 186 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 194 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 195 ; 187 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 195 ; 187 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 196 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 197 ; 191 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 198 ; 192 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 199 ; 195 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 200 ; 196 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 201 ; 197 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 197 ; 191 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 198 ; 192 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 199 ; 195 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 200 ; 196 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 201 ; 197 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 202 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 203 ; 198 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 203 ; 198 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 204 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 205 ; 199 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 206 ; 200 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 207 ; 201 ; 2 ; B4 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
-; 208 ; 202 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 205 ; 199 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 206 ; 200 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 207 ; 201 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 208 ; 202 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
@@ -592,10 +593,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; A3 ; Input ; 6 ; 6 ; -- ; -- ;
; B3 ; Input ; 6 ; 6 ; -- ; -- ;
; A4 ; Input ; 6 ; 6 ; -- ; -- ;
-; A2 ; Input ; 0 ; 0 ; -- ; -- ;
-; A0 ; Input ; 0 ; 0 ; -- ; -- ;
+; A2 ; Input ; 6 ; 6 ; -- ; -- ;
+; A0 ; Input ; 6 ; 6 ; -- ; -- ;
; CI ; Input ; 0 ; 0 ; -- ; -- ;
-; B0 ; Input ; 0 ; 0 ; -- ; -- ;
+; B0 ; Input ; 6 ; 6 ; -- ; -- ;
; A1 ; Input ; 6 ; 6 ; -- ; -- ;
; B1 ; Input ; 6 ; 6 ; -- ; -- ;
; B2 ; Input ; 6 ; 6 ; -- ; -- ;
@@ -622,17 +623,26 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; - 7400:inst18|4~0 ; 0 ; 6 ;
; - 7486:inst20|4 ; 0 ; 6 ;
; B3 ; ; ;
-; - 7400:inst23|4~8 ; 1 ; 6 ;
-; - 7400:inst18|4~0 ; 1 ; 6 ;
-; - 7486:inst20|4 ; 1 ; 6 ;
+; - 7400:inst23|4~8 ; 0 ; 6 ;
+; - 7400:inst18|4~0 ; 0 ; 6 ;
+; - 7486:inst20|4 ; 0 ; 6 ;
; A4 ; ; ;
; - 7400:inst23|4~8 ; 0 ; 6 ;
; - 7400:inst23|4~9 ; 0 ; 6 ;
; - 7486:inst25|4~0 ; 0 ; 6 ;
; A2 ; ; ;
+; - 7400:inst13|4~0 ; 0 ; 6 ;
+; - 7400:inst13|4~1 ; 0 ; 6 ;
+; - 7486:inst15|4~0 ; 0 ; 6 ;
+; - 7400:inst23|4~10 ; 0 ; 6 ;
; A0 ; ; ;
+; - 7400:inst3|4~0 ; 0 ; 6 ;
+; - 7400:inst3|4~1 ; 0 ; 6 ;
+; - 7486:inst5|4~0 ; 0 ; 6 ;
; CI ; ; ;
; B0 ; ; ;
+; - 7400:inst3|4~1 ; 0 ; 6 ;
+; - 7486:inst5|4~0 ; 0 ; 6 ;
; A1 ; ; ;
; - 7400:inst8|4~0 ; 0 ; 6 ;
; - 7486:inst10|4 ; 0 ; 6 ;
@@ -640,9 +650,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; - 7400:inst8|4~0 ; 0 ; 6 ;
; - 7486:inst10|4 ; 0 ; 6 ;
; B2 ; ; ;
-; - 7400:inst13|4~1 ; 1 ; 6 ;
-; - 7486:inst15|4~0 ; 1 ; 6 ;
-; - 7400:inst23|4~10 ; 1 ; 6 ;
+; - 7400:inst13|4~1 ; 0 ; 6 ;
+; - 7486:inst15|4~0 ; 0 ; 6 ;
+; - 7400:inst23|4~10 ; 0 ; 6 ;
; B4 ; ; ;
; - 7400:inst23|4~9 ; 0 ; 6 ;
; - 7486:inst25|4~0 ; 0 ; 6 ;
@@ -659,8 +669,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; - 7400:inst38|4~0 ; 0 ; 6 ;
; - 7486:inst40|4 ; 0 ; 6 ;
; B7 ; ; ;
-; - 7400:inst38|4~0 ; 1 ; 6 ;
-; - 7486:inst40|4 ; 1 ; 6 ;
+; - 7400:inst38|4~0 ; 0 ; 6 ;
+; - 7486:inst40|4 ; 0 ; 6 ;
+-------------------------+-------------------+---------+
@@ -715,14 +725,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------+-----------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+-----------------------+
-; Block interconnects ; 29 / 26,052 ( < 1 % ) ;
-; C16 interconnects ; 2 / 1,156 ( < 1 % ) ;
-; C4 interconnects ; 31 / 17,952 ( < 1 % ) ;
-; Direct links ; 2 / 26,052 ( < 1 % ) ;
+; Block interconnects ; 27 / 26,052 ( < 1 % ) ;
+; C16 interconnects ; 7 / 1,156 ( < 1 % ) ;
+; C4 interconnects ; 37 / 17,952 ( < 1 % ) ;
+; Direct links ; 0 / 26,052 ( 0 % ) ;
; Global clocks ; 0 / 8 ( 0 % ) ;
-; Local interconnects ; 10 / 8,256 ( < 1 % ) ;
-; R24 interconnects ; 3 / 1,020 ( < 1 % ) ;
-; R4 interconnects ; 18 / 22,440 ( < 1 % ) ;
+; Local interconnects ; 11 / 8,256 ( < 1 % ) ;
+; R24 interconnects ; 5 / 1,020 ( < 1 % ) ;
+; R4 interconnects ; 47 / 22,440 ( < 1 % ) ;
+----------------------------+-----------------------+
@@ -826,7 +836,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Error detection CRC ; Off ;
; nCEO ; As output driving ground ;
; ASDO,nCSO ; As input tri-stated ;
-; Reserve all unused pins ; As output driving ground ;
+; Reserve all unused pins ; As input tri-stated ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+--------------------------+
@@ -921,19 +931,20 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+------------------------------------+------------+
-+--------------------------------------------------+
-; Advanced Data - Routing ;
-+------------------------------------+-------------+
-; Name ; Value ;
-+------------------------------------+-------------+
-; Early Slack - Fit Attempt 1 ; 2147483639 ;
-; Early Wire Use - Fit Attempt 1 ; 0 ;
-; Peak Regional Wire - Fit Attempt 1 ; 0 ;
-; Mid Slack - Fit Attempt 1 ; 2147483639 ;
-; Late Slack - Fit Attempt 1 ; -2147483648 ;
-; Late Wire Use - Fit Attempt 1 ; 0 ;
-; Time - Fit Attempt 1 ; 0 ;
-+------------------------------------+-------------+
++---------------------------------------------------+
+; Advanced Data - Routing ;
++-------------------------------------+-------------+
+; Name ; Value ;
++-------------------------------------+-------------+
+; Early Slack - Fit Attempt 1 ; 2147483639 ;
+; Early Wire Use - Fit Attempt 1 ; 0 ;
+; Peak Regional Wire - Fit Attempt 1 ; 1 ;
+; Mid Slack - Fit Attempt 1 ; 2147483639 ;
+; Late Slack - Fit Attempt 1 ; -2147483648 ;
+; Late Wire Use - Fit Attempt 1 ; 0 ;
+; Time - Fit Attempt 1 ; 0 ;
+; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016 ;
++-------------------------------------+-------------+
+-----------------+
@@ -942,7 +953,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
- Info: Processing started: Mon Mar 07 10:22:22 2022
+ Info: Processing started: Mon Mar 07 11:28:56 2022
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Info: Selected device EP2C8Q208C8 for design "adder_8b"
@@ -957,47 +968,11 @@ Info: Fitter converted 3 user pins into dedicated programming pins
Info: Pin ~ASDO~ is reserved at location 1
Info: Pin ~nCSO~ is reserved at location 2
Info: Pin ~LVDS54p/nCEO~ is reserved at location 108
-Warning: No exact pin location assignment(s) for 26 pins of 26 total pins
- Info: Pin CO not assigned to an exact location on the device
- Info: Pin S7 not assigned to an exact location on the device
- Info: Pin S0 not assigned to an exact location on the device
- Info: Pin S1 not assigned to an exact location on the device
- Info: Pin S2 not assigned to an exact location on the device
- Info: Pin S3 not assigned to an exact location on the device
- Info: Pin S4 not assigned to an exact location on the device
- Info: Pin S5 not assigned to an exact location on the device
- Info: Pin S6 not assigned to an exact location on the device
- Info: Pin A6 not assigned to an exact location on the device
- Info: Pin A3 not assigned to an exact location on the device
- Info: Pin B3 not assigned to an exact location on the device
- Info: Pin A4 not assigned to an exact location on the device
- Info: Pin A2 not assigned to an exact location on the device
- Info: Pin A0 not assigned to an exact location on the device
- Info: Pin CI not assigned to an exact location on the device
- Info: Pin B0 not assigned to an exact location on the device
- Info: Pin A1 not assigned to an exact location on the device
- Info: Pin B1 not assigned to an exact location on the device
- Info: Pin B2 not assigned to an exact location on the device
- Info: Pin B4 not assigned to an exact location on the device
- Info: Pin A5 not assigned to an exact location on the device
- Info: Pin B5 not assigned to an exact location on the device
- Info: Pin B6 not assigned to an exact location on the device
- Info: Pin A7 not assigned to an exact location on the device
- Info: Pin B7 not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Starting register packing
Info: Finished register packing
Extra Info: No registers were packed into other blocks
-Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
- Info: Number of I/O pins in group: 26 (unused VREF, 3.3V VCCIO, 17 input, 9 output, 0 bidirectional)
- Info: I/O standards used: 3.3-V LVTTL.
-Info: I/O bank details before I/O pin placement
- Info: Statistics of I/O banks
- Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available
- Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available
- Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available
- Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available
Info: Fitter preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
@@ -1006,7 +981,7 @@ Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources
- Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9
+ Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y9
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
@@ -1023,11 +998,10 @@ Warning: Found 9 output pins without output pin load capacitance assignment
Info: Pin "S5" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "S6" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
-Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Generated suppressed messages file D:/projects/quartus/adder_8b/adder_8b.fit.smsg
-Info: Quartus II Fitter was successful. 0 errors, 3 warnings
+Info: Quartus II Fitter was successful. 0 errors, 1 warning
Info: Peak virtual memory: 305 megabytes
- Info: Processing ended: Mon Mar 07 10:22:23 2022
+ Info: Processing ended: Mon Mar 07 11:28:57 2022
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
diff --git a/adder_8b/adder_8b.fit.summary b/adder_8b/adder_8b.fit.summary
index 57cef3e..b6ffc12 100644
--- a/adder_8b/adder_8b.fit.summary
+++ b/adder_8b/adder_8b.fit.summary
@@ -1,4 +1,4 @@
-Fitter Status : Successful - Mon Mar 07 10:22:23 2022
+Fitter Status : Successful - Mon Mar 07 11:28:57 2022
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : adder_8b
Top-level Entity Name : adder_8b
diff --git a/adder_8b/adder_8b.flow.rpt b/adder_8b/adder_8b.flow.rpt
index 3a1614b..3b89ce5 100644
--- a/adder_8b/adder_8b.flow.rpt
+++ b/adder_8b/adder_8b.flow.rpt
@@ -1,5 +1,5 @@
Flow report for adder_8b
-Mon Mar 07 10:22:25 2022
+Mon Mar 07 11:28:59 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@@ -38,7 +38,7 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+----------------------------------------------+
-; Flow Status ; Successful - Mon Mar 07 10:22:25 2022 ;
+; Flow Status ; Successful - Mon Mar 07 11:28:59 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; adder_8b ;
; Top-level Entity Name ; adder_8b ;
@@ -63,24 +63,25 @@ applicable agreement for further details.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
-; Start date & time ; 03/07/2022 10:22:21 ;
+; Start date & time ; 03/07/2022 11:28:55 ;
; Main task ; Compilation ;
; Revision Name ; adder_8b ;
+-------------------+---------------------+
-+---------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+------------------------------------+---------------------------------+---------------+-------------+----------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+------------------------------------+---------------------------------+---------------+-------------+----------------+
-; COMPILER_SIGNATURE_ID ; 220283517943889.164661974110084 ; -- ; -- ; -- ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
-; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
-; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
-; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
-+------------------------------------+---------------------------------+---------------+-------------+----------------+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings ;
++------------------------------------+-------------------------------------------+---------------+-------------+----------------+
+; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
++------------------------------------+-------------------------------------------+---------------+-------------+----------------+
+; COMPILER_SIGNATURE_ID ; 220283517943889.164662373514744 ; -- ; -- ; -- ;
+; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
+; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
+; MISC_FILE ; D:/projects/quartus/adder_8b/adder_8b.dpf ; -- ; -- ; -- ;
+; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
+; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
+; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
++------------------------------------+-------------------------------------------+---------------+-------------+----------------+
+-----------------------------------------------------------------------------------------------------------------------------+
@@ -88,10 +89,10 @@ applicable agreement for further details.
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 245 MB ; 00:00:00 ;
+; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 246 MB ; 00:00:00 ;
; Fitter ; 00:00:01 ; 1.0 ; 305 MB ; 00:00:01 ;
; Assembler ; 00:00:00 ; 1.0 ; 242 MB ; 00:00:00 ;
-; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 198 MB ; 00:00:00 ;
+; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 199 MB ; 00:00:00 ;
; Total ; 00:00:02 ; -- ; -- ; 00:00:01 ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
diff --git a/adder_8b/adder_8b.map.rpt b/adder_8b/adder_8b.map.rpt
index b559eeb..9c6e794 100644
--- a/adder_8b/adder_8b.map.rpt
+++ b/adder_8b/adder_8b.map.rpt
@@ -1,5 +1,5 @@
Analysis & Synthesis report for adder_8b
-Mon Mar 07 10:22:21 2022
+Mon Mar 07 11:28:55 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@@ -39,7 +39,7 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+----------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Mon Mar 07 10:22:21 2022 ;
+; Analysis & Synthesis Status ; Successful - Mon Mar 07 11:28:55 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; adder_8b ;
; Top-level Entity Name ; adder_8b ;
@@ -218,7 +218,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
- Info: Processing started: Mon Mar 07 10:22:20 2022
+ Info: Processing started: Mon Mar 07 11:28:54 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adder_8b -c adder_8b
Info: Found 1 design units, including 1 entities, in source file adder_8b.bdf
Info: Found entity 1: adder_8b
@@ -232,8 +232,8 @@ Info: Implemented 47 device resources after synthesis - the final resource count
Info: Implemented 9 output pins
Info: Implemented 21 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
- Info: Peak virtual memory: 248 megabytes
- Info: Processing ended: Mon Mar 07 10:22:21 2022
+ Info: Peak virtual memory: 250 megabytes
+ Info: Processing ended: Mon Mar 07 11:28:55 2022
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
diff --git a/adder_8b/adder_8b.map.summary b/adder_8b/adder_8b.map.summary
index 06c7abe..cdd9d47 100644
--- a/adder_8b/adder_8b.map.summary
+++ b/adder_8b/adder_8b.map.summary
@@ -1,4 +1,4 @@
-Analysis & Synthesis Status : Successful - Mon Mar 07 10:22:21 2022
+Analysis & Synthesis Status : Successful - Mon Mar 07 11:28:55 2022
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : adder_8b
Top-level Entity Name : adder_8b
diff --git a/adder_8b/adder_8b.pin b/adder_8b/adder_8b.pin
index ea6c706..55a9646 100644
--- a/adder_8b/adder_8b.pin
+++ b/adder_8b/adder_8b.pin
@@ -70,19 +70,19 @@ Pin Name/Usage : Location : Dir. : I/O Standard : Voltage
-------------------------------------------------------------------------------------------------------------
~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVTTL : : 1 : N
~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVTTL : : 1 : N
-GND* : 3 : : : : 1 :
-GND* : 4 : : : : 1 :
-A7 : 5 : input : 3.3-V LVTTL : : 1 : N
-S7 : 6 : output : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 3 : : : : 1 :
+RESERVED_INPUT : 4 : : : : 1 :
+RESERVED_INPUT : 5 : : : : 1 :
+RESERVED_INPUT : 6 : : : : 1 :
VCCIO1 : 7 : power : : 3.3V : 1 :
-GND* : 8 : : : : 1 :
+RESERVED_INPUT : 8 : : : : 1 :
GND : 9 : gnd : : : :
-B6 : 10 : input : 3.3-V LVTTL : : 1 : N
-B7 : 11 : input : 3.3-V LVTTL : : 1 : N
-S6 : 12 : output : 3.3-V LVTTL : : 1 : N
-A6 : 13 : input : 3.3-V LVTTL : : 1 : N
-B5 : 14 : input : 3.3-V LVTTL : : 1 : N
-GND* : 15 : : : : 1 :
+RESERVED_INPUT : 10 : : : : 1 :
+RESERVED_INPUT : 11 : : : : 1 :
+RESERVED_INPUT : 12 : : : : 1 :
+RESERVED_INPUT : 13 : : : : 1 :
+RESERVED_INPUT : 14 : : : : 1 :
+RESERVED_INPUT : 15 : : : : 1 :
TDO : 16 : output : : : 1 :
TMS : 17 : input : : : 1 :
TCK : 18 : input : : : 1 :
@@ -90,32 +90,32 @@ TDI : 19 : input : :
DATA0 : 20 : input : : : 1 :
DCLK : 21 : : : : 1 :
nCE : 22 : : : : 1 :
-A2 : 23 : input : 3.3-V LVTTL : : 1 : N
-A0 : 24 : input : 3.3-V LVTTL : : 1 : N
+CI : 23 : input : 3.3-V LVTTL : : 1 : Y
+GND+ : 24 : : : : 1 :
GND : 25 : gnd : : : :
nCONFIG : 26 : : : : 1 :
-CI : 27 : input : 3.3-V LVTTL : : 1 : N
-B0 : 28 : input : 3.3-V LVTTL : : 1 : N
+GND+ : 27 : : : : 1 :
+GND+ : 28 : : : : 1 :
VCCIO1 : 29 : power : : 3.3V : 1 :
-B2 : 30 : input : 3.3-V LVTTL : : 1 : N
-S3 : 31 : output : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 30 : : : : 1 :
+RESERVED_INPUT : 31 : : : : 1 :
VCCINT : 32 : power : : 1.2V : :
-GND* : 33 : : : : 1 :
-S1 : 34 : output : 3.3-V LVTTL : : 1 : N
-S5 : 35 : output : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 33 : : : : 1 :
+RESERVED_INPUT : 34 : : : : 1 :
+RESERVED_INPUT : 35 : : : : 1 :
GND : 36 : gnd : : : :
-S4 : 37 : output : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 37 : : : : 1 :
GND : 38 : gnd : : : :
-B3 : 39 : input : 3.3-V LVTTL : : 1 : N
-A3 : 40 : input : 3.3-V LVTTL : : 1 : N
-A4 : 41 : input : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 39 : : : : 1 :
+RESERVED_INPUT : 40 : : : : 1 :
+RESERVED_INPUT : 41 : : : : 1 :
VCCIO1 : 42 : power : : 3.3V : 1 :
-GND* : 43 : : : : 1 :
-GND* : 44 : : : : 1 :
-GND* : 45 : : : : 1 :
-GND* : 46 : : : : 1 :
-GND* : 47 : : : : 1 :
-GND* : 48 : : : : 1 :
+RESERVED_INPUT : 43 : : : : 1 :
+RESERVED_INPUT : 44 : : : : 1 :
+RESERVED_INPUT : 45 : : : : 1 :
+RESERVED_INPUT : 46 : : : : 1 :
+RESERVED_INPUT : 47 : : : : 1 :
+RESERVED_INPUT : 48 : : : : 1 :
GND : 49 : gnd : : : :
GND_PLL1 : 50 : gnd : : : :
VCCD_PLL1 : 51 : power : : 1.2V : :
@@ -123,69 +123,69 @@ GND_PLL1 : 52 : gnd : :
VCCA_PLL1 : 53 : power : : 1.2V : :
GNDA_PLL1 : 54 : gnd : : : :
GND : 55 : gnd : : : :
-GND* : 56 : : : : 4 :
-A1 : 57 : input : 3.3-V LVTTL : : 4 : N
-CO : 58 : output : 3.3-V LVTTL : : 4 : N
-GND* : 59 : : : : 4 :
-B1 : 60 : input : 3.3-V LVTTL : : 4 : N
-GND* : 61 : : : : 4 :
+RESERVED_INPUT : 56 : : : : 4 :
+RESERVED_INPUT : 57 : : : : 4 :
+RESERVED_INPUT : 58 : : : : 4 :
+RESERVED_INPUT : 59 : : : : 4 :
+RESERVED_INPUT : 60 : : : : 4 :
+RESERVED_INPUT : 61 : : : : 4 :
VCCIO4 : 62 : power : : 3.3V : 4 :
-GND* : 63 : : : : 4 :
-GND* : 64 : : : : 4 :
+RESERVED_INPUT : 63 : : : : 4 :
+RESERVED_INPUT : 64 : : : : 4 :
GND : 65 : gnd : : : :
VCCINT : 66 : power : : 1.2V : :
-GND* : 67 : : : : 4 :
-GND* : 68 : : : : 4 :
-GND* : 69 : : : : 4 :
-GND* : 70 : : : : 4 :
+B0 : 67 : input : 3.3-V LVTTL : : 4 : Y
+B1 : 68 : input : 3.3-V LVTTL : : 4 : Y
+B2 : 69 : input : 3.3-V LVTTL : : 4 : Y
+B3 : 70 : input : 3.3-V LVTTL : : 4 : Y
VCCIO4 : 71 : power : : 3.3V : 4 :
-GND* : 72 : : : : 4 :
+B4 : 72 : input : 3.3-V LVTTL : : 4 : Y
GND : 73 : gnd : : : :
-GND* : 74 : : : : 4 :
-GND* : 75 : : : : 4 :
-GND* : 76 : : : : 4 :
-GND* : 77 : : : : 4 :
+B5 : 74 : input : 3.3-V LVTTL : : 4 : Y
+B6 : 75 : input : 3.3-V LVTTL : : 4 : Y
+B7 : 76 : input : 3.3-V LVTTL : : 4 : Y
+A0 : 77 : input : 3.3-V LVTTL : : 4 : Y
GND : 78 : gnd : : : :
VCCINT : 79 : power : : 1.2V : :
-GND* : 80 : : : : 4 :
-GND* : 81 : : : : 4 :
-GND* : 82 : : : : 4 :
+A1 : 80 : input : 3.3-V LVTTL : : 4 : Y
+A2 : 81 : input : 3.3-V LVTTL : : 4 : Y
+A3 : 82 : input : 3.3-V LVTTL : : 4 : Y
VCCIO4 : 83 : power : : 3.3V : 4 :
-GND* : 84 : : : : 4 :
+A4 : 84 : input : 3.3-V LVTTL : : 4 : Y
GND : 85 : gnd : : : :
-GND* : 86 : : : : 4 :
-GND* : 87 : : : : 4 :
-GND* : 88 : : : : 4 :
-GND* : 89 : : : : 4 :
-GND* : 90 : : : : 4 :
+A5 : 86 : input : 3.3-V LVTTL : : 4 : Y
+A6 : 87 : input : 3.3-V LVTTL : : 4 : Y
+A7 : 88 : input : 3.3-V LVTTL : : 4 : Y
+RESERVED_INPUT : 89 : : : : 4 :
+RESERVED_INPUT : 90 : : : : 4 :
VCCIO4 : 91 : power : : 3.3V : 4 :
-GND* : 92 : : : : 4 :
+RESERVED_INPUT : 92 : : : : 4 :
GND : 93 : gnd : : : :
-GND* : 94 : : : : 4 :
-GND* : 95 : : : : 4 :
-GND* : 96 : : : : 4 :
-GND* : 97 : : : : 4 :
+RESERVED_INPUT : 94 : : : : 4 :
+RESERVED_INPUT : 95 : : : : 4 :
+RESERVED_INPUT : 96 : : : : 4 :
+RESERVED_INPUT : 97 : : : : 4 :
VCCIO4 : 98 : power : : 3.3V : 4 :
-GND* : 99 : : : : 4 :
+RESERVED_INPUT : 99 : : : : 4 :
GND : 100 : gnd : : : :
-GND* : 101 : : : : 4 :
-S0 : 102 : output : 3.3-V LVTTL : : 4 : N
-GND* : 103 : : : : 4 :
-GND* : 104 : : : : 4 :
-GND* : 105 : : : : 3 :
-GND* : 106 : : : : 3 :
-GND* : 107 : : : : 3 :
+RESERVED_INPUT : 101 : : : : 4 :
+RESERVED_INPUT : 102 : : : : 4 :
+RESERVED_INPUT : 103 : : : : 4 :
+RESERVED_INPUT : 104 : : : : 4 :
+RESERVED_INPUT : 105 : : : : 3 :
+RESERVED_INPUT : 106 : : : : 3 :
+RESERVED_INPUT : 107 : : : : 3 :
~LVDS54p/nCEO~ : 108 : output : 3.3-V LVTTL : : 3 : N
VCCIO3 : 109 : power : : 3.3V : 3 :
-GND* : 110 : : : : 3 :
+RESERVED_INPUT : 110 : : : : 3 :
GND : 111 : gnd : : : :
-GND* : 112 : : : : 3 :
-GND* : 113 : : : : 3 :
-GND* : 114 : : : : 3 :
-GND* : 115 : : : : 3 :
-GND* : 116 : : : : 3 :
-GND* : 117 : : : : 3 :
-S2 : 118 : output : 3.3-V LVTTL : : 3 : N
+RESERVED_INPUT : 112 : : : : 3 :
+RESERVED_INPUT : 113 : : : : 3 :
+RESERVED_INPUT : 114 : : : : 3 :
+RESERVED_INPUT : 115 : : : : 3 :
+RESERVED_INPUT : 116 : : : : 3 :
+RESERVED_INPUT : 117 : : : : 3 :
+RESERVED_INPUT : 118 : : : : 3 :
GND : 119 : gnd : : : :
VCCINT : 120 : power : : 1.2V : :
nSTATUS : 121 : : : : 3 :
@@ -194,32 +194,32 @@ CONF_DONE : 123 : : :
GND : 124 : gnd : : : :
MSEL1 : 125 : : : : 3 :
MSEL0 : 126 : : : : 3 :
-GND* : 127 : : : : 3 :
-GND* : 128 : : : : 3 :
+RESERVED_INPUT : 127 : : : : 3 :
+RESERVED_INPUT : 128 : : : : 3 :
GND+ : 129 : : : : 3 :
GND+ : 130 : : : : 3 :
GND+ : 131 : : : : 3 :
GND+ : 132 : : : : 3 :
-GND* : 133 : : : : 3 :
-GND* : 134 : : : : 3 :
-GND* : 135 : : : : 3 :
+RESERVED_INPUT : 133 : : : : 3 :
+RESERVED_INPUT : 134 : : : : 3 :
+RESERVED_INPUT : 135 : : : : 3 :
VCCIO3 : 136 : power : : 3.3V : 3 :
-GND* : 137 : : : : 3 :
-GND* : 138 : : : : 3 :
-GND* : 139 : : : : 3 :
+RESERVED_INPUT : 137 : : : : 3 :
+RESERVED_INPUT : 138 : : : : 3 :
+RESERVED_INPUT : 139 : : : : 3 :
GND : 140 : gnd : : : :
-GND* : 141 : : : : 3 :
-GND* : 142 : : : : 3 :
-GND* : 143 : : : : 3 :
-GND* : 144 : : : : 3 :
-GND* : 145 : : : : 3 :
-GND* : 146 : : : : 3 :
-GND* : 147 : : : : 3 :
+RESERVED_INPUT : 141 : : : : 3 :
+S0 : 142 : output : 3.3-V LVTTL : : 3 : Y
+S1 : 143 : output : 3.3-V LVTTL : : 3 : Y
+S2 : 144 : output : 3.3-V LVTTL : : 3 : Y
+S3 : 145 : output : 3.3-V LVTTL : : 3 : Y
+S4 : 146 : output : 3.3-V LVTTL : : 3 : Y
+S5 : 147 : output : 3.3-V LVTTL : : 3 : Y
VCCIO3 : 148 : power : : 3.3V : 3 :
-GND* : 149 : : : : 3 :
-A5 : 150 : input : 3.3-V LVTTL : : 3 : N
-GND* : 151 : : : : 3 :
-GND* : 152 : : : : 3 :
+S6 : 149 : output : 3.3-V LVTTL : : 3 : Y
+S7 : 150 : output : 3.3-V LVTTL : : 3 : Y
+CO : 151 : output : 3.3-V LVTTL : : 3 : Y
+RESERVED_INPUT : 152 : : : : 3 :
GND : 153 : gnd : : : :
GND_PLL2 : 154 : gnd : : : :
VCCD_PLL2 : 155 : power : : 1.2V : :
@@ -227,52 +227,52 @@ GND_PLL2 : 156 : gnd : :
VCCA_PLL2 : 157 : power : : 1.2V : :
GNDA_PLL2 : 158 : gnd : : : :
GND : 159 : gnd : : : :
-GND* : 160 : : : : 2 :
-GND* : 161 : : : : 2 :
-GND* : 162 : : : : 2 :
-GND* : 163 : : : : 2 :
-GND* : 164 : : : : 2 :
-GND* : 165 : : : : 2 :
+RESERVED_INPUT : 160 : : : : 2 :
+RESERVED_INPUT : 161 : : : : 2 :
+RESERVED_INPUT : 162 : : : : 2 :
+RESERVED_INPUT : 163 : : : : 2 :
+RESERVED_INPUT : 164 : : : : 2 :
+RESERVED_INPUT : 165 : : : : 2 :
VCCIO2 : 166 : power : : 3.3V : 2 :
GND : 167 : gnd : : : :
-GND* : 168 : : : : 2 :
-GND* : 169 : : : : 2 :
-GND* : 170 : : : : 2 :
-GND* : 171 : : : : 2 :
+RESERVED_INPUT : 168 : : : : 2 :
+RESERVED_INPUT : 169 : : : : 2 :
+RESERVED_INPUT : 170 : : : : 2 :
+RESERVED_INPUT : 171 : : : : 2 :
VCCIO2 : 172 : power : : 3.3V : 2 :
-GND* : 173 : : : : 2 :
+RESERVED_INPUT : 173 : : : : 2 :
GND : 174 : gnd : : : :
-GND* : 175 : : : : 2 :
-GND* : 176 : : : : 2 :
+RESERVED_INPUT : 175 : : : : 2 :
+RESERVED_INPUT : 176 : : : : 2 :
GND : 177 : gnd : : : :
VCCINT : 178 : power : : 1.2V : :
-GND* : 179 : : : : 2 :
-GND* : 180 : : : : 2 :
-GND* : 181 : : : : 2 :
-GND* : 182 : : : : 2 :
+RESERVED_INPUT : 179 : : : : 2 :
+RESERVED_INPUT : 180 : : : : 2 :
+RESERVED_INPUT : 181 : : : : 2 :
+RESERVED_INPUT : 182 : : : : 2 :
VCCIO2 : 183 : power : : 3.3V : 2 :
GND : 184 : gnd : : : :
-GND* : 185 : : : : 2 :
+RESERVED_INPUT : 185 : : : : 2 :
GND : 186 : gnd : : : :
-GND* : 187 : : : : 2 :
-GND* : 188 : : : : 2 :
-GND* : 189 : : : : 2 :
+RESERVED_INPUT : 187 : : : : 2 :
+RESERVED_INPUT : 188 : : : : 2 :
+RESERVED_INPUT : 189 : : : : 2 :
VCCINT : 190 : power : : 1.2V : :
-GND* : 191 : : : : 2 :
-GND* : 192 : : : : 2 :
-GND* : 193 : : : : 2 :
+RESERVED_INPUT : 191 : : : : 2 :
+RESERVED_INPUT : 192 : : : : 2 :
+RESERVED_INPUT : 193 : : : : 2 :
VCCIO2 : 194 : power : : 3.3V : 2 :
-GND* : 195 : : : : 2 :
+RESERVED_INPUT : 195 : : : : 2 :
GND : 196 : gnd : : : :
-GND* : 197 : : : : 2 :
-GND* : 198 : : : : 2 :
-GND* : 199 : : : : 2 :
-GND* : 200 : : : : 2 :
-GND* : 201 : : : : 2 :
+RESERVED_INPUT : 197 : : : : 2 :
+RESERVED_INPUT : 198 : : : : 2 :
+RESERVED_INPUT : 199 : : : : 2 :
+RESERVED_INPUT : 200 : : : : 2 :
+RESERVED_INPUT : 201 : : : : 2 :
VCCIO2 : 202 : power : : 3.3V : 2 :
-GND* : 203 : : : : 2 :
+RESERVED_INPUT : 203 : : : : 2 :
GND : 204 : gnd : : : :
-GND* : 205 : : : : 2 :
-GND* : 206 : : : : 2 :
-B4 : 207 : input : 3.3-V LVTTL : : 2 : N
-GND* : 208 : : : : 2 :
+RESERVED_INPUT : 205 : : : : 2 :
+RESERVED_INPUT : 206 : : : : 2 :
+RESERVED_INPUT : 207 : : : : 2 :
+RESERVED_INPUT : 208 : : : : 2 :
diff --git a/adder_8b/adder_8b.pof b/adder_8b/adder_8b.pof
index 29b3267..16bf68f 100644
Binary files a/adder_8b/adder_8b.pof and b/adder_8b/adder_8b.pof differ
diff --git a/adder_8b/adder_8b.qsf b/adder_8b/adder_8b.qsf
index 22d8fce..360e6bc 100644
--- a/adder_8b/adder_8b.qsf
+++ b/adder_8b/adder_8b.qsf
@@ -50,4 +50,34 @@ set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
\ No newline at end of file
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name MISC_FILE "D:/projects/quartus/adder_8b/adder_8b.dpf"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_location_assignment PIN_77 -to A0
+set_location_assignment PIN_80 -to A1
+set_location_assignment PIN_81 -to A2
+set_location_assignment PIN_82 -to A3
+set_location_assignment PIN_84 -to A4
+set_location_assignment PIN_86 -to A5
+set_location_assignment PIN_87 -to A6
+set_location_assignment PIN_88 -to A7
+set_location_assignment PIN_67 -to B0
+set_location_assignment PIN_68 -to B1
+set_location_assignment PIN_69 -to B2
+set_location_assignment PIN_70 -to B3
+set_location_assignment PIN_72 -to B4
+set_location_assignment PIN_74 -to B5
+set_location_assignment PIN_75 -to B6
+set_location_assignment PIN_76 -to B7
+set_location_assignment PIN_23 -to CI
+set_location_assignment PIN_142 -to S0
+set_location_assignment PIN_143 -to S1
+set_location_assignment PIN_144 -to S2
+set_location_assignment PIN_145 -to S3
+set_location_assignment PIN_146 -to S4
+set_location_assignment PIN_147 -to S5
+set_location_assignment PIN_149 -to S6
+set_location_assignment PIN_150 -to S7
+set_location_assignment PIN_151 -to CO
\ No newline at end of file
diff --git a/adder_8b/adder_8b.sof b/adder_8b/adder_8b.sof
index 6cc9658..18edc05 100644
Binary files a/adder_8b/adder_8b.sof and b/adder_8b/adder_8b.sof differ
diff --git a/adder_8b/adder_8b.tan.rpt b/adder_8b/adder_8b.tan.rpt
index 81dd933..8d0407b 100644
--- a/adder_8b/adder_8b.tan.rpt
+++ b/adder_8b/adder_8b.tan.rpt
@@ -1,5 +1,5 @@
Classic Timing Analyzer report for adder_8b
-Mon Mar 07 10:22:25 2022
+Mon Mar 07 11:28:59 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@@ -39,7 +39,7 @@ applicable agreement for further details.
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
-; Worst-case tpd ; N/A ; None ; 19.344 ns ; A1 ; CO ; -- ; -- ; 0 ;
+; Worst-case tpd ; N/A ; None ; 22.018 ns ; B0 ; CO ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
@@ -98,103 +98,103 @@ applicable agreement for further details.
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
-; N/A ; None ; 19.344 ns ; A1 ; CO ;
-; N/A ; None ; 19.220 ns ; B1 ; CO ;
-; N/A ; None ; 18.199 ns ; B2 ; CO ;
-; N/A ; None ; 18.173 ns ; A1 ; S7 ;
-; N/A ; None ; 18.049 ns ; B1 ; S7 ;
-; N/A ; None ; 17.501 ns ; A3 ; CO ;
-; N/A ; None ; 17.423 ns ; B3 ; CO ;
-; N/A ; None ; 17.266 ns ; B4 ; CO ;
-; N/A ; None ; 17.091 ns ; A5 ; CO ;
-; N/A ; None ; 17.075 ns ; A4 ; CO ;
-; N/A ; None ; 17.028 ns ; B2 ; S7 ;
-; N/A ; None ; 17.000 ns ; A1 ; S6 ;
-; N/A ; None ; 16.876 ns ; B1 ; S6 ;
-; N/A ; None ; 16.330 ns ; A3 ; S7 ;
-; N/A ; None ; 16.252 ns ; B3 ; S7 ;
-; N/A ; None ; 16.095 ns ; B4 ; S7 ;
-; N/A ; None ; 15.940 ns ; B5 ; CO ;
-; N/A ; None ; 15.920 ns ; A5 ; S7 ;
-; N/A ; None ; 15.904 ns ; A4 ; S7 ;
-; N/A ; None ; 15.855 ns ; B2 ; S6 ;
-; N/A ; None ; 15.259 ns ; A0 ; CO ;
-; N/A ; None ; 15.157 ns ; A3 ; S6 ;
-; N/A ; None ; 15.079 ns ; B3 ; S6 ;
-; N/A ; None ; 15.027 ns ; B0 ; CO ;
-; N/A ; None ; 14.922 ns ; B4 ; S6 ;
-; N/A ; None ; 14.769 ns ; B5 ; S7 ;
-; N/A ; None ; 14.762 ns ; CI ; CO ;
-; N/A ; None ; 14.759 ns ; A1 ; S5 ;
-; N/A ; None ; 14.747 ns ; A5 ; S6 ;
-; N/A ; None ; 14.731 ns ; A4 ; S6 ;
-; N/A ; None ; 14.635 ns ; B1 ; S5 ;
-; N/A ; None ; 14.560 ns ; A1 ; S2 ;
-; N/A ; None ; 14.436 ns ; B1 ; S2 ;
-; N/A ; None ; 14.088 ns ; A0 ; S7 ;
-; N/A ; None ; 14.087 ns ; A1 ; S4 ;
-; N/A ; None ; 13.963 ns ; B1 ; S4 ;
-; N/A ; None ; 13.856 ns ; B0 ; S7 ;
-; N/A ; None ; 13.695 ns ; A6 ; CO ;
-; N/A ; None ; 13.614 ns ; B2 ; S5 ;
-; N/A ; None ; 13.596 ns ; B5 ; S6 ;
-; N/A ; None ; 13.591 ns ; CI ; S7 ;
-; N/A ; None ; 13.448 ns ; A2 ; CO ;
-; N/A ; None ; 13.408 ns ; B2 ; S2 ;
-; N/A ; None ; 13.338 ns ; A1 ; S3 ;
-; N/A ; None ; 13.214 ns ; B1 ; S3 ;
-; N/A ; None ; 12.955 ns ; B6 ; CO ;
-; N/A ; None ; 12.942 ns ; B2 ; S4 ;
-; N/A ; None ; 12.916 ns ; A3 ; S5 ;
-; N/A ; None ; 12.915 ns ; A0 ; S6 ;
-; N/A ; None ; 12.838 ns ; B3 ; S5 ;
-; N/A ; None ; 12.683 ns ; B0 ; S6 ;
-; N/A ; None ; 12.681 ns ; B4 ; S5 ;
-; N/A ; None ; 12.613 ns ; B7 ; CO ;
-; N/A ; None ; 12.524 ns ; A6 ; S7 ;
-; N/A ; None ; 12.501 ns ; A5 ; S5 ;
-; N/A ; None ; 12.488 ns ; A4 ; S5 ;
-; N/A ; None ; 12.418 ns ; CI ; S6 ;
-; N/A ; None ; 12.408 ns ; A7 ; CO ;
-; N/A ; None ; 12.277 ns ; A2 ; S7 ;
-; N/A ; None ; 12.244 ns ; A3 ; S4 ;
-; N/A ; None ; 12.193 ns ; B2 ; S3 ;
-; N/A ; None ; 12.166 ns ; B3 ; S4 ;
-; N/A ; None ; 12.007 ns ; B4 ; S4 ;
-; N/A ; None ; 11.786 ns ; B6 ; S7 ;
-; N/A ; None ; 11.579 ns ; A1 ; S1 ;
-; N/A ; None ; 11.527 ns ; A4 ; S4 ;
-; N/A ; None ; 11.489 ns ; A3 ; S3 ;
-; N/A ; None ; 11.458 ns ; B1 ; S1 ;
-; N/A ; None ; 11.443 ns ; B7 ; S7 ;
-; N/A ; None ; 11.415 ns ; B3 ; S3 ;
-; N/A ; None ; 11.378 ns ; A6 ; S6 ;
-; N/A ; None ; 11.337 ns ; B5 ; S5 ;
-; N/A ; None ; 11.243 ns ; A7 ; S7 ;
-; N/A ; None ; 11.104 ns ; A2 ; S6 ;
-; N/A ; None ; 11.091 ns ; B6 ; S6 ;
-; N/A ; None ; 10.674 ns ; A0 ; S5 ;
-; N/A ; None ; 10.475 ns ; A0 ; S2 ;
-; N/A ; None ; 10.442 ns ; B0 ; S5 ;
-; N/A ; None ; 10.294 ns ; A0 ; S0 ;
-; N/A ; None ; 10.243 ns ; B0 ; S2 ;
-; N/A ; None ; 10.177 ns ; CI ; S5 ;
-; N/A ; None ; 10.065 ns ; B0 ; S0 ;
-; N/A ; None ; 10.002 ns ; A0 ; S4 ;
-; N/A ; None ; 9.978 ns ; CI ; S2 ;
-; N/A ; None ; 9.800 ns ; CI ; S0 ;
-; N/A ; None ; 9.770 ns ; B0 ; S4 ;
-; N/A ; None ; 9.505 ns ; CI ; S4 ;
-; N/A ; None ; 9.253 ns ; A0 ; S3 ;
-; N/A ; None ; 9.021 ns ; B0 ; S3 ;
-; N/A ; None ; 8.863 ns ; A2 ; S5 ;
-; N/A ; None ; 8.756 ns ; CI ; S3 ;
-; N/A ; None ; 8.661 ns ; A2 ; S2 ;
-; N/A ; None ; 8.191 ns ; A2 ; S4 ;
-; N/A ; None ; 7.490 ns ; A0 ; S1 ;
-; N/A ; None ; 7.442 ns ; A2 ; S3 ;
-; N/A ; None ; 7.258 ns ; B0 ; S1 ;
-; N/A ; None ; 6.993 ns ; CI ; S1 ;
+; N/A ; None ; 22.018 ns ; B0 ; CO ;
+; N/A ; None ; 21.780 ns ; B0 ; S7 ;
+; N/A ; None ; 21.052 ns ; B1 ; CO ;
+; N/A ; None ; 20.864 ns ; A0 ; CO ;
+; N/A ; None ; 20.814 ns ; B1 ; S7 ;
+; N/A ; None ; 20.626 ns ; A0 ; S7 ;
+; N/A ; None ; 20.579 ns ; A1 ; CO ;
+; N/A ; None ; 20.442 ns ; B0 ; S6 ;
+; N/A ; None ; 20.341 ns ; A1 ; S7 ;
+; N/A ; None ; 20.259 ns ; B2 ; CO ;
+; N/A ; None ; 20.021 ns ; B2 ; S7 ;
+; N/A ; None ; 19.812 ns ; A2 ; CO ;
+; N/A ; None ; 19.574 ns ; A2 ; S7 ;
+; N/A ; None ; 19.476 ns ; B1 ; S6 ;
+; N/A ; None ; 19.288 ns ; A0 ; S6 ;
+; N/A ; None ; 19.089 ns ; B0 ; S5 ;
+; N/A ; None ; 19.003 ns ; A1 ; S6 ;
+; N/A ; None ; 18.831 ns ; B3 ; CO ;
+; N/A ; None ; 18.728 ns ; A3 ; CO ;
+; N/A ; None ; 18.683 ns ; B2 ; S6 ;
+; N/A ; None ; 18.593 ns ; B3 ; S7 ;
+; N/A ; None ; 18.490 ns ; A3 ; S7 ;
+; N/A ; None ; 18.303 ns ; B0 ; S4 ;
+; N/A ; None ; 18.291 ns ; A4 ; CO ;
+; N/A ; None ; 18.236 ns ; A2 ; S6 ;
+; N/A ; None ; 18.123 ns ; B1 ; S5 ;
+; N/A ; None ; 18.053 ns ; A4 ; S7 ;
+; N/A ; None ; 17.935 ns ; A0 ; S5 ;
+; N/A ; None ; 17.650 ns ; A1 ; S5 ;
+; N/A ; None ; 17.587 ns ; B4 ; CO ;
+; N/A ; None ; 17.447 ns ; CI ; CO ;
+; N/A ; None ; 17.370 ns ; B0 ; S3 ;
+; N/A ; None ; 17.349 ns ; B4 ; S7 ;
+; N/A ; None ; 17.337 ns ; B1 ; S4 ;
+; N/A ; None ; 17.330 ns ; B2 ; S5 ;
+; N/A ; None ; 17.255 ns ; B3 ; S6 ;
+; N/A ; None ; 17.209 ns ; CI ; S7 ;
+; N/A ; None ; 17.202 ns ; A5 ; CO ;
+; N/A ; None ; 17.152 ns ; A3 ; S6 ;
+; N/A ; None ; 17.149 ns ; A0 ; S4 ;
+; N/A ; None ; 16.987 ns ; B5 ; CO ;
+; N/A ; None ; 16.964 ns ; A5 ; S7 ;
+; N/A ; None ; 16.883 ns ; A2 ; S5 ;
+; N/A ; None ; 16.864 ns ; A1 ; S4 ;
+; N/A ; None ; 16.749 ns ; B5 ; S7 ;
+; N/A ; None ; 16.715 ns ; A4 ; S6 ;
+; N/A ; None ; 16.544 ns ; B2 ; S4 ;
+; N/A ; None ; 16.404 ns ; B1 ; S3 ;
+; N/A ; None ; 16.306 ns ; B0 ; S2 ;
+; N/A ; None ; 16.216 ns ; A0 ; S3 ;
+; N/A ; None ; 16.097 ns ; A2 ; S4 ;
+; N/A ; None ; 16.011 ns ; B4 ; S6 ;
+; N/A ; None ; 15.931 ns ; A1 ; S3 ;
+; N/A ; None ; 15.902 ns ; B3 ; S5 ;
+; N/A ; None ; 15.871 ns ; CI ; S6 ;
+; N/A ; None ; 15.799 ns ; A3 ; S5 ;
+; N/A ; None ; 15.626 ns ; A5 ; S6 ;
+; N/A ; None ; 15.611 ns ; B2 ; S3 ;
+; N/A ; None ; 15.411 ns ; B5 ; S6 ;
+; N/A ; None ; 15.366 ns ; A4 ; S5 ;
+; N/A ; None ; 15.340 ns ; B1 ; S2 ;
+; N/A ; None ; 15.164 ns ; A2 ; S3 ;
+; N/A ; None ; 15.152 ns ; A0 ; S2 ;
+; N/A ; None ; 15.116 ns ; B3 ; S4 ;
+; N/A ; None ; 15.042 ns ; B6 ; CO ;
+; N/A ; None ; 15.013 ns ; A3 ; S4 ;
+; N/A ; None ; 14.892 ns ; B0 ; S1 ;
+; N/A ; None ; 14.867 ns ; A1 ; S2 ;
+; N/A ; None ; 14.804 ns ; B6 ; S7 ;
+; N/A ; None ; 14.658 ns ; B4 ; S5 ;
+; N/A ; None ; 14.543 ns ; B2 ; S2 ;
+; N/A ; None ; 14.518 ns ; CI ; S5 ;
+; N/A ; None ; 14.282 ns ; A5 ; S5 ;
+; N/A ; None ; 14.173 ns ; B3 ; S3 ;
+; N/A ; None ; 14.162 ns ; B0 ; S0 ;
+; N/A ; None ; 14.098 ns ; A2 ; S2 ;
+; N/A ; None ; 14.088 ns ; A4 ; S4 ;
+; N/A ; None ; 14.077 ns ; A3 ; S3 ;
+; N/A ; None ; 14.063 ns ; B5 ; S5 ;
+; N/A ; None ; 14.043 ns ; B7 ; CO ;
+; N/A ; None ; 13.974 ns ; A6 ; CO ;
+; N/A ; None ; 13.933 ns ; B1 ; S1 ;
+; N/A ; None ; 13.865 ns ; B4 ; S4 ;
+; N/A ; None ; 13.816 ns ; B7 ; S7 ;
+; N/A ; None ; 13.738 ns ; A0 ; S1 ;
+; N/A ; None ; 13.736 ns ; A6 ; S7 ;
+; N/A ; None ; 13.732 ns ; CI ; S4 ;
+; N/A ; None ; 13.470 ns ; A1 ; S1 ;
+; N/A ; None ; 13.462 ns ; B6 ; S6 ;
+; N/A ; None ; 13.415 ns ; A7 ; CO ;
+; N/A ; None ; 13.184 ns ; A7 ; S7 ;
+; N/A ; None ; 13.004 ns ; A0 ; S0 ;
+; N/A ; None ; 12.799 ns ; CI ; S3 ;
+; N/A ; None ; 12.403 ns ; A6 ; S6 ;
+; N/A ; None ; 11.735 ns ; CI ; S2 ;
+; N/A ; None ; 10.321 ns ; CI ; S1 ;
+; N/A ; None ; 9.587 ns ; CI ; S0 ;
+-------+-------------------+-----------------+------+----+
@@ -204,24 +204,25 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
- Info: Processing started: Mon Mar 07 10:22:25 2022
+ Info: Processing started: Mon Mar 07 11:28:59 2022
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b --timing_analysis_only
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info: Longest tpd from source pin "A1" to destination pin "CO" is 19.344 ns
- Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_57; Fanout = 2; PIN Node = 'A1'
- Info: 2: + IC(6.202 ns) + CELL(0.651 ns) = 7.847 ns; Loc. = LCCOMB_X1_Y7_N12; Fanout = 4; COMB Node = '7400:inst8|4~0'
- Info: 3: + IC(0.391 ns) + CELL(0.206 ns) = 8.444 ns; Loc. = LCCOMB_X1_Y7_N8; Fanout = 2; COMB Node = '7400:inst13|4~1'
- Info: 4: + IC(0.387 ns) + CELL(0.370 ns) = 9.201 ns; Loc. = LCCOMB_X1_Y7_N4; Fanout = 2; COMB Node = '7400:inst18|4~0'
- Info: 5: + IC(0.387 ns) + CELL(0.370 ns) = 9.958 ns; Loc. = LCCOMB_X1_Y7_N6; Fanout = 2; COMB Node = '7400:inst23|4~9'
- Info: 6: + IC(0.412 ns) + CELL(0.650 ns) = 11.020 ns; Loc. = LCCOMB_X1_Y7_N0; Fanout = 3; COMB Node = '7400:inst28|4~0'
- Info: 7: + IC(1.736 ns) + CELL(0.206 ns) = 12.962 ns; Loc. = LCCOMB_X1_Y15_N24; Fanout = 2; COMB Node = '7400:inst33|4~0'
- Info: 8: + IC(0.396 ns) + CELL(0.651 ns) = 14.009 ns; Loc. = LCCOMB_X1_Y15_N4; Fanout = 1; COMB Node = '7400:inst38|4~0'
- Info: 9: + IC(2.039 ns) + CELL(3.296 ns) = 19.344 ns; Loc. = PIN_58; Fanout = 0; PIN Node = 'CO'
- Info: Total cell delay = 7.394 ns ( 38.22 % )
- Info: Total interconnect delay = 11.950 ns ( 61.78 % )
+Info: Longest tpd from source pin "B0" to destination pin "CO" is 22.018 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 2; PIN Node = 'B0'
+ Info: 2: + IC(6.491 ns) + CELL(0.624 ns) = 8.109 ns; Loc. = LCCOMB_X18_Y4_N2; Fanout = 2; COMB Node = '7400:inst3|4~1'
+ Info: 3: + IC(0.373 ns) + CELL(0.624 ns) = 9.106 ns; Loc. = LCCOMB_X18_Y4_N20; Fanout = 4; COMB Node = '7400:inst8|4~0'
+ Info: 4: + IC(0.407 ns) + CELL(0.370 ns) = 9.883 ns; Loc. = LCCOMB_X18_Y4_N16; Fanout = 2; COMB Node = '7400:inst13|4~1'
+ Info: 5: + IC(0.426 ns) + CELL(0.650 ns) = 10.959 ns; Loc. = LCCOMB_X18_Y4_N12; Fanout = 2; COMB Node = '7400:inst18|4~0'
+ Info: 6: + IC(0.408 ns) + CELL(0.650 ns) = 12.017 ns; Loc. = LCCOMB_X18_Y4_N30; Fanout = 2; COMB Node = '7400:inst23|4~9'
+ Info: 7: + IC(0.365 ns) + CELL(0.206 ns) = 12.588 ns; Loc. = LCCOMB_X18_Y4_N0; Fanout = 3; COMB Node = '7400:inst28|4~0'
+ Info: 8: + IC(2.636 ns) + CELL(0.370 ns) = 15.594 ns; Loc. = LCCOMB_X28_Y11_N26; Fanout = 2; COMB Node = '7400:inst33|4~1'
+ Info: 9: + IC(0.370 ns) + CELL(0.624 ns) = 16.588 ns; Loc. = LCCOMB_X28_Y11_N12; Fanout = 1; COMB Node = '7400:inst38|4~0'
+ Info: 10: + IC(2.150 ns) + CELL(3.280 ns) = 22.018 ns; Loc. = PIN_151; Fanout = 0; PIN Node = 'CO'
+ Info: Total cell delay = 8.392 ns ( 38.11 % )
+ Info: Total interconnect delay = 13.626 ns ( 61.89 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
- Info: Peak virtual memory: 212 megabytes
- Info: Processing ended: Mon Mar 07 10:22:25 2022
+ Info: Peak virtual memory: 213 megabytes
+ Info: Processing ended: Mon Mar 07 11:28:59 2022
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00
diff --git a/adder_8b/adder_8b.tan.summary b/adder_8b/adder_8b.tan.summary
index b333f61..31339f3 100644
--- a/adder_8b/adder_8b.tan.summary
+++ b/adder_8b/adder_8b.tan.summary
@@ -5,8 +5,8 @@ Timing Analyzer Summary
Type : Worst-case tpd
Slack : N/A
Required Time : None
-Actual Time : 19.344 ns
-From : A1
+Actual Time : 22.018 ns
+From : B0
To : CO
From Clock : --
To Clock : --
diff --git a/adder_8b/db/adder_8b.asm.qmsg b/adder_8b/db/adder_8b.asm.qmsg
index 3d63743..25f2d0b 100644
--- a/adder_8b/db/adder_8b.asm.qmsg
+++ b/adder_8b/db/adder_8b.asm.qmsg
@@ -1,7 +1,7 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:22:24 2022 " "Info: Processing started: Mon Mar 07 10:22:24 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:28:58 2022 " "Info: Processing started: Mon Mar 07 11:28:58 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "242 " "Info: Peak virtual memory: 242 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 10:22:24 2022 " "Info: Processing ended: Mon Mar 07 10:22:24 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "242 " "Info: Peak virtual memory: 242 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:28:58 2022 " "Info: Processing ended: Mon Mar 07 11:28:58 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/adder_8b/db/adder_8b.asm_labs.ddb b/adder_8b/db/adder_8b.asm_labs.ddb
index 94fd686..b001fb6 100644
Binary files a/adder_8b/db/adder_8b.asm_labs.ddb and b/adder_8b/db/adder_8b.asm_labs.ddb differ
diff --git a/adder_8b/db/adder_8b.cmp.bpm b/adder_8b/db/adder_8b.cmp.bpm
index 276f82b..333f8e9 100644
Binary files a/adder_8b/db/adder_8b.cmp.bpm and b/adder_8b/db/adder_8b.cmp.bpm differ
diff --git a/adder_8b/db/adder_8b.cmp.cdb b/adder_8b/db/adder_8b.cmp.cdb
index 4df6d6f..c5c753f 100644
Binary files a/adder_8b/db/adder_8b.cmp.cdb and b/adder_8b/db/adder_8b.cmp.cdb differ
diff --git a/adder_8b/db/adder_8b.cmp.hdb b/adder_8b/db/adder_8b.cmp.hdb
index ae45bbe..e5e14c8 100644
Binary files a/adder_8b/db/adder_8b.cmp.hdb and b/adder_8b/db/adder_8b.cmp.hdb differ
diff --git a/adder_8b/db/adder_8b.cmp.rdb b/adder_8b/db/adder_8b.cmp.rdb
index b417b27..e029167 100644
Binary files a/adder_8b/db/adder_8b.cmp.rdb and b/adder_8b/db/adder_8b.cmp.rdb differ
diff --git a/adder_8b/db/adder_8b.cmp.tdb b/adder_8b/db/adder_8b.cmp.tdb
index ee6d8e8..9302998 100644
Binary files a/adder_8b/db/adder_8b.cmp.tdb and b/adder_8b/db/adder_8b.cmp.tdb differ
diff --git a/adder_8b/db/adder_8b.cmp0.ddb b/adder_8b/db/adder_8b.cmp0.ddb
index bb7b0b3..50cd6fa 100644
Binary files a/adder_8b/db/adder_8b.cmp0.ddb and b/adder_8b/db/adder_8b.cmp0.ddb differ
diff --git a/adder_8b/db/adder_8b.cmp2.ddb b/adder_8b/db/adder_8b.cmp2.ddb
index 0a3ce14..a275f51 100644
Binary files a/adder_8b/db/adder_8b.cmp2.ddb and b/adder_8b/db/adder_8b.cmp2.ddb differ
diff --git a/adder_8b/db/adder_8b.fit.qmsg b/adder_8b/db/adder_8b.fit.qmsg
index 5e266ed..dccb36a 100644
--- a/adder_8b/db/adder_8b.fit.qmsg
+++ b/adder_8b/db/adder_8b.fit.qmsg
@@ -1,5 +1,5 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:22:22 2022 " "Info: Processing started: Mon Mar 07 10:22:22 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:28:56 2022 " "Info: Processing started: Mon Mar 07 11:28:56 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "IMPP_MPP_USER_DEVICE" "adder_8b EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"adder_8b\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
@@ -8,7 +8,6 @@
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
-{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "26 26 " "Warning: No exact pin location assignment(s) for 26 pins of 26 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CO " "Info: Pin CO not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { CO } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 32 504 680 48 "CO" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CO } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S7 " "Info: Pin S7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S7 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 64 504 680 80 "S7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S0 " "Info: Pin S0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S0 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2120 504 680 2136 "S0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S1 " "Info: Pin S1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S1 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1840 504 680 1856 "S1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S2 " "Info: Pin S2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S2 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1544 504 680 1560 "S2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S3 " "Info: Pin S3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S3 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1248 504 680 1264 "S3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S4 " "Info: Pin S4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S4 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 952 504 680 968 "S4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S5 " "Info: Pin S5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S5 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 656 504 680 672 "S5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S6 " "Info: Pin S6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S6 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 360 504 680 376 "S6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A6 " "Info: Pin A6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A6 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 344 48 216 360 "A6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A3 " "Info: Pin A3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A3 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1232 48 216 1248 "A3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B3 " "Info: Pin B3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B3 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1248 48 216 1264 "B3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A4 " "Info: Pin A4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A4 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 936 48 216 952 "A4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A2 " "Info: Pin A2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A2 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1528 48 216 1544 "A2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A0 " "Info: Pin A0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A0 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2104 48 216 2120 "A0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CI " "Info: Pin CI not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { CI } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2136 48 216 2152 "CI" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CI } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B0 " "Info: Pin B0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B0 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2120 48 216 2136 "B0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A1 " "Info: Pin A1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A1 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1824 48 216 1840 "A1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B1 " "Info: Pin B1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B1 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1840 48 216 1856 "B1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B2 " "Info: Pin B2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B2 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1544 48 216 1560 "B2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B4 " "Info: Pin B4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B4 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 952 48 216 968 "B4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A5 " "Info: Pin A5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A5 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 640 48 216 656 "A5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B5 " "Info: Pin B5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B5 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 656 48 216 672 "B5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B6 " "Info: Pin B6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B6 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 360 48 216 376 "B6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A7 " "Info: Pin A7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A7 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 48 48 216 64 "A7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B7 " "Info: Pin B7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B7 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 64 48 216 80 "B7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
@@ -19,8 +18,6 @@
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
-{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "26 unused 3.3V 17 9 0 " "Info: Number of I/O pins in group: 26 (unused VREF, 3.3V VCCIO, 17 input, 9 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
-{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 2 30 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 35 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 34 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 36 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
@@ -28,12 +25,11 @@
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X10_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X11_Y0 X22_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X22_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "9 " "Warning: Found 9 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "CO 0 " "Info: Pin \"CO\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S7 0 " "Info: Pin \"S7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S0 0 " "Info: Pin \"S0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S1 0 " "Info: Pin \"S1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S2 0 " "Info: Pin \"S2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S3 0 " "Info: Pin \"S3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S4 0 " "Info: Pin \"S4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S5 0 " "Info: Pin \"S5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S6 0 " "Info: Pin \"S6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
-{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/adder_8b/adder_8b.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/adder_8b/adder_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "305 " "Info: Peak virtual memory: 305 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 10:22:23 2022 " "Info: Processing ended: Mon Mar 07 10:22:23 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "305 " "Info: Peak virtual memory: 305 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:28:57 2022 " "Info: Processing ended: Mon Mar 07 11:28:57 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/adder_8b/db/adder_8b.map.bpm b/adder_8b/db/adder_8b.map.bpm
index d76aff7..6b400b8 100644
Binary files a/adder_8b/db/adder_8b.map.bpm and b/adder_8b/db/adder_8b.map.bpm differ
diff --git a/adder_8b/db/adder_8b.map.cdb b/adder_8b/db/adder_8b.map.cdb
index abed25c..e55bf57 100644
Binary files a/adder_8b/db/adder_8b.map.cdb and b/adder_8b/db/adder_8b.map.cdb differ
diff --git a/adder_8b/db/adder_8b.map.hdb b/adder_8b/db/adder_8b.map.hdb
index 08f1806..c639357 100644
Binary files a/adder_8b/db/adder_8b.map.hdb and b/adder_8b/db/adder_8b.map.hdb differ
diff --git a/adder_8b/db/adder_8b.map.qmsg b/adder_8b/db/adder_8b.map.qmsg
index ca9ca77..a0e05b9 100644
--- a/adder_8b/db/adder_8b.map.qmsg
+++ b/adder_8b/db/adder_8b.map.qmsg
@@ -1,5 +1,5 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:22:20 2022 " "Info: Processing started: Mon Mar 07 10:22:20 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:28:54 2022 " "Info: Processing started: Mon Mar 07 11:28:54 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off adder_8b -c adder_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adder_8b -c adder_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adder_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file adder_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 adder_8b " "Info: Found entity 1: adder_8b" { } { { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "adder_8b " "Info: Elaborating entity \"adder_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
@@ -8,4 +8,4 @@
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7486 7486:inst " "Info: Elaborating entity \"7486\" for hierarchy \"7486:inst\"" { } { { "adder_8b.bdf" "inst" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2096 272 336 2136 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "7486:inst " "Info: Elaborated megafunction instantiation \"7486:inst\"" { } { { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2096 272 336 2136 "inst" "" } } } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "47 " "Info: Implemented 47 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "17 " "Info: Implemented 17 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Info: Implemented 9 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "21 " "Info: Implemented 21 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "248 " "Info: Peak virtual memory: 248 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 10:22:21 2022 " "Info: Processing ended: Mon Mar 07 10:22:21 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:28:55 2022 " "Info: Processing ended: Mon Mar 07 11:28:55 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/adder_8b/db/adder_8b.map_bb.cdb b/adder_8b/db/adder_8b.map_bb.cdb
index dc5ba25..90e0434 100644
Binary files a/adder_8b/db/adder_8b.map_bb.cdb and b/adder_8b/db/adder_8b.map_bb.cdb differ
diff --git a/adder_8b/db/adder_8b.map_bb.hdb b/adder_8b/db/adder_8b.map_bb.hdb
index ae9b438..fb153dc 100644
Binary files a/adder_8b/db/adder_8b.map_bb.hdb and b/adder_8b/db/adder_8b.map_bb.hdb differ
diff --git a/adder_8b/db/adder_8b.pre_map.cdb b/adder_8b/db/adder_8b.pre_map.cdb
index fdbc9eb..6d220fc 100644
Binary files a/adder_8b/db/adder_8b.pre_map.cdb and b/adder_8b/db/adder_8b.pre_map.cdb differ
diff --git a/adder_8b/db/adder_8b.pre_map.hdb b/adder_8b/db/adder_8b.pre_map.hdb
index a39219f..70558d1 100644
Binary files a/adder_8b/db/adder_8b.pre_map.hdb and b/adder_8b/db/adder_8b.pre_map.hdb differ
diff --git a/adder_8b/db/adder_8b.rtlv.hdb b/adder_8b/db/adder_8b.rtlv.hdb
index f76d237..b908ac5 100644
Binary files a/adder_8b/db/adder_8b.rtlv.hdb and b/adder_8b/db/adder_8b.rtlv.hdb differ
diff --git a/adder_8b/db/adder_8b.rtlv_sg.cdb b/adder_8b/db/adder_8b.rtlv_sg.cdb
index f1be617..6f1ac1e 100644
Binary files a/adder_8b/db/adder_8b.rtlv_sg.cdb and b/adder_8b/db/adder_8b.rtlv_sg.cdb differ
diff --git a/adder_8b/db/adder_8b.rtlv_sg_swap.cdb b/adder_8b/db/adder_8b.rtlv_sg_swap.cdb
index 7e46c61..1459f59 100644
Binary files a/adder_8b/db/adder_8b.rtlv_sg_swap.cdb and b/adder_8b/db/adder_8b.rtlv_sg_swap.cdb differ
diff --git a/adder_8b/db/adder_8b.sgdiff.cdb b/adder_8b/db/adder_8b.sgdiff.cdb
index 2ebafb3..c6d7ce3 100644
Binary files a/adder_8b/db/adder_8b.sgdiff.cdb and b/adder_8b/db/adder_8b.sgdiff.cdb differ
diff --git a/adder_8b/db/adder_8b.sgdiff.hdb b/adder_8b/db/adder_8b.sgdiff.hdb
index e10e311..50a3264 100644
Binary files a/adder_8b/db/adder_8b.sgdiff.hdb and b/adder_8b/db/adder_8b.sgdiff.hdb differ
diff --git a/adder_8b/db/adder_8b.tan.qmsg b/adder_8b/db/adder_8b.tan.qmsg
index 14356c5..22927b9 100644
--- a/adder_8b/db/adder_8b.tan.qmsg
+++ b/adder_8b/db/adder_8b.tan.qmsg
@@ -1,6 +1,6 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:22:25 2022 " "Info: Processing started: Mon Mar 07 10:22:25 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:28:59 2022 " "Info: Processing started: Mon Mar 07 11:28:59 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
-{ "Info" "ITDB_FULL_TPD_RESULT" "A1 CO 19.344 ns Longest " "Info: Longest tpd from source pin \"A1\" to destination pin \"CO\" is 19.344 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns A1 1 PIN PIN_57 2 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_57; Fanout = 2; PIN Node = 'A1'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A1 } "NODE_NAME" } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1824 48 216 1840 "A1" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.202 ns) + CELL(0.651 ns) 7.847 ns 7400:inst8\|4~0 2 COMB LCCOMB_X1_Y7_N12 4 " "Info: 2: + IC(6.202 ns) + CELL(0.651 ns) = 7.847 ns; Loc. = LCCOMB_X1_Y7_N12; Fanout = 4; COMB Node = '7400:inst8\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.853 ns" { A1 7400:inst8|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.391 ns) + CELL(0.206 ns) 8.444 ns 7400:inst13\|4~1 3 COMB LCCOMB_X1_Y7_N8 2 " "Info: 3: + IC(0.391 ns) + CELL(0.206 ns) = 8.444 ns; Loc. = LCCOMB_X1_Y7_N8; Fanout = 2; COMB Node = '7400:inst13\|4~1'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.597 ns" { 7400:inst8|4~0 7400:inst13|4~1 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.387 ns) + CELL(0.370 ns) 9.201 ns 7400:inst18\|4~0 4 COMB LCCOMB_X1_Y7_N4 2 " "Info: 4: + IC(0.387 ns) + CELL(0.370 ns) = 9.201 ns; Loc. = LCCOMB_X1_Y7_N4; Fanout = 2; COMB Node = '7400:inst18\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.757 ns" { 7400:inst13|4~1 7400:inst18|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.387 ns) + CELL(0.370 ns) 9.958 ns 7400:inst23\|4~9 5 COMB LCCOMB_X1_Y7_N6 2 " "Info: 5: + IC(0.387 ns) + CELL(0.370 ns) = 9.958 ns; Loc. = LCCOMB_X1_Y7_N6; Fanout = 2; COMB Node = '7400:inst23\|4~9'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.757 ns" { 7400:inst18|4~0 7400:inst23|4~9 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.412 ns) + CELL(0.650 ns) 11.020 ns 7400:inst28\|4~0 6 COMB LCCOMB_X1_Y7_N0 3 " "Info: 6: + IC(0.412 ns) + CELL(0.650 ns) = 11.020 ns; Loc. = LCCOMB_X1_Y7_N0; Fanout = 3; COMB Node = '7400:inst28\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.062 ns" { 7400:inst23|4~9 7400:inst28|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.736 ns) + CELL(0.206 ns) 12.962 ns 7400:inst33\|4~0 7 COMB LCCOMB_X1_Y15_N24 2 " "Info: 7: + IC(1.736 ns) + CELL(0.206 ns) = 12.962 ns; Loc. = LCCOMB_X1_Y15_N24; Fanout = 2; COMB Node = '7400:inst33\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.942 ns" { 7400:inst28|4~0 7400:inst33|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.396 ns) + CELL(0.651 ns) 14.009 ns 7400:inst38\|4~0 8 COMB LCCOMB_X1_Y15_N4 1 " "Info: 8: + IC(0.396 ns) + CELL(0.651 ns) = 14.009 ns; Loc. = LCCOMB_X1_Y15_N4; Fanout = 1; COMB Node = '7400:inst38\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.047 ns" { 7400:inst33|4~0 7400:inst38|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.039 ns) + CELL(3.296 ns) 19.344 ns CO 9 PIN PIN_58 0 " "Info: 9: + IC(2.039 ns) + CELL(3.296 ns) = 19.344 ns; Loc. = PIN_58; Fanout = 0; PIN Node = 'CO'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.335 ns" { 7400:inst38|4~0 CO } "NODE_NAME" } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 32 504 680 48 "CO" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.394 ns ( 38.22 % ) " "Info: Total cell delay = 7.394 ns ( 38.22 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "11.950 ns ( 61.78 % ) " "Info: Total interconnect delay = 11.950 ns ( 61.78 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "19.344 ns" { A1 7400:inst8|4~0 7400:inst13|4~1 7400:inst18|4~0 7400:inst23|4~9 7400:inst28|4~0 7400:inst33|4~0 7400:inst38|4~0 CO } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "19.344 ns" { A1 {} A1~combout {} 7400:inst8|4~0 {} 7400:inst13|4~1 {} 7400:inst18|4~0 {} 7400:inst23|4~9 {} 7400:inst28|4~0 {} 7400:inst33|4~0 {} 7400:inst38|4~0 {} CO {} } { 0.000ns 0.000ns 6.202ns 0.391ns 0.387ns 0.387ns 0.412ns 1.736ns 0.396ns 2.039ns } { 0.000ns 0.994ns 0.651ns 0.206ns 0.370ns 0.370ns 0.650ns 0.206ns 0.651ns 3.296ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 10:22:25 2022 " "Info: Processing ended: Mon Mar 07 10:22:25 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TPD_RESULT" "B0 CO 22.018 ns Longest " "Info: Longest tpd from source pin \"B0\" to destination pin \"CO\" is 22.018 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns B0 1 PIN PIN_67 2 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 2; PIN Node = 'B0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B0 } "NODE_NAME" } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2120 48 216 2136 "B0" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.491 ns) + CELL(0.624 ns) 8.109 ns 7400:inst3\|4~1 2 COMB LCCOMB_X18_Y4_N2 2 " "Info: 2: + IC(6.491 ns) + CELL(0.624 ns) = 8.109 ns; Loc. = LCCOMB_X18_Y4_N2; Fanout = 2; COMB Node = '7400:inst3\|4~1'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.115 ns" { B0 7400:inst3|4~1 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.373 ns) + CELL(0.624 ns) 9.106 ns 7400:inst8\|4~0 3 COMB LCCOMB_X18_Y4_N20 4 " "Info: 3: + IC(0.373 ns) + CELL(0.624 ns) = 9.106 ns; Loc. = LCCOMB_X18_Y4_N20; Fanout = 4; COMB Node = '7400:inst8\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.997 ns" { 7400:inst3|4~1 7400:inst8|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.407 ns) + CELL(0.370 ns) 9.883 ns 7400:inst13\|4~1 4 COMB LCCOMB_X18_Y4_N16 2 " "Info: 4: + IC(0.407 ns) + CELL(0.370 ns) = 9.883 ns; Loc. = LCCOMB_X18_Y4_N16; Fanout = 2; COMB Node = '7400:inst13\|4~1'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.777 ns" { 7400:inst8|4~0 7400:inst13|4~1 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.426 ns) + CELL(0.650 ns) 10.959 ns 7400:inst18\|4~0 5 COMB LCCOMB_X18_Y4_N12 2 " "Info: 5: + IC(0.426 ns) + CELL(0.650 ns) = 10.959 ns; Loc. = LCCOMB_X18_Y4_N12; Fanout = 2; COMB Node = '7400:inst18\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.076 ns" { 7400:inst13|4~1 7400:inst18|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.408 ns) + CELL(0.650 ns) 12.017 ns 7400:inst23\|4~9 6 COMB LCCOMB_X18_Y4_N30 2 " "Info: 6: + IC(0.408 ns) + CELL(0.650 ns) = 12.017 ns; Loc. = LCCOMB_X18_Y4_N30; Fanout = 2; COMB Node = '7400:inst23\|4~9'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.058 ns" { 7400:inst18|4~0 7400:inst23|4~9 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.206 ns) 12.588 ns 7400:inst28\|4~0 7 COMB LCCOMB_X18_Y4_N0 3 " "Info: 7: + IC(0.365 ns) + CELL(0.206 ns) = 12.588 ns; Loc. = LCCOMB_X18_Y4_N0; Fanout = 3; COMB Node = '7400:inst28\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.571 ns" { 7400:inst23|4~9 7400:inst28|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.636 ns) + CELL(0.370 ns) 15.594 ns 7400:inst33\|4~1 8 COMB LCCOMB_X28_Y11_N26 2 " "Info: 8: + IC(2.636 ns) + CELL(0.370 ns) = 15.594 ns; Loc. = LCCOMB_X28_Y11_N26; Fanout = 2; COMB Node = '7400:inst33\|4~1'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.006 ns" { 7400:inst28|4~0 7400:inst33|4~1 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.370 ns) + CELL(0.624 ns) 16.588 ns 7400:inst38\|4~0 9 COMB LCCOMB_X28_Y11_N12 1 " "Info: 9: + IC(0.370 ns) + CELL(0.624 ns) = 16.588 ns; Loc. = LCCOMB_X28_Y11_N12; Fanout = 1; COMB Node = '7400:inst38\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.994 ns" { 7400:inst33|4~1 7400:inst38|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.150 ns) + CELL(3.280 ns) 22.018 ns CO 10 PIN PIN_151 0 " "Info: 10: + IC(2.150 ns) + CELL(3.280 ns) = 22.018 ns; Loc. = PIN_151; Fanout = 0; PIN Node = 'CO'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.430 ns" { 7400:inst38|4~0 CO } "NODE_NAME" } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 32 504 680 48 "CO" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.392 ns ( 38.11 % ) " "Info: Total cell delay = 8.392 ns ( 38.11 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "13.626 ns ( 61.89 % ) " "Info: Total interconnect delay = 13.626 ns ( 61.89 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "22.018 ns" { B0 7400:inst3|4~1 7400:inst8|4~0 7400:inst13|4~1 7400:inst18|4~0 7400:inst23|4~9 7400:inst28|4~0 7400:inst33|4~1 7400:inst38|4~0 CO } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "22.018 ns" { B0 {} B0~combout {} 7400:inst3|4~1 {} 7400:inst8|4~0 {} 7400:inst13|4~1 {} 7400:inst18|4~0 {} 7400:inst23|4~9 {} 7400:inst28|4~0 {} 7400:inst33|4~1 {} 7400:inst38|4~0 {} CO {} } { 0.000ns 0.000ns 6.491ns 0.373ns 0.407ns 0.426ns 0.408ns 0.365ns 2.636ns 0.370ns 2.150ns } { 0.000ns 0.994ns 0.624ns 0.624ns 0.370ns 0.650ns 0.650ns 0.206ns 0.370ns 0.624ns 3.280ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "213 " "Info: Peak virtual memory: 213 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:28:59 2022 " "Info: Processing ended: Mon Mar 07 11:28:59 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/data_selector/db/data_selector.asm.qmsg b/adder_8b/db/prev_cmp_adder_8b.asm.qmsg
similarity index 61%
rename from data_selector/db/data_selector.asm.qmsg
rename to adder_8b/db/prev_cmp_adder_8b.asm.qmsg
index ff61c95..3d63743 100644
--- a/data_selector/db/data_selector.asm.qmsg
+++ b/adder_8b/db/prev_cmp_adder_8b.asm.qmsg
@@ -1,7 +1,7 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 06 21:29:30 2022 " "Info: Processing started: Sun Mar 06 21:29:30 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off data_selector -c data_selector " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off data_selector -c data_selector" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:22:24 2022 " "Info: Processing started: Mon Mar 07 10:22:24 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "221 " "Info: Peak virtual memory: 221 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 06 21:29:31 2022 " "Info: Processing ended: Sun Mar 06 21:29:31 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "242 " "Info: Peak virtual memory: 242 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 10:22:24 2022 " "Info: Processing ended: Mon Mar 07 10:22:24 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/adder_8b/db/prev_cmp_adder_8b.fit.qmsg b/adder_8b/db/prev_cmp_adder_8b.fit.qmsg
new file mode 100644
index 0000000..5e266ed
--- /dev/null
+++ b/adder_8b/db/prev_cmp_adder_8b.fit.qmsg
@@ -0,0 +1,39 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:22:22 2022 " "Info: Processing started: Mon Mar 07 10:22:22 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "IMPP_MPP_USER_DEVICE" "adder_8b EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"adder_8b\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "26 26 " "Warning: No exact pin location assignment(s) for 26 pins of 26 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CO " "Info: Pin CO not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { CO } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 32 504 680 48 "CO" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CO } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S7 " "Info: Pin S7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S7 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 64 504 680 80 "S7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S0 " "Info: Pin S0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S0 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2120 504 680 2136 "S0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S1 " "Info: Pin S1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S1 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1840 504 680 1856 "S1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S2 " "Info: Pin S2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S2 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1544 504 680 1560 "S2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S3 " "Info: Pin S3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S3 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1248 504 680 1264 "S3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S4 " "Info: Pin S4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S4 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 952 504 680 968 "S4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S5 " "Info: Pin S5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S5 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 656 504 680 672 "S5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S6 " "Info: Pin S6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S6 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 360 504 680 376 "S6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A6 " "Info: Pin A6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A6 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 344 48 216 360 "A6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A3 " "Info: Pin A3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A3 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1232 48 216 1248 "A3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B3 " "Info: Pin B3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B3 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1248 48 216 1264 "B3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A4 " "Info: Pin A4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A4 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 936 48 216 952 "A4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A2 " "Info: Pin A2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A2 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1528 48 216 1544 "A2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A0 " "Info: Pin A0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A0 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2104 48 216 2120 "A0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CI " "Info: Pin CI not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { CI } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2136 48 216 2152 "CI" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CI } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B0 " "Info: Pin B0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B0 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2120 48 216 2136 "B0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A1 " "Info: Pin A1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A1 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1824 48 216 1840 "A1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B1 " "Info: Pin B1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B1 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1840 48 216 1856 "B1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B2 " "Info: Pin B2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B2 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1544 48 216 1560 "B2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B4 " "Info: Pin B4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B4 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 952 48 216 968 "B4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A5 " "Info: Pin A5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A5 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 640 48 216 656 "A5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B5 " "Info: Pin B5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B5 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 656 48 216 672 "B5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B6 " "Info: Pin B6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B6 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 360 48 216 376 "B6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A7 " "Info: Pin A7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A7 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 48 48 216 64 "A7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B7 " "Info: Pin B7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B7 } } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 64 48 216 80 "B7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
+{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
+{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "26 unused 3.3V 17 9 0 " "Info: Number of I/O pins in group: 26 (unused VREF, 3.3V VCCIO, 17 input, 9 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 2 30 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 35 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 34 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 36 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X10_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
+{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "9 " "Warning: Found 9 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "CO 0 " "Info: Pin \"CO\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S7 0 " "Info: Pin \"S7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S0 0 " "Info: Pin \"S0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S1 0 " "Info: Pin \"S1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S2 0 " "Info: Pin \"S2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S3 0 " "Info: Pin \"S3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S4 0 " "Info: Pin \"S4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S5 0 " "Info: Pin \"S5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S6 0 " "Info: Pin \"S6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/adder_8b/adder_8b.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/adder_8b/adder_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "305 " "Info: Peak virtual memory: 305 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 10:22:23 2022 " "Info: Processing ended: Mon Mar 07 10:22:23 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/adder_8b/db/prev_cmp_adder_8b.map.qmsg b/adder_8b/db/prev_cmp_adder_8b.map.qmsg
new file mode 100644
index 0000000..ca9ca77
--- /dev/null
+++ b/adder_8b/db/prev_cmp_adder_8b.map.qmsg
@@ -0,0 +1,11 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:22:20 2022 " "Info: Processing started: Mon Mar 07 10:22:20 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off adder_8b -c adder_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adder_8b -c adder_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adder_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file adder_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 adder_8b " "Info: Found entity 1: adder_8b" { } { { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_TOP" "adder_8b " "Info: Elaborating entity \"adder_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7400 7400:inst38 " "Info: Elaborating entity \"7400\" for hierarchy \"7400:inst38\"" { } { { "adder_8b.bdf" "inst38" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 184 400 464 224 "inst38" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_ELABORATION_HEADER" "7400:inst38 " "Info: Elaborated megafunction instantiation \"7400:inst38\"" { } { { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 184 400 464 224 "inst38" "" } } } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7486 7486:inst " "Info: Elaborating entity \"7486\" for hierarchy \"7486:inst\"" { } { { "adder_8b.bdf" "inst" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2096 272 336 2136 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_ELABORATION_HEADER" "7486:inst " "Info: Elaborated megafunction instantiation \"7486:inst\"" { } { { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 2096 272 336 2136 "inst" "" } } } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "47 " "Info: Implemented 47 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "17 " "Info: Implemented 17 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Info: Implemented 9 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "21 " "Info: Implemented 21 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "248 " "Info: Peak virtual memory: 248 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 10:22:21 2022 " "Info: Processing ended: Mon Mar 07 10:22:21 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/adder_8b/db/prev_cmp_adder_8b.tan.qmsg b/adder_8b/db/prev_cmp_adder_8b.tan.qmsg
new file mode 100644
index 0000000..14356c5
--- /dev/null
+++ b/adder_8b/db/prev_cmp_adder_8b.tan.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:22:25 2022 " "Info: Processing started: Mon Mar 07 10:22:25 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off adder_8b -c adder_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TPD_RESULT" "A1 CO 19.344 ns Longest " "Info: Longest tpd from source pin \"A1\" to destination pin \"CO\" is 19.344 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns A1 1 PIN PIN_57 2 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_57; Fanout = 2; PIN Node = 'A1'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A1 } "NODE_NAME" } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 1824 48 216 1840 "A1" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.202 ns) + CELL(0.651 ns) 7.847 ns 7400:inst8\|4~0 2 COMB LCCOMB_X1_Y7_N12 4 " "Info: 2: + IC(6.202 ns) + CELL(0.651 ns) = 7.847 ns; Loc. = LCCOMB_X1_Y7_N12; Fanout = 4; COMB Node = '7400:inst8\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.853 ns" { A1 7400:inst8|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.391 ns) + CELL(0.206 ns) 8.444 ns 7400:inst13\|4~1 3 COMB LCCOMB_X1_Y7_N8 2 " "Info: 3: + IC(0.391 ns) + CELL(0.206 ns) = 8.444 ns; Loc. = LCCOMB_X1_Y7_N8; Fanout = 2; COMB Node = '7400:inst13\|4~1'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.597 ns" { 7400:inst8|4~0 7400:inst13|4~1 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.387 ns) + CELL(0.370 ns) 9.201 ns 7400:inst18\|4~0 4 COMB LCCOMB_X1_Y7_N4 2 " "Info: 4: + IC(0.387 ns) + CELL(0.370 ns) = 9.201 ns; Loc. = LCCOMB_X1_Y7_N4; Fanout = 2; COMB Node = '7400:inst18\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.757 ns" { 7400:inst13|4~1 7400:inst18|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.387 ns) + CELL(0.370 ns) 9.958 ns 7400:inst23\|4~9 5 COMB LCCOMB_X1_Y7_N6 2 " "Info: 5: + IC(0.387 ns) + CELL(0.370 ns) = 9.958 ns; Loc. = LCCOMB_X1_Y7_N6; Fanout = 2; COMB Node = '7400:inst23\|4~9'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.757 ns" { 7400:inst18|4~0 7400:inst23|4~9 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.412 ns) + CELL(0.650 ns) 11.020 ns 7400:inst28\|4~0 6 COMB LCCOMB_X1_Y7_N0 3 " "Info: 6: + IC(0.412 ns) + CELL(0.650 ns) = 11.020 ns; Loc. = LCCOMB_X1_Y7_N0; Fanout = 3; COMB Node = '7400:inst28\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.062 ns" { 7400:inst23|4~9 7400:inst28|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.736 ns) + CELL(0.206 ns) 12.962 ns 7400:inst33\|4~0 7 COMB LCCOMB_X1_Y15_N24 2 " "Info: 7: + IC(1.736 ns) + CELL(0.206 ns) = 12.962 ns; Loc. = LCCOMB_X1_Y15_N24; Fanout = 2; COMB Node = '7400:inst33\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.942 ns" { 7400:inst28|4~0 7400:inst33|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.396 ns) + CELL(0.651 ns) 14.009 ns 7400:inst38\|4~0 8 COMB LCCOMB_X1_Y15_N4 1 " "Info: 8: + IC(0.396 ns) + CELL(0.651 ns) = 14.009 ns; Loc. = LCCOMB_X1_Y15_N4; Fanout = 1; COMB Node = '7400:inst38\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.047 ns" { 7400:inst33|4~0 7400:inst38|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.039 ns) + CELL(3.296 ns) 19.344 ns CO 9 PIN PIN_58 0 " "Info: 9: + IC(2.039 ns) + CELL(3.296 ns) = 19.344 ns; Loc. = PIN_58; Fanout = 0; PIN Node = 'CO'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.335 ns" { 7400:inst38|4~0 CO } "NODE_NAME" } } { "adder_8b.bdf" "" { Schematic "D:/projects/quartus/adder_8b/adder_8b.bdf" { { 32 504 680 48 "CO" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.394 ns ( 38.22 % ) " "Info: Total cell delay = 7.394 ns ( 38.22 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "11.950 ns ( 61.78 % ) " "Info: Total interconnect delay = 11.950 ns ( 61.78 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "19.344 ns" { A1 7400:inst8|4~0 7400:inst13|4~1 7400:inst18|4~0 7400:inst23|4~9 7400:inst28|4~0 7400:inst33|4~0 7400:inst38|4~0 CO } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "19.344 ns" { A1 {} A1~combout {} 7400:inst8|4~0 {} 7400:inst13|4~1 {} 7400:inst18|4~0 {} 7400:inst23|4~9 {} 7400:inst28|4~0 {} 7400:inst33|4~0 {} 7400:inst38|4~0 {} CO {} } { 0.000ns 0.000ns 6.202ns 0.391ns 0.387ns 0.387ns 0.412ns 1.736ns 0.396ns 2.039ns } { 0.000ns 0.994ns 0.651ns 0.206ns 0.370ns 0.370ns 0.650ns 0.206ns 0.651ns 3.296ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 10:22:25 2022 " "Info: Processing ended: Mon Mar 07 10:22:25 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.atm b/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.atm
index ddb4508..75f3669 100644
Binary files a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.atm and b/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.atm differ
diff --git a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.hdbx b/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.hdbx
index 88453f0..94b88f3 100644
Binary files a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.hdbx and b/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.hdbx differ
diff --git a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.rcf b/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.rcf
index f60c384..0b52b28 100644
Binary files a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.rcf and b/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.cmp.rcf differ
diff --git a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.map.atm b/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.map.atm
index 7ae03df..9f52d79 100644
Binary files a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.map.atm and b/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.map.atm differ
diff --git a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.map.hdbx b/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.map.hdbx
index 06f8fcd..f47544c 100644
Binary files a/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.map.hdbx and b/adder_8b/incremental_db/compiled_partitions/adder_8b.root_partition.map.hdbx differ
diff --git a/data_selector/data_selector.done b/data_selector/data_selector.done
deleted file mode 100644
index a8b8ebc..0000000
--- a/data_selector/data_selector.done
+++ /dev/null
@@ -1 +0,0 @@
-Sun Mar 06 21:30:44 2022
diff --git a/data_selector/data_selector.eda.rpt b/data_selector/data_selector.eda.rpt
deleted file mode 100644
index e9f55eb..0000000
--- a/data_selector/data_selector.eda.rpt
+++ /dev/null
@@ -1,59 +0,0 @@
-EDA Netlist Writer report for data_selector
-Sun Mar 06 21:30:44 2022
-Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. EDA Netlist Writer Summary
- 3. EDA Netlist Writer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2009 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, Altera MegaCore Function License
-Agreement, or other applicable license agreement, including,
-without limitation, that your use is for the sole purpose of
-programming logic devices manufactured by Altera and sold by
-Altera or its authorized distributors. Please refer to the
-applicable agreement for further details.
-
-
-
-+----------------------------------------------------------------------------------+
-; EDA Netlist Writer Summary ;
-+---------------------------+------------------------------------------------------+
-; EDA Netlist Writer Status ; No Output Files Generated - Sun Mar 06 21:30:44 2022 ;
-; Revision Name ; data_selector ;
-; Top-level Entity Name ; data_selector ;
-; Family ; Cyclone II ;
-+---------------------------+------------------------------------------------------+
-
-
-+-----------------------------+
-; EDA Netlist Writer Messages ;
-+-----------------------------+
-Info: *******************************************************************
-Info: Running Quartus II EDA Netlist Writer
- Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
- Info: Processing started: Sun Mar 06 21:30:43 2022
-Info: Command: quartus_eda --read_settings_files=on --write_settings_files=off data_selector -c data_selector
-Warning: Can't generate output files. Specify command-line options to generate output files, or update EDA tool settings using GUI or Tcl script.
-Info: Quartus II EDA Netlist Writer was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 167 megabytes
- Info: Processing ended: Sun Mar 06 21:30:44 2022
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:00
-
-
diff --git a/data_selector/db/data_selector.(0).cnf.hdb b/data_selector/db/data_selector.(0).cnf.hdb
deleted file mode 100644
index 0bbc5cb..0000000
Binary files a/data_selector/db/data_selector.(0).cnf.hdb and /dev/null differ
diff --git a/data_selector/db/data_selector.asm_labs.ddb b/data_selector/db/data_selector.asm_labs.ddb
deleted file mode 100644
index d733dcb..0000000
Binary files a/data_selector/db/data_selector.asm_labs.ddb and /dev/null differ
diff --git a/data_selector/db/data_selector.cmp.bpm b/data_selector/db/data_selector.cmp.bpm
deleted file mode 100644
index 27276f8..0000000
Binary files a/data_selector/db/data_selector.cmp.bpm and /dev/null differ
diff --git a/data_selector/db/data_selector.cmp.cdb b/data_selector/db/data_selector.cmp.cdb
deleted file mode 100644
index e4cd8a4..0000000
Binary files a/data_selector/db/data_selector.cmp.cdb and /dev/null differ
diff --git a/data_selector/db/data_selector.cmp.hdb b/data_selector/db/data_selector.cmp.hdb
deleted file mode 100644
index b7d744c..0000000
Binary files a/data_selector/db/data_selector.cmp.hdb and /dev/null differ
diff --git a/data_selector/db/data_selector.cmp.rdb b/data_selector/db/data_selector.cmp.rdb
deleted file mode 100644
index 4140176..0000000
Binary files a/data_selector/db/data_selector.cmp.rdb and /dev/null differ
diff --git a/data_selector/db/data_selector.cmp.tdb b/data_selector/db/data_selector.cmp.tdb
deleted file mode 100644
index c9c92e7..0000000
Binary files a/data_selector/db/data_selector.cmp.tdb and /dev/null differ
diff --git a/data_selector/db/data_selector.cmp0.ddb b/data_selector/db/data_selector.cmp0.ddb
deleted file mode 100644
index 05f408a..0000000
Binary files a/data_selector/db/data_selector.cmp0.ddb and /dev/null differ
diff --git a/data_selector/db/data_selector.cmp2.ddb b/data_selector/db/data_selector.cmp2.ddb
deleted file mode 100644
index 79a1b01..0000000
Binary files a/data_selector/db/data_selector.cmp2.ddb and /dev/null differ
diff --git a/data_selector/db/data_selector.eda.qmsg b/data_selector/db/data_selector.eda.qmsg
deleted file mode 100644
index 7bf8953..0000000
--- a/data_selector/db/data_selector.eda.qmsg
+++ /dev/null
@@ -1,5 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II " "Info: Running Quartus II EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 06 21:30:43 2022 " "Info: Processing started: Sun Mar 06 21:30:43 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=on --write_settings_files=off data_selector -c data_selector " "Info: Command: quartus_eda --read_settings_files=on --write_settings_files=off data_selector -c data_selector" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
-{ "Warning" "WQNETO_NO_OUTPUT_FILES" "" "Warning: Can't generate output files. Specify command-line options to generate output files, or update EDA tool settings using GUI or Tcl script." { } { } 0 0 "Can't generate output files. Specify command-line options to generate output files, or update EDA tool settings using GUI or Tcl script." 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus II " "Info: Quartus II EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "167 " "Info: Peak virtual memory: 167 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 06 21:30:44 2022 " "Info: Processing ended: Sun Mar 06 21:30:44 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/data_selector/db/data_selector.fit.qmsg b/data_selector/db/data_selector.fit.qmsg
deleted file mode 100644
index 4ad3426..0000000
--- a/data_selector/db/data_selector.fit.qmsg
+++ /dev/null
@@ -1,38 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 06 21:29:26 2022 " "Info: Processing started: Sun Mar 06 21:29:26 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off data_selector -c data_selector " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off data_selector -c data_selector" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 6 " "Info: Parallel compilation is enabled and will use 4 of the 6 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
-{ "Info" "IMPP_MPP_USER_DEVICE" "data_selector EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"data_selector\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
-{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "26 26 " "Warning: No exact pin location assignment(s) for 26 pins of 26 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y0 " "Info: Pin Y0 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y0 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { -136 928 1104 -120 "Y0" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y1 " "Info: Pin Y1 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y1 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { -80 928 1104 -64 "Y1" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y2 " "Info: Pin Y2 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y2 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { -24 928 1104 -8 "Y2" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y3 " "Info: Pin Y3 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y3 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 32 928 1104 48 "Y3" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y4 " "Info: Pin Y4 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y4 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 88 928 1104 104 "Y4" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y5 " "Info: Pin Y5 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y5 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 144 928 1104 160 "Y5" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y6 " "Info: Pin Y6 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y6 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 200 928 1104 216 "Y6" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y7 " "Info: Pin Y7 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y7 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 256 928 1104 272 "Y7" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b0 " "Info: Pin b0 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { b0 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 312 176 344 328 "b0" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a0 " "Info: Pin a0 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { a0 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 64 176 344 80 "a0" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "AY " "Info: Pin AY not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { AY } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 576 176 344 592 "AY" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AY } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "BY " "Info: Pin BY not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { BY } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 600 176 344 616 "BY" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { BY } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a1 " "Info: Pin a1 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { a1 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 88 176 344 104 "a1" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b1 " "Info: Pin b1 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { b1 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 336 176 344 352 "b1" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a2 " "Info: Pin a2 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { a2 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 112 176 344 128 "a2" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b2 " "Info: Pin b2 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { b2 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 360 176 344 376 "b2" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a3 " "Info: Pin a3 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { a3 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 136 176 344 152 "a3" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b3 " "Info: Pin b3 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { b3 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 384 176 344 400 "b3" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a4 " "Info: Pin a4 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { a4 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 160 176 344 176 "a4" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b4 " "Info: Pin b4 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { b4 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 408 176 344 424 "b4" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a5 " "Info: Pin a5 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { a5 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 184 176 344 200 "a5" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b5 " "Info: Pin b5 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { b5 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 432 176 344 448 "b5" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a6 " "Info: Pin a6 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { a6 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 208 176 344 224 "a6" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b6 " "Info: Pin b6 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { b6 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 456 176 344 472 "b6" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a7 " "Info: Pin a7 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { a7 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 232 176 344 248 "a7" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b7 " "Info: Pin b7 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { b7 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 480 176 344 496 "b7" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
-{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
-{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
-{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "26 unused 3.3V 18 8 0 " "Info: Number of I/O pins in group: 26 (unused VREF, 3.3V VCCIO, 18 input, 8 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
-{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 2 30 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 35 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 34 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 36 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Info: Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X10_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
-{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
-{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y0 0 " "Info: Pin \"Y0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y1 0 " "Info: Pin \"Y1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y2 0 " "Info: Pin \"Y2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y3 0 " "Info: Pin \"Y3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y4 0 " "Info: Pin \"Y4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y5 0 " "Info: Pin \"Y5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y6 0 " "Info: Pin \"Y6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y7 0 " "Info: Pin \"Y7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
-{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/dev/quartus/data_selector/data_selector.fit.smsg " "Info: Generated suppressed messages file D:/dev/quartus/data_selector/data_selector.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "286 " "Info: Peak virtual memory: 286 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 06 21:29:29 2022 " "Info: Processing ended: Sun Mar 06 21:29:29 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/data_selector/db/data_selector.map.bpm b/data_selector/db/data_selector.map.bpm
deleted file mode 100644
index 86fc3a5..0000000
Binary files a/data_selector/db/data_selector.map.bpm and /dev/null differ
diff --git a/data_selector/db/data_selector.map.cdb b/data_selector/db/data_selector.map.cdb
deleted file mode 100644
index d765179..0000000
Binary files a/data_selector/db/data_selector.map.cdb and /dev/null differ
diff --git a/data_selector/db/data_selector.map.hdb b/data_selector/db/data_selector.map.hdb
deleted file mode 100644
index 0ee64e9..0000000
Binary files a/data_selector/db/data_selector.map.hdb and /dev/null differ
diff --git a/data_selector/db/data_selector.map_bb.cdb b/data_selector/db/data_selector.map_bb.cdb
deleted file mode 100644
index 39abc69..0000000
Binary files a/data_selector/db/data_selector.map_bb.cdb and /dev/null differ
diff --git a/data_selector/db/data_selector.map_bb.hdb b/data_selector/db/data_selector.map_bb.hdb
deleted file mode 100644
index 686d902..0000000
Binary files a/data_selector/db/data_selector.map_bb.hdb and /dev/null differ
diff --git a/data_selector/db/data_selector.pre_map.cdb b/data_selector/db/data_selector.pre_map.cdb
deleted file mode 100644
index d56c1ab..0000000
Binary files a/data_selector/db/data_selector.pre_map.cdb and /dev/null differ
diff --git a/data_selector/db/data_selector.pre_map.hdb b/data_selector/db/data_selector.pre_map.hdb
deleted file mode 100644
index b7cde31..0000000
Binary files a/data_selector/db/data_selector.pre_map.hdb and /dev/null differ
diff --git a/data_selector/db/data_selector.rtlv.hdb b/data_selector/db/data_selector.rtlv.hdb
deleted file mode 100644
index dfd6a95..0000000
Binary files a/data_selector/db/data_selector.rtlv.hdb and /dev/null differ
diff --git a/data_selector/db/data_selector.rtlv_sg.cdb b/data_selector/db/data_selector.rtlv_sg.cdb
deleted file mode 100644
index 7aaf4e1..0000000
Binary files a/data_selector/db/data_selector.rtlv_sg.cdb and /dev/null differ
diff --git a/data_selector/db/data_selector.sgdiff.cdb b/data_selector/db/data_selector.sgdiff.cdb
deleted file mode 100644
index df0bde8..0000000
Binary files a/data_selector/db/data_selector.sgdiff.cdb and /dev/null differ
diff --git a/data_selector/db/data_selector.sgdiff.hdb b/data_selector/db/data_selector.sgdiff.hdb
deleted file mode 100644
index 25750d2..0000000
Binary files a/data_selector/db/data_selector.sgdiff.hdb and /dev/null differ
diff --git a/data_selector/db/data_selector.tan.qmsg b/data_selector/db/data_selector.tan.qmsg
deleted file mode 100644
index 09d9276..0000000
--- a/data_selector/db/data_selector.tan.qmsg
+++ /dev/null
@@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 06 21:29:32 2022 " "Info: Processing started: Sun Mar 06 21:29:32 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off data_selector -c data_selector --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off data_selector -c data_selector --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 6 " "Info: Parallel compilation is enabled and will use 4 of the 6 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
-{ "Info" "ITDB_FULL_TPD_RESULT" "b5 Y5 12.694 ns Longest " "Info: Longest tpd from source pin \"b5\" to destination pin \"Y5\" is 12.694 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns b5 1 PIN PIN_45 1 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_45; Fanout = 1; PIN Node = 'b5'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b5 } "NODE_NAME" } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 432 176 344 448 "b5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.147 ns) + CELL(0.624 ns) 7.766 ns inst6 2 COMB LCCOMB_X1_Y9_N26 1 " "Info: 2: + IC(6.147 ns) + CELL(0.624 ns) = 7.766 ns; Loc. = LCCOMB_X1_Y9_N26; Fanout = 1; COMB Node = 'inst6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.771 ns" { b5 inst6 } "NODE_NAME" } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 128 776 840 176 "inst6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.642 ns) + CELL(3.286 ns) 12.694 ns Y5 3 PIN PIN_208 0 " "Info: 3: + IC(1.642 ns) + CELL(3.286 ns) = 12.694 ns; Loc. = PIN_208; Fanout = 0; PIN Node = 'Y5'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.928 ns" { inst6 Y5 } "NODE_NAME" } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 144 928 1104 160 "Y5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.905 ns ( 38.64 % ) " "Info: Total cell delay = 4.905 ns ( 38.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "7.789 ns ( 61.36 % ) " "Info: Total interconnect delay = 7.789 ns ( 61.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "12.694 ns" { b5 inst6 Y5 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "12.694 ns" { b5 {} b5~combout {} inst6 {} Y5 {} } { 0.000ns 0.000ns 6.147ns 1.642ns } { 0.000ns 0.995ns 0.624ns 3.286ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "192 " "Info: Peak virtual memory: 192 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 06 21:29:32 2022 " "Info: Processing ended: Sun Mar 06 21:29:32 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/data_selector/db/data_selector.tmw_info b/data_selector/db/data_selector.tmw_info
deleted file mode 100644
index 84ebf94..0000000
--- a/data_selector/db/data_selector.tmw_info
+++ /dev/null
@@ -1,7 +0,0 @@
-start_full_compilation:s:00:00:15
-start_analysis_synthesis:s:00:00:09-start_full_compilation
-start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:03-start_full_compilation
-start_assembler:s:00:00:02-start_full_compilation
-start_timing_analyzer:s:00:00:01-start_full_compilation
-start_eda_netlist_writer:s:00:00:01
diff --git a/data_selector/db/prev_cmp_data_selector.fit.qmsg b/data_selector/db/prev_cmp_data_selector.fit.qmsg
deleted file mode 100644
index 4ad3426..0000000
--- a/data_selector/db/prev_cmp_data_selector.fit.qmsg
+++ /dev/null
@@ -1,38 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 06 21:29:26 2022 " "Info: Processing started: Sun Mar 06 21:29:26 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off data_selector -c data_selector " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off data_selector -c data_selector" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 6 " "Info: Parallel compilation is enabled and will use 4 of the 6 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
-{ "Info" "IMPP_MPP_USER_DEVICE" "data_selector EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"data_selector\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
-{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "26 26 " "Warning: No exact pin location assignment(s) for 26 pins of 26 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y0 " "Info: Pin Y0 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y0 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { -136 928 1104 -120 "Y0" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y1 " "Info: Pin Y1 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y1 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { -80 928 1104 -64 "Y1" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y2 " "Info: Pin Y2 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y2 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { -24 928 1104 -8 "Y2" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y3 " "Info: Pin Y3 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y3 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 32 928 1104 48 "Y3" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y4 " "Info: Pin Y4 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y4 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 88 928 1104 104 "Y4" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y5 " "Info: Pin Y5 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y5 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 144 928 1104 160 "Y5" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y6 " "Info: Pin Y6 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y6 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 200 928 1104 216 "Y6" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y7 " "Info: Pin Y7 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y7 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 256 928 1104 272 "Y7" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b0 " "Info: Pin b0 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { b0 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 312 176 344 328 "b0" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a0 " "Info: Pin a0 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { a0 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 64 176 344 80 "a0" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "AY " "Info: Pin AY not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { AY } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 576 176 344 592 "AY" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AY } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "BY " "Info: Pin BY not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { BY } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 600 176 344 616 "BY" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { BY } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a1 " "Info: Pin a1 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { a1 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 88 176 344 104 "a1" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b1 " "Info: Pin b1 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { b1 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 336 176 344 352 "b1" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a2 " "Info: Pin a2 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { a2 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 112 176 344 128 "a2" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b2 " "Info: Pin b2 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { b2 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 360 176 344 376 "b2" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a3 " "Info: Pin a3 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { a3 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 136 176 344 152 "a3" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b3 " "Info: Pin b3 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { b3 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 384 176 344 400 "b3" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a4 " "Info: Pin a4 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { a4 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 160 176 344 176 "a4" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b4 " "Info: Pin b4 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { b4 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 408 176 344 424 "b4" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a5 " "Info: Pin a5 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { a5 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 184 176 344 200 "a5" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b5 " "Info: Pin b5 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { b5 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 432 176 344 448 "b5" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a6 " "Info: Pin a6 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { a6 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 208 176 344 224 "a6" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b6 " "Info: Pin b6 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { b6 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 456 176 344 472 "b6" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a7 " "Info: Pin a7 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { a7 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 232 176 344 248 "a7" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b7 " "Info: Pin b7 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { b7 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 480 176 344 496 "b7" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
-{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
-{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
-{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "26 unused 3.3V 18 8 0 " "Info: Number of I/O pins in group: 26 (unused VREF, 3.3V VCCIO, 18 input, 8 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
-{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 2 30 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 35 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 34 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 36 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Info: Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X10_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
-{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
-{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y0 0 " "Info: Pin \"Y0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y1 0 " "Info: Pin \"Y1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y2 0 " "Info: Pin \"Y2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y3 0 " "Info: Pin \"Y3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y4 0 " "Info: Pin \"Y4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y5 0 " "Info: Pin \"Y5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y6 0 " "Info: Pin \"Y6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y7 0 " "Info: Pin \"Y7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
-{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/dev/quartus/data_selector/data_selector.fit.smsg " "Info: Generated suppressed messages file D:/dev/quartus/data_selector/data_selector.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "286 " "Info: Peak virtual memory: 286 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 06 21:29:29 2022 " "Info: Processing ended: Sun Mar 06 21:29:29 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/data_selector/db/prev_cmp_data_selector.qmsg b/data_selector/db/prev_cmp_data_selector.qmsg
deleted file mode 100644
index 0da5be2..0000000
--- a/data_selector/db/prev_cmp_data_selector.qmsg
+++ /dev/null
@@ -1,59 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 06 21:29:23 2022 " "Info: Processing started: Sun Mar 06 21:29:23 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off data_selector -c data_selector " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off data_selector -c data_selector" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_selector.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file data_selector.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 data_selector " "Info: Found entity 1: data_selector" { } { { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
-{ "Info" "ISGN_START_ELABORATION_TOP" "data_selector " "Info: Elaborating entity \"data_selector\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "34 " "Info: Implemented 34 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "18 " "Info: Implemented 18 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "230 " "Info: Peak virtual memory: 230 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 06 21:29:25 2022 " "Info: Processing ended: Sun Mar 06 21:29:25 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 06 21:29:26 2022 " "Info: Processing started: Sun Mar 06 21:29:26 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off data_selector -c data_selector " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off data_selector -c data_selector" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 6 " "Info: Parallel compilation is enabled and will use 4 of the 6 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
-{ "Info" "IMPP_MPP_USER_DEVICE" "data_selector EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"data_selector\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
-{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "26 26 " "Warning: No exact pin location assignment(s) for 26 pins of 26 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y0 " "Info: Pin Y0 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y0 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { -136 928 1104 -120 "Y0" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y1 " "Info: Pin Y1 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y1 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { -80 928 1104 -64 "Y1" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y2 " "Info: Pin Y2 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y2 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { -24 928 1104 -8 "Y2" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y3 " "Info: Pin Y3 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y3 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 32 928 1104 48 "Y3" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y4 " "Info: Pin Y4 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y4 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 88 928 1104 104 "Y4" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y5 " "Info: Pin Y5 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y5 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 144 928 1104 160 "Y5" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y6 " "Info: Pin Y6 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y6 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 200 928 1104 216 "Y6" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y7 " "Info: Pin Y7 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { Y7 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 256 928 1104 272 "Y7" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b0 " "Info: Pin b0 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { b0 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 312 176 344 328 "b0" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a0 " "Info: Pin a0 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { a0 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 64 176 344 80 "a0" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "AY " "Info: Pin AY not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { AY } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 576 176 344 592 "AY" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { AY } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "BY " "Info: Pin BY not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { BY } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 600 176 344 616 "BY" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { BY } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a1 " "Info: Pin a1 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { a1 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 88 176 344 104 "a1" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b1 " "Info: Pin b1 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { b1 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 336 176 344 352 "b1" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a2 " "Info: Pin a2 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { a2 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 112 176 344 128 "a2" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b2 " "Info: Pin b2 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { b2 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 360 176 344 376 "b2" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a3 " "Info: Pin a3 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { a3 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 136 176 344 152 "a3" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b3 " "Info: Pin b3 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { b3 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 384 176 344 400 "b3" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a4 " "Info: Pin a4 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { a4 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 160 176 344 176 "a4" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b4 " "Info: Pin b4 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { b4 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 408 176 344 424 "b4" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a5 " "Info: Pin a5 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { a5 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 184 176 344 200 "a5" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b5 " "Info: Pin b5 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { b5 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 432 176 344 448 "b5" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a6 " "Info: Pin a6 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { a6 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 208 176 344 224 "a6" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b6 " "Info: Pin b6 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { b6 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 456 176 344 472 "b6" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "a7 " "Info: Pin a7 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { a7 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 232 176 344 248 "a7" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { a7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "b7 " "Info: Pin b7 not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { b7 } } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 480 176 344 496 "b7" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
-{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
-{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
-{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "26 unused 3.3V 18 8 0 " "Info: Number of I/O pins in group: 26 (unused VREF, 3.3V VCCIO, 18 input, 8 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
-{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 2 30 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 35 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 34 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 36 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Info: Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X10_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
-{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
-{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y0 0 " "Info: Pin \"Y0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y1 0 " "Info: Pin \"Y1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y2 0 " "Info: Pin \"Y2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y3 0 " "Info: Pin \"Y3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y4 0 " "Info: Pin \"Y4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y5 0 " "Info: Pin \"Y5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y6 0 " "Info: Pin \"Y6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y7 0 " "Info: Pin \"Y7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
-{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/dev/quartus/data_selector/data_selector.fit.smsg " "Info: Generated suppressed messages file D:/dev/quartus/data_selector/data_selector.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "286 " "Info: Peak virtual memory: 286 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 06 21:29:29 2022 " "Info: Processing ended: Sun Mar 06 21:29:29 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 06 21:29:30 2022 " "Info: Processing started: Sun Mar 06 21:29:30 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off data_selector -c data_selector " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off data_selector -c data_selector" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
-{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "221 " "Info: Peak virtual memory: 221 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 06 21:29:31 2022 " "Info: Processing ended: Sun Mar 06 21:29:31 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 06 21:29:32 2022 " "Info: Processing started: Sun Mar 06 21:29:32 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off data_selector -c data_selector --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off data_selector -c data_selector --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 6 " "Info: Parallel compilation is enabled and will use 4 of the 6 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
-{ "Info" "ITDB_FULL_TPD_RESULT" "b5 Y5 12.694 ns Longest " "Info: Longest tpd from source pin \"b5\" to destination pin \"Y5\" is 12.694 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns b5 1 PIN PIN_45 1 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_45; Fanout = 1; PIN Node = 'b5'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b5 } "NODE_NAME" } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 432 176 344 448 "b5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.147 ns) + CELL(0.624 ns) 7.766 ns inst6 2 COMB LCCOMB_X1_Y9_N26 1 " "Info: 2: + IC(6.147 ns) + CELL(0.624 ns) = 7.766 ns; Loc. = LCCOMB_X1_Y9_N26; Fanout = 1; COMB Node = 'inst6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.771 ns" { b5 inst6 } "NODE_NAME" } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 128 776 840 176 "inst6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.642 ns) + CELL(3.286 ns) 12.694 ns Y5 3 PIN PIN_208 0 " "Info: 3: + IC(1.642 ns) + CELL(3.286 ns) = 12.694 ns; Loc. = PIN_208; Fanout = 0; PIN Node = 'Y5'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.928 ns" { inst6 Y5 } "NODE_NAME" } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 144 928 1104 160 "Y5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.905 ns ( 38.64 % ) " "Info: Total cell delay = 4.905 ns ( 38.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "7.789 ns ( 61.36 % ) " "Info: Total interconnect delay = 7.789 ns ( 61.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "12.694 ns" { b5 inst6 Y5 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "12.694 ns" { b5 {} b5~combout {} inst6 {} Y5 {} } { 0.000ns 0.000ns 6.147ns 1.642ns } { 0.000ns 0.995ns 0.624ns 3.286ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "192 " "Info: Peak virtual memory: 192 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 06 21:29:32 2022 " "Info: Processing ended: Sun Mar 06 21:29:32 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
-{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 2 s " "Info: Quartus II Full Compilation was successful. 0 errors, 2 warnings" { } { } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/data_selector/db/prev_cmp_data_selector.tan.qmsg b/data_selector/db/prev_cmp_data_selector.tan.qmsg
deleted file mode 100644
index 09d9276..0000000
--- a/data_selector/db/prev_cmp_data_selector.tan.qmsg
+++ /dev/null
@@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 06 21:29:32 2022 " "Info: Processing started: Sun Mar 06 21:29:32 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off data_selector -c data_selector --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off data_selector -c data_selector --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 6 " "Info: Parallel compilation is enabled and will use 4 of the 6 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
-{ "Info" "ITDB_FULL_TPD_RESULT" "b5 Y5 12.694 ns Longest " "Info: Longest tpd from source pin \"b5\" to destination pin \"Y5\" is 12.694 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns b5 1 PIN PIN_45 1 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_45; Fanout = 1; PIN Node = 'b5'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b5 } "NODE_NAME" } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 432 176 344 448 "b5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.147 ns) + CELL(0.624 ns) 7.766 ns inst6 2 COMB LCCOMB_X1_Y9_N26 1 " "Info: 2: + IC(6.147 ns) + CELL(0.624 ns) = 7.766 ns; Loc. = LCCOMB_X1_Y9_N26; Fanout = 1; COMB Node = 'inst6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.771 ns" { b5 inst6 } "NODE_NAME" } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 128 776 840 176 "inst6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.642 ns) + CELL(3.286 ns) 12.694 ns Y5 3 PIN PIN_208 0 " "Info: 3: + IC(1.642 ns) + CELL(3.286 ns) = 12.694 ns; Loc. = PIN_208; Fanout = 0; PIN Node = 'Y5'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.928 ns" { inst6 Y5 } "NODE_NAME" } } { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { { 144 928 1104 160 "Y5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.905 ns ( 38.64 % ) " "Info: Total cell delay = 4.905 ns ( 38.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "7.789 ns ( 61.36 % ) " "Info: Total interconnect delay = 7.789 ns ( 61.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "12.694 ns" { b5 inst6 Y5 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "12.694 ns" { b5 {} b5~combout {} inst6 {} Y5 {} } { 0.000ns 0.000ns 6.147ns 1.642ns } { 0.000ns 0.995ns 0.624ns 3.286ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "192 " "Info: Peak virtual memory: 192 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 06 21:29:32 2022 " "Info: Processing ended: Sun Mar 06 21:29:32 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.atm b/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.atm
deleted file mode 100644
index 26f89f8..0000000
Binary files a/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.atm and /dev/null differ
diff --git a/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.hdbx b/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.hdbx
deleted file mode 100644
index c826cdc..0000000
Binary files a/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.hdbx and /dev/null differ
diff --git a/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.rcf b/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.rcf
deleted file mode 100644
index 8c3c6b2..0000000
Binary files a/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.rcf and /dev/null differ
diff --git a/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.atm b/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.atm
deleted file mode 100644
index a686051..0000000
Binary files a/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.atm and /dev/null differ
diff --git a/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.dpi b/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.dpi
deleted file mode 100644
index 7a33474..0000000
Binary files a/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.dpi and /dev/null differ
diff --git a/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.hdbx b/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.hdbx
deleted file mode 100644
index 812284c..0000000
Binary files a/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.hdbx and /dev/null differ
diff --git a/data_selector/db/data_selector.(0).cnf.cdb b/double_selector_8b/db/double_selector_8b.(0).cnf.cdb
similarity index 100%
rename from data_selector/db/data_selector.(0).cnf.cdb
rename to double_selector_8b/db/double_selector_8b.(0).cnf.cdb
diff --git a/double_selector_8b/db/double_selector_8b.(0).cnf.hdb b/double_selector_8b/db/double_selector_8b.(0).cnf.hdb
new file mode 100644
index 0000000..054e176
Binary files /dev/null and b/double_selector_8b/db/double_selector_8b.(0).cnf.hdb differ
diff --git a/double_selector_8b/db/double_selector_8b.asm.qmsg b/double_selector_8b/db/double_selector_8b.asm.qmsg
new file mode 100644
index 0000000..9137121
--- /dev/null
+++ b/double_selector_8b/db/double_selector_8b.asm.qmsg
@@ -0,0 +1,7 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:22:46 2022 " "Info: Processing started: Mon Mar 07 11:22:46 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
+{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:22:46 2022 " "Info: Processing ended: Mon Mar 07 11:22:46 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/double_selector_8b/db/double_selector_8b.asm_labs.ddb b/double_selector_8b/db/double_selector_8b.asm_labs.ddb
new file mode 100644
index 0000000..17df122
Binary files /dev/null and b/double_selector_8b/db/double_selector_8b.asm_labs.ddb differ
diff --git a/data_selector/db/data_selector.cbx.xml b/double_selector_8b/db/double_selector_8b.cbx.xml
similarity index 61%
rename from data_selector/db/data_selector.cbx.xml
rename to double_selector_8b/db/double_selector_8b.cbx.xml
index 042417b..0706c40 100644
--- a/data_selector/db/data_selector.cbx.xml
+++ b/double_selector_8b/db/double_selector_8b.cbx.xml
@@ -1,5 +1,5 @@
-
+
diff --git a/double_selector_8b/db/double_selector_8b.cmp.bpm b/double_selector_8b/db/double_selector_8b.cmp.bpm
new file mode 100644
index 0000000..b178f62
Binary files /dev/null and b/double_selector_8b/db/double_selector_8b.cmp.bpm differ
diff --git a/double_selector_8b/db/double_selector_8b.cmp.cdb b/double_selector_8b/db/double_selector_8b.cmp.cdb
new file mode 100644
index 0000000..63b3f44
Binary files /dev/null and b/double_selector_8b/db/double_selector_8b.cmp.cdb differ
diff --git a/data_selector/db/data_selector.cmp.ecobp b/double_selector_8b/db/double_selector_8b.cmp.ecobp
similarity index 100%
rename from data_selector/db/data_selector.cmp.ecobp
rename to double_selector_8b/db/double_selector_8b.cmp.ecobp
diff --git a/double_selector_8b/db/double_selector_8b.cmp.hdb b/double_selector_8b/db/double_selector_8b.cmp.hdb
new file mode 100644
index 0000000..d222470
Binary files /dev/null and b/double_selector_8b/db/double_selector_8b.cmp.hdb differ
diff --git a/data_selector/db/data_selector.cmp.kpt b/double_selector_8b/db/double_selector_8b.cmp.kpt
similarity index 83%
rename from data_selector/db/data_selector.cmp.kpt
rename to double_selector_8b/db/double_selector_8b.cmp.kpt
index 94e542d..45362cb 100644
--- a/data_selector/db/data_selector.cmp.kpt
+++ b/double_selector_8b/db/double_selector_8b.cmp.kpt
@@ -1,4 +1,4 @@
-
+
diff --git a/data_selector/db/data_selector.cmp.logdb b/double_selector_8b/db/double_selector_8b.cmp.logdb
similarity index 100%
rename from data_selector/db/data_selector.cmp.logdb
rename to double_selector_8b/db/double_selector_8b.cmp.logdb
diff --git a/double_selector_8b/db/double_selector_8b.cmp.rdb b/double_selector_8b/db/double_selector_8b.cmp.rdb
new file mode 100644
index 0000000..323137d
Binary files /dev/null and b/double_selector_8b/db/double_selector_8b.cmp.rdb differ
diff --git a/double_selector_8b/db/double_selector_8b.cmp.tdb b/double_selector_8b/db/double_selector_8b.cmp.tdb
new file mode 100644
index 0000000..9144a32
Binary files /dev/null and b/double_selector_8b/db/double_selector_8b.cmp.tdb differ
diff --git a/double_selector_8b/db/double_selector_8b.cmp0.ddb b/double_selector_8b/db/double_selector_8b.cmp0.ddb
new file mode 100644
index 0000000..1409b5e
Binary files /dev/null and b/double_selector_8b/db/double_selector_8b.cmp0.ddb differ
diff --git a/double_selector_8b/db/double_selector_8b.cmp2.ddb b/double_selector_8b/db/double_selector_8b.cmp2.ddb
new file mode 100644
index 0000000..5c5ef95
Binary files /dev/null and b/double_selector_8b/db/double_selector_8b.cmp2.ddb differ
diff --git a/data_selector/db/data_selector.cmp_merge.kpt b/double_selector_8b/db/double_selector_8b.cmp_merge.kpt
similarity index 81%
rename from data_selector/db/data_selector.cmp_merge.kpt
rename to double_selector_8b/db/double_selector_8b.cmp_merge.kpt
index 70cf43e..a0a9dd2 100644
--- a/data_selector/db/data_selector.cmp_merge.kpt
+++ b/double_selector_8b/db/double_selector_8b.cmp_merge.kpt
@@ -1,4 +1,4 @@
-
+
diff --git a/data_selector/db/data_selector.db_info b/double_selector_8b/db/double_selector_8b.db_info
similarity index 72%
rename from data_selector/db/data_selector.db_info
rename to double_selector_8b/db/double_selector_8b.db_info
index 7581217..82c5a61 100644
--- a/data_selector/db/data_selector.db_info
+++ b/double_selector_8b/db/double_selector_8b.db_info
@@ -1,3 +1,3 @@
Quartus_Version = Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Version_Index = 167832322
-Creation_Time = Sat Mar 05 19:48:38 2022
+Creation_Time = Mon Mar 07 11:06:00 2022
diff --git a/data_selector/db/data_selector.eco.cdb b/double_selector_8b/db/double_selector_8b.eco.cdb
similarity index 100%
rename from data_selector/db/data_selector.eco.cdb
rename to double_selector_8b/db/double_selector_8b.eco.cdb
diff --git a/double_selector_8b/db/double_selector_8b.fit.qmsg b/double_selector_8b/db/double_selector_8b.fit.qmsg
new file mode 100644
index 0000000..8947a74
--- /dev/null
+++ b/double_selector_8b/db/double_selector_8b.fit.qmsg
@@ -0,0 +1,35 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:22:44 2022 " "Info: Processing started: Mon Mar 07 11:22:44 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "IMPP_MPP_USER_DEVICE" "double_selector_8b EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"double_selector_8b\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
+{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
+{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y0 X34_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X34_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
+{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y0 0 " "Info: Pin \"Y0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y1 0 " "Info: Pin \"Y1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y2 0 " "Info: Pin \"Y2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y3 0 " "Info: Pin \"Y3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y4 0 " "Info: Pin \"Y4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y5 0 " "Info: Pin \"Y5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y6 0 " "Info: Pin \"Y6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y7 0 " "Info: Pin \"Y7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/double_selector_8b/double_selector_8b.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/double_selector_8b/double_selector_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "307 " "Info: Peak virtual memory: 307 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:22:45 2022 " "Info: Processing ended: Mon Mar 07 11:22:45 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/data_selector/db/data_selector.hier_info b/double_selector_8b/db/double_selector_8b.hier_info
similarity index 97%
rename from data_selector/db/data_selector.hier_info
rename to double_selector_8b/db/double_selector_8b.hier_info
index fa4b6e8..d4be631 100644
--- a/data_selector/db/data_selector.hier_info
+++ b/double_selector_8b/db/double_selector_8b.hier_info
@@ -1,4 +1,4 @@
-|data_selector
+|double_selector_8b
Y0 <= inst1.DB_MAX_OUTPUT_PORT_TYPE
b0 => inst25.IN0
BY => inst25.IN1
diff --git a/data_selector/db/data_selector.hif b/double_selector_8b/db/double_selector_8b.hif
similarity index 68%
rename from data_selector/db/data_selector.hif
rename to double_selector_8b/db/double_selector_8b.hif
index fcb3c76..d85a08f 100644
--- a/data_selector/db/data_selector.hif
+++ b/double_selector_8b/db/double_selector_8b.hif
@@ -19,14 +19,14 @@ VHSM_ON
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
-data_selector
+double_selector_8b
# storage
-db|data_selector.(0).cnf
-db|data_selector.(0).cnf
+db|double_selector_8b.(0).cnf
+db|double_selector_8b.(0).cnf
# case_insensitive
# source_file
-data_selector.bdf
-bca46c741e5dd2513eb8c7ec51bf2eee
+double_selector_8b.bdf
+175873c0dd68c1f8d97dd4bedd5ca23
26
# internal_option {
BLOCK_DESIGN_NAMING
diff --git a/data_selector/db/data_selector.lpc.html b/double_selector_8b/db/double_selector_8b.lpc.html
similarity index 100%
rename from data_selector/db/data_selector.lpc.html
rename to double_selector_8b/db/double_selector_8b.lpc.html
diff --git a/data_selector/db/data_selector.lpc.rdb b/double_selector_8b/db/double_selector_8b.lpc.rdb
similarity index 100%
rename from data_selector/db/data_selector.lpc.rdb
rename to double_selector_8b/db/double_selector_8b.lpc.rdb
diff --git a/data_selector/db/data_selector.lpc.txt b/double_selector_8b/db/double_selector_8b.lpc.txt
similarity index 100%
rename from data_selector/db/data_selector.lpc.txt
rename to double_selector_8b/db/double_selector_8b.lpc.txt
diff --git a/double_selector_8b/db/double_selector_8b.map.bpm b/double_selector_8b/db/double_selector_8b.map.bpm
new file mode 100644
index 0000000..238bb68
Binary files /dev/null and b/double_selector_8b/db/double_selector_8b.map.bpm differ
diff --git a/double_selector_8b/db/double_selector_8b.map.cdb b/double_selector_8b/db/double_selector_8b.map.cdb
new file mode 100644
index 0000000..145b848
Binary files /dev/null and b/double_selector_8b/db/double_selector_8b.map.cdb differ
diff --git a/data_selector/db/data_selector.map.ecobp b/double_selector_8b/db/double_selector_8b.map.ecobp
similarity index 100%
rename from data_selector/db/data_selector.map.ecobp
rename to double_selector_8b/db/double_selector_8b.map.ecobp
diff --git a/double_selector_8b/db/double_selector_8b.map.hdb b/double_selector_8b/db/double_selector_8b.map.hdb
new file mode 100644
index 0000000..6d78a2c
Binary files /dev/null and b/double_selector_8b/db/double_selector_8b.map.hdb differ
diff --git a/data_selector/db/data_selector.map.kpt b/double_selector_8b/db/double_selector_8b.map.kpt
similarity index 83%
rename from data_selector/db/data_selector.map.kpt
rename to double_selector_8b/db/double_selector_8b.map.kpt
index a58ed0f..491f4b2 100644
--- a/data_selector/db/data_selector.map.kpt
+++ b/double_selector_8b/db/double_selector_8b.map.kpt
@@ -1,4 +1,4 @@
-
+
diff --git a/data_selector/db/data_selector.map.logdb b/double_selector_8b/db/double_selector_8b.map.logdb
similarity index 100%
rename from data_selector/db/data_selector.map.logdb
rename to double_selector_8b/db/double_selector_8b.map.logdb
diff --git a/data_selector/db/prev_cmp_data_selector.map.qmsg b/double_selector_8b/db/double_selector_8b.map.qmsg
similarity index 52%
rename from data_selector/db/prev_cmp_data_selector.map.qmsg
rename to double_selector_8b/db/double_selector_8b.map.qmsg
index b42dad9..0551647 100644
--- a/data_selector/db/prev_cmp_data_selector.map.qmsg
+++ b/double_selector_8b/db/double_selector_8b.map.qmsg
@@ -1,7 +1,7 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 06 21:29:23 2022 " "Info: Processing started: Sun Mar 06 21:29:23 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off data_selector -c data_selector " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off data_selector -c data_selector" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_selector.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file data_selector.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 data_selector " "Info: Found entity 1: data_selector" { } { { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
-{ "Info" "ISGN_START_ELABORATION_TOP" "data_selector " "Info: Elaborating entity \"data_selector\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:22:43 2022 " "Info: Processing started: Mon Mar 07 11:22:43 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off double_selector_8b -c double_selector_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off double_selector_8b -c double_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "double_selector_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file double_selector_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 double_selector_8b " "Info: Found entity 1: double_selector_8b" { } { { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_TOP" "double_selector_8b " "Info: Elaborating entity \"double_selector_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "34 " "Info: Implemented 34 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "18 " "Info: Implemented 18 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "230 " "Info: Peak virtual memory: 230 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 06 21:29:25 2022 " "Info: Processing ended: Sun Mar 06 21:29:25 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:22:43 2022 " "Info: Processing ended: Mon Mar 07 11:22:43 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/double_selector_8b/db/double_selector_8b.map_bb.cdb b/double_selector_8b/db/double_selector_8b.map_bb.cdb
new file mode 100644
index 0000000..4bfa27a
Binary files /dev/null and b/double_selector_8b/db/double_selector_8b.map_bb.cdb differ
diff --git a/double_selector_8b/db/double_selector_8b.map_bb.hdb b/double_selector_8b/db/double_selector_8b.map_bb.hdb
new file mode 100644
index 0000000..b075daa
Binary files /dev/null and b/double_selector_8b/db/double_selector_8b.map_bb.hdb differ
diff --git a/data_selector/db/data_selector.map_bb.logdb b/double_selector_8b/db/double_selector_8b.map_bb.logdb
similarity index 100%
rename from data_selector/db/data_selector.map_bb.logdb
rename to double_selector_8b/db/double_selector_8b.map_bb.logdb
diff --git a/double_selector_8b/db/double_selector_8b.pre_map.cdb b/double_selector_8b/db/double_selector_8b.pre_map.cdb
new file mode 100644
index 0000000..f516281
Binary files /dev/null and b/double_selector_8b/db/double_selector_8b.pre_map.cdb differ
diff --git a/double_selector_8b/db/double_selector_8b.pre_map.hdb b/double_selector_8b/db/double_selector_8b.pre_map.hdb
new file mode 100644
index 0000000..161ae71
Binary files /dev/null and b/double_selector_8b/db/double_selector_8b.pre_map.hdb differ
diff --git a/double_selector_8b/db/double_selector_8b.rtlv.hdb b/double_selector_8b/db/double_selector_8b.rtlv.hdb
new file mode 100644
index 0000000..67f8688
Binary files /dev/null and b/double_selector_8b/db/double_selector_8b.rtlv.hdb differ
diff --git a/double_selector_8b/db/double_selector_8b.rtlv_sg.cdb b/double_selector_8b/db/double_selector_8b.rtlv_sg.cdb
new file mode 100644
index 0000000..5bd4828
Binary files /dev/null and b/double_selector_8b/db/double_selector_8b.rtlv_sg.cdb differ
diff --git a/data_selector/db/data_selector.rtlv_sg_swap.cdb b/double_selector_8b/db/double_selector_8b.rtlv_sg_swap.cdb
similarity index 100%
rename from data_selector/db/data_selector.rtlv_sg_swap.cdb
rename to double_selector_8b/db/double_selector_8b.rtlv_sg_swap.cdb
diff --git a/double_selector_8b/db/double_selector_8b.sgdiff.cdb b/double_selector_8b/db/double_selector_8b.sgdiff.cdb
new file mode 100644
index 0000000..c37bb12
Binary files /dev/null and b/double_selector_8b/db/double_selector_8b.sgdiff.cdb differ
diff --git a/double_selector_8b/db/double_selector_8b.sgdiff.hdb b/double_selector_8b/db/double_selector_8b.sgdiff.hdb
new file mode 100644
index 0000000..7984dfd
Binary files /dev/null and b/double_selector_8b/db/double_selector_8b.sgdiff.hdb differ
diff --git a/data_selector/db/data_selector.sld_design_entry.sci b/double_selector_8b/db/double_selector_8b.sld_design_entry.sci
similarity index 100%
rename from data_selector/db/data_selector.sld_design_entry.sci
rename to double_selector_8b/db/double_selector_8b.sld_design_entry.sci
diff --git a/data_selector/db/data_selector.sld_design_entry_dsc.sci b/double_selector_8b/db/double_selector_8b.sld_design_entry_dsc.sci
similarity index 100%
rename from data_selector/db/data_selector.sld_design_entry_dsc.sci
rename to double_selector_8b/db/double_selector_8b.sld_design_entry_dsc.sci
diff --git a/data_selector/db/data_selector.syn_hier_info b/double_selector_8b/db/double_selector_8b.syn_hier_info
similarity index 100%
rename from data_selector/db/data_selector.syn_hier_info
rename to double_selector_8b/db/double_selector_8b.syn_hier_info
diff --git a/double_selector_8b/db/double_selector_8b.tan.qmsg b/double_selector_8b/db/double_selector_8b.tan.qmsg
new file mode 100644
index 0000000..2f6e0ca
--- /dev/null
+++ b/double_selector_8b/db/double_selector_8b.tan.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:22:47 2022 " "Info: Processing started: Mon Mar 07 11:22:47 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TPD_RESULT" "b6 Y6 14.785 ns Longest " "Info: Longest tpd from source pin \"b6\" to destination pin \"Y6\" is 14.785 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns b6 1 PIN PIN_75 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_75; Fanout = 1; PIN Node = 'b6'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b6 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 664 64 232 680 "b6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.679 ns) + CELL(0.651 ns) 8.304 ns inst7 2 COMB LCCOMB_X25_Y2_N12 1 " "Info: 2: + IC(6.679 ns) + CELL(0.651 ns) = 8.304 ns; Loc. = LCCOMB_X25_Y2_N12; Fanout = 1; COMB Node = 'inst7'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.330 ns" { b6 inst7 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 392 664 728 440 "inst7" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.365 ns) + CELL(3.116 ns) 14.785 ns Y6 3 PIN PIN_149 0 " "Info: 3: + IC(3.365 ns) + CELL(3.116 ns) = 14.785 ns; Loc. = PIN_149; Fanout = 0; PIN Node = 'Y6'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.481 ns" { inst7 Y6 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 408 816 992 424 "Y6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.741 ns ( 32.07 % ) " "Info: Total cell delay = 4.741 ns ( 32.07 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "10.044 ns ( 67.93 % ) " "Info: Total interconnect delay = 10.044 ns ( 67.93 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "14.785 ns" { b6 inst7 Y6 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "14.785 ns" { b6 {} b6~combout {} inst7 {} Y6 {} } { 0.000ns 0.000ns 6.679ns 3.365ns } { 0.000ns 0.974ns 0.651ns 3.116ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:22:47 2022 " "Info: Processing ended: Mon Mar 07 11:22:47 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/data_selector/db/data_selector.tis_db_list.ddb b/double_selector_8b/db/double_selector_8b.tis_db_list.ddb
similarity index 100%
rename from data_selector/db/data_selector.tis_db_list.ddb
rename to double_selector_8b/db/double_selector_8b.tis_db_list.ddb
diff --git a/double_selector_8b/db/double_selector_8b.tmw_info b/double_selector_8b/db/double_selector_8b.tmw_info
new file mode 100644
index 0000000..6516e48
--- /dev/null
+++ b/double_selector_8b/db/double_selector_8b.tmw_info
@@ -0,0 +1,6 @@
+start_full_compilation:s:00:00:05
+start_analysis_synthesis:s:00:00:02-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:01-start_full_compilation
+start_assembler:s:00:00:02-start_full_compilation
+start_timing_analyzer:s:00:00:00-start_full_compilation
diff --git a/data_selector/db/prev_cmp_data_selector.asm.qmsg b/double_selector_8b/db/prev_cmp_double_selector_8b.asm.qmsg
similarity index 66%
rename from data_selector/db/prev_cmp_data_selector.asm.qmsg
rename to double_selector_8b/db/prev_cmp_double_selector_8b.asm.qmsg
index ff61c95..d249efb 100644
--- a/data_selector/db/prev_cmp_data_selector.asm.qmsg
+++ b/double_selector_8b/db/prev_cmp_double_selector_8b.asm.qmsg
@@ -1,7 +1,7 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 06 21:29:30 2022 " "Info: Processing started: Sun Mar 06 21:29:30 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off data_selector -c data_selector " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off data_selector -c data_selector" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:20:35 2022 " "Info: Processing started: Mon Mar 07 11:20:35 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "221 " "Info: Peak virtual memory: 221 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 06 21:29:31 2022 " "Info: Processing ended: Sun Mar 06 21:29:31 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:20:36 2022 " "Info: Processing ended: Mon Mar 07 11:20:36 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/double_selector_8b/db/prev_cmp_double_selector_8b.fit.qmsg b/double_selector_8b/db/prev_cmp_double_selector_8b.fit.qmsg
new file mode 100644
index 0000000..8adea03
--- /dev/null
+++ b/double_selector_8b/db/prev_cmp_double_selector_8b.fit.qmsg
@@ -0,0 +1,36 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:20:34 2022 " "Info: Processing started: Mon Mar 07 11:20:34 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "IMPP_MPP_USER_DEVICE" "double_selector_8b EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"double_selector_8b\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
+{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
+{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y0 X34_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X34_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
+{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y0 0 " "Info: Pin \"Y0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y1 0 " "Info: Pin \"Y1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y2 0 " "Info: Pin \"Y2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y3 0 " "Info: Pin \"Y3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y4 0 " "Info: Pin \"Y4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y5 0 " "Info: Pin \"Y5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y6 0 " "Info: Pin \"Y6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y7 0 " "Info: Pin \"Y7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/double_selector_8b/double_selector_8b.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/double_selector_8b/double_selector_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "306 " "Info: Peak virtual memory: 306 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:20:35 2022 " "Info: Processing ended: Mon Mar 07 11:20:35 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/data_selector/db/data_selector.map.qmsg b/double_selector_8b/db/prev_cmp_double_selector_8b.map.qmsg
similarity index 52%
rename from data_selector/db/data_selector.map.qmsg
rename to double_selector_8b/db/prev_cmp_double_selector_8b.map.qmsg
index b42dad9..247e595 100644
--- a/data_selector/db/data_selector.map.qmsg
+++ b/double_selector_8b/db/prev_cmp_double_selector_8b.map.qmsg
@@ -1,7 +1,7 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 06 21:29:23 2022 " "Info: Processing started: Sun Mar 06 21:29:23 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off data_selector -c data_selector " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off data_selector -c data_selector" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_selector.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file data_selector.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 data_selector " "Info: Found entity 1: data_selector" { } { { "data_selector.bdf" "" { Schematic "D:/dev/quartus/data_selector/data_selector.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
-{ "Info" "ISGN_START_ELABORATION_TOP" "data_selector " "Info: Elaborating entity \"data_selector\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:20:32 2022 " "Info: Processing started: Mon Mar 07 11:20:32 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off double_selector_8b -c double_selector_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off double_selector_8b -c double_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "double_selector_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file double_selector_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 double_selector_8b " "Info: Found entity 1: double_selector_8b" { } { { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_TOP" "double_selector_8b " "Info: Elaborating entity \"double_selector_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "34 " "Info: Implemented 34 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "18 " "Info: Implemented 18 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "230 " "Info: Peak virtual memory: 230 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 06 21:29:25 2022 " "Info: Processing ended: Sun Mar 06 21:29:25 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:20:33 2022 " "Info: Processing ended: Mon Mar 07 11:20:33 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/double_selector_8b/db/prev_cmp_double_selector_8b.qmsg b/double_selector_8b/db/prev_cmp_double_selector_8b.qmsg
new file mode 100644
index 0000000..d43f8c3
--- /dev/null
+++ b/double_selector_8b/db/prev_cmp_double_selector_8b.qmsg
@@ -0,0 +1,57 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:20:32 2022 " "Info: Processing started: Mon Mar 07 11:20:32 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off double_selector_8b -c double_selector_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off double_selector_8b -c double_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "double_selector_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file double_selector_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 double_selector_8b " "Info: Found entity 1: double_selector_8b" { } { { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_TOP" "double_selector_8b " "Info: Elaborating entity \"double_selector_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "34 " "Info: Implemented 34 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "18 " "Info: Implemented 18 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:20:33 2022 " "Info: Processing ended: Mon Mar 07 11:20:33 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:20:34 2022 " "Info: Processing started: Mon Mar 07 11:20:34 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "IMPP_MPP_USER_DEVICE" "double_selector_8b EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"double_selector_8b\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
+{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
+{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y0 X34_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X34_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
+{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y0 0 " "Info: Pin \"Y0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y1 0 " "Info: Pin \"Y1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y2 0 " "Info: Pin \"Y2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y3 0 " "Info: Pin \"Y3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y4 0 " "Info: Pin \"Y4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y5 0 " "Info: Pin \"Y5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y6 0 " "Info: Pin \"Y6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y7 0 " "Info: Pin \"Y7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/double_selector_8b/double_selector_8b.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/double_selector_8b/double_selector_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "306 " "Info: Peak virtual memory: 306 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:20:35 2022 " "Info: Processing ended: Mon Mar 07 11:20:35 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:20:35 2022 " "Info: Processing started: Mon Mar 07 11:20:35 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
+{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:20:36 2022 " "Info: Processing ended: Mon Mar 07 11:20:36 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:20:37 2022 " "Info: Processing started: Mon Mar 07 11:20:37 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TPD_RESULT" "b6 Y6 14.785 ns Longest " "Info: Longest tpd from source pin \"b6\" to destination pin \"Y6\" is 14.785 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns b6 1 PIN PIN_75 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_75; Fanout = 1; PIN Node = 'b6'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b6 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 664 64 232 680 "b6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.679 ns) + CELL(0.651 ns) 8.304 ns inst7 2 COMB LCCOMB_X25_Y2_N12 1 " "Info: 2: + IC(6.679 ns) + CELL(0.651 ns) = 8.304 ns; Loc. = LCCOMB_X25_Y2_N12; Fanout = 1; COMB Node = 'inst7'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.330 ns" { b6 inst7 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 392 664 728 440 "inst7" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.365 ns) + CELL(3.116 ns) 14.785 ns Y6 3 PIN PIN_149 0 " "Info: 3: + IC(3.365 ns) + CELL(3.116 ns) = 14.785 ns; Loc. = PIN_149; Fanout = 0; PIN Node = 'Y6'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.481 ns" { inst7 Y6 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 408 816 992 424 "Y6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.741 ns ( 32.07 % ) " "Info: Total cell delay = 4.741 ns ( 32.07 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "10.044 ns ( 67.93 % ) " "Info: Total interconnect delay = 10.044 ns ( 67.93 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "14.785 ns" { b6 inst7 Y6 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "14.785 ns" { b6 {} b6~combout {} inst7 {} Y6 {} } { 0.000ns 0.000ns 6.679ns 3.365ns } { 0.000ns 0.974ns 0.651ns 3.116ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:20:37 2022 " "Info: Processing ended: Mon Mar 07 11:20:37 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 2 s " "Info: Quartus II Full Compilation was successful. 0 errors, 2 warnings" { } { } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/double_selector_8b/db/prev_cmp_double_selector_8b.tan.qmsg b/double_selector_8b/db/prev_cmp_double_selector_8b.tan.qmsg
new file mode 100644
index 0000000..48e0594
--- /dev/null
+++ b/double_selector_8b/db/prev_cmp_double_selector_8b.tan.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:20:37 2022 " "Info: Processing started: Mon Mar 07 11:20:37 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TPD_RESULT" "b6 Y6 14.785 ns Longest " "Info: Longest tpd from source pin \"b6\" to destination pin \"Y6\" is 14.785 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns b6 1 PIN PIN_75 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_75; Fanout = 1; PIN Node = 'b6'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b6 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 664 64 232 680 "b6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.679 ns) + CELL(0.651 ns) 8.304 ns inst7 2 COMB LCCOMB_X25_Y2_N12 1 " "Info: 2: + IC(6.679 ns) + CELL(0.651 ns) = 8.304 ns; Loc. = LCCOMB_X25_Y2_N12; Fanout = 1; COMB Node = 'inst7'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.330 ns" { b6 inst7 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 392 664 728 440 "inst7" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.365 ns) + CELL(3.116 ns) 14.785 ns Y6 3 PIN PIN_149 0 " "Info: 3: + IC(3.365 ns) + CELL(3.116 ns) = 14.785 ns; Loc. = PIN_149; Fanout = 0; PIN Node = 'Y6'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.481 ns" { inst7 Y6 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 408 816 992 424 "Y6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.741 ns ( 32.07 % ) " "Info: Total cell delay = 4.741 ns ( 32.07 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "10.044 ns ( 67.93 % ) " "Info: Total interconnect delay = 10.044 ns ( 67.93 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "14.785 ns" { b6 inst7 Y6 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "14.785 ns" { b6 {} b6~combout {} inst7 {} Y6 {} } { 0.000ns 0.000ns 6.679ns 3.365ns } { 0.000ns 0.974ns 0.651ns 3.116ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:20:37 2022 " "Info: Processing ended: Mon Mar 07 11:20:37 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/data_selector/data_selector.asm.rpt b/double_selector_8b/double_selector_8b.asm.rpt
similarity index 74%
rename from data_selector/data_selector.asm.rpt
rename to double_selector_8b/double_selector_8b.asm.rpt
index 3723dbd..7acc524 100644
--- a/data_selector/data_selector.asm.rpt
+++ b/double_selector_8b/double_selector_8b.asm.rpt
@@ -1,5 +1,5 @@
-Assembler report for data_selector
-Sun Mar 06 21:29:31 2022
+Assembler report for double_selector_8b
+Mon Mar 07 11:22:46 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@@ -10,8 +10,8 @@ Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
- 5. Assembler Device Options: D:/dev/quartus/data_selector/data_selector.sof
- 6. Assembler Device Options: D:/dev/quartus/data_selector/data_selector.pof
+ 5. Assembler Device Options: D:/projects/quartus/double_selector_8b/double_selector_8b.sof
+ 6. Assembler Device Options: D:/projects/quartus/double_selector_8b/double_selector_8b.pof
7. Assembler Messages
@@ -38,9 +38,9 @@ applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Sun Mar 06 21:29:31 2022 ;
-; Revision Name ; data_selector ;
-; Top-level Entity Name ; data_selector ;
+; Assembler Status ; Successful - Mon Mar 07 11:22:46 2022 ;
+; Revision Name ; double_selector_8b ;
+; Top-level Entity Name ; double_selector_8b ;
; Family ; Cyclone II ;
; Device ; EP2C8Q208C8 ;
+-----------------------+---------------------------------------+
@@ -76,37 +76,37 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+----------+---------------+
-+------------------------------------------------+
-; Assembler Generated Files ;
-+------------------------------------------------+
-; File Name ;
-+------------------------------------------------+
-; D:/dev/quartus/data_selector/data_selector.sof ;
-; D:/dev/quartus/data_selector/data_selector.pof ;
-+------------------------------------------------+
++---------------------------------------------------------------+
+; Assembler Generated Files ;
++---------------------------------------------------------------+
+; File Name ;
++---------------------------------------------------------------+
+; D:/projects/quartus/double_selector_8b/double_selector_8b.sof ;
+; D:/projects/quartus/double_selector_8b/double_selector_8b.pof ;
++---------------------------------------------------------------+
-+--------------------------------------------------------------------------+
-; Assembler Device Options: D:/dev/quartus/data_selector/data_selector.sof ;
-+----------------+---------------------------------------------------------+
-; Option ; Setting ;
-+----------------+---------------------------------------------------------+
-; Device ; EP2C8Q208C8 ;
-; JTAG usercode ; 0xFFFFFFFF ;
-; Checksum ; 0x000C1D58 ;
-+----------------+---------------------------------------------------------+
++-----------------------------------------------------------------------------------------+
+; Assembler Device Options: D:/projects/quartus/double_selector_8b/double_selector_8b.sof ;
++----------------+------------------------------------------------------------------------+
+; Option ; Setting ;
++----------------+------------------------------------------------------------------------+
+; Device ; EP2C8Q208C8 ;
+; JTAG usercode ; 0xFFFFFFFF ;
+; Checksum ; 0x000C2319 ;
++----------------+------------------------------------------------------------------------+
-+--------------------------------------------------------------------------+
-; Assembler Device Options: D:/dev/quartus/data_selector/data_selector.pof ;
-+--------------------+-----------------------------------------------------+
-; Option ; Setting ;
-+--------------------+-----------------------------------------------------+
-; Device ; EPCS4 ;
-; JTAG usercode ; 0x00000000 ;
-; Checksum ; 0x06EFE46F ;
-; Compression Ratio ; 3 ;
-+--------------------+-----------------------------------------------------+
++-----------------------------------------------------------------------------------------+
+; Assembler Device Options: D:/projects/quartus/double_selector_8b/double_selector_8b.pof ;
++--------------------+--------------------------------------------------------------------+
+; Option ; Setting ;
++--------------------+--------------------------------------------------------------------+
+; Device ; EPCS4 ;
+; JTAG usercode ; 0x00000000 ;
+; Checksum ; 0x06EFE4CF ;
+; Compression Ratio ; 3 ;
++--------------------+--------------------------------------------------------------------+
+--------------------+
@@ -115,15 +115,15 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
- Info: Processing started: Sun Mar 06 21:29:30 2022
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off data_selector -c data_selector
+ Info: Processing started: Mon Mar 07 11:22:46 2022
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b
Info: Writing out detailed assembly data for power analysis
Info: Assembler is generating device programming files
Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
- Info: Peak virtual memory: 221 megabytes
- Info: Processing ended: Sun Mar 06 21:29:31 2022
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:01
+ Info: Peak virtual memory: 241 megabytes
+ Info: Processing ended: Mon Mar 07 11:22:46 2022
+ Info: Elapsed time: 00:00:00
+ Info: Total CPU time (on all processors): 00:00:00
diff --git a/data_selector/data_selector.bdf b/double_selector_8b/double_selector_8b.bdf
similarity index 87%
rename from data_selector/data_selector.bdf
rename to double_selector_8b/double_selector_8b.bdf
index e8c03eb..b616c98 100644
--- a/data_selector/data_selector.bdf
+++ b/double_selector_8b/double_selector_8b.bdf
@@ -22,7 +22,7 @@ applicable agreement for further details.
(header "graphic" (version "1.3"))
(pin
(input)
- (rect 176 64 344 80)
+ (rect 64 272 232 288)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "a0" (rect 5 0 16 12)(font "Arial" ))
(pt 168 8)
@@ -38,7 +38,7 @@ applicable agreement for further details.
)
(pin
(input)
- (rect 176 88 344 104)
+ (rect 64 296 232 312)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "a1" (rect 5 0 16 12)(font "Arial" ))
(pt 168 8)
@@ -54,7 +54,7 @@ applicable agreement for further details.
)
(pin
(input)
- (rect 176 112 344 128)
+ (rect 64 320 232 336)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "a2" (rect 5 0 16 12)(font "Arial" ))
(pt 168 8)
@@ -70,7 +70,7 @@ applicable agreement for further details.
)
(pin
(input)
- (rect 176 136 344 152)
+ (rect 64 344 232 360)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "a3" (rect 5 0 16 12)(font "Arial" ))
(pt 168 8)
@@ -86,7 +86,7 @@ applicable agreement for further details.
)
(pin
(input)
- (rect 176 160 344 176)
+ (rect 64 368 232 384)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "a4" (rect 5 0 16 12)(font "Arial" ))
(pt 168 8)
@@ -102,7 +102,7 @@ applicable agreement for further details.
)
(pin
(input)
- (rect 176 184 344 200)
+ (rect 64 392 232 408)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "a5" (rect 5 0 16 12)(font "Arial" ))
(pt 168 8)
@@ -118,7 +118,7 @@ applicable agreement for further details.
)
(pin
(input)
- (rect 176 208 344 224)
+ (rect 64 416 232 432)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "a6" (rect 5 0 16 12)(font "Arial" ))
(pt 168 8)
@@ -134,7 +134,7 @@ applicable agreement for further details.
)
(pin
(input)
- (rect 176 232 344 248)
+ (rect 64 440 232 456)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "a7" (rect 5 0 16 12)(font "Arial" ))
(pt 168 8)
@@ -150,7 +150,7 @@ applicable agreement for further details.
)
(pin
(input)
- (rect 176 312 344 328)
+ (rect 64 520 232 536)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "b0" (rect 5 0 16 12)(font "Arial" ))
(pt 168 8)
@@ -166,7 +166,7 @@ applicable agreement for further details.
)
(pin
(input)
- (rect 176 336 344 352)
+ (rect 64 544 232 560)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "b1" (rect 5 0 16 12)(font "Arial" ))
(pt 168 8)
@@ -182,7 +182,7 @@ applicable agreement for further details.
)
(pin
(input)
- (rect 176 360 344 376)
+ (rect 64 568 232 584)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "b2" (rect 5 0 16 12)(font "Arial" ))
(pt 168 8)
@@ -198,7 +198,7 @@ applicable agreement for further details.
)
(pin
(input)
- (rect 176 384 344 400)
+ (rect 64 592 232 608)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "b3" (rect 5 0 16 12)(font "Arial" ))
(pt 168 8)
@@ -214,7 +214,7 @@ applicable agreement for further details.
)
(pin
(input)
- (rect 176 408 344 424)
+ (rect 64 616 232 632)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "b4" (rect 5 0 16 12)(font "Arial" ))
(pt 168 8)
@@ -230,7 +230,7 @@ applicable agreement for further details.
)
(pin
(input)
- (rect 176 432 344 448)
+ (rect 64 640 232 656)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "b5" (rect 5 0 16 12)(font "Arial" ))
(pt 168 8)
@@ -246,7 +246,7 @@ applicable agreement for further details.
)
(pin
(input)
- (rect 176 456 344 472)
+ (rect 64 664 232 680)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "b6" (rect 5 0 16 12)(font "Arial" ))
(pt 168 8)
@@ -262,7 +262,7 @@ applicable agreement for further details.
)
(pin
(input)
- (rect 176 480 344 496)
+ (rect 64 688 232 704)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "b7" (rect 5 0 16 12)(font "Arial" ))
(pt 168 8)
@@ -278,7 +278,7 @@ applicable agreement for further details.
)
(pin
(input)
- (rect 176 576 344 592)
+ (rect 40 784 208 800)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "AY" (rect 5 0 20 12)(font "Arial" ))
(pt 168 8)
@@ -294,7 +294,7 @@ applicable agreement for further details.
)
(pin
(input)
- (rect 176 600 344 616)
+ (rect 40 808 208 824)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "BY" (rect 5 0 20 12)(font "Arial" ))
(pt 168 8)
@@ -310,7 +310,7 @@ applicable agreement for further details.
)
(pin
(output)
- (rect 928 -136 1104 -120)
+ (rect 816 72 992 88)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "Y0" (rect 90 0 104 12)(font "Arial" ))
(pt 0 8)
@@ -326,7 +326,7 @@ applicable agreement for further details.
)
(pin
(output)
- (rect 928 -80 1104 -64)
+ (rect 816 128 992 144)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "Y1" (rect 90 0 104 12)(font "Arial" ))
(pt 0 8)
@@ -342,7 +342,7 @@ applicable agreement for further details.
)
(pin
(output)
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- (pt 776 160)
+ (pt 216 216)
+ (pt 216 272)
)
(connector
- (pt 712 160)
- (pt 712 600)
+ (pt 216 272)
+ (pt 216 344)
)
(connector
- (pt 728 656)
- (pt 544 656)
+ (pt 288 536)
+ (pt 288 592)
)
(connector
- (pt 728 656)
- (pt 728 216)
+ (pt 288 592)
+ (pt 288 640)
)
(connector
- (pt 728 216)
- (pt 776 216)
+ (pt 288 640)
+ (pt 288 704)
)
(connector
- (pt 544 712)
- (pt 744 712)
+ (pt 288 704)
+ (pt 288 760)
)
(connector
- (pt 840 -128)
- (pt 928 -128)
+ (pt 288 872)
+ (pt 288 928)
)
(connector
- (pt 840 -72)
- (pt 928 -72)
+ (pt 216 48)
+ (pt 216 104)
)
(connector
- (pt 840 -16)
- (pt 928 -16)
+ (pt 216 104)
+ (pt 216 160)
)
(connector
- (pt 840 40)
- (pt 928 40)
+ (pt 288 760)
+ (pt 288 816)
)
(connector
- (pt 840 96)
- (pt 928 96)
+ (pt 288 816)
+ (pt 288 872)
)
(connector
- (pt 840 152)
- (pt 928 152)
+ (pt 208 816)
+ (pt 288 816)
)
(connector
- (pt 840 208)
- (pt 928 208)
+ (pt 288 816)
+ (pt 368 816)
)
(connector
- (pt 328 -160)
- (pt 328 -104)
+ (pt 216 344)
+ (pt 216 384)
)
(connector
- (pt 560 32)
- (pt 776 32)
+ (pt 216 384)
+ (pt 216 440)
)
(connector
- (pt 840 264)
- (pt 928 264)
+ (pt 216 440)
+ (pt 216 792)
)
-(connector
- (pt 744 272)
- (pt 744 712)
-)
-(connector
- (pt 744 272)
- (pt 776 272)
-)
-(junction (pt 328 -104))
-(junction (pt 328 -48))
-(junction (pt 328 8))
-(junction (pt 328 64))
-(junction (pt 328 136))
-(junction (pt 328 176))
-(junction (pt 328 232))
-(junction (pt 400 608))
-(junction (pt 400 328))
-(junction (pt 400 384))
-(junction (pt 400 432))
-(junction (pt 400 496))
-(junction (pt 400 552))
-(junction (pt 400 664))
-(junction (pt 400 720))
+(junction (pt 216 104))
+(junction (pt 216 160))
+(junction (pt 216 216))
+(junction (pt 216 272))
+(junction (pt 216 344))
+(junction (pt 216 384))
+(junction (pt 288 592))
+(junction (pt 288 640))
+(junction (pt 288 704))
+(junction (pt 288 760))
+(junction (pt 288 872))
+(junction (pt 288 816))
+(junction (pt 216 440))
diff --git a/data_selector/data_selector.bsf b/double_selector_8b/double_selector_8b.bsf
similarity index 98%
rename from data_selector/data_selector.bsf
rename to double_selector_8b/double_selector_8b.bsf
index 25cf9a0..ff68d31 100644
--- a/data_selector/data_selector.bsf
+++ b/double_selector_8b/double_selector_8b.bsf
@@ -21,7 +21,7 @@ applicable agreement for further details.
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 112 368)
- (text "data_selector" (rect 5 0 82 14)(font "Arial" (font_size 8)))
+ (text "double_selector_8b" (rect 5 0 117 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 336 25 348)(font "Arial" ))
(port
(pt 0 32)
diff --git a/double_selector_8b/double_selector_8b.done b/double_selector_8b/double_selector_8b.done
new file mode 100644
index 0000000..42c6fdc
--- /dev/null
+++ b/double_selector_8b/double_selector_8b.done
@@ -0,0 +1 @@
+Mon Mar 07 11:22:47 2022
diff --git a/double_selector_8b/double_selector_8b.dpf b/double_selector_8b/double_selector_8b.dpf
new file mode 100644
index 0000000..abe19d9
--- /dev/null
+++ b/double_selector_8b/double_selector_8b.dpf
@@ -0,0 +1,12 @@
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/data_selector/data_selector.fit.rpt b/double_selector_8b/double_selector_8b.fit.rpt
similarity index 84%
rename from data_selector/data_selector.fit.rpt
rename to double_selector_8b/double_selector_8b.fit.rpt
index 4aa9d68..59b0dd9 100644
--- a/data_selector/data_selector.fit.rpt
+++ b/double_selector_8b/double_selector_8b.fit.rpt
@@ -1,5 +1,5 @@
-Fitter report for data_selector
-Sun Mar 06 21:29:28 2022
+Fitter report for double_selector_8b
+Mon Mar 07 11:22:45 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@@ -63,10 +63,10 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+----------------------------------------------+
-; Fitter Status ; Successful - Sun Mar 06 21:29:28 2022 ;
+; Fitter Status ; Successful - Mon Mar 07 11:22:45 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
-; Revision Name ; data_selector ;
-; Top-level Entity Name ; data_selector ;
+; Revision Name ; double_selector_8b ;
+; Top-level Entity Name ; double_selector_8b ;
; Family ; Cyclone II ;
; Device ; EP2C8Q208C8 ;
; Timing Models ; Final ;
@@ -91,6 +91,7 @@ applicable agreement for further details.
; Minimum Core Junction Temperature ; 0 ; ;
; Maximum Core Junction Temperature ; 85 ; ;
; Fit Attempts to Skip ; 0 ; 0.0 ;
+; Device I/O Standard ; 3.3-V LVTTL ; ;
; Use smart compilation ; Off ; Off ;
; Use TimeQuest Timing Analyzer ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
@@ -137,7 +138,7 @@ applicable agreement for further details.
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
-; Number detected on machine ; 6 ;
+; Number detected on machine ; 4 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
@@ -146,7 +147,6 @@ applicable agreement for further details.
; Usage by Processor ; % Time Used ;
; 1 processor ; 100.0% ;
; 2-4 processors ; < 0.1% ;
-; 5-6 processors ; 0.0% ;
+----------------------------+-------------+
@@ -186,7 +186,7 @@ applicable agreement for further details.
+--------------+
; Pin-Out File ;
+--------------+
-The pin-out file can be found in D:/dev/quartus/data_selector/data_selector.pin.
+The pin-out file can be found in D:/projects/quartus/double_selector_8b/double_selector_8b.pin.
+-------------------------------------------------------------------+
@@ -217,7 +217,7 @@ The pin-out file can be found in D:/dev/quartus/data_selector/data_selector.pin.
; User inserted logic elements ; 0 ;
; Virtual pins ; 0 ;
; I/O pins ; 26 / 138 ( 19 % ) ;
-; -- Clock pins ; 2 / 4 ( 50 % ) ;
+; -- Clock pins ; 1 / 4 ( 25 % ) ;
; Global signals ; 0 ;
; M4Ks ; 0 / 36 ( 0 % ) ;
; Total block memory bits ; 0 / 165,888 ( 0 % ) ;
@@ -246,24 +246,24 @@ The pin-out file can be found in D:/dev/quartus/data_selector/data_selector.pin.
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
-; AY ; 56 ; 4 ; 1 ; 0 ; 3 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; BY ; 44 ; 1 ; 0 ; 3 ; 1 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; a0 ; 39 ; 1 ; 0 ; 5 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; a1 ; 37 ; 1 ; 0 ; 6 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; a2 ; 24 ; 1 ; 0 ; 9 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; a3 ; 28 ; 1 ; 0 ; 9 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; a4 ; 12 ; 1 ; 0 ; 16 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; a5 ; 31 ; 1 ; 0 ; 8 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; a6 ; 34 ; 1 ; 0 ; 7 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; a7 ; 3 ; 1 ; 0 ; 18 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; b0 ; 40 ; 1 ; 0 ; 5 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; b1 ; 23 ; 1 ; 0 ; 9 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; b2 ; 27 ; 1 ; 0 ; 9 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; b3 ; 59 ; 4 ; 1 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; b4 ; 41 ; 1 ; 0 ; 4 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; b5 ; 45 ; 1 ; 0 ; 3 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; b6 ; 57 ; 4 ; 1 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
-; b7 ; 33 ; 1 ; 0 ; 8 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; AY ; 23 ; 1 ; 0 ; 9 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; BY ; 24 ; 1 ; 0 ; 9 ; 1 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; a0 ; 77 ; 4 ; 18 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; a1 ; 80 ; 4 ; 23 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; a2 ; 81 ; 4 ; 23 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; a3 ; 82 ; 4 ; 23 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; a4 ; 84 ; 4 ; 25 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; a5 ; 86 ; 4 ; 25 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; a6 ; 87 ; 4 ; 25 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; a7 ; 88 ; 4 ; 25 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; b0 ; 67 ; 4 ; 9 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; b1 ; 68 ; 4 ; 12 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; b2 ; 69 ; 4 ; 12 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; b3 ; 70 ; 4 ; 14 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; b4 ; 72 ; 4 ; 16 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; b5 ; 74 ; 4 ; 16 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; b6 ; 75 ; 4 ; 16 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+; b7 ; 76 ; 4 ; 18 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
@@ -272,14 +272,14 @@ The pin-out file can be found in D:/dev/quartus/data_selector/data_selector.pin.
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
-; Y0 ; 58 ; 4 ; 1 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; Y1 ; 35 ; 1 ; 0 ; 7 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; Y2 ; 14 ; 1 ; 0 ; 14 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; Y3 ; 15 ; 1 ; 0 ; 14 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; Y4 ; 10 ; 1 ; 0 ; 17 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; Y5 ; 208 ; 2 ; 1 ; 19 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; Y6 ; 30 ; 1 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
-; Y7 ; 48 ; 1 ; 0 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; Y0 ; 142 ; 3 ; 34 ; 12 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; Y1 ; 143 ; 3 ; 34 ; 13 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; Y2 ; 144 ; 3 ; 34 ; 13 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; Y3 ; 145 ; 3 ; 34 ; 14 ; 4 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; Y4 ; 146 ; 3 ; 34 ; 15 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; Y5 ; 147 ; 3 ; 34 ; 15 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; Y6 ; 149 ; 3 ; 34 ; 16 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+; Y7 ; 150 ; 3 ; 34 ; 16 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
@@ -288,10 +288,10 @@ The pin-out file can be found in D:/dev/quartus/data_selector/data_selector.pin.
+----------+------------------+---------------+--------------+
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
+----------+------------------+---------------+--------------+
-; 1 ; 23 / 32 ( 72 % ) ; 3.3V ; -- ;
-; 2 ; 1 / 35 ( 3 % ) ; 3.3V ; -- ;
-; 3 ; 1 / 35 ( 3 % ) ; 3.3V ; -- ;
-; 4 ; 4 / 36 ( 11 % ) ; 3.3V ; -- ;
+; 1 ; 4 / 32 ( 13 % ) ; 3.3V ; -- ;
+; 2 ; 0 / 35 ( 0 % ) ; 3.3V ; -- ;
+; 3 ; 9 / 35 ( 26 % ) ; 3.3V ; -- ;
+; 4 ; 16 / 36 ( 44 % ) ; 3.3V ; -- ;
+----------+------------------+---------------+--------------+
@@ -302,19 +302,19 @@ The pin-out file can be found in D:/dev/quartus/data_selector/data_selector.pin.
+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; 1 ; 0 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
; 2 ; 1 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
-; 3 ; 2 ; 1 ; a7 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 3 ; 2 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 4 ; 3 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 5 ; 4 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 6 ; 5 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 8 ; 6 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 10 ; 7 ; 1 ; Y4 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 10 ; 7 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 11 ; 8 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 12 ; 9 ; 1 ; a4 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 12 ; 9 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 13 ; 10 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 14 ; 18 ; 1 ; Y2 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 15 ; 19 ; 1 ; Y3 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 14 ; 18 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 15 ; 19 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
; 18 ; 22 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
@@ -322,32 +322,32 @@ The pin-out file can be found in D:/dev/quartus/data_selector/data_selector.pin.
; 20 ; 24 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ;
; 21 ; 25 ; 1 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ;
; 22 ; 26 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
-; 23 ; 27 ; 1 ; b1 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 24 ; 28 ; 1 ; a2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 23 ; 27 ; 1 ; AY ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 24 ; 28 ; 1 ; BY ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 26 ; 29 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
-; 27 ; 30 ; 1 ; b2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 28 ; 31 ; 1 ; a3 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 27 ; 30 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; 28 ; 31 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 30 ; 32 ; 1 ; Y6 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 31 ; 33 ; 1 ; a5 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 30 ; 32 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 31 ; 33 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 33 ; 35 ; 1 ; b7 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 34 ; 36 ; 1 ; a6 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 35 ; 37 ; 1 ; Y1 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 33 ; 35 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 34 ; 36 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 35 ; 37 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 37 ; 39 ; 1 ; a1 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 37 ; 39 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 39 ; 43 ; 1 ; a0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 40 ; 44 ; 1 ; b0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 41 ; 45 ; 1 ; b4 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 39 ; 43 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 40 ; 44 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 41 ; 45 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 42 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 43 ; 48 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 44 ; 49 ; 1 ; BY ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
-; 45 ; 50 ; 1 ; b5 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 44 ; 49 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 45 ; 50 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 46 ; 51 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 47 ; 52 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 48 ; 53 ; 1 ; Y7 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 48 ; 53 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 49 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 50 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
; 51 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
@@ -355,10 +355,10 @@ The pin-out file can be found in D:/dev/quartus/data_selector/data_selector.pin.
; 53 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 54 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
; 55 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 56 ; 54 ; 4 ; AY ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
-; 57 ; 55 ; 4 ; b6 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
-; 58 ; 56 ; 4 ; Y0 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
-; 59 ; 57 ; 4 ; b3 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 56 ; 54 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 57 ; 55 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 58 ; 56 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 59 ; 57 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 60 ; 58 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 61 ; 59 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
@@ -366,28 +366,28 @@ The pin-out file can be found in D:/dev/quartus/data_selector/data_selector.pin.
; 64 ; 61 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 67 ; 69 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 68 ; 70 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 69 ; 71 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 70 ; 74 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 67 ; 69 ; 4 ; b0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 68 ; 70 ; 4 ; b1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 69 ; 71 ; 4 ; b2 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 70 ; 74 ; 4 ; b3 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 71 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 72 ; 75 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 72 ; 75 ; 4 ; b4 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 74 ; 76 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 75 ; 77 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 76 ; 78 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 77 ; 79 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 74 ; 76 ; 4 ; b5 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 75 ; 77 ; 4 ; b6 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 76 ; 78 ; 4 ; b7 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 77 ; 79 ; 4 ; a0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 80 ; 82 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 81 ; 83 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 82 ; 84 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 80 ; 82 ; 4 ; a1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 81 ; 83 ; 4 ; a2 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 82 ; 84 ; 4 ; a3 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 83 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 84 ; 85 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 84 ; 85 ; 4 ; a4 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 85 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 86 ; 86 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 87 ; 87 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 88 ; 88 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 86 ; 86 ; 4 ; a5 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 87 ; 87 ; 4 ; a6 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+; 88 ; 88 ; 4 ; a7 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 89 ; 89 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 90 ; 90 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 91 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
@@ -441,15 +441,15 @@ The pin-out file can be found in D:/dev/quartus/data_selector/data_selector.pin.
; 139 ; 136 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 141 ; 137 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 142 ; 138 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 143 ; 141 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 144 ; 142 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 145 ; 143 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 146 ; 149 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 147 ; 150 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 142 ; 138 ; 3 ; Y0 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 143 ; 141 ; 3 ; Y1 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 144 ; 142 ; 3 ; Y2 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 145 ; 143 ; 3 ; Y3 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 146 ; 149 ; 3 ; Y4 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 147 ; 150 ; 3 ; Y5 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 148 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 149 ; 151 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 150 ; 152 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 149 ; 151 ; 3 ; Y6 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
+; 150 ; 152 ; 3 ; Y7 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 151 ; 153 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 152 ; 154 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 153 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
@@ -507,7 +507,7 @@ The pin-out file can be found in D:/dev/quartus/data_selector/data_selector.pin.
; 205 ; 199 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 206 ; 200 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 207 ; 201 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 208 ; 202 ; 2 ; Y5 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 208 ; 202 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
@@ -554,7 +554,7 @@ Note: User assignments will override these defaults. The user specified values a
+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
-; |data_selector ; 8 (8) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 26 ; 0 ; 8 (8) ; 0 (0) ; 0 (0) ; |data_selector ; work ;
+; |double_selector_8b ; 8 (8) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 26 ; 0 ; 8 (8) ; 0 (0) ; 0 (0) ; |double_selector_8b ; work ;
+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@@ -574,13 +574,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Y7 ; Output ; -- ; -- ; -- ; -- ;
; b0 ; Input ; 6 ; 6 ; -- ; -- ;
; a0 ; Input ; 6 ; 6 ; -- ; -- ;
-; AY ; Input ; 6 ; 6 ; -- ; -- ;
-; BY ; Input ; 6 ; 6 ; -- ; -- ;
+; AY ; Input ; 0 ; 0 ; -- ; -- ;
+; BY ; Input ; 0 ; 0 ; -- ; -- ;
; a1 ; Input ; 6 ; 6 ; -- ; -- ;
-; b1 ; Input ; 0 ; 0 ; -- ; -- ;
-; a2 ; Input ; 0 ; 0 ; -- ; -- ;
-; b2 ; Input ; 0 ; 0 ; -- ; -- ;
-; a3 ; Input ; 0 ; 0 ; -- ; -- ;
+; b1 ; Input ; 6 ; 6 ; -- ; -- ;
+; a2 ; Input ; 6 ; 6 ; -- ; -- ;
+; b2 ; Input ; 6 ; 6 ; -- ; -- ;
+; a3 ; Input ; 6 ; 6 ; -- ; -- ;
; b3 ; Input ; 6 ; 6 ; -- ; -- ;
; a4 ; Input ; 6 ; 6 ; -- ; -- ;
; b4 ; Input ; 6 ; 6 ; -- ; -- ;
@@ -599,47 +599,35 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
+---------------------+-------------------+---------+
; b0 ; ; ;
-; - inst1 ; 1 ; 6 ;
+; - inst1 ; 0 ; 6 ;
; a0 ; ; ;
; - inst1 ; 0 ; 6 ;
; AY ; ; ;
-; - inst1 ; 0 ; 6 ;
-; - inst2 ; 0 ; 6 ;
-; - inst3 ; 0 ; 6 ;
-; - inst4 ; 0 ; 6 ;
-; - inst5 ; 0 ; 6 ;
-; - inst6 ; 0 ; 6 ;
-; - inst7 ; 0 ; 6 ;
-; - inst8 ; 0 ; 6 ;
; BY ; ; ;
-; - inst1 ; 1 ; 6 ;
-; - inst2 ; 1 ; 6 ;
-; - inst3 ; 1 ; 6 ;
-; - inst4 ; 1 ; 6 ;
-; - inst5 ; 1 ; 6 ;
-; - inst6 ; 1 ; 6 ;
-; - inst7 ; 1 ; 6 ;
-; - inst8 ; 1 ; 6 ;
; a1 ; ; ;
; - inst2 ; 0 ; 6 ;
; b1 ; ; ;
+; - inst2 ; 0 ; 6 ;
; a2 ; ; ;
+; - inst3 ; 0 ; 6 ;
; b2 ; ; ;
+; - inst3 ; 0 ; 6 ;
; a3 ; ; ;
-; b3 ; ; ;
; - inst4 ; 0 ; 6 ;
+; b3 ; ; ;
+; - inst4 ; 1 ; 6 ;
; a4 ; ; ;
; - inst5 ; 0 ; 6 ;
; b4 ; ; ;
-; - inst5 ; 1 ; 6 ;
+; - inst5 ; 0 ; 6 ;
; a5 ; ; ;
; - inst6 ; 0 ; 6 ;
; b5 ; ; ;
-; - inst6 ; 1 ; 6 ;
+; - inst6 ; 0 ; 6 ;
; a6 ; ; ;
; - inst7 ; 0 ; 6 ;
; b6 ; ; ;
-; - inst7 ; 1 ; 6 ;
+; - inst7 ; 0 ; 6 ;
; a7 ; ; ;
; - inst8 ; 0 ; 6 ;
; b7 ; ; ;
@@ -687,13 +675,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Interconnect Resource Type ; Usage ;
+----------------------------+-----------------------+
; Block interconnects ; 26 / 26,052 ( < 1 % ) ;
-; C16 interconnects ; 3 / 1,156 ( < 1 % ) ;
-; C4 interconnects ; 35 / 17,952 ( < 1 % ) ;
+; C16 interconnects ; 7 / 1,156 ( < 1 % ) ;
+; C4 interconnects ; 42 / 17,952 ( < 1 % ) ;
; Direct links ; 0 / 26,052 ( 0 % ) ;
; Global clocks ; 0 / 8 ( 0 % ) ;
; Local interconnects ; 0 / 8,256 ( 0 % ) ;
-; R24 interconnects ; 0 / 1,020 ( 0 % ) ;
-; R4 interconnects ; 3 / 22,440 ( < 1 % ) ;
+; R24 interconnects ; 9 / 1,020 ( < 1 % ) ;
+; R4 interconnects ; 33 / 22,440 ( < 1 % ) ;
+----------------------------+-----------------------+
@@ -870,6 +858,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Name ; Value ;
+------------------------------------+------------+
; Auto Fit Point 2 - Fit Attempt 1 ; ff ;
+; Early Wire Use - Fit Attempt 1 ; 0 ;
+; Early Slack - Fit Attempt 1 ; 2147483639 ;
; Auto Fit Point 5 - Fit Attempt 1 ; ff ;
; Mid Wire Use - Fit Attempt 1 ; 0 ;
; Mid Slack - Fit Attempt 1 ; 2147483639 ;
@@ -897,7 +887,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+------------------------------------+-------------+
; Early Slack - Fit Attempt 1 ; 2147483639 ;
; Early Wire Use - Fit Attempt 1 ; 0 ;
-; Peak Regional Wire - Fit Attempt 1 ; 0 ;
+; Peak Regional Wire - Fit Attempt 1 ; 1 ;
; Mid Slack - Fit Attempt 1 ; 2147483639 ;
; Late Slack - Fit Attempt 1 ; -2147483648 ;
; Late Wire Use - Fit Attempt 1 ; 0 ;
@@ -911,10 +901,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
- Info: Processing started: Sun Mar 06 21:29:26 2022
-Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off data_selector -c data_selector
-Info: Parallel compilation is enabled and will use 4 of the 6 processors detected
-Info: Selected device EP2C8Q208C8 for design "data_selector"
+ Info: Processing started: Mon Mar 07 11:22:44 2022
+Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b
+Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info: Selected device EP2C8Q208C8 for design "double_selector_8b"
Info: Low junction temperature is 0 degrees C
Info: High junction temperature is 85 degrees C
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
@@ -926,48 +916,12 @@ Info: Fitter converted 3 user pins into dedicated programming pins
Info: Pin ~ASDO~ is reserved at location 1
Info: Pin ~nCSO~ is reserved at location 2
Info: Pin ~LVDS54p/nCEO~ is reserved at location 108
-Warning: No exact pin location assignment(s) for 26 pins of 26 total pins
- Info: Pin Y0 not assigned to an exact location on the device
- Info: Pin Y1 not assigned to an exact location on the device
- Info: Pin Y2 not assigned to an exact location on the device
- Info: Pin Y3 not assigned to an exact location on the device
- Info: Pin Y4 not assigned to an exact location on the device
- Info: Pin Y5 not assigned to an exact location on the device
- Info: Pin Y6 not assigned to an exact location on the device
- Info: Pin Y7 not assigned to an exact location on the device
- Info: Pin b0 not assigned to an exact location on the device
- Info: Pin a0 not assigned to an exact location on the device
- Info: Pin AY not assigned to an exact location on the device
- Info: Pin BY not assigned to an exact location on the device
- Info: Pin a1 not assigned to an exact location on the device
- Info: Pin b1 not assigned to an exact location on the device
- Info: Pin a2 not assigned to an exact location on the device
- Info: Pin b2 not assigned to an exact location on the device
- Info: Pin a3 not assigned to an exact location on the device
- Info: Pin b3 not assigned to an exact location on the device
- Info: Pin a4 not assigned to an exact location on the device
- Info: Pin b4 not assigned to an exact location on the device
- Info: Pin a5 not assigned to an exact location on the device
- Info: Pin b5 not assigned to an exact location on the device
- Info: Pin a6 not assigned to an exact location on the device
- Info: Pin b6 not assigned to an exact location on the device
- Info: Pin a7 not assigned to an exact location on the device
- Info: Pin b7 not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Starting register packing
Info: Finished register packing
Extra Info: No registers were packed into other blocks
-Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
- Info: Number of I/O pins in group: 26 (unused VREF, 3.3V VCCIO, 18 input, 8 output, 0 bidirectional)
- Info: I/O standards used: 3.3-V LVTTL.
-Info: I/O bank details before I/O pin placement
- Info: Statistics of I/O banks
- Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available
- Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available
- Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available
- Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available
-Info: Fitter preparation operations ending: elapsed time is 00:00:01
+Info: Fitter preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
@@ -975,7 +929,7 @@ Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources
- Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9
+ Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X34_Y9
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
@@ -991,17 +945,17 @@ Warning: Found 8 output pins without output pin load capacitance assignment
Info: Pin "Y6" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "Y7" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
-Info: Generated suppressed messages file D:/dev/quartus/data_selector/data_selector.fit.smsg
-Info: Quartus II Fitter was successful. 0 errors, 2 warnings
- Info: Peak virtual memory: 286 megabytes
- Info: Processing ended: Sun Mar 06 21:29:29 2022
- Info: Elapsed time: 00:00:03
+Info: Generated suppressed messages file D:/projects/quartus/double_selector_8b/double_selector_8b.fit.smsg
+Info: Quartus II Fitter was successful. 0 errors, 1 warning
+ Info: Peak virtual memory: 307 megabytes
+ Info: Processing ended: Mon Mar 07 11:22:45 2022
+ Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
-The suppressed messages can be found in D:/dev/quartus/data_selector/data_selector.fit.smsg.
+The suppressed messages can be found in D:/projects/quartus/double_selector_8b/double_selector_8b.fit.smsg.
diff --git a/data_selector/data_selector.fit.smsg b/double_selector_8b/double_selector_8b.fit.smsg
similarity index 100%
rename from data_selector/data_selector.fit.smsg
rename to double_selector_8b/double_selector_8b.fit.smsg
diff --git a/data_selector/data_selector.fit.summary b/double_selector_8b/double_selector_8b.fit.summary
similarity index 78%
rename from data_selector/data_selector.fit.summary
rename to double_selector_8b/double_selector_8b.fit.summary
index 812a951..69240c2 100644
--- a/data_selector/data_selector.fit.summary
+++ b/double_selector_8b/double_selector_8b.fit.summary
@@ -1,7 +1,7 @@
-Fitter Status : Successful - Sun Mar 06 21:29:28 2022
+Fitter Status : Successful - Mon Mar 07 11:22:45 2022
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
-Revision Name : data_selector
-Top-level Entity Name : data_selector
+Revision Name : double_selector_8b
+Top-level Entity Name : double_selector_8b
Family : Cyclone II
Device : EP2C8Q208C8
Timing Models : Final
diff --git a/data_selector/data_selector.flow.rpt b/double_selector_8b/double_selector_8b.flow.rpt
similarity index 69%
rename from data_selector/data_selector.flow.rpt
rename to double_selector_8b/double_selector_8b.flow.rpt
index 403e9a8..959e6e9 100644
--- a/data_selector/data_selector.flow.rpt
+++ b/double_selector_8b/double_selector_8b.flow.rpt
@@ -1,5 +1,5 @@
-Flow report for data_selector
-Sun Mar 06 21:30:44 2022
+Flow report for double_selector_8b
+Mon Mar 07 11:22:47 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@@ -38,10 +38,10 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+----------------------------------------------+
-; Flow Status ; Successful - Sun Mar 06 21:30:44 2022 ;
+; Flow Status ; Successful - Mon Mar 07 11:22:47 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
-; Revision Name ; data_selector ;
-; Top-level Entity Name ; data_selector ;
+; Revision Name ; double_selector_8b ;
+; Top-level Entity Name ; double_selector_8b ;
; Family ; Cyclone II ;
; Device ; EP2C8Q208C8 ;
; Timing Models ; Final ;
@@ -63,25 +63,25 @@ applicable agreement for further details.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
-; Start date & time ; 03/06/2022 21:29:24 ;
+; Start date & time ; 03/07/2022 11:22:43 ;
; Main task ; Compilation ;
-; Revision Name ; data_selector ;
+; Revision Name ; double_selector_8b ;
+-------------------+---------------------+
-+-----------------------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+------------------------------------+-----------------------------------------------------+---------------+-------------+----------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+------------------------------------+-----------------------------------------------------+---------------+-------------+----------------+
-; COMPILER_SIGNATURE_ID ; 136411542855513.164657336336460 ; -- ; -- ; -- ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
-; MISC_FILE ; D:/projects/quartus/data_selector/data_selector.dpf ; -- ; -- ; -- ;
-; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
-; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
-; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
-+------------------------------------+-----------------------------------------------------+---------------+-------------+----------------+
++---------------------------------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings ;
++------------------------------------+---------------------------------------------------------------+---------------+-------------+----------------+
+; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
++------------------------------------+---------------------------------------------------------------+---------------+-------------+----------------+
+; COMPILER_SIGNATURE_ID ; 220283517943889.164662336312624 ; -- ; -- ; -- ;
+; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
+; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
+; MISC_FILE ; D:/projects/quartus/double_selector_8b/double_selector_8b.dpf ; -- ; -- ; -- ;
+; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
+; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
+; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
++------------------------------------+---------------------------------------------------------------+---------------+-------------+----------------+
+-----------------------------------------------------------------------------------------------------------------------------+
@@ -89,11 +89,11 @@ applicable agreement for further details.
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 226 MB ; 00:00:01 ;
-; Fitter ; 00:00:02 ; 1.0 ; 286 MB ; 00:00:01 ;
-; Assembler ; 00:00:01 ; 1.0 ; 221 MB ; 00:00:01 ;
-; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 178 MB ; 00:00:00 ;
-; Total ; 00:00:04 ; -- ; -- ; 00:00:03 ;
+; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 246 MB ; 00:00:00 ;
+; Fitter ; 00:00:01 ; 1.0 ; 307 MB ; 00:00:01 ;
+; Assembler ; 00:00:00 ; 1.0 ; 241 MB ; 00:00:00 ;
+; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 198 MB ; 00:00:00 ;
+; Total ; 00:00:01 ; -- ; -- ; 00:00:01 ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
@@ -102,21 +102,20 @@ applicable agreement for further details.
+-------------------------+------------------+---------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+-------------------------+------------------+---------------+------------+----------------+
-; Analysis & Synthesis ; DESKTOP-G0CBSMT ; Windows Vista ; 6.2 ; x86_64 ;
-; Fitter ; DESKTOP-G0CBSMT ; Windows Vista ; 6.2 ; x86_64 ;
-; Assembler ; DESKTOP-G0CBSMT ; Windows Vista ; 6.2 ; x86_64 ;
-; Classic Timing Analyzer ; DESKTOP-G0CBSMT ; Windows Vista ; 6.2 ; x86_64 ;
+; Analysis & Synthesis ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
+; Fitter ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
+; Assembler ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
+; Classic Timing Analyzer ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
+-------------------------+------------------+---------------+------------+----------------+
------------
; Flow Log ;
------------
-quartus_map --read_settings_files=on --write_settings_files=off data_selector -c data_selector
-quartus_fit --read_settings_files=off --write_settings_files=off data_selector -c data_selector
-quartus_asm --read_settings_files=off --write_settings_files=off data_selector -c data_selector
-quartus_tan --read_settings_files=off --write_settings_files=off data_selector -c data_selector --timing_analysis_only
-quartus_eda --read_settings_files=on --write_settings_files=off data_selector -c data_selector
+quartus_map --read_settings_files=on --write_settings_files=off double_selector_8b -c double_selector_8b
+quartus_fit --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b
+quartus_asm --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b
+quartus_tan --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b --timing_analysis_only
diff --git a/data_selector/data_selector.map.rpt b/double_selector_8b/double_selector_8b.map.rpt
similarity index 92%
rename from data_selector/data_selector.map.rpt
rename to double_selector_8b/double_selector_8b.map.rpt
index 3d23707..0b9d6f6 100644
--- a/data_selector/data_selector.map.rpt
+++ b/double_selector_8b/double_selector_8b.map.rpt
@@ -1,5 +1,5 @@
-Analysis & Synthesis report for data_selector
-Sun Mar 06 21:29:25 2022
+Analysis & Synthesis report for double_selector_8b
+Mon Mar 07 11:22:43 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@@ -39,10 +39,10 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+----------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Sun Mar 06 21:29:25 2022 ;
+; Analysis & Synthesis Status ; Successful - Mon Mar 07 11:22:43 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
-; Revision Name ; data_selector ;
-; Top-level Entity Name ; data_selector ;
+; Revision Name ; double_selector_8b ;
+; Top-level Entity Name ; double_selector_8b ;
; Family ; Cyclone II ;
; Total logic elements ; 8 ;
; Total combinational functions ; 8 ;
@@ -62,7 +62,7 @@ applicable agreement for further details.
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------+--------------------+--------------------+
; Device ; EP2C8Q208C8 ; ;
-; Top-level entity name ; data_selector ; data_selector ;
+; Top-level entity name ; double_selector_8b ; double_selector_8b ;
; Family name ; Cyclone II ; Stratix II ;
; Use Generated Physical Constraints File ; Off ; ;
; Use smart compilation ; Off ; Off ;
@@ -131,13 +131,13 @@ applicable agreement for further details.
+--------------------------------------------------------------+--------------------+--------------------+
-+------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+------------------------------------+------------------------------------------------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
-+----------------------------------+-----------------+------------------------------------+------------------------------------------------+
-; data_selector.bdf ; yes ; User Block Diagram/Schematic File ; D:/dev/quartus/data_selector/data_selector.bdf ;
-+----------------------------------+-----------------+------------------------------------+------------------------------------------------+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
++----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+
+; double_selector_8b.bdf ; yes ; User Block Diagram/Schematic File ; D:/projects/quartus/double_selector_8b/double_selector_8b.bdf ;
++----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+
+-----------------------------------------------------+
@@ -174,7 +174,7 @@ applicable agreement for further details.
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
-; |data_selector ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 26 ; 0 ; |data_selector ; work ;
+; |double_selector_8b ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 26 ; 0 ; |double_selector_8b ; work ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@@ -200,19 +200,19 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
- Info: Processing started: Sun Mar 06 21:29:23 2022
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off data_selector -c data_selector
-Info: Found 1 design units, including 1 entities, in source file data_selector.bdf
- Info: Found entity 1: data_selector
-Info: Elaborating entity "data_selector" for the top level hierarchy
+ Info: Processing started: Mon Mar 07 11:22:43 2022
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off double_selector_8b -c double_selector_8b
+Info: Found 1 design units, including 1 entities, in source file double_selector_8b.bdf
+ Info: Found entity 1: double_selector_8b
+Info: Elaborating entity "double_selector_8b" for the top level hierarchy
Info: Implemented 34 device resources after synthesis - the final resource count might be different
Info: Implemented 18 input pins
Info: Implemented 8 output pins
Info: Implemented 8 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
- Info: Peak virtual memory: 230 megabytes
- Info: Processing ended: Sun Mar 06 21:29:25 2022
- Info: Elapsed time: 00:00:02
- Info: Total CPU time (on all processors): 00:00:01
+ Info: Peak virtual memory: 250 megabytes
+ Info: Processing ended: Mon Mar 07 11:22:43 2022
+ Info: Elapsed time: 00:00:00
+ Info: Total CPU time (on all processors): 00:00:00
diff --git a/data_selector/data_selector.map.summary b/double_selector_8b/double_selector_8b.map.summary
similarity index 69%
rename from data_selector/data_selector.map.summary
rename to double_selector_8b/double_selector_8b.map.summary
index 49cc5f2..22369a7 100644
--- a/data_selector/data_selector.map.summary
+++ b/double_selector_8b/double_selector_8b.map.summary
@@ -1,7 +1,7 @@
-Analysis & Synthesis Status : Successful - Sun Mar 06 21:29:25 2022
+Analysis & Synthesis Status : Successful - Mon Mar 07 11:22:43 2022
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
-Revision Name : data_selector
-Top-level Entity Name : data_selector
+Revision Name : double_selector_8b
+Top-level Entity Name : double_selector_8b
Family : Cyclone II
Total logic elements : 8
Total combinational functions : 8
diff --git a/data_selector/data_selector.pin b/double_selector_8b/double_selector_8b.pin
similarity index 80%
rename from data_selector/data_selector.pin
rename to double_selector_8b/double_selector_8b.pin
index a5a89bd..3b67fe5 100644
--- a/data_selector/data_selector.pin
+++ b/double_selector_8b/double_selector_8b.pin
@@ -64,25 +64,25 @@
---------------------------------------------------------------------------------
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
-CHIP "data_selector" ASSIGNED TO AN: EP2C8Q208C8
+CHIP "double_selector_8b" ASSIGNED TO AN: EP2C8Q208C8
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVTTL : : 1 : N
~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVTTL : : 1 : N
-a7 : 3 : input : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 3 : : : : 1 :
RESERVED_INPUT : 4 : : : : 1 :
RESERVED_INPUT : 5 : : : : 1 :
RESERVED_INPUT : 6 : : : : 1 :
VCCIO1 : 7 : power : : 3.3V : 1 :
RESERVED_INPUT : 8 : : : : 1 :
GND : 9 : gnd : : : :
-Y4 : 10 : output : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 10 : : : : 1 :
RESERVED_INPUT : 11 : : : : 1 :
-a4 : 12 : input : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 12 : : : : 1 :
RESERVED_INPUT : 13 : : : : 1 :
-Y2 : 14 : output : 3.3-V LVTTL : : 1 : N
-Y3 : 15 : output : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 14 : : : : 1 :
+RESERVED_INPUT : 15 : : : : 1 :
TDO : 16 : output : : : 1 :
TMS : 17 : input : : : 1 :
TCK : 18 : input : : : 1 :
@@ -90,32 +90,32 @@ TDI : 19 : input : :
DATA0 : 20 : input : : : 1 :
DCLK : 21 : : : : 1 :
nCE : 22 : : : : 1 :
-b1 : 23 : input : 3.3-V LVTTL : : 1 : N
-a2 : 24 : input : 3.3-V LVTTL : : 1 : N
+AY : 23 : input : 3.3-V LVTTL : : 1 : Y
+BY : 24 : input : 3.3-V LVTTL : : 1 : Y
GND : 25 : gnd : : : :
nCONFIG : 26 : : : : 1 :
-b2 : 27 : input : 3.3-V LVTTL : : 1 : N
-a3 : 28 : input : 3.3-V LVTTL : : 1 : N
+GND+ : 27 : : : : 1 :
+GND+ : 28 : : : : 1 :
VCCIO1 : 29 : power : : 3.3V : 1 :
-Y6 : 30 : output : 3.3-V LVTTL : : 1 : N
-a5 : 31 : input : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 30 : : : : 1 :
+RESERVED_INPUT : 31 : : : : 1 :
VCCINT : 32 : power : : 1.2V : :
-b7 : 33 : input : 3.3-V LVTTL : : 1 : N
-a6 : 34 : input : 3.3-V LVTTL : : 1 : N
-Y1 : 35 : output : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 33 : : : : 1 :
+RESERVED_INPUT : 34 : : : : 1 :
+RESERVED_INPUT : 35 : : : : 1 :
GND : 36 : gnd : : : :
-a1 : 37 : input : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 37 : : : : 1 :
GND : 38 : gnd : : : :
-a0 : 39 : input : 3.3-V LVTTL : : 1 : N
-b0 : 40 : input : 3.3-V LVTTL : : 1 : N
-b4 : 41 : input : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 39 : : : : 1 :
+RESERVED_INPUT : 40 : : : : 1 :
+RESERVED_INPUT : 41 : : : : 1 :
VCCIO1 : 42 : power : : 3.3V : 1 :
RESERVED_INPUT : 43 : : : : 1 :
-BY : 44 : input : 3.3-V LVTTL : : 1 : N
-b5 : 45 : input : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 44 : : : : 1 :
+RESERVED_INPUT : 45 : : : : 1 :
RESERVED_INPUT : 46 : : : : 1 :
RESERVED_INPUT : 47 : : : : 1 :
-Y7 : 48 : output : 3.3-V LVTTL : : 1 : N
+RESERVED_INPUT : 48 : : : : 1 :
GND : 49 : gnd : : : :
GND_PLL1 : 50 : gnd : : : :
VCCD_PLL1 : 51 : power : : 1.2V : :
@@ -123,10 +123,10 @@ GND_PLL1 : 52 : gnd : :
VCCA_PLL1 : 53 : power : : 1.2V : :
GNDA_PLL1 : 54 : gnd : : : :
GND : 55 : gnd : : : :
-AY : 56 : input : 3.3-V LVTTL : : 4 : N
-b6 : 57 : input : 3.3-V LVTTL : : 4 : N
-Y0 : 58 : output : 3.3-V LVTTL : : 4 : N
-b3 : 59 : input : 3.3-V LVTTL : : 4 : N
+RESERVED_INPUT : 56 : : : : 4 :
+RESERVED_INPUT : 57 : : : : 4 :
+RESERVED_INPUT : 58 : : : : 4 :
+RESERVED_INPUT : 59 : : : : 4 :
RESERVED_INPUT : 60 : : : : 4 :
RESERVED_INPUT : 61 : : : : 4 :
VCCIO4 : 62 : power : : 3.3V : 4 :
@@ -134,28 +134,28 @@ RESERVED_INPUT : 63 : : :
RESERVED_INPUT : 64 : : : : 4 :
GND : 65 : gnd : : : :
VCCINT : 66 : power : : 1.2V : :
-RESERVED_INPUT : 67 : : : : 4 :
-RESERVED_INPUT : 68 : : : : 4 :
-RESERVED_INPUT : 69 : : : : 4 :
-RESERVED_INPUT : 70 : : : : 4 :
+b0 : 67 : input : 3.3-V LVTTL : : 4 : Y
+b1 : 68 : input : 3.3-V LVTTL : : 4 : Y
+b2 : 69 : input : 3.3-V LVTTL : : 4 : Y
+b3 : 70 : input : 3.3-V LVTTL : : 4 : Y
VCCIO4 : 71 : power : : 3.3V : 4 :
-RESERVED_INPUT : 72 : : : : 4 :
+b4 : 72 : input : 3.3-V LVTTL : : 4 : Y
GND : 73 : gnd : : : :
-RESERVED_INPUT : 74 : : : : 4 :
-RESERVED_INPUT : 75 : : : : 4 :
-RESERVED_INPUT : 76 : : : : 4 :
-RESERVED_INPUT : 77 : : : : 4 :
+b5 : 74 : input : 3.3-V LVTTL : : 4 : Y
+b6 : 75 : input : 3.3-V LVTTL : : 4 : Y
+b7 : 76 : input : 3.3-V LVTTL : : 4 : Y
+a0 : 77 : input : 3.3-V LVTTL : : 4 : Y
GND : 78 : gnd : : : :
VCCINT : 79 : power : : 1.2V : :
-RESERVED_INPUT : 80 : : : : 4 :
-RESERVED_INPUT : 81 : : : : 4 :
-RESERVED_INPUT : 82 : : : : 4 :
+a1 : 80 : input : 3.3-V LVTTL : : 4 : Y
+a2 : 81 : input : 3.3-V LVTTL : : 4 : Y
+a3 : 82 : input : 3.3-V LVTTL : : 4 : Y
VCCIO4 : 83 : power : : 3.3V : 4 :
-RESERVED_INPUT : 84 : : : : 4 :
+a4 : 84 : input : 3.3-V LVTTL : : 4 : Y
GND : 85 : gnd : : : :
-RESERVED_INPUT : 86 : : : : 4 :
-RESERVED_INPUT : 87 : : : : 4 :
-RESERVED_INPUT : 88 : : : : 4 :
+a5 : 86 : input : 3.3-V LVTTL : : 4 : Y
+a6 : 87 : input : 3.3-V LVTTL : : 4 : Y
+a7 : 88 : input : 3.3-V LVTTL : : 4 : Y
RESERVED_INPUT : 89 : : : : 4 :
RESERVED_INPUT : 90 : : : : 4 :
VCCIO4 : 91 : power : : 3.3V : 4 :
@@ -209,15 +209,15 @@ RESERVED_INPUT : 138 : : :
RESERVED_INPUT : 139 : : : : 3 :
GND : 140 : gnd : : : :
RESERVED_INPUT : 141 : : : : 3 :
-RESERVED_INPUT : 142 : : : : 3 :
-RESERVED_INPUT : 143 : : : : 3 :
-RESERVED_INPUT : 144 : : : : 3 :
-RESERVED_INPUT : 145 : : : : 3 :
-RESERVED_INPUT : 146 : : : : 3 :
-RESERVED_INPUT : 147 : : : : 3 :
+Y0 : 142 : output : 3.3-V LVTTL : : 3 : Y
+Y1 : 143 : output : 3.3-V LVTTL : : 3 : Y
+Y2 : 144 : output : 3.3-V LVTTL : : 3 : Y
+Y3 : 145 : output : 3.3-V LVTTL : : 3 : Y
+Y4 : 146 : output : 3.3-V LVTTL : : 3 : Y
+Y5 : 147 : output : 3.3-V LVTTL : : 3 : Y
VCCIO3 : 148 : power : : 3.3V : 3 :
-RESERVED_INPUT : 149 : : : : 3 :
-RESERVED_INPUT : 150 : : : : 3 :
+Y6 : 149 : output : 3.3-V LVTTL : : 3 : Y
+Y7 : 150 : output : 3.3-V LVTTL : : 3 : Y
RESERVED_INPUT : 151 : : : : 3 :
RESERVED_INPUT : 152 : : : : 3 :
GND : 153 : gnd : : : :
@@ -275,4 +275,4 @@ GND : 204 : gnd : :
RESERVED_INPUT : 205 : : : : 2 :
RESERVED_INPUT : 206 : : : : 2 :
RESERVED_INPUT : 207 : : : : 2 :
-Y5 : 208 : output : 3.3-V LVTTL : : 2 : N
+RESERVED_INPUT : 208 : : : : 2 :
diff --git a/data_selector/data_selector.pof b/double_selector_8b/double_selector_8b.pof
similarity index 93%
rename from data_selector/data_selector.pof
rename to double_selector_8b/double_selector_8b.pof
index 044a1d0..00ffa17 100644
Binary files a/data_selector/data_selector.pof and b/double_selector_8b/double_selector_8b.pof differ
diff --git a/data_selector/data_selector.qpf b/double_selector_8b/double_selector_8b.qpf
similarity index 90%
rename from data_selector/data_selector.qpf
rename to double_selector_8b/double_selector_8b.qpf
index 32e9aef..fb5934c 100644
--- a/data_selector/data_selector.qpf
+++ b/double_selector_8b/double_selector_8b.qpf
@@ -18,13 +18,13 @@
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
-# Date created = 19:48:38 March 05, 2022
+# Date created = 11:06:00 March 07, 2022
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "9.0"
-DATE = "19:48:38 March 05, 2022"
+DATE = "11:06:00 March 07, 2022"
# Revisions
-PROJECT_REVISION = "data_selector"
+PROJECT_REVISION = "double_selector_8b"
diff --git a/data_selector/data_selector.qsf b/double_selector_8b/double_selector_8b.qsf
similarity index 62%
rename from data_selector/data_selector.qsf
rename to double_selector_8b/double_selector_8b.qsf
index a1faa02..606e5a3 100644
--- a/data_selector/data_selector.qsf
+++ b/double_selector_8b/double_selector_8b.qsf
@@ -18,14 +18,14 @@
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
-# Date created = 19:48:38 March 05, 2022
+# Date created = 11:06:00 March 07, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
-# data_selector_assignment_defaults.qdf
+# double_selector_8b_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
@@ -38,20 +38,46 @@
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C8Q208C8
-set_global_assignment -name TOP_LEVEL_ENTITY data_selector
+set_global_assignment -name TOP_LEVEL_ENTITY double_selector_8b
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:48:38 MARCH 05, 2022"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:06:00 MARCH 07, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name BDF_FILE data_selector.bdf
-set_global_assignment -name USE_CONFIGURATION_DEVICE ON
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
+set_global_assignment -name BDF_FILE double_selector_8b.bdf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-set_global_assignment -name MISC_FILE "D:/projects/quartus/data_selector/data_selector.dpf"
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
\ No newline at end of file
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_location_assignment PIN_77 -to a0
+set_location_assignment PIN_80 -to a1
+set_location_assignment PIN_81 -to a2
+set_location_assignment PIN_82 -to a3
+set_location_assignment PIN_84 -to a4
+set_location_assignment PIN_86 -to a5
+set_location_assignment PIN_87 -to a6
+set_location_assignment PIN_88 -to a7
+set_location_assignment PIN_67 -to b0
+set_location_assignment PIN_68 -to b1
+set_location_assignment PIN_69 -to b2
+set_location_assignment PIN_70 -to b3
+set_location_assignment PIN_72 -to b4
+set_location_assignment PIN_74 -to b5
+set_location_assignment PIN_75 -to b6
+set_location_assignment PIN_76 -to b7
+set_location_assignment PIN_23 -to AY
+set_location_assignment PIN_24 -to BY
+set_location_assignment PIN_142 -to Y0
+set_location_assignment PIN_143 -to Y1
+set_location_assignment PIN_144 -to Y2
+set_location_assignment PIN_145 -to Y3
+set_location_assignment PIN_146 -to Y4
+set_location_assignment PIN_147 -to Y5
+set_location_assignment PIN_149 -to Y6
+set_location_assignment PIN_150 -to Y7
+set_global_assignment -name MISC_FILE "D:/projects/quartus/double_selector_8b/double_selector_8b.dpf"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
\ No newline at end of file
diff --git a/data_selector/data_selector.qws b/double_selector_8b/double_selector_8b.qws
similarity index 92%
rename from data_selector/data_selector.qws
rename to double_selector_8b/double_selector_8b.qws
index 42962c6..b5f620c 100644
--- a/data_selector/data_selector.qws
+++ b/double_selector_8b/double_selector_8b.qws
@@ -7,7 +7,7 @@ ptn_Child1=Document-0
[ProjectWorkspace.Frames.ChildFrames.Document-0]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
-DocPathName=data_selector.bdf
+DocPathName=double_selector_8b.bdf
DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde}
IsChildFrameDetached=False
IsActiveChildFrame=True
diff --git a/data_selector/data_selector.sof b/double_selector_8b/double_selector_8b.sof
similarity index 82%
rename from data_selector/data_selector.sof
rename to double_selector_8b/double_selector_8b.sof
index 4cb434c..45626a8 100644
Binary files a/data_selector/data_selector.sof and b/double_selector_8b/double_selector_8b.sof differ
diff --git a/data_selector/data_selector.tan.rpt b/double_selector_8b/double_selector_8b.tan.rpt
similarity index 69%
rename from data_selector/data_selector.tan.rpt
rename to double_selector_8b/double_selector_8b.tan.rpt
index 2a38069..b33f819 100644
--- a/data_selector/data_selector.tan.rpt
+++ b/double_selector_8b/double_selector_8b.tan.rpt
@@ -1,5 +1,5 @@
-Classic Timing Analyzer report for data_selector
-Sun Mar 06 21:29:32 2022
+Classic Timing Analyzer report for double_selector_8b
+Mon Mar 07 11:22:47 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@@ -39,7 +39,7 @@ applicable agreement for further details.
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
-; Worst-case tpd ; N/A ; None ; 12.694 ns ; b5 ; Y5 ; -- ; -- ; 0 ;
+; Worst-case tpd ; N/A ; None ; 14.785 ns ; b6 ; Y6 ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
@@ -81,7 +81,7 @@ applicable agreement for further details.
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
-; Number detected on machine ; 6 ;
+; Number detected on machine ; 4 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
@@ -89,7 +89,7 @@ applicable agreement for further details.
; ; ;
; Usage by Processor ; % Time Used ;
; 1 processor ; 100.0% ;
-; 2-6 processors ; 0.0% ;
+; 2-4 processors ; 0.0% ;
+----------------------------+-------------+
@@ -98,38 +98,38 @@ applicable agreement for further details.
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
-; N/A ; None ; 12.694 ns ; b5 ; Y5 ;
-; N/A ; None ; 12.565 ns ; BY ; Y7 ;
-; N/A ; None ; 12.553 ns ; BY ; Y0 ;
-; N/A ; None ; 12.543 ns ; a7 ; Y7 ;
-; N/A ; None ; 12.522 ns ; AY ; Y0 ;
-; N/A ; None ; 12.477 ns ; BY ; Y5 ;
-; N/A ; None ; 12.469 ns ; a4 ; Y4 ;
-; N/A ; None ; 12.451 ns ; AY ; Y5 ;
-; N/A ; None ; 12.396 ns ; b3 ; Y3 ;
-; N/A ; None ; 12.360 ns ; a0 ; Y0 ;
-; N/A ; None ; 12.298 ns ; b0 ; Y0 ;
-; N/A ; None ; 12.293 ns ; AY ; Y7 ;
-; N/A ; None ; 12.239 ns ; a5 ; Y5 ;
-; N/A ; None ; 12.214 ns ; b4 ; Y4 ;
-; N/A ; None ; 12.099 ns ; AY ; Y1 ;
-; N/A ; None ; 12.083 ns ; b7 ; Y7 ;
-; N/A ; None ; 12.036 ns ; BY ; Y2 ;
-; N/A ; None ; 12.035 ns ; BY ; Y4 ;
-; N/A ; None ; 12.030 ns ; BY ; Y3 ;
-; N/A ; None ; 12.014 ns ; AY ; Y4 ;
-; N/A ; None ; 12.010 ns ; AY ; Y2 ;
-; N/A ; None ; 11.998 ns ; AY ; Y3 ;
-; N/A ; None ; 11.941 ns ; b6 ; Y6 ;
-; N/A ; None ; 11.823 ns ; a1 ; Y1 ;
-; N/A ; None ; 11.701 ns ; BY ; Y1 ;
-; N/A ; None ; 11.697 ns ; BY ; Y6 ;
-; N/A ; None ; 11.670 ns ; AY ; Y6 ;
-; N/A ; None ; 11.480 ns ; a6 ; Y6 ;
-; N/A ; None ; 6.818 ns ; a3 ; Y3 ;
-; N/A ; None ; 6.817 ns ; b2 ; Y2 ;
-; N/A ; None ; 6.775 ns ; a2 ; Y2 ;
-; N/A ; None ; 6.079 ns ; b1 ; Y1 ;
+; N/A ; None ; 14.785 ns ; b6 ; Y6 ;
+; N/A ; None ; 14.732 ns ; b5 ; Y5 ;
+; N/A ; None ; 14.623 ns ; b0 ; Y0 ;
+; N/A ; None ; 14.408 ns ; b4 ; Y4 ;
+; N/A ; None ; 14.174 ns ; b1 ; Y1 ;
+; N/A ; None ; 14.155 ns ; b7 ; Y7 ;
+; N/A ; None ; 14.070 ns ; b2 ; Y2 ;
+; N/A ; None ; 14.007 ns ; b3 ; Y3 ;
+; N/A ; None ; 13.636 ns ; a0 ; Y0 ;
+; N/A ; None ; 13.392 ns ; a6 ; Y6 ;
+; N/A ; None ; 13.327 ns ; a5 ; Y5 ;
+; N/A ; None ; 13.142 ns ; a3 ; Y3 ;
+; N/A ; None ; 13.132 ns ; a2 ; Y2 ;
+; N/A ; None ; 12.984 ns ; a7 ; Y7 ;
+; N/A ; None ; 12.917 ns ; a4 ; Y4 ;
+; N/A ; None ; 12.863 ns ; a1 ; Y1 ;
+; N/A ; None ; 10.926 ns ; AY ; Y6 ;
+; N/A ; None ; 10.880 ns ; AY ; Y5 ;
+; N/A ; None ; 10.740 ns ; BY ; Y6 ;
+; N/A ; None ; 10.694 ns ; BY ; Y5 ;
+; N/A ; None ; 10.632 ns ; BY ; Y3 ;
+; N/A ; None ; 10.630 ns ; BY ; Y2 ;
+; N/A ; None ; 10.571 ns ; BY ; Y1 ;
+; N/A ; None ; 10.534 ns ; AY ; Y7 ;
+; N/A ; None ; 10.528 ns ; AY ; Y3 ;
+; N/A ; None ; 10.506 ns ; AY ; Y2 ;
+; N/A ; None ; 10.484 ns ; AY ; Y0 ;
+; N/A ; None ; 10.463 ns ; AY ; Y4 ;
+; N/A ; None ; 10.459 ns ; AY ; Y1 ;
+; N/A ; None ; 10.346 ns ; BY ; Y7 ;
+; N/A ; None ; 10.288 ns ; BY ; Y4 ;
+; N/A ; None ; 10.285 ns ; BY ; Y0 ;
+-------+-------------------+-----------------+------+----+
@@ -139,18 +139,18 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
- Info: Processing started: Sun Mar 06 21:29:32 2022
-Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off data_selector -c data_selector --timing_analysis_only
-Info: Parallel compilation is enabled and will use 4 of the 6 processors detected
-Info: Longest tpd from source pin "b5" to destination pin "Y5" is 12.694 ns
- Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_45; Fanout = 1; PIN Node = 'b5'
- Info: 2: + IC(6.147 ns) + CELL(0.624 ns) = 7.766 ns; Loc. = LCCOMB_X1_Y9_N26; Fanout = 1; COMB Node = 'inst6'
- Info: 3: + IC(1.642 ns) + CELL(3.286 ns) = 12.694 ns; Loc. = PIN_208; Fanout = 0; PIN Node = 'Y5'
- Info: Total cell delay = 4.905 ns ( 38.64 % )
- Info: Total interconnect delay = 7.789 ns ( 61.36 % )
+ Info: Processing started: Mon Mar 07 11:22:47 2022
+Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b --timing_analysis_only
+Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info: Longest tpd from source pin "b6" to destination pin "Y6" is 14.785 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_75; Fanout = 1; PIN Node = 'b6'
+ Info: 2: + IC(6.679 ns) + CELL(0.651 ns) = 8.304 ns; Loc. = LCCOMB_X25_Y2_N12; Fanout = 1; COMB Node = 'inst7'
+ Info: 3: + IC(3.365 ns) + CELL(3.116 ns) = 14.785 ns; Loc. = PIN_149; Fanout = 0; PIN Node = 'Y6'
+ Info: Total cell delay = 4.741 ns ( 32.07 % )
+ Info: Total interconnect delay = 10.044 ns ( 67.93 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
- Info: Peak virtual memory: 192 megabytes
- Info: Processing ended: Sun Mar 06 21:29:32 2022
+ Info: Peak virtual memory: 212 megabytes
+ Info: Processing ended: Mon Mar 07 11:22:47 2022
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00
diff --git a/data_selector/data_selector.tan.summary b/double_selector_8b/double_selector_8b.tan.summary
similarity index 90%
rename from data_selector/data_selector.tan.summary
rename to double_selector_8b/double_selector_8b.tan.summary
index 957d2f4..e39f4c1 100644
--- a/data_selector/data_selector.tan.summary
+++ b/double_selector_8b/double_selector_8b.tan.summary
@@ -5,9 +5,9 @@ Timing Analyzer Summary
Type : Worst-case tpd
Slack : N/A
Required Time : None
-Actual Time : 12.694 ns
-From : b5
-To : Y5
+Actual Time : 14.785 ns
+From : b6
+To : Y6
From Clock : --
To Clock : --
Failed Paths : 0
diff --git a/data_selector/incremental_db/README b/double_selector_8b/incremental_db/README
similarity index 100%
rename from data_selector/incremental_db/README
rename to double_selector_8b/incremental_db/README
diff --git a/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.atm b/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.atm
new file mode 100644
index 0000000..42a32b0
Binary files /dev/null and b/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.atm differ
diff --git a/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.dfp b/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.dfp
similarity index 100%
rename from data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.dfp
rename to double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.dfp
diff --git a/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.hdbx b/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.hdbx
new file mode 100644
index 0000000..0761db7
Binary files /dev/null and b/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.hdbx differ
diff --git a/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.kpt b/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.kpt
similarity index 100%
rename from data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.kpt
rename to double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.kpt
diff --git a/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.logdb b/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.logdb
similarity index 100%
rename from data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.logdb
rename to double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.logdb
diff --git a/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.rcf b/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.rcf
new file mode 100644
index 0000000..c2c32ef
Binary files /dev/null and b/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.rcf differ
diff --git a/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.map.atm b/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.map.atm
new file mode 100644
index 0000000..e61f1f0
Binary files /dev/null and b/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.map.atm differ
diff --git a/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.map.dpi b/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.map.dpi
new file mode 100644
index 0000000..5d6b23c
Binary files /dev/null and b/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.map.dpi differ
diff --git a/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.map.hdbx b/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.map.hdbx
new file mode 100644
index 0000000..e717b3a
Binary files /dev/null and b/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.map.hdbx differ
diff --git a/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.kpt b/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.map.kpt
similarity index 82%
rename from data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.kpt
rename to double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.map.kpt
index 1372c2e..94168b0 100644
--- a/data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.kpt
+++ b/double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.map.kpt
@@ -1,4 +1,4 @@
-
+