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create machine_alpha

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juzeon 2022-03-29 16:52:11 +08:00
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1048
ALU_3_in_1/ALU_3_in_1.bdf
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80
ALU_3_in_1/ALU_3_in_1.bsf
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@ -20,7 +20,7 @@ applicable agreement for further details.
*/
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@ -164,62 +164,90 @@ applicable agreement for further details.
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instructions.xlsx Normal file
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2400
machine_alpha/ALU_3_in_1.bdf Normal file
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253
machine_alpha/ALU_3_in_1.bsf Normal file
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@ -0,0 +1,253 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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2046
machine_alpha/ALU_parallel_8b.bdf Normal file
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246
machine_alpha/ALU_parallel_8b.bsf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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machine_alpha/adder_8b.bdf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
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1375
machine_alpha/counter_8b_with_input.bdf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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(text "counter_8b_with_input" (rect 5 0 135 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 208 25 220)(font "Arial" ))
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(text "D7" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "D7" (rect 21 27 36 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
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(line (pt 96 112)(pt 80 112)(line_width 1))
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)
)

1791
machine_alpha/double_selector_8b.bdf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
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(text "inst" (rect 8 336 25 348)(font "Arial" ))
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)
)

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machine_alpha/machine_alpha.bdf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 18:43:10 March 24, 2022
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "9.0"
DATE = "18:43:10 March 24, 2022"
# Revisions
PROJECT_REVISION = "machine_alpha"

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 18:43:10 March 24, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# machine_alpha_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C8Q208C8
set_global_assignment -name TOP_LEVEL_ENTITY machine_alpha
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:43:10 MARCH 24, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name BDF_FILE machine_alpha.bdf

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machine_alpha/register_4x.bdf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 112 272)
(text "register_4x" (rect 5 0 69 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 240 25 252)(font "Arial" ))
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(pt 0 32)
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(text "CLR" (rect 21 27 44 41)(font "Arial" (font_size 8)))
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)
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(text "CP" (rect 0 0 15 14)(font "Arial" (font_size 8)))
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(line (pt 0 208)(pt 16 208)(line_width 1))
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(line (pt 96 32)(pt 80 32)(line_width 1))
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(line (pt 96 48)(pt 80 48)(line_width 1))
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(line (pt 96 64)(pt 80 64)(line_width 1))
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(text "Q4" (rect 59 75 75 89)(font "Arial" (font_size 8)))
(line (pt 96 80)(pt 80 80)(line_width 1))
)
(port
(pt 96 96)
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(text "Q3" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "Q3" (rect 59 91 75 105)(font "Arial" (font_size 8)))
(line (pt 96 96)(pt 80 96)(line_width 1))
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(text "Q2" (rect 59 107 75 121)(font "Arial" (font_size 8)))
(line (pt 96 112)(pt 80 112)(line_width 1))
)
(port
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(output)
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(text "Q1" (rect 59 123 75 137)(font "Arial" (font_size 8)))
(line (pt 96 128)(pt 80 128)(line_width 1))
)
(port
(pt 96 144)
(output)
(text "Q0" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "Q0" (rect 59 139 75 153)(font "Arial" (font_size 8)))
(line (pt 96 144)(pt 80 144)(line_width 1))
)
(drawing
(rectangle (rect 16 16 80 240)(line_width 1))
)
)

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machine_alpha/register_8b.bdf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 112 240)
(text "register_8b" (rect 5 0 69 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 208 25 220)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "CLR" (rect 0 0 23 14)(font "Arial" (font_size 8)))
(text "CLR" (rect 21 27 44 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "CP" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "CP" (rect 21 43 36 57)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "D7" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "D7" (rect 21 59 36 73)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 0 80)
(input)
(text "D6" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "D6" (rect 21 75 36 89)(font "Arial" (font_size 8)))
(line (pt 0 80)(pt 16 80)(line_width 1))
)
(port
(pt 0 96)
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(text "D5" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "D5" (rect 21 91 36 105)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 16 96)(line_width 1))
)
(port
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(input)
(text "D4" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "D4" (rect 21 107 36 121)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 16 112)(line_width 1))
)
(port
(pt 0 128)
(input)
(text "D3" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "D3" (rect 21 123 36 137)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 16 128)(line_width 1))
)
(port
(pt 0 144)
(input)
(text "D2" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "D2" (rect 21 139 36 153)(font "Arial" (font_size 8)))
(line (pt 0 144)(pt 16 144)(line_width 1))
)
(port
(pt 0 160)
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(text "D1" (rect 21 155 36 169)(font "Arial" (font_size 8)))
(line (pt 0 160)(pt 16 160)(line_width 1))
)
(port
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(input)
(text "D0" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "D0" (rect 21 171 36 185)(font "Arial" (font_size 8)))
(line (pt 0 176)(pt 16 176)(line_width 1))
)
(port
(pt 96 32)
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(text "Q7" (rect 59 27 75 41)(font "Arial" (font_size 8)))
(line (pt 96 32)(pt 80 32)(line_width 1))
)
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(text "Q6" (rect 59 43 75 57)(font "Arial" (font_size 8)))
(line (pt 96 48)(pt 80 48)(line_width 1))
)
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(pt 96 64)
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(text "Q5" (rect 59 59 75 73)(font "Arial" (font_size 8)))
(line (pt 96 64)(pt 80 64)(line_width 1))
)
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(pt 96 80)
(output)
(text "Q4" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "Q4" (rect 59 75 75 89)(font "Arial" (font_size 8)))
(line (pt 96 80)(pt 80 80)(line_width 1))
)
(port
(pt 96 96)
(output)
(text "Q3" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "Q3" (rect 59 91 75 105)(font "Arial" (font_size 8)))
(line (pt 96 96)(pt 80 96)(line_width 1))
)
(port
(pt 96 112)
(output)
(text "Q2" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "Q2" (rect 59 107 75 121)(font "Arial" (font_size 8)))
(line (pt 96 112)(pt 80 112)(line_width 1))
)
(port
(pt 96 128)
(output)
(text "Q1" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "Q1" (rect 59 123 75 137)(font "Arial" (font_size 8)))
(line (pt 96 128)(pt 80 128)(line_width 1))
)
(port
(pt 96 144)
(output)
(text "Q0" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "Q0" (rect 59 139 75 153)(font "Arial" (font_size 8)))
(line (pt 96 144)(pt 80 144)(line_width 1))
)
(drawing
(rectangle (rect 16 16 80 208)(line_width 1))
)
)

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machine_alpha/register_8b_premium.bdf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 136 272)
(text "register_8b_premium" (rect 5 0 124 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 240 25 252)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "EN_IN" (rect 0 0 33 14)(font "Arial" (font_size 8)))
(text "EN_IN" (rect 21 27 54 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
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(text "EN_OUT" (rect 0 0 47 14)(font "Arial" (font_size 8)))
(text "EN_OUT" (rect 21 43 68 57)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "CLR" (rect 0 0 23 14)(font "Arial" (font_size 8)))
(text "CLR" (rect 21 59 44 73)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 0 80)
(input)
(text "CP" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "CP" (rect 21 75 36 89)(font "Arial" (font_size 8)))
(line (pt 0 80)(pt 16 80)(line_width 1))
)
(port
(pt 0 96)
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(text "D7" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "D7" (rect 21 91 36 105)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 16 96)(line_width 1))
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(port
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(text "D6" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "D6" (rect 21 107 36 121)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 16 112)(line_width 1))
)
(port
(pt 0 128)
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(text "D5" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "D5" (rect 21 123 36 137)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 16 128)(line_width 1))
)
(port
(pt 0 144)
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(text "D4" (rect 0 0 15 14)(font "Arial" (font_size 8)))
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(input)
(text "D1" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "D1" (rect 21 187 36 201)(font "Arial" (font_size 8)))
(line (pt 0 192)(pt 16 192)(line_width 1))
)
(port
(pt 0 208)
(input)
(text "D0" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "D0" (rect 21 203 36 217)(font "Arial" (font_size 8)))
(line (pt 0 208)(pt 16 208)(line_width 1))
)
(port
(pt 120 32)
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(text "Q7" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "Q7" (rect 83 27 99 41)(font "Arial" (font_size 8)))
(line (pt 120 32)(pt 104 32)(line_width 1))
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(port
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(text "Q5" (rect 83 59 99 73)(font "Arial" (font_size 8)))
(line (pt 120 64)(pt 104 64)(line_width 1))
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(text "Q4" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "Q4" (rect 83 75 99 89)(font "Arial" (font_size 8)))
(line (pt 120 80)(pt 104 80)(line_width 1))
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(pt 120 96)
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(text "Q3" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "Q3" (rect 83 91 99 105)(font "Arial" (font_size 8)))
(line (pt 120 96)(pt 104 96)(line_width 1))
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(output)
(text "Q2" (rect 0 0 16 14)(font "Arial" (font_size 8)))
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(line (pt 120 112)(pt 104 112)(line_width 1))
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(port
(pt 120 128)
(output)
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(text "Q1" (rect 83 123 99 137)(font "Arial" (font_size 8)))
(line (pt 120 128)(pt 104 128)(line_width 1))
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(port
(pt 120 144)
(output)
(text "Q0" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "Q0" (rect 83 139 99 153)(font "Arial" (font_size 8)))
(line (pt 120 144)(pt 104 144)(line_width 1))
)
(drawing
(rectangle (rect 16 16 104 240)(line_width 1))
)
)

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machine_alpha/register_8b_with_switch.bdf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 112 240)
(text "register_8b_with_switch" (rect 5 0 147 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 208 25 220)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "EN" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "EN" (rect 21 27 36 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "CLR" (rect 0 0 23 14)(font "Arial" (font_size 8)))
(text "CLR" (rect 21 43 44 57)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "CP" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "CP" (rect 21 59 36 73)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 0 80)
(input)
(text "D7" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "D7" (rect 21 75 36 89)(font "Arial" (font_size 8)))
(line (pt 0 80)(pt 16 80)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "D6" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "D6" (rect 21 91 36 105)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 16 96)(line_width 1))
)
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)

451
machine_alpha/start_circuit.bdf Normal file
查看文件

@ -0,0 +1,451 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
//#pragma file_not_in_maxplusii_format
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)
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64
machine_alpha/start_circuit.bsf Normal file
查看文件

@ -0,0 +1,64 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 112 144)
(text "start_circuit" (rect 5 0 72 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 112 25 124)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "HALT" (rect 0 0 31 14)(font "Arial" (font_size 8)))
(text "HALT" (rect 21 27 52 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "CK_C" (rect 0 0 31 14)(font "Arial" (font_size 8)))
(text "CK_C" (rect 21 43 52 57)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "CK" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "CK" (rect 21 59 37 73)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 0 80)
(input)
(text "CLR" (rect 0 0 23 14)(font "Arial" (font_size 8)))
(text "CLR" (rect 21 75 44 89)(font "Arial" (font_size 8)))
(line (pt 0 80)(pt 16 80)(line_width 1))
)
(port
(pt 96 32)
(output)
(text "CP" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "CP" (rect 60 27 75 41)(font "Arial" (font_size 8)))
(line (pt 96 32)(pt 80 32)(line_width 1))
)
(drawing
(rectangle (rect 16 16 80 112)(line_width 1))
)
)