diff --git a/adder/adder.asm.rpt b/adder/adder.asm.rpt
new file mode 100644
index 0000000..dc2646b
--- /dev/null
+++ b/adder/adder.asm.rpt
@@ -0,0 +1,129 @@
+Assembler report for adder
+Mon Mar 07 08:49:26 2022
+Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Assembler Summary
+ 3. Assembler Settings
+ 4. Assembler Generated Files
+ 5. Assembler Device Options: D:/projects/quartus/adder/adder.sof
+ 6. Assembler Device Options: D:/projects/quartus/adder/adder.pof
+ 7. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary ;
++-----------------------+---------------------------------------+
+; Assembler Status ; Successful - Mon Mar 07 08:49:26 2022 ;
+; Revision Name ; adder ;
+; Top-level Entity Name ; adder ;
+; Family ; Cyclone II ;
+; Device ; EP2C8Q208C8 ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option ; Setting ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation ; Off ; Off ;
+; Generate compressed bitstreams ; On ; On ;
+; Compression mode ; Off ; Off ;
+; Clock source for configuration device ; Internal ; Internal ;
+; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
+; Divide clock frequency by ; 1 ; 1 ;
+; Auto user code ; Off ; Off ;
+; Use configuration device ; On ; On ;
+; Configuration device ; Auto ; Auto ;
+; Configuration device auto user code ; Off ; Off ;
+; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
+; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
+; Hexadecimal Output File start address ; 0 ; 0 ;
+; Hexadecimal Output File count direction ; Up ; Up ;
+; Release clears before tri-states ; Off ; Off ;
+; Auto-restart configuration after error ; On ; On ;
+; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ;
+; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++-------------------------------------+
+; Assembler Generated Files ;
++-------------------------------------+
+; File Name ;
++-------------------------------------+
+; D:/projects/quartus/adder/adder.sof ;
+; D:/projects/quartus/adder/adder.pof ;
++-------------------------------------+
+
+
++---------------------------------------------------------------+
+; Assembler Device Options: D:/projects/quartus/adder/adder.sof ;
++----------------+----------------------------------------------+
+; Option ; Setting ;
++----------------+----------------------------------------------+
+; Device ; EP2C8Q208C8 ;
+; JTAG usercode ; 0xFFFFFFFF ;
+; Checksum ; 0x000C8655 ;
++----------------+----------------------------------------------+
+
+
++---------------------------------------------------------------+
+; Assembler Device Options: D:/projects/quartus/adder/adder.pof ;
++--------------------+------------------------------------------+
+; Option ; Setting ;
++--------------------+------------------------------------------+
+; Device ; EPCS4 ;
+; JTAG usercode ; 0x00000000 ;
+; Checksum ; 0x06F061B0 ;
+; Compression Ratio ; 3 ;
++--------------------+------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II Assembler
+ Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+ Info: Processing started: Mon Mar 07 08:49:25 2022
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off adder -c adder
+Info: Writing out detailed assembly data for power analysis
+Info: Assembler is generating device programming files
+Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled
+Info: Quartus II Assembler was successful. 0 errors, 0 warnings
+ Info: Peak virtual memory: 242 megabytes
+ Info: Processing ended: Mon Mar 07 08:49:26 2022
+ Info: Elapsed time: 00:00:01
+ Info: Total CPU time (on all processors): 00:00:00
+
+
diff --git a/adder/adder.bdf b/adder/adder.bdf
new file mode 100644
index 0000000..6d769db
--- /dev/null
+++ b/adder/adder.bdf
@@ -0,0 +1,2906 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+*/
+//#pragma file_not_in_maxplusii_format
+(header "graphic" (version "1.3"))
+(pin
+ (input)
+ (rect 80 48 248 64)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "A7" (rect 5 0 17 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 80 64 248 80)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "B7" (rect 5 0 17 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 80 344 248 360)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "A6" (rect 5 0 17 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 80 360 248 376)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "B6" (rect 5 0 17 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 80 640 248 656)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "A5" (rect 5 0 17 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 80 656 248 672)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "B5" (rect 5 0 17 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 80 936 248 952)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "A4" (rect 5 0 17 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 80 952 248 968)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "B4" (rect 5 0 17 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 80 1232 248 1248)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "A3" (rect 5 0 17 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 80 1248 248 1264)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "B3" (rect 5 0 17 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 80 1528 248 1544)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "A2" (rect 5 0 17 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 80 1544 248 1560)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "B2" (rect 5 0 17 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 80 1824 248 1840)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "A1" (rect 5 0 17 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 80 1840 248 1856)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "B1" (rect 5 0 17 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 80 2104 248 2120)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "A0" (rect 5 0 17 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 80 2120 248 2136)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "B0" (rect 5 0 17 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 80 2136 248 2152)
+ (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+ (text "CI" (rect 5 0 16 12)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 92 12)(pt 117 12)(line_width 1))
+ (line (pt 92 4)(pt 117 4)(line_width 1))
+ (line (pt 121 8)(pt 168 8)(line_width 1))
+ (line (pt 92 12)(pt 92 4)(line_width 1))
+ (line (pt 117 4)(pt 121 8)(line_width 1))
+ (line (pt 117 12)(pt 121 8)(line_width 1))
+ )
+ (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (output)
+ (rect 536 32 712 48)
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+ (text "CO" (rect 90 0 106 12)(font "Arial" ))
+ (pt 0 8)
+ (drawing
+ (line (pt 0 8)(pt 52 8)(line_width 1))
+ (line (pt 52 4)(pt 78 4)(line_width 1))
+ (line (pt 52 12)(pt 78 12)(line_width 1))
+ (line (pt 52 12)(pt 52 4)(line_width 1))
+ (line (pt 78 4)(pt 82 8)(line_width 1))
+ (line (pt 82 8)(pt 78 12)(line_width 1))
+ (line (pt 78 12)(pt 82 8)(line_width 1))
+ )
+)
+(pin
+ (output)
+ (rect 536 64 712 80)
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+ (text "S7" (rect 90 0 102 12)(font "Arial" ))
+ (pt 0 8)
+ (drawing
+ (line (pt 0 8)(pt 52 8)(line_width 1))
+ (line (pt 52 4)(pt 78 4)(line_width 1))
+ (line (pt 52 12)(pt 78 12)(line_width 1))
+ (line (pt 52 12)(pt 52 4)(line_width 1))
+ (line (pt 78 4)(pt 82 8)(line_width 1))
+ (line (pt 82 8)(pt 78 12)(line_width 1))
+ (line (pt 78 12)(pt 82 8)(line_width 1))
+ )
+)
+(pin
+ (output)
+ (rect 536 2120 712 2136)
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+ (text "S0" (rect 90 0 102 12)(font "Arial" ))
+ (pt 0 8)
+ (drawing
+ (line (pt 0 8)(pt 52 8)(line_width 1))
+ (line (pt 52 4)(pt 78 4)(line_width 1))
+ (line (pt 52 12)(pt 78 12)(line_width 1))
+ (line (pt 52 12)(pt 52 4)(line_width 1))
+ (line (pt 78 4)(pt 82 8)(line_width 1))
+ (line (pt 82 8)(pt 78 12)(line_width 1))
+ (line (pt 78 12)(pt 82 8)(line_width 1))
+ )
+)
+(pin
+ (output)
+ (rect 536 1840 712 1856)
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+ (text "S1" (rect 90 0 102 12)(font "Arial" ))
+ (pt 0 8)
+ (drawing
+ (line (pt 0 8)(pt 52 8)(line_width 1))
+ (line (pt 52 4)(pt 78 4)(line_width 1))
+ (line (pt 52 12)(pt 78 12)(line_width 1))
+ (line (pt 52 12)(pt 52 4)(line_width 1))
+ (line (pt 78 4)(pt 82 8)(line_width 1))
+ (line (pt 82 8)(pt 78 12)(line_width 1))
+ (line (pt 78 12)(pt 82 8)(line_width 1))
+ )
+)
+(pin
+ (output)
+ (rect 536 1544 712 1560)
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+ (text "S2" (rect 90 0 102 12)(font "Arial" ))
+ (pt 0 8)
+ (drawing
+ (line (pt 0 8)(pt 52 8)(line_width 1))
+ (line (pt 52 4)(pt 78 4)(line_width 1))
+ (line (pt 52 12)(pt 78 12)(line_width 1))
+ (line (pt 52 12)(pt 52 4)(line_width 1))
+ (line (pt 78 4)(pt 82 8)(line_width 1))
+ (line (pt 82 8)(pt 78 12)(line_width 1))
+ (line (pt 78 12)(pt 82 8)(line_width 1))
+ )
+)
+(pin
+ (output)
+ (rect 536 1248 712 1264)
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+ (text "S3" (rect 90 0 102 12)(font "Arial" ))
+ (pt 0 8)
+ (drawing
+ (line (pt 0 8)(pt 52 8)(line_width 1))
+ (line (pt 52 4)(pt 78 4)(line_width 1))
+ (line (pt 52 12)(pt 78 12)(line_width 1))
+ (line (pt 52 12)(pt 52 4)(line_width 1))
+ (line (pt 78 4)(pt 82 8)(line_width 1))
+ (line (pt 82 8)(pt 78 12)(line_width 1))
+ (line (pt 78 12)(pt 82 8)(line_width 1))
+ )
+)
+(pin
+ (output)
+ (rect 536 952 712 968)
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+ (text "S4" (rect 90 0 102 12)(font "Arial" ))
+ (pt 0 8)
+ (drawing
+ (line (pt 0 8)(pt 52 8)(line_width 1))
+ (line (pt 52 4)(pt 78 4)(line_width 1))
+ (line (pt 52 12)(pt 78 12)(line_width 1))
+ (line (pt 52 12)(pt 52 4)(line_width 1))
+ (line (pt 78 4)(pt 82 8)(line_width 1))
+ (line (pt 82 8)(pt 78 12)(line_width 1))
+ (line (pt 78 12)(pt 82 8)(line_width 1))
+ )
+)
+(pin
+ (output)
+ (rect 536 656 712 672)
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+ (text "S5" (rect 90 0 102 12)(font "Arial" ))
+ (pt 0 8)
+ (drawing
+ (line (pt 0 8)(pt 52 8)(line_width 1))
+ (line (pt 52 4)(pt 78 4)(line_width 1))
+ (line (pt 52 12)(pt 78 12)(line_width 1))
+ (line (pt 52 12)(pt 52 4)(line_width 1))
+ (line (pt 78 4)(pt 82 8)(line_width 1))
+ (line (pt 82 8)(pt 78 12)(line_width 1))
+ (line (pt 78 12)(pt 82 8)(line_width 1))
+ )
+)
+(pin
+ (output)
+ (rect 536 360 712 376)
+ (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+ (text "S6" (rect 90 0 102 12)(font "Arial" ))
+ (pt 0 8)
+ (drawing
+ (line (pt 0 8)(pt 52 8)(line_width 1))
+ (line (pt 52 4)(pt 78 4)(line_width 1))
+ (line (pt 52 12)(pt 78 12)(line_width 1))
+ (line (pt 52 12)(pt 52 4)(line_width 1))
+ (line (pt 78 4)(pt 82 8)(line_width 1))
+ (line (pt 82 8)(pt 78 12)(line_width 1))
+ (line (pt 78 12)(pt 82 8)(line_width 1))
+ )
+)
+(symbol
+ (rect 304 2096 368 2136)
+ (text "7486" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst" (rect 3 29 17 39)(font "Arial" (font_size 6)))
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (line (pt 48 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 13 13)(pt 24 13)(line_width 1))
+ (line (pt 13 35)(pt 24 35)(line_width 1))
+ (line (pt 6 32)(pt 10 32)(line_width 1))
+ (line (pt 6 16)(pt 11 16)(line_width 1))
+ (line (pt 45 21)(pt 48 24)(line_width 1))
+ (line (pt 45 27)(pt 48 24)(line_width 1))
+ (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)(line_width 1))
+ (arc (pt 24 35)(pt 35 14)(rect -8 -29 57 36)(line_width 1))
+ (arc (pt 35 34)(pt 24 13)(rect -8 13 57 78)(line_width 1))
+ (arc (pt 2 29)(pt 2 19)(rect -19 8 14 41)(line_width 1))
+ )
+)
+(symbol
+ (rect 336 2208 400 2248)
+ (text "7400" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst2" (rect 3 29 26 41)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (line (pt 51 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 15 12)(pt 31 12)(line_width 1))
+ (line (pt 5 32)(pt 15 32)(line_width 1))
+ (line (pt 15 36)(pt 31 36)(line_width 1))
+ (line (pt 7 16)(pt 15 16)(line_width 1))
+ (line (pt 15 36)(pt 15 12)(line_width 1))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37)(line_width 1))
+ (circle (rect 43 20 51 28)(line_width 1))
+ )
+)
+(symbol
+ (rect 432 2240 496 2280)
+ (text "7400" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst3" (rect 3 29 26 41)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (line (pt 51 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 15 12)(pt 31 12)(line_width 1))
+ (line (pt 5 32)(pt 15 32)(line_width 1))
+ (line (pt 15 36)(pt 31 36)(line_width 1))
+ (line (pt 7 16)(pt 15 16)(line_width 1))
+ (line (pt 15 36)(pt 15 12)(line_width 1))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37)(line_width 1))
+ (circle (rect 43 20 51 28)(line_width 1))
+ )
+)
+(symbol
+ (rect 336 2272 400 2312)
+ (text "7400" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst4" (rect 3 29 26 41)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (line (pt 51 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 15 12)(pt 31 12)(line_width 1))
+ (line (pt 5 32)(pt 15 32)(line_width 1))
+ (line (pt 15 36)(pt 31 36)(line_width 1))
+ (line (pt 7 16)(pt 15 16)(line_width 1))
+ (line (pt 15 36)(pt 15 12)(line_width 1))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37)(line_width 1))
+ (circle (rect 43 20 51 28)(line_width 1))
+ )
+)
+(symbol
+ (rect 408 2104 472 2144)
+ (text "7486" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst5" (rect 3 29 26 41)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (line (pt 48 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 13 13)(pt 24 13)(line_width 1))
+ (line (pt 13 35)(pt 24 35)(line_width 1))
+ (line (pt 6 32)(pt 10 32)(line_width 1))
+ (line (pt 6 16)(pt 11 16)(line_width 1))
+ (line (pt 45 21)(pt 48 24)(line_width 1))
+ (line (pt 45 27)(pt 48 24)(line_width 1))
+ (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)(line_width 1))
+ (arc (pt 24 35)(pt 35 14)(rect -8 -29 57 36)(line_width 1))
+ (arc (pt 35 34)(pt 24 13)(rect -8 13 57 78)(line_width 1))
+ (arc (pt 2 29)(pt 2 19)(rect -19 8 14 41)(line_width 1))
+ )
+)
+(symbol
+ (rect 304 1816 368 1856)
+ (text "7486" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst6" (rect 3 29 26 41)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (line (pt 48 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 13 13)(pt 24 13)(line_width 1))
+ (line (pt 13 35)(pt 24 35)(line_width 1))
+ (line (pt 6 32)(pt 10 32)(line_width 1))
+ (line (pt 6 16)(pt 11 16)(line_width 1))
+ (line (pt 45 21)(pt 48 24)(line_width 1))
+ (line (pt 45 27)(pt 48 24)(line_width 1))
+ (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)(line_width 1))
+ (arc (pt 24 35)(pt 35 14)(rect -8 -29 57 36)(line_width 1))
+ (arc (pt 35 34)(pt 24 13)(rect -8 13 57 78)(line_width 1))
+ (arc (pt 2 29)(pt 2 19)(rect -19 8 14 41)(line_width 1))
+ )
+)
+(symbol
+ (rect 336 1928 400 1968)
+ (text "7400" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst7" (rect 3 29 26 41)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (line (pt 51 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 15 12)(pt 31 12)(line_width 1))
+ (line (pt 5 32)(pt 15 32)(line_width 1))
+ (line (pt 15 36)(pt 31 36)(line_width 1))
+ (line (pt 7 16)(pt 15 16)(line_width 1))
+ (line (pt 15 36)(pt 15 12)(line_width 1))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37)(line_width 1))
+ (circle (rect 43 20 51 28)(line_width 1))
+ )
+)
+(symbol
+ (rect 432 1960 496 2000)
+ (text "7400" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst8" (rect 3 29 26 41)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (line (pt 51 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 15 12)(pt 31 12)(line_width 1))
+ (line (pt 5 32)(pt 15 32)(line_width 1))
+ (line (pt 15 36)(pt 31 36)(line_width 1))
+ (line (pt 7 16)(pt 15 16)(line_width 1))
+ (line (pt 15 36)(pt 15 12)(line_width 1))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37)(line_width 1))
+ (circle (rect 43 20 51 28)(line_width 1))
+ )
+)
+(symbol
+ (rect 336 1992 400 2032)
+ (text "7400" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst9" (rect 3 29 26 41)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (line (pt 51 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 15 12)(pt 31 12)(line_width 1))
+ (line (pt 5 32)(pt 15 32)(line_width 1))
+ (line (pt 15 36)(pt 31 36)(line_width 1))
+ (line (pt 7 16)(pt 15 16)(line_width 1))
+ (line (pt 15 36)(pt 15 12)(line_width 1))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37)(line_width 1))
+ (circle (rect 43 20 51 28)(line_width 1))
+ )
+)
+(symbol
+ (rect 408 1824 472 1864)
+ (text "7486" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst10" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (line (pt 48 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 13 13)(pt 24 13)(line_width 1))
+ (line (pt 13 35)(pt 24 35)(line_width 1))
+ (line (pt 6 32)(pt 10 32)(line_width 1))
+ (line (pt 6 16)(pt 11 16)(line_width 1))
+ (line (pt 45 21)(pt 48 24)(line_width 1))
+ (line (pt 45 27)(pt 48 24)(line_width 1))
+ (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)(line_width 1))
+ (arc (pt 24 35)(pt 35 14)(rect -8 -29 57 36)(line_width 1))
+ (arc (pt 35 34)(pt 24 13)(rect -8 13 57 78)(line_width 1))
+ (arc (pt 2 29)(pt 2 19)(rect -19 8 14 41)(line_width 1))
+ )
+)
+(symbol
+ (rect 304 1520 368 1560)
+ (text "7486" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst11" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (line (pt 48 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 13 13)(pt 24 13)(line_width 1))
+ (line (pt 13 35)(pt 24 35)(line_width 1))
+ (line (pt 6 32)(pt 10 32)(line_width 1))
+ (line (pt 6 16)(pt 11 16)(line_width 1))
+ (line (pt 45 21)(pt 48 24)(line_width 1))
+ (line (pt 45 27)(pt 48 24)(line_width 1))
+ (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)(line_width 1))
+ (arc (pt 24 35)(pt 35 14)(rect -8 -29 57 36)(line_width 1))
+ (arc (pt 35 34)(pt 24 13)(rect -8 13 57 78)(line_width 1))
+ (arc (pt 2 29)(pt 2 19)(rect -19 8 14 41)(line_width 1))
+ )
+)
+(symbol
+ (rect 336 1632 400 1672)
+ (text "7400" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst12" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (line (pt 51 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 15 12)(pt 31 12)(line_width 1))
+ (line (pt 5 32)(pt 15 32)(line_width 1))
+ (line (pt 15 36)(pt 31 36)(line_width 1))
+ (line (pt 7 16)(pt 15 16)(line_width 1))
+ (line (pt 15 36)(pt 15 12)(line_width 1))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37)(line_width 1))
+ (circle (rect 43 20 51 28)(line_width 1))
+ )
+)
+(symbol
+ (rect 432 1664 496 1704)
+ (text "7400" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst13" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (line (pt 51 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 15 12)(pt 31 12)(line_width 1))
+ (line (pt 5 32)(pt 15 32)(line_width 1))
+ (line (pt 15 36)(pt 31 36)(line_width 1))
+ (line (pt 7 16)(pt 15 16)(line_width 1))
+ (line (pt 15 36)(pt 15 12)(line_width 1))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37)(line_width 1))
+ (circle (rect 43 20 51 28)(line_width 1))
+ )
+)
+(symbol
+ (rect 336 1696 400 1736)
+ (text "7400" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst14" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (line (pt 51 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 15 12)(pt 31 12)(line_width 1))
+ (line (pt 5 32)(pt 15 32)(line_width 1))
+ (line (pt 15 36)(pt 31 36)(line_width 1))
+ (line (pt 7 16)(pt 15 16)(line_width 1))
+ (line (pt 15 36)(pt 15 12)(line_width 1))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37)(line_width 1))
+ (circle (rect 43 20 51 28)(line_width 1))
+ )
+)
+(symbol
+ (rect 408 1528 472 1568)
+ (text "7486" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst15" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (line (pt 48 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 13 13)(pt 24 13)(line_width 1))
+ (line (pt 13 35)(pt 24 35)(line_width 1))
+ (line (pt 6 32)(pt 10 32)(line_width 1))
+ (line (pt 6 16)(pt 11 16)(line_width 1))
+ (line (pt 45 21)(pt 48 24)(line_width 1))
+ (line (pt 45 27)(pt 48 24)(line_width 1))
+ (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)(line_width 1))
+ (arc (pt 24 35)(pt 35 14)(rect -8 -29 57 36)(line_width 1))
+ (arc (pt 35 34)(pt 24 13)(rect -8 13 57 78)(line_width 1))
+ (arc (pt 2 29)(pt 2 19)(rect -19 8 14 41)(line_width 1))
+ )
+)
+(symbol
+ (rect 304 1224 368 1264)
+ (text "7486" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst16" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (line (pt 48 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 13 13)(pt 24 13)(line_width 1))
+ (line (pt 13 35)(pt 24 35)(line_width 1))
+ (line (pt 6 32)(pt 10 32)(line_width 1))
+ (line (pt 6 16)(pt 11 16)(line_width 1))
+ (line (pt 45 21)(pt 48 24)(line_width 1))
+ (line (pt 45 27)(pt 48 24)(line_width 1))
+ (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)(line_width 1))
+ (arc (pt 24 35)(pt 35 14)(rect -8 -29 57 36)(line_width 1))
+ (arc (pt 35 34)(pt 24 13)(rect -8 13 57 78)(line_width 1))
+ (arc (pt 2 29)(pt 2 19)(rect -19 8 14 41)(line_width 1))
+ )
+)
+(symbol
+ (rect 336 1336 400 1376)
+ (text "7400" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst17" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (line (pt 51 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 15 12)(pt 31 12)(line_width 1))
+ (line (pt 5 32)(pt 15 32)(line_width 1))
+ (line (pt 15 36)(pt 31 36)(line_width 1))
+ (line (pt 7 16)(pt 15 16)(line_width 1))
+ (line (pt 15 36)(pt 15 12)(line_width 1))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37)(line_width 1))
+ (circle (rect 43 20 51 28)(line_width 1))
+ )
+)
+(symbol
+ (rect 432 1368 496 1408)
+ (text "7400" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst18" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (line (pt 51 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 15 12)(pt 31 12)(line_width 1))
+ (line (pt 5 32)(pt 15 32)(line_width 1))
+ (line (pt 15 36)(pt 31 36)(line_width 1))
+ (line (pt 7 16)(pt 15 16)(line_width 1))
+ (line (pt 15 36)(pt 15 12)(line_width 1))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37)(line_width 1))
+ (circle (rect 43 20 51 28)(line_width 1))
+ )
+)
+(symbol
+ (rect 336 1400 400 1440)
+ (text "7400" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst19" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (line (pt 51 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 15 12)(pt 31 12)(line_width 1))
+ (line (pt 5 32)(pt 15 32)(line_width 1))
+ (line (pt 15 36)(pt 31 36)(line_width 1))
+ (line (pt 7 16)(pt 15 16)(line_width 1))
+ (line (pt 15 36)(pt 15 12)(line_width 1))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37)(line_width 1))
+ (circle (rect 43 20 51 28)(line_width 1))
+ )
+)
+(symbol
+ (rect 408 1232 472 1272)
+ (text "7486" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst20" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (line (pt 48 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 13 13)(pt 24 13)(line_width 1))
+ (line (pt 13 35)(pt 24 35)(line_width 1))
+ (line (pt 6 32)(pt 10 32)(line_width 1))
+ (line (pt 6 16)(pt 11 16)(line_width 1))
+ (line (pt 45 21)(pt 48 24)(line_width 1))
+ (line (pt 45 27)(pt 48 24)(line_width 1))
+ (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)(line_width 1))
+ (arc (pt 24 35)(pt 35 14)(rect -8 -29 57 36)(line_width 1))
+ (arc (pt 35 34)(pt 24 13)(rect -8 13 57 78)(line_width 1))
+ (arc (pt 2 29)(pt 2 19)(rect -19 8 14 41)(line_width 1))
+ )
+)
+(symbol
+ (rect 304 928 368 968)
+ (text "7486" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst21" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (line (pt 48 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 13 13)(pt 24 13)(line_width 1))
+ (line (pt 13 35)(pt 24 35)(line_width 1))
+ (line (pt 6 32)(pt 10 32)(line_width 1))
+ (line (pt 6 16)(pt 11 16)(line_width 1))
+ (line (pt 45 21)(pt 48 24)(line_width 1))
+ (line (pt 45 27)(pt 48 24)(line_width 1))
+ (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)(line_width 1))
+ (arc (pt 24 35)(pt 35 14)(rect -8 -29 57 36)(line_width 1))
+ (arc (pt 35 34)(pt 24 13)(rect -8 13 57 78)(line_width 1))
+ (arc (pt 2 29)(pt 2 19)(rect -19 8 14 41)(line_width 1))
+ )
+)
+(symbol
+ (rect 336 1040 400 1080)
+ (text "7400" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst22" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (line (pt 51 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 15 12)(pt 31 12)(line_width 1))
+ (line (pt 5 32)(pt 15 32)(line_width 1))
+ (line (pt 15 36)(pt 31 36)(line_width 1))
+ (line (pt 7 16)(pt 15 16)(line_width 1))
+ (line (pt 15 36)(pt 15 12)(line_width 1))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37)(line_width 1))
+ (circle (rect 43 20 51 28)(line_width 1))
+ )
+)
+(symbol
+ (rect 432 1072 496 1112)
+ (text "7400" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst23" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (line (pt 51 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 15 12)(pt 31 12)(line_width 1))
+ (line (pt 5 32)(pt 15 32)(line_width 1))
+ (line (pt 15 36)(pt 31 36)(line_width 1))
+ (line (pt 7 16)(pt 15 16)(line_width 1))
+ (line (pt 15 36)(pt 15 12)(line_width 1))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37)(line_width 1))
+ (circle (rect 43 20 51 28)(line_width 1))
+ )
+)
+(symbol
+ (rect 336 1104 400 1144)
+ (text "7400" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst24" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (line (pt 51 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 15 12)(pt 31 12)(line_width 1))
+ (line (pt 5 32)(pt 15 32)(line_width 1))
+ (line (pt 15 36)(pt 31 36)(line_width 1))
+ (line (pt 7 16)(pt 15 16)(line_width 1))
+ (line (pt 15 36)(pt 15 12)(line_width 1))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37)(line_width 1))
+ (circle (rect 43 20 51 28)(line_width 1))
+ )
+)
+(symbol
+ (rect 408 936 472 976)
+ (text "7486" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst25" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (line (pt 48 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 13 13)(pt 24 13)(line_width 1))
+ (line (pt 13 35)(pt 24 35)(line_width 1))
+ (line (pt 6 32)(pt 10 32)(line_width 1))
+ (line (pt 6 16)(pt 11 16)(line_width 1))
+ (line (pt 45 21)(pt 48 24)(line_width 1))
+ (line (pt 45 27)(pt 48 24)(line_width 1))
+ (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)(line_width 1))
+ (arc (pt 24 35)(pt 35 14)(rect -8 -29 57 36)(line_width 1))
+ (arc (pt 35 34)(pt 24 13)(rect -8 13 57 78)(line_width 1))
+ (arc (pt 2 29)(pt 2 19)(rect -19 8 14 41)(line_width 1))
+ )
+)
+(symbol
+ (rect 304 632 368 672)
+ (text "7486" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst26" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (line (pt 48 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 13 13)(pt 24 13)(line_width 1))
+ (line (pt 13 35)(pt 24 35)(line_width 1))
+ (line (pt 6 32)(pt 10 32)(line_width 1))
+ (line (pt 6 16)(pt 11 16)(line_width 1))
+ (line (pt 45 21)(pt 48 24)(line_width 1))
+ (line (pt 45 27)(pt 48 24)(line_width 1))
+ (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)(line_width 1))
+ (arc (pt 24 35)(pt 35 14)(rect -8 -29 57 36)(line_width 1))
+ (arc (pt 35 34)(pt 24 13)(rect -8 13 57 78)(line_width 1))
+ (arc (pt 2 29)(pt 2 19)(rect -19 8 14 41)(line_width 1))
+ )
+)
+(symbol
+ (rect 336 744 400 784)
+ (text "7400" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst27" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (line (pt 51 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 15 12)(pt 31 12)(line_width 1))
+ (line (pt 5 32)(pt 15 32)(line_width 1))
+ (line (pt 15 36)(pt 31 36)(line_width 1))
+ (line (pt 7 16)(pt 15 16)(line_width 1))
+ (line (pt 15 36)(pt 15 12)(line_width 1))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37)(line_width 1))
+ (circle (rect 43 20 51 28)(line_width 1))
+ )
+)
+(symbol
+ (rect 432 776 496 816)
+ (text "7400" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst28" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (line (pt 51 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 15 12)(pt 31 12)(line_width 1))
+ (line (pt 5 32)(pt 15 32)(line_width 1))
+ (line (pt 15 36)(pt 31 36)(line_width 1))
+ (line (pt 7 16)(pt 15 16)(line_width 1))
+ (line (pt 15 36)(pt 15 12)(line_width 1))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37)(line_width 1))
+ (circle (rect 43 20 51 28)(line_width 1))
+ )
+)
+(symbol
+ (rect 336 808 400 848)
+ (text "7400" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst29" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (line (pt 51 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 15 12)(pt 31 12)(line_width 1))
+ (line (pt 5 32)(pt 15 32)(line_width 1))
+ (line (pt 15 36)(pt 31 36)(line_width 1))
+ (line (pt 7 16)(pt 15 16)(line_width 1))
+ (line (pt 15 36)(pt 15 12)(line_width 1))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37)(line_width 1))
+ (circle (rect 43 20 51 28)(line_width 1))
+ )
+)
+(symbol
+ (rect 408 640 472 680)
+ (text "7486" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst30" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (line (pt 48 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 13 13)(pt 24 13)(line_width 1))
+ (line (pt 13 35)(pt 24 35)(line_width 1))
+ (line (pt 6 32)(pt 10 32)(line_width 1))
+ (line (pt 6 16)(pt 11 16)(line_width 1))
+ (line (pt 45 21)(pt 48 24)(line_width 1))
+ (line (pt 45 27)(pt 48 24)(line_width 1))
+ (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)(line_width 1))
+ (arc (pt 24 35)(pt 35 14)(rect -8 -29 57 36)(line_width 1))
+ (arc (pt 35 34)(pt 24 13)(rect -8 13 57 78)(line_width 1))
+ (arc (pt 2 29)(pt 2 19)(rect -19 8 14 41)(line_width 1))
+ )
+)
+(symbol
+ (rect 304 336 368 376)
+ (text "7486" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst31" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (line (pt 48 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 13 13)(pt 24 13)(line_width 1))
+ (line (pt 13 35)(pt 24 35)(line_width 1))
+ (line (pt 6 32)(pt 10 32)(line_width 1))
+ (line (pt 6 16)(pt 11 16)(line_width 1))
+ (line (pt 45 21)(pt 48 24)(line_width 1))
+ (line (pt 45 27)(pt 48 24)(line_width 1))
+ (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)(line_width 1))
+ (arc (pt 24 35)(pt 35 14)(rect -8 -29 57 36)(line_width 1))
+ (arc (pt 35 34)(pt 24 13)(rect -8 13 57 78)(line_width 1))
+ (arc (pt 2 29)(pt 2 19)(rect -19 8 14 41)(line_width 1))
+ )
+)
+(symbol
+ (rect 336 448 400 488)
+ (text "7400" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst32" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (line (pt 51 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 15 12)(pt 31 12)(line_width 1))
+ (line (pt 5 32)(pt 15 32)(line_width 1))
+ (line (pt 15 36)(pt 31 36)(line_width 1))
+ (line (pt 7 16)(pt 15 16)(line_width 1))
+ (line (pt 15 36)(pt 15 12)(line_width 1))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37)(line_width 1))
+ (circle (rect 43 20 51 28)(line_width 1))
+ )
+)
+(symbol
+ (rect 432 480 496 520)
+ (text "7400" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst33" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (line (pt 51 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 15 12)(pt 31 12)(line_width 1))
+ (line (pt 5 32)(pt 15 32)(line_width 1))
+ (line (pt 15 36)(pt 31 36)(line_width 1))
+ (line (pt 7 16)(pt 15 16)(line_width 1))
+ (line (pt 15 36)(pt 15 12)(line_width 1))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37)(line_width 1))
+ (circle (rect 43 20 51 28)(line_width 1))
+ )
+)
+(symbol
+ (rect 336 512 400 552)
+ (text "7400" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst34" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (line (pt 51 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 15 12)(pt 31 12)(line_width 1))
+ (line (pt 5 32)(pt 15 32)(line_width 1))
+ (line (pt 15 36)(pt 31 36)(line_width 1))
+ (line (pt 7 16)(pt 15 16)(line_width 1))
+ (line (pt 15 36)(pt 15 12)(line_width 1))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37)(line_width 1))
+ (circle (rect 43 20 51 28)(line_width 1))
+ )
+)
+(symbol
+ (rect 408 344 472 384)
+ (text "7486" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst35" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (line (pt 48 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 13 13)(pt 24 13)(line_width 1))
+ (line (pt 13 35)(pt 24 35)(line_width 1))
+ (line (pt 6 32)(pt 10 32)(line_width 1))
+ (line (pt 6 16)(pt 11 16)(line_width 1))
+ (line (pt 45 21)(pt 48 24)(line_width 1))
+ (line (pt 45 27)(pt 48 24)(line_width 1))
+ (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)(line_width 1))
+ (arc (pt 24 35)(pt 35 14)(rect -8 -29 57 36)(line_width 1))
+ (arc (pt 35 34)(pt 24 13)(rect -8 13 57 78)(line_width 1))
+ (arc (pt 2 29)(pt 2 19)(rect -19 8 14 41)(line_width 1))
+ )
+)
+(symbol
+ (rect 304 40 368 80)
+ (text "7486" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst36" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (line (pt 48 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 13 13)(pt 24 13)(line_width 1))
+ (line (pt 13 35)(pt 24 35)(line_width 1))
+ (line (pt 6 32)(pt 10 32)(line_width 1))
+ (line (pt 6 16)(pt 11 16)(line_width 1))
+ (line (pt 45 21)(pt 48 24)(line_width 1))
+ (line (pt 45 27)(pt 48 24)(line_width 1))
+ (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)(line_width 1))
+ (arc (pt 24 35)(pt 35 14)(rect -8 -29 57 36)(line_width 1))
+ (arc (pt 35 34)(pt 24 13)(rect -8 13 57 78)(line_width 1))
+ (arc (pt 2 29)(pt 2 19)(rect -19 8 14 41)(line_width 1))
+ )
+)
+(symbol
+ (rect 336 152 400 192)
+ (text "7400" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst37" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (line (pt 51 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 15 12)(pt 31 12)(line_width 1))
+ (line (pt 5 32)(pt 15 32)(line_width 1))
+ (line (pt 15 36)(pt 31 36)(line_width 1))
+ (line (pt 7 16)(pt 15 16)(line_width 1))
+ (line (pt 15 36)(pt 15 12)(line_width 1))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37)(line_width 1))
+ (circle (rect 43 20 51 28)(line_width 1))
+ )
+)
+(symbol
+ (rect 432 184 496 224)
+ (text "7400" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst38" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (line (pt 51 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 15 12)(pt 31 12)(line_width 1))
+ (line (pt 5 32)(pt 15 32)(line_width 1))
+ (line (pt 15 36)(pt 31 36)(line_width 1))
+ (line (pt 7 16)(pt 15 16)(line_width 1))
+ (line (pt 15 36)(pt 15 12)(line_width 1))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37)(line_width 1))
+ (circle (rect 43 20 51 28)(line_width 1))
+ )
+)
+(symbol
+ (rect 336 216 400 256)
+ (text "7400" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst39" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 7 22 12 34)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 7 6 12 18)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 54 14 59 26)(font "Courier New" (bold))(invisible))
+ (line (pt 51 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 15 12)(pt 31 12)(line_width 1))
+ (line (pt 5 32)(pt 15 32)(line_width 1))
+ (line (pt 15 36)(pt 31 36)(line_width 1))
+ (line (pt 7 16)(pt 15 16)(line_width 1))
+ (line (pt 15 36)(pt 15 12)(line_width 1))
+ (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37)(line_width 1))
+ (circle (rect 43 20 51 28)(line_width 1))
+ )
+)
+(symbol
+ (rect 408 48 472 88)
+ (text "7486" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+ (text "inst40" (rect 3 29 32 41)(font "Arial" ))
+ (port
+ (pt 0 16)
+ (input)
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (text "2" (rect 4 5 9 17)(font "Courier New" (bold))(invisible))
+ (line (pt 0 16)(pt 8 16)(line_width 1))
+ )
+ (port
+ (pt 0 32)
+ (input)
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (text "3" (rect 4 21 9 33)(font "Courier New" (bold))(invisible))
+ (line (pt 0 32)(pt 8 32)(line_width 1))
+ )
+ (port
+ (pt 64 24)
+ (output)
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (text "1" (rect 52 14 57 26)(font "Courier New" (bold))(invisible))
+ (line (pt 48 24)(pt 64 24)(line_width 1))
+ )
+ (drawing
+ (line (pt 13 13)(pt 24 13)(line_width 1))
+ (line (pt 13 35)(pt 24 35)(line_width 1))
+ (line (pt 6 32)(pt 10 32)(line_width 1))
+ (line (pt 6 16)(pt 11 16)(line_width 1))
+ (line (pt 45 21)(pt 48 24)(line_width 1))
+ (line (pt 45 27)(pt 48 24)(line_width 1))
+ (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)(line_width 1))
+ (arc (pt 24 35)(pt 35 14)(rect -8 -29 57 36)(line_width 1))
+ (arc (pt 35 34)(pt 24 13)(rect -8 13 57 78)(line_width 1))
+ (arc (pt 2 29)(pt 2 19)(rect -19 8 14 41)(line_width 1))
+ )
+)
+(connector
+ (pt 472 2128)
+ (pt 536 2128)
+)
+(connector
+ (pt 384 2144)
+ (pt 384 2136)
+)
+(connector
+ (pt 384 2136)
+ (pt 408 2136)
+)
+(connector
+ (pt 376 2120)
+ (pt 376 2192)
+)
+(connector
+ (pt 376 2192)
+ (pt 312 2192)
+)
+(connector
+ (pt 312 2192)
+ (pt 312 2224)
+)
+(connector
+ (pt 312 2224)
+ (pt 336 2224)
+)
+(connector
+ (pt 288 2144)
+ (pt 288 2240)
+)
+(connector
+ (pt 288 2240)
+ (pt 336 2240)
+)
+(connector
+ (pt 400 2232)
+ (pt 416 2232)
+)
+(connector
+ (pt 416 2232)
+ (pt 416 2256)
+)
+(connector
+ (pt 416 2256)
+ (pt 432 2256)
+)
+(connector
+ (pt 416 2272)
+ (pt 432 2272)
+)
+(connector
+ (pt 416 2296)
+ (pt 416 2272)
+)
+(connector
+ (pt 416 2296)
+ (pt 400 2296)
+)
+(connector
+ (pt 336 2288)
+ (pt 272 2288)
+)
+(connector
+ (pt 272 2288)
+ (pt 272 2128)
+)
+(connector
+ (pt 336 2304)
+ (pt 256 2304)
+)
+(connector
+ (pt 256 2304)
+ (pt 256 2112)
+)
+(connector
+ (pt 472 1848)
+ (pt 536 1848)
+)
+(connector
+ (pt 384 1864)
+ (pt 384 1856)
+)
+(connector
+ (pt 384 1856)
+ (pt 408 1856)
+)
+(connector
+ (pt 376 1840)
+ (pt 376 1912)
+)
+(connector
+ (pt 376 1912)
+ (pt 312 1912)
+)
+(connector
+ (pt 312 1912)
+ (pt 312 1944)
+)
+(connector
+ (pt 312 1944)
+ (pt 336 1944)
+)
+(connector
+ (pt 288 1864)
+ (pt 288 1960)
+)
+(connector
+ (pt 288 1960)
+ (pt 336 1960)
+)
+(connector
+ (pt 400 1952)
+ (pt 416 1952)
+)
+(connector
+ (pt 416 1952)
+ (pt 416 1976)
+)
+(connector
+ (pt 416 1976)
+ (pt 432 1976)
+)
+(connector
+ (pt 416 1992)
+ (pt 432 1992)
+)
+(connector
+ (pt 416 2016)
+ (pt 416 1992)
+)
+(connector
+ (pt 416 2016)
+ (pt 400 2016)
+)
+(connector
+ (pt 336 2008)
+ (pt 272 2008)
+)
+(connector
+ (pt 272 2008)
+ (pt 272 1848)
+)
+(connector
+ (pt 336 2024)
+ (pt 256 2024)
+)
+(connector
+ (pt 256 2024)
+ (pt 256 1832)
+)
+(connector
+ (pt 176 2072)
+ (pt 176 1864)
+)
+(connector
+ (pt 176 2072)
+ (pt 736 2072)
+)
+(connector
+ (pt 736 2264)
+ (pt 736 2072)
+)
+(connector
+ (pt 496 2264)
+ (pt 736 2264)
+)
+(connector
+ (pt 496 1984)
+ (pt 728 1984)
+)
+(connector
+ (pt 472 1552)
+ (pt 536 1552)
+)
+(connector
+ (pt 384 1568)
+ (pt 384 1560)
+)
+(connector
+ (pt 384 1560)
+ (pt 408 1560)
+)
+(connector
+ (pt 376 1544)
+ (pt 376 1616)
+)
+(connector
+ (pt 376 1616)
+ (pt 312 1616)
+)
+(connector
+ (pt 312 1616)
+ (pt 312 1648)
+)
+(connector
+ (pt 312 1648)
+ (pt 336 1648)
+)
+(connector
+ (pt 288 1568)
+ (pt 288 1664)
+)
+(connector
+ (pt 288 1664)
+ (pt 336 1664)
+)
+(connector
+ (pt 400 1656)
+ (pt 416 1656)
+)
+(connector
+ (pt 416 1656)
+ (pt 416 1680)
+)
+(connector
+ (pt 416 1680)
+ (pt 432 1680)
+)
+(connector
+ (pt 416 1696)
+ (pt 432 1696)
+)
+(connector
+ (pt 416 1720)
+ (pt 416 1696)
+)
+(connector
+ (pt 416 1720)
+ (pt 400 1720)
+)
+(connector
+ (pt 336 1712)
+ (pt 272 1712)
+)
+(connector
+ (pt 272 1712)
+ (pt 272 1552)
+)
+(connector
+ (pt 336 1728)
+ (pt 256 1728)
+)
+(connector
+ (pt 256 1728)
+ (pt 256 1536)
+)
+(connector
+ (pt 496 1688)
+ (pt 728 1688)
+)
+(connector
+ (pt 176 1568)
+ (pt 176 1768)
+)
+(connector
+ (pt 472 1256)
+ (pt 536 1256)
+)
+(connector
+ (pt 384 1272)
+ (pt 384 1264)
+)
+(connector
+ (pt 384 1264)
+ (pt 408 1264)
+)
+(connector
+ (pt 376 1248)
+ (pt 376 1320)
+)
+(connector
+ (pt 376 1320)
+ (pt 312 1320)
+)
+(connector
+ (pt 312 1320)
+ (pt 312 1352)
+)
+(connector
+ (pt 312 1352)
+ (pt 336 1352)
+)
+(connector
+ (pt 288 1272)
+ (pt 288 1368)
+)
+(connector
+ (pt 288 1368)
+ (pt 336 1368)
+)
+(connector
+ (pt 400 1360)
+ (pt 416 1360)
+)
+(connector
+ (pt 416 1360)
+ (pt 416 1384)
+)
+(connector
+ (pt 416 1384)
+ (pt 432 1384)
+)
+(connector
+ (pt 416 1400)
+ (pt 432 1400)
+)
+(connector
+ (pt 416 1424)
+ (pt 416 1400)
+)
+(connector
+ (pt 416 1424)
+ (pt 400 1424)
+)
+(connector
+ (pt 336 1416)
+ (pt 272 1416)
+)
+(connector
+ (pt 272 1416)
+ (pt 272 1256)
+)
+(connector
+ (pt 336 1432)
+ (pt 256 1432)
+)
+(connector
+ (pt 256 1432)
+ (pt 256 1240)
+)
+(connector
+ (pt 496 1392)
+ (pt 728 1392)
+)
+(connector
+ (pt 176 1272)
+ (pt 176 1472)
+)
+(connector
+ (pt 472 960)
+ (pt 536 960)
+)
+(connector
+ (pt 384 976)
+ (pt 384 968)
+)
+(connector
+ (pt 384 968)
+ (pt 408 968)
+)
+(connector
+ (pt 376 952)
+ (pt 376 1024)
+)
+(connector
+ (pt 376 1024)
+ (pt 312 1024)
+)
+(connector
+ (pt 312 1024)
+ (pt 312 1056)
+)
+(connector
+ (pt 312 1056)
+ (pt 336 1056)
+)
+(connector
+ (pt 288 976)
+ (pt 288 1072)
+)
+(connector
+ (pt 288 1072)
+ (pt 336 1072)
+)
+(connector
+ (pt 400 1064)
+ (pt 416 1064)
+)
+(connector
+ (pt 416 1064)
+ (pt 416 1088)
+)
+(connector
+ (pt 416 1088)
+ (pt 432 1088)
+)
+(connector
+ (pt 416 1104)
+ (pt 432 1104)
+)
+(connector
+ (pt 416 1128)
+ (pt 416 1104)
+)
+(connector
+ (pt 416 1128)
+ (pt 400 1128)
+)
+(connector
+ (pt 336 1120)
+ (pt 272 1120)
+)
+(connector
+ (pt 272 1120)
+ (pt 272 960)
+)
+(connector
+ (pt 336 1136)
+ (pt 256 1136)
+)
+(connector
+ (pt 256 1136)
+ (pt 256 944)
+)
+(connector
+ (pt 496 1096)
+ (pt 728 1096)
+)
+(connector
+ (pt 176 976)
+ (pt 176 1176)
+)
+(connector
+ (pt 472 664)
+ (pt 536 664)
+)
+(connector
+ (pt 384 680)
+ (pt 384 672)
+)
+(connector
+ (pt 384 672)
+ (pt 408 672)
+)
+(connector
+ (pt 376 656)
+ (pt 376 728)
+)
+(connector
+ (pt 376 728)
+ (pt 312 728)
+)
+(connector
+ (pt 312 728)
+ (pt 312 760)
+)
+(connector
+ (pt 312 760)
+ (pt 336 760)
+)
+(connector
+ (pt 288 680)
+ (pt 288 776)
+)
+(connector
+ (pt 288 776)
+ (pt 336 776)
+)
+(connector
+ (pt 400 768)
+ (pt 416 768)
+)
+(connector
+ (pt 416 768)
+ (pt 416 792)
+)
+(connector
+ (pt 416 792)
+ (pt 432 792)
+)
+(connector
+ (pt 416 808)
+ (pt 432 808)
+)
+(connector
+ (pt 416 832)
+ (pt 416 808)
+)
+(connector
+ (pt 416 832)
+ (pt 400 832)
+)
+(connector
+ (pt 336 824)
+ (pt 272 824)
+)
+(connector
+ (pt 272 824)
+ (pt 272 664)
+)
+(connector
+ (pt 336 840)
+ (pt 256 840)
+)
+(connector
+ (pt 256 840)
+ (pt 256 648)
+)
+(connector
+ (pt 496 800)
+ (pt 728 800)
+)
+(connector
+ (pt 176 680)
+ (pt 176 880)
+)
+(connector
+ (pt 472 368)
+ (pt 536 368)
+)
+(connector
+ (pt 384 384)
+ (pt 384 376)
+)
+(connector
+ (pt 384 376)
+ (pt 408 376)
+)
+(connector
+ (pt 376 360)
+ (pt 376 432)
+)
+(connector
+ (pt 376 432)
+ (pt 312 432)
+)
+(connector
+ (pt 312 432)
+ (pt 312 464)
+)
+(connector
+ (pt 312 464)
+ (pt 336 464)
+)
+(connector
+ (pt 288 384)
+ (pt 288 480)
+)
+(connector
+ (pt 288 480)
+ (pt 336 480)
+)
+(connector
+ (pt 400 472)
+ (pt 416 472)
+)
+(connector
+ (pt 416 472)
+ (pt 416 496)
+)
+(connector
+ (pt 416 496)
+ (pt 432 496)
+)
+(connector
+ (pt 416 512)
+ (pt 432 512)
+)
+(connector
+ (pt 416 536)
+ (pt 416 512)
+)
+(connector
+ (pt 416 536)
+ (pt 400 536)
+)
+(connector
+ (pt 336 528)
+ (pt 272 528)
+)
+(connector
+ (pt 272 528)
+ (pt 272 368)
+)
+(connector
+ (pt 336 544)
+ (pt 256 544)
+)
+(connector
+ (pt 256 544)
+ (pt 256 352)
+)
+(connector
+ (pt 496 504)
+ (pt 728 504)
+)
+(connector
+ (pt 176 384)
+ (pt 176 584)
+)
+(connector
+ (pt 472 72)
+ (pt 536 72)
+)
+(connector
+ (pt 384 88)
+ (pt 384 80)
+)
+(connector
+ (pt 384 80)
+ (pt 408 80)
+)
+(connector
+ (pt 376 64)
+ (pt 376 136)
+)
+(connector
+ (pt 376 136)
+ (pt 312 136)
+)
+(connector
+ (pt 312 136)
+ (pt 312 168)
+)
+(connector
+ (pt 312 168)
+ (pt 336 168)
+)
+(connector
+ (pt 288 88)
+ (pt 288 184)
+)
+(connector
+ (pt 288 184)
+ (pt 336 184)
+)
+(connector
+ (pt 400 176)
+ (pt 416 176)
+)
+(connector
+ (pt 416 176)
+ (pt 416 200)
+)
+(connector
+ (pt 416 200)
+ (pt 432 200)
+)
+(connector
+ (pt 416 216)
+ (pt 432 216)
+)
+(connector
+ (pt 416 240)
+ (pt 416 216)
+)
+(connector
+ (pt 416 240)
+ (pt 400 240)
+)
+(connector
+ (pt 336 232)
+ (pt 272 232)
+)
+(connector
+ (pt 272 232)
+ (pt 272 72)
+)
+(connector
+ (pt 336 248)
+ (pt 256 248)
+)
+(connector
+ (pt 256 248)
+ (pt 256 56)
+)
+(connector
+ (pt 176 88)
+ (pt 176 288)
+)
+(connector
+ (pt 496 208)
+ (pt 520 208)
+)
+(connector
+ (pt 520 40)
+ (pt 520 208)
+)
+(connector
+ (pt 520 40)
+ (pt 536 40)
+)
+(connector
+ (pt 368 2120)
+ (pt 376 2120)
+)
+(connector
+ (pt 376 2120)
+ (pt 408 2120)
+)
+(connector
+ (pt 248 2144)
+ (pt 288 2144)
+)
+(connector
+ (pt 288 2144)
+ (pt 384 2144)
+)
+(connector
+ (pt 248 2128)
+ (pt 272 2128)
+)
+(connector
+ (pt 272 2128)
+ (pt 304 2128)
+)
+(connector
+ (pt 248 2112)
+ (pt 256 2112)
+)
+(connector
+ (pt 256 2112)
+ (pt 304 2112)
+)
+(connector
+ (pt 368 1840)
+ (pt 376 1840)
+)
+(connector
+ (pt 376 1840)
+ (pt 408 1840)
+)
+(connector
+ (pt 248 1848)
+ (pt 272 1848)
+)
+(connector
+ (pt 272 1848)
+ (pt 304 1848)
+)
+(connector
+ (pt 248 1832)
+ (pt 256 1832)
+)
+(connector
+ (pt 256 1832)
+ (pt 304 1832)
+)
+(connector
+ (pt 176 1864)
+ (pt 288 1864)
+)
+(connector
+ (pt 288 1864)
+ (pt 384 1864)
+)
+(connector
+ (pt 368 1544)
+ (pt 376 1544)
+)
+(connector
+ (pt 376 1544)
+ (pt 408 1544)
+)
+(connector
+ (pt 248 1552)
+ (pt 272 1552)
+)
+(connector
+ (pt 272 1552)
+ (pt 304 1552)
+)
+(connector
+ (pt 248 1536)
+ (pt 256 1536)
+)
+(connector
+ (pt 256 1536)
+ (pt 304 1536)
+)
+(connector
+ (pt 176 1568)
+ (pt 288 1568)
+)
+(connector
+ (pt 288 1568)
+ (pt 384 1568)
+)
+(connector
+ (pt 368 1248)
+ (pt 376 1248)
+)
+(connector
+ (pt 376 1248)
+ (pt 408 1248)
+)
+(connector
+ (pt 248 1256)
+ (pt 272 1256)
+)
+(connector
+ (pt 272 1256)
+ (pt 304 1256)
+)
+(connector
+ (pt 248 1240)
+ (pt 256 1240)
+)
+(connector
+ (pt 256 1240)
+ (pt 304 1240)
+)
+(connector
+ (pt 176 1272)
+ (pt 288 1272)
+)
+(connector
+ (pt 288 1272)
+ (pt 384 1272)
+)
+(connector
+ (pt 368 952)
+ (pt 376 952)
+)
+(connector
+ (pt 376 952)
+ (pt 408 952)
+)
+(connector
+ (pt 248 960)
+ (pt 272 960)
+)
+(connector
+ (pt 272 960)
+ (pt 304 960)
+)
+(connector
+ (pt 248 944)
+ (pt 256 944)
+)
+(connector
+ (pt 256 944)
+ (pt 304 944)
+)
+(connector
+ (pt 176 976)
+ (pt 288 976)
+)
+(connector
+ (pt 288 976)
+ (pt 384 976)
+)
+(connector
+ (pt 368 656)
+ (pt 376 656)
+)
+(connector
+ (pt 376 656)
+ (pt 408 656)
+)
+(connector
+ (pt 248 664)
+ (pt 272 664)
+)
+(connector
+ (pt 272 664)
+ (pt 304 664)
+)
+(connector
+ (pt 248 648)
+ (pt 256 648)
+)
+(connector
+ (pt 256 648)
+ (pt 304 648)
+)
+(connector
+ (pt 176 680)
+ (pt 288 680)
+)
+(connector
+ (pt 288 680)
+ (pt 384 680)
+)
+(connector
+ (pt 368 360)
+ (pt 376 360)
+)
+(connector
+ (pt 376 360)
+ (pt 408 360)
+)
+(connector
+ (pt 248 368)
+ (pt 272 368)
+)
+(connector
+ (pt 272 368)
+ (pt 304 368)
+)
+(connector
+ (pt 248 352)
+ (pt 256 352)
+)
+(connector
+ (pt 256 352)
+ (pt 304 352)
+)
+(connector
+ (pt 176 384)
+ (pt 288 384)
+)
+(connector
+ (pt 288 384)
+ (pt 384 384)
+)
+(connector
+ (pt 368 64)
+ (pt 376 64)
+)
+(connector
+ (pt 376 64)
+ (pt 408 64)
+)
+(connector
+ (pt 248 72)
+ (pt 272 72)
+)
+(connector
+ (pt 272 72)
+ (pt 304 72)
+)
+(connector
+ (pt 248 56)
+ (pt 256 56)
+)
+(connector
+ (pt 256 56)
+ (pt 304 56)
+)
+(connector
+ (pt 176 88)
+ (pt 288 88)
+)
+(connector
+ (pt 288 88)
+ (pt 384 88)
+)
+(connector
+ (pt 728 1768)
+ (pt 728 1984)
+)
+(connector
+ (pt 728 1472)
+ (pt 728 1688)
+)
+(connector
+ (pt 176 1768)
+ (pt 728 1768)
+)
+(connector
+ (pt 728 1176)
+ (pt 728 1392)
+)
+(connector
+ (pt 176 1472)
+ (pt 728 1472)
+)
+(connector
+ (pt 728 880)
+ (pt 728 1096)
+)
+(connector
+ (pt 176 1176)
+ (pt 728 1176)
+)
+(connector
+ (pt 728 584)
+ (pt 728 800)
+)
+(connector
+ (pt 176 880)
+ (pt 728 880)
+)
+(connector
+ (pt 728 288)
+ (pt 728 504)
+)
+(connector
+ (pt 176 584)
+ (pt 728 584)
+)
+(connector
+ (pt 176 288)
+ (pt 728 288)
+)
+(junction (pt 376 2120))
+(junction (pt 288 2144))
+(junction (pt 272 2128))
+(junction (pt 256 2112))
+(junction (pt 376 1840))
+(junction (pt 272 1848))
+(junction (pt 256 1832))
+(junction (pt 288 1864))
+(junction (pt 376 1544))
+(junction (pt 272 1552))
+(junction (pt 256 1536))
+(junction (pt 288 1568))
+(junction (pt 376 1248))
+(junction (pt 272 1256))
+(junction (pt 256 1240))
+(junction (pt 288 1272))
+(junction (pt 376 952))
+(junction (pt 272 960))
+(junction (pt 256 944))
+(junction (pt 288 976))
+(junction (pt 376 656))
+(junction (pt 272 664))
+(junction (pt 256 648))
+(junction (pt 288 680))
+(junction (pt 376 360))
+(junction (pt 272 368))
+(junction (pt 256 352))
+(junction (pt 288 384))
+(junction (pt 376 64))
+(junction (pt 272 72))
+(junction (pt 256 56))
+(junction (pt 288 88))
diff --git a/adder/adder.bsf b/adder/adder.bsf
new file mode 100644
index 0000000..0eb6e3f
--- /dev/null
+++ b/adder/adder.bsf
@@ -0,0 +1,211 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 16 16 112 336)
+ (text "adder" (rect 5 0 38 14)(font "Arial" (font_size 8)))
+ (text "inst" (rect 8 304 25 316)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "A7" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+ (text "A7" (rect 21 27 37 41)(font "Arial" (font_size 8)))
+ (line (pt 0 32)(pt 16 32)(line_width 1))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "B7" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+ (text "B7" (rect 21 43 36 57)(font "Arial" (font_size 8)))
+ (line (pt 0 48)(pt 16 48)(line_width 1))
+ )
+ (port
+ (pt 0 64)
+ (input)
+ (text "A6" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+ (text "A6" (rect 21 59 37 73)(font "Arial" (font_size 8)))
+ (line (pt 0 64)(pt 16 64)(line_width 1))
+ )
+ (port
+ (pt 0 80)
+ (input)
+ (text "B6" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+ (text "B6" (rect 21 75 36 89)(font "Arial" (font_size 8)))
+ (line (pt 0 80)(pt 16 80)(line_width 1))
+ )
+ (port
+ (pt 0 96)
+ (input)
+ (text "A5" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+ (text "A5" (rect 21 91 37 105)(font "Arial" (font_size 8)))
+ (line (pt 0 96)(pt 16 96)(line_width 1))
+ )
+ (port
+ (pt 0 112)
+ (input)
+ (text "B5" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+ (text "B5" (rect 21 107 36 121)(font "Arial" (font_size 8)))
+ (line (pt 0 112)(pt 16 112)(line_width 1))
+ )
+ (port
+ (pt 0 128)
+ (input)
+ (text "A4" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+ (text "A4" (rect 21 123 37 137)(font "Arial" (font_size 8)))
+ (line (pt 0 128)(pt 16 128)(line_width 1))
+ )
+ (port
+ (pt 0 144)
+ (input)
+ (text "B4" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+ (text "B4" (rect 21 139 36 153)(font "Arial" (font_size 8)))
+ (line (pt 0 144)(pt 16 144)(line_width 1))
+ )
+ (port
+ (pt 0 160)
+ (input)
+ (text "A3" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+ (text "A3" (rect 21 155 37 169)(font "Arial" (font_size 8)))
+ (line (pt 0 160)(pt 16 160)(line_width 1))
+ )
+ (port
+ (pt 0 176)
+ (input)
+ (text "B3" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+ (text "B3" (rect 21 171 36 185)(font "Arial" (font_size 8)))
+ (line (pt 0 176)(pt 16 176)(line_width 1))
+ )
+ (port
+ (pt 0 192)
+ (input)
+ (text "A2" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+ (text "A2" (rect 21 187 37 201)(font "Arial" (font_size 8)))
+ (line (pt 0 192)(pt 16 192)(line_width 1))
+ )
+ (port
+ (pt 0 208)
+ (input)
+ (text "B2" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+ (text "B2" (rect 21 203 36 217)(font "Arial" (font_size 8)))
+ (line (pt 0 208)(pt 16 208)(line_width 1))
+ )
+ (port
+ (pt 0 224)
+ (input)
+ (text "A1" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+ (text "A1" (rect 21 219 37 233)(font "Arial" (font_size 8)))
+ (line (pt 0 224)(pt 16 224)(line_width 1))
+ )
+ (port
+ (pt 0 240)
+ (input)
+ (text "B1" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+ (text "B1" (rect 21 235 36 249)(font "Arial" (font_size 8)))
+ (line (pt 0 240)(pt 16 240)(line_width 1))
+ )
+ (port
+ (pt 0 256)
+ (input)
+ (text "A0" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+ (text "A0" (rect 21 251 37 265)(font "Arial" (font_size 8)))
+ (line (pt 0 256)(pt 16 256)(line_width 1))
+ )
+ (port
+ (pt 0 272)
+ (input)
+ (text "B0" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+ (text "B0" (rect 21 267 36 281)(font "Arial" (font_size 8)))
+ (line (pt 0 272)(pt 16 272)(line_width 1))
+ )
+ (port
+ (pt 0 288)
+ (input)
+ (text "CI" (rect 0 0 10 14)(font "Arial" (font_size 8)))
+ (text "CI" (rect 21 283 31 297)(font "Arial" (font_size 8)))
+ (line (pt 0 288)(pt 16 288)(line_width 1))
+ )
+ (port
+ (pt 96 32)
+ (output)
+ (text "CO" (rect 0 0 17 14)(font "Arial" (font_size 8)))
+ (text "CO" (rect 58 27 75 41)(font "Arial" (font_size 8)))
+ (line (pt 96 32)(pt 80 32)(line_width 1))
+ )
+ (port
+ (pt 96 48)
+ (output)
+ (text "S7" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+ (text "S7" (rect 60 43 75 57)(font "Arial" (font_size 8)))
+ (line (pt 96 48)(pt 80 48)(line_width 1))
+ )
+ (port
+ (pt 96 64)
+ (output)
+ (text "S6" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+ (text "S6" (rect 60 59 75 73)(font "Arial" (font_size 8)))
+ (line (pt 96 64)(pt 80 64)(line_width 1))
+ )
+ (port
+ (pt 96 80)
+ (output)
+ (text "S5" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+ (text "S5" (rect 60 75 75 89)(font "Arial" (font_size 8)))
+ (line (pt 96 80)(pt 80 80)(line_width 1))
+ )
+ (port
+ (pt 96 96)
+ (output)
+ (text "S4" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+ (text "S4" (rect 60 91 75 105)(font "Arial" (font_size 8)))
+ (line (pt 96 96)(pt 80 96)(line_width 1))
+ )
+ (port
+ (pt 96 112)
+ (output)
+ (text "S3" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+ (text "S3" (rect 60 107 75 121)(font "Arial" (font_size 8)))
+ (line (pt 96 112)(pt 80 112)(line_width 1))
+ )
+ (port
+ (pt 96 128)
+ (output)
+ (text "S2" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+ (text "S2" (rect 60 123 75 137)(font "Arial" (font_size 8)))
+ (line (pt 96 128)(pt 80 128)(line_width 1))
+ )
+ (port
+ (pt 96 144)
+ (output)
+ (text "S1" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+ (text "S1" (rect 60 139 75 153)(font "Arial" (font_size 8)))
+ (line (pt 96 144)(pt 80 144)(line_width 1))
+ )
+ (port
+ (pt 96 160)
+ (output)
+ (text "S0" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+ (text "S0" (rect 60 155 75 169)(font "Arial" (font_size 8)))
+ (line (pt 96 160)(pt 80 160)(line_width 1))
+ )
+ (drawing
+ (rectangle (rect 16 16 80 304)(line_width 1))
+ )
+)
diff --git a/adder/adder.done b/adder/adder.done
new file mode 100644
index 0000000..393f79d
--- /dev/null
+++ b/adder/adder.done
@@ -0,0 +1 @@
+Mon Mar 07 08:49:27 2022
diff --git a/adder/adder.fit.rpt b/adder/adder.fit.rpt
new file mode 100644
index 0000000..5d58891
--- /dev/null
+++ b/adder/adder.fit.rpt
@@ -0,0 +1,1040 @@
+Fitter report for adder
+Mon Mar 07 08:49:24 2022
+Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Fitter Summary
+ 3. Fitter Settings
+ 4. Parallel Compilation
+ 5. Incremental Compilation Preservation Summary
+ 6. Incremental Compilation Partition Settings
+ 7. Incremental Compilation Placement Preservation
+ 8. Pin-Out File
+ 9. Fitter Resource Usage Summary
+ 10. Input Pins
+ 11. Output Pins
+ 12. I/O Bank Usage
+ 13. All Package Pins
+ 14. Output Pin Default Load For Reported TCO
+ 15. Fitter Resource Utilization by Entity
+ 16. Delay Chain Summary
+ 17. Pad To Core Delay Chain Fanout
+ 18. Non-Global High Fan-Out Signals
+ 19. Interconnect Usage Summary
+ 20. LAB Logic Elements
+ 21. LAB Signals Sourced
+ 22. LAB Signals Sourced Out
+ 23. LAB Distinct Inputs
+ 24. Fitter Device Options
+ 25. Operating Settings and Conditions
+ 26. Estimated Delay Added for Hold Timing
+ 27. Advanced Data - General
+ 28. Advanced Data - Placement Preparation
+ 29. Advanced Data - Placement
+ 30. Advanced Data - Routing
+ 31. Fitter Messages
+ 32. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Fitter Summary ;
++------------------------------------+----------------------------------------------+
+; Fitter Status ; Successful - Mon Mar 07 08:49:24 2022 ;
+; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
+; Revision Name ; adder ;
+; Top-level Entity Name ; adder ;
+; Family ; Cyclone II ;
+; Device ; EP2C8Q208C8 ;
+; Timing Models ; Final ;
+; Total logic elements ; 21 / 8,256 ( < 1 % ) ;
+; Total combinational functions ; 21 / 8,256 ( < 1 % ) ;
+; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ;
+; Total registers ; 0 ;
+; Total pins ; 26 / 138 ( 19 % ) ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 0 / 165,888 ( 0 % ) ;
+; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
+; Total PLLs ; 0 / 2 ( 0 % ) ;
++------------------------------------+----------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+; Option ; Setting ; Default Value ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+; Device ; EP2C8Q208C8 ; ;
+; Minimum Core Junction Temperature ; 0 ; ;
+; Maximum Core Junction Temperature ; 85 ; ;
+; Fit Attempts to Skip ; 0 ; 0.0 ;
+; Use smart compilation ; Off ; Off ;
+; Use TimeQuest Timing Analyzer ; Off ; Off ;
+; Router Timing Optimization Level ; Normal ; Normal ;
+; Placement Effort Multiplier ; 1.0 ; 1.0 ;
+; Router Effort Multiplier ; 1.0 ; 1.0 ;
+; Always Enable Input Buffers ; Off ; Off ;
+; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
+; Optimize Multi-Corner Timing ; Off ; Off ;
+; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
+; Optimize Timing ; Normal compilation ; Normal compilation ;
+; Optimize Timing for ECOs ; Off ; Off ;
+; Regenerate full fit report during ECO compiles ; Off ; Off ;
+; Optimize IOC Register Placement for Timing ; On ; On ;
+; Limit to One Fitting Attempt ; Off ; Off ;
+; Final Placement Optimizations ; Automatically ; Automatically ;
+; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
+; Fitter Initial Placement Seed ; 1 ; 1 ;
+; PCI I/O ; Off ; Off ;
+; Weak Pull-Up Resistor ; Off ; Off ;
+; Enable Bus-Hold Circuitry ; Off ; Off ;
+; Auto Global Memory Control Signals ; Off ; Off ;
+; Auto Packed Registers ; Auto ; Auto ;
+; Auto Delay Chains ; On ; On ;
+; Auto Merge PLLs ; On ; On ;
+; Ignore PLL Mode When Merging PLLs ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
+; Perform Register Duplication for Performance ; Off ; Off ;
+; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
+; Perform Register Retiming for Performance ; Off ; Off ;
+; Perform Asynchronous Signal Pipelining ; Off ; Off ;
+; Fitter Effort ; Auto Fit ; Auto Fit ;
+; Physical Synthesis Effort Level ; Normal ; Normal ;
+; Auto Global Clock ; On ; On ;
+; Auto Global Register Control Signals ; On ; On ;
+; Stop After Congestion Map Generation ; Off ; Off ;
+; Save Intermediate Fitting Results ; Off ; Off ;
+; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
++--------------------------------------------------------------------+--------------------------------+--------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 4 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.00 ;
+; Maximum used ; 4 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; 1 processor ; 100.0% ;
+; 2-4 processors ; < 0.1% ;
++----------------------------+-------------+
+
+
++----------------------------------------------+
+; Incremental Compilation Preservation Summary ;
++-------------------------+--------------------+
+; Type ; Value ;
++-------------------------+--------------------+
+; Placement ; ;
+; -- Requested ; 0 / 47 ( 0.00 % ) ;
+; -- Achieved ; 0 / 47 ( 0.00 % ) ;
+; ; ;
+; Routing (by Connection) ; ;
+; -- Requested ; 0 / 0 ( 0.00 % ) ;
+; -- Achieved ; 0 / 0 ( 0.00 % ) ;
++-------------------------+--------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings ;
++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
+; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
+; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
+
+
++--------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation ;
++----------------+---------+-------------------+-------------------------+-------------------+
+; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
++----------------+---------+-------------------+-------------------------+-------------------+
+; Top ; 47 ; 0 ; N/A ; Source File ;
++----------------+---------+-------------------+-------------------------+-------------------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in D:/projects/quartus/adder/adder.pin.
+
+
++--------------------------------------------------------------------+
+; Fitter Resource Usage Summary ;
++---------------------------------------------+----------------------+
+; Resource ; Usage ;
++---------------------------------------------+----------------------+
+; Total logic elements ; 21 / 8,256 ( < 1 % ) ;
+; -- Combinational with no register ; 21 ;
+; -- Register only ; 0 ;
+; -- Combinational with a register ; 0 ;
+; ; ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 9 ;
+; -- 3 input functions ; 9 ;
+; -- <=2 input functions ; 3 ;
+; -- Register only ; 0 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 21 ;
+; -- arithmetic mode ; 0 ;
+; ; ;
+; Total registers* ; 0 / 8,646 ( 0 % ) ;
+; -- Dedicated logic registers ; 0 / 8,256 ( 0 % ) ;
+; -- I/O registers ; 0 / 390 ( 0 % ) ;
+; ; ;
+; Total LABs: partially or completely used ; 2 / 516 ( < 1 % ) ;
+; User inserted logic elements ; 0 ;
+; Virtual pins ; 0 ;
+; I/O pins ; 26 / 138 ( 19 % ) ;
+; -- Clock pins ; 2 / 4 ( 50 % ) ;
+; Global signals ; 0 ;
+; M4Ks ; 0 / 36 ( 0 % ) ;
+; Total block memory bits ; 0 / 165,888 ( 0 % ) ;
+; Total block memory implementation bits ; 0 / 165,888 ( 0 % ) ;
+; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
+; PLLs ; 0 / 2 ( 0 % ) ;
+; Global clocks ; 0 / 8 ( 0 % ) ;
+; JTAGs ; 0 / 1 ( 0 % ) ;
+; ASMI blocks ; 0 / 1 ( 0 % ) ;
+; CRC blocks ; 0 / 1 ( 0 % ) ;
+; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ;
+; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ;
+; Maximum fan-out node ; 7400:inst8|4~0 ;
+; Maximum fan-out ; 4 ;
+; Highest non-global fan-out signal ; 7400:inst8|4~0 ;
+; Highest non-global fan-out ; 4 ;
+; Total fan-out ; 78 ;
+; Average fan-out ; 1.56 ;
++---------------------------------------------+----------------------+
+* Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins ;
++------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
++------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+; A0 ; 24 ; 1 ; 0 ; 9 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; A1 ; 57 ; 4 ; 1 ; 0 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; A2 ; 23 ; 1 ; 0 ; 9 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; A3 ; 40 ; 1 ; 0 ; 5 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; A4 ; 41 ; 1 ; 0 ; 4 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; A5 ; 150 ; 3 ; 34 ; 16 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; A6 ; 13 ; 1 ; 0 ; 16 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; A7 ; 5 ; 1 ; 0 ; 17 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; B0 ; 28 ; 1 ; 0 ; 9 ; 3 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; B1 ; 60 ; 4 ; 3 ; 0 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; B2 ; 30 ; 1 ; 0 ; 8 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; B3 ; 39 ; 1 ; 0 ; 5 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; B4 ; 207 ; 2 ; 1 ; 19 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; B5 ; 14 ; 1 ; 0 ; 14 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; B6 ; 10 ; 1 ; 0 ; 17 ; 3 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; B7 ; 11 ; 1 ; 0 ; 16 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; CI ; 27 ; 1 ; 0 ; 9 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
++------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins ;
++------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
++------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
+; CO ; 58 ; 4 ; 1 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; S0 ; 102 ; 4 ; 32 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; S1 ; 34 ; 1 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; S2 ; 118 ; 3 ; 34 ; 7 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; S3 ; 31 ; 1 ; 0 ; 8 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; S4 ; 37 ; 1 ; 0 ; 6 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; S5 ; 35 ; 1 ; 0 ; 7 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; S6 ; 12 ; 1 ; 0 ; 16 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+; S7 ; 6 ; 1 ; 0 ; 17 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
++------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
+
+
++------------------------------------------------------------+
+; I/O Bank Usage ;
++----------+------------------+---------------+--------------+
+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
++----------+------------------+---------------+--------------+
+; 1 ; 21 / 32 ( 66 % ) ; 3.3V ; -- ;
+; 2 ; 1 / 35 ( 3 % ) ; 3.3V ; -- ;
+; 3 ; 3 / 35 ( 9 % ) ; 3.3V ; -- ;
+; 4 ; 4 / 36 ( 11 % ) ; 3.3V ; -- ;
++----------+------------------+---------------+--------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins ;
++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; 1 ; 0 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
+; 2 ; 1 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
+; 3 ; 2 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 4 ; 3 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 5 ; 4 ; 1 ; A7 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 6 ; 5 ; 1 ; S7 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 8 ; 6 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 10 ; 7 ; 1 ; B6 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 11 ; 8 ; 1 ; B7 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 12 ; 9 ; 1 ; S6 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 13 ; 10 ; 1 ; A6 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 14 ; 18 ; 1 ; B5 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 15 ; 19 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
+; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
+; 18 ; 22 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
+; 19 ; 23 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
+; 20 ; 24 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ;
+; 21 ; 25 ; 1 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ;
+; 22 ; 26 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
+; 23 ; 27 ; 1 ; A2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 24 ; 28 ; 1 ; A0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 26 ; 29 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
+; 27 ; 30 ; 1 ; CI ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 28 ; 31 ; 1 ; B0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 30 ; 32 ; 1 ; B2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 31 ; 33 ; 1 ; S3 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 33 ; 35 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 34 ; 36 ; 1 ; S1 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 35 ; 37 ; 1 ; S5 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 37 ; 39 ; 1 ; S4 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 39 ; 43 ; 1 ; B3 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 40 ; 44 ; 1 ; A3 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 41 ; 45 ; 1 ; A4 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 42 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 43 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 44 ; 49 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 45 ; 50 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 46 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 47 ; 52 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 48 ; 53 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 49 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 50 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
+; 51 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 52 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
+; 53 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 54 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
+; 55 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 56 ; 54 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 57 ; 55 ; 4 ; A1 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 58 ; 56 ; 4 ; CO ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 59 ; 57 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 60 ; 58 ; 4 ; B1 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 61 ; 59 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 63 ; 60 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 64 ; 61 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 67 ; 69 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 68 ; 70 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 69 ; 71 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 70 ; 74 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 71 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 72 ; 75 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 74 ; 76 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 75 ; 77 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 76 ; 78 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 77 ; 79 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 80 ; 82 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 81 ; 83 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 82 ; 84 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 83 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 84 ; 85 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 85 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 86 ; 86 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 87 ; 87 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 88 ; 88 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 89 ; 89 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 90 ; 90 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 91 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 92 ; 91 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 94 ; 92 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 95 ; 93 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 96 ; 94 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 97 ; 95 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 98 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 99 ; 96 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 100 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 101 ; 97 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 102 ; 98 ; 4 ; S0 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 103 ; 99 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 104 ; 100 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 105 ; 101 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 106 ; 102 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 107 ; 105 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 108 ; 106 ; 3 ; ~LVDS54p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 109 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 110 ; 107 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 111 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 112 ; 108 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 113 ; 109 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 114 ; 110 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 115 ; 112 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 116 ; 113 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 117 ; 114 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 118 ; 117 ; 3 ; S2 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 119 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 120 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 121 ; 121 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
+; 122 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 123 ; 122 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
+; 124 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 125 ; 123 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
+; 126 ; 124 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
+; 127 ; 125 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 128 ; 126 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 129 ; 127 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; 130 ; 128 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; 131 ; 129 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; 132 ; 130 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; 133 ; 131 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 134 ; 132 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 135 ; 133 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 136 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 137 ; 134 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 138 ; 135 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 139 ; 136 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 141 ; 137 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 142 ; 138 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 143 ; 141 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 144 ; 142 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 145 ; 143 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 146 ; 149 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 147 ; 150 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 148 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 149 ; 151 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 150 ; 152 ; 3 ; A5 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; 151 ; 153 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 152 ; 154 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 153 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 154 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
+; 155 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 156 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
+; 157 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 158 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
+; 159 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 160 ; 155 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 161 ; 156 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 162 ; 157 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 163 ; 158 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 164 ; 159 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 165 ; 160 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 166 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 167 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 168 ; 161 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 169 ; 162 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 170 ; 163 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 171 ; 164 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 172 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 173 ; 165 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 174 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 175 ; 168 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 176 ; 169 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 177 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 178 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 179 ; 173 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 180 ; 174 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 181 ; 175 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 182 ; 176 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 183 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 184 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 185 ; 180 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 186 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 187 ; 181 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 188 ; 182 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 189 ; 183 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 190 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; 191 ; 184 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 192 ; 185 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 193 ; 186 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 194 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 195 ; 187 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 196 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 197 ; 191 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 198 ; 192 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 199 ; 195 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 200 ; 196 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 201 ; 197 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 202 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 203 ; 198 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 204 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 205 ; 199 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 206 ; 200 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 207 ; 201 ; 2 ; B4 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; 208 ; 202 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-------------------------------------------------------------------------------+
+; Output Pin Default Load For Reported TCO ;
++----------------------------------+-------+------------------------------------+
+; I/O Standard ; Load ; Termination Resistance ;
++----------------------------------+-------+------------------------------------+
+; 3.3-V LVTTL ; 0 pF ; Not Available ;
+; 3.3-V LVCMOS ; 0 pF ; Not Available ;
+; 2.5 V ; 0 pF ; Not Available ;
+; 1.8 V ; 0 pF ; Not Available ;
+; 1.5 V ; 0 pF ; Not Available ;
+; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ;
+; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ;
+; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
+; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;
+; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;
+; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;
+; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;
+; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ;
+; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ;
+; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ;
+; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ;
+; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ;
+; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ;
+; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ;
+; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ;
+; LVDS ; 0 pF ; 100 Ohm (Differential) ;
+; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ;
+; RSDS ; 0 pF ; 100 Ohm (Differential) ;
+; Simple RSDS ; 0 pF ; Not Available ;
+; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ;
++----------------------------------+-------+------------------------------------+
+Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
+; |adder ; 21 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 26 ; 0 ; 21 (0) ; 0 (0) ; 0 (0) ; |adder ; work ;
+; |7400:inst13| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |adder|7400:inst13 ; work ;
+; |7400:inst18| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder|7400:inst18 ; work ;
+; |7400:inst23| ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 0 (0) ; |adder|7400:inst23 ; work ;
+; |7400:inst28| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder|7400:inst28 ; work ;
+; |7400:inst33| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |adder|7400:inst33 ; work ;
+; |7400:inst38| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder|7400:inst38 ; work ;
+; |7400:inst3| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |adder|7400:inst3 ; work ;
+; |7400:inst8| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder|7400:inst8 ; work ;
+; |7486:inst10| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder|7486:inst10 ; work ;
+; |7486:inst15| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder|7486:inst15 ; work ;
+; |7486:inst20| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder|7486:inst20 ; work ;
+; |7486:inst25| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder|7486:inst25 ; work ;
+; |7486:inst30| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder|7486:inst30 ; work ;
+; |7486:inst35| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder|7486:inst35 ; work ;
+; |7486:inst40| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder|7486:inst40 ; work ;
+; |7486:inst5| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |adder|7486:inst5 ; work ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-------------------------------------------------------------------------------+
+; Delay Chain Summary ;
++------+----------+---------------+---------------+-----------------------+-----+
+; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
++------+----------+---------------+---------------+-----------------------+-----+
+; CO ; Output ; -- ; -- ; -- ; -- ;
+; S7 ; Output ; -- ; -- ; -- ; -- ;
+; S0 ; Output ; -- ; -- ; -- ; -- ;
+; S1 ; Output ; -- ; -- ; -- ; -- ;
+; S2 ; Output ; -- ; -- ; -- ; -- ;
+; S3 ; Output ; -- ; -- ; -- ; -- ;
+; S4 ; Output ; -- ; -- ; -- ; -- ;
+; S5 ; Output ; -- ; -- ; -- ; -- ;
+; S6 ; Output ; -- ; -- ; -- ; -- ;
+; A6 ; Input ; 6 ; 6 ; -- ; -- ;
+; A3 ; Input ; 6 ; 6 ; -- ; -- ;
+; B3 ; Input ; 6 ; 6 ; -- ; -- ;
+; A4 ; Input ; 6 ; 6 ; -- ; -- ;
+; A2 ; Input ; 0 ; 0 ; -- ; -- ;
+; A0 ; Input ; 0 ; 0 ; -- ; -- ;
+; CI ; Input ; 0 ; 0 ; -- ; -- ;
+; B0 ; Input ; 0 ; 0 ; -- ; -- ;
+; A1 ; Input ; 6 ; 6 ; -- ; -- ;
+; B1 ; Input ; 6 ; 6 ; -- ; -- ;
+; B2 ; Input ; 6 ; 6 ; -- ; -- ;
+; B4 ; Input ; 6 ; 6 ; -- ; -- ;
+; A5 ; Input ; 6 ; 6 ; -- ; -- ;
+; B5 ; Input ; 6 ; 6 ; -- ; -- ;
+; B6 ; Input ; 6 ; 6 ; -- ; -- ;
+; A7 ; Input ; 6 ; 6 ; -- ; -- ;
+; B7 ; Input ; 6 ; 6 ; -- ; -- ;
++------+----------+---------------+---------------+-----------------------+-----+
+
+
++-------------------------------------------------------+
+; Pad To Core Delay Chain Fanout ;
++-------------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++-------------------------+-------------------+---------+
+; A6 ; ; ;
+; - 7400:inst33|4~0 ; 1 ; 6 ;
+; - 7400:inst33|4~1 ; 1 ; 6 ;
+; - 7486:inst35|4~0 ; 1 ; 6 ;
+; A3 ; ; ;
+; - 7400:inst23|4~8 ; 0 ; 6 ;
+; - 7400:inst18|4~0 ; 0 ; 6 ;
+; - 7486:inst20|4 ; 0 ; 6 ;
+; B3 ; ; ;
+; - 7400:inst23|4~8 ; 1 ; 6 ;
+; - 7400:inst18|4~0 ; 1 ; 6 ;
+; - 7486:inst20|4 ; 1 ; 6 ;
+; A4 ; ; ;
+; - 7400:inst23|4~8 ; 0 ; 6 ;
+; - 7400:inst23|4~9 ; 0 ; 6 ;
+; - 7486:inst25|4~0 ; 0 ; 6 ;
+; A2 ; ; ;
+; A0 ; ; ;
+; CI ; ; ;
+; B0 ; ; ;
+; A1 ; ; ;
+; - 7400:inst8|4~0 ; 0 ; 6 ;
+; - 7486:inst10|4 ; 0 ; 6 ;
+; B1 ; ; ;
+; - 7400:inst8|4~0 ; 0 ; 6 ;
+; - 7486:inst10|4 ; 0 ; 6 ;
+; B2 ; ; ;
+; - 7400:inst13|4~1 ; 1 ; 6 ;
+; - 7486:inst15|4~0 ; 1 ; 6 ;
+; - 7400:inst23|4~10 ; 1 ; 6 ;
+; B4 ; ; ;
+; - 7400:inst23|4~9 ; 0 ; 6 ;
+; - 7486:inst25|4~0 ; 0 ; 6 ;
+; A5 ; ; ;
+; - 7400:inst28|4~0 ; 0 ; 6 ;
+; - 7486:inst30|4 ; 0 ; 6 ;
+; B5 ; ; ;
+; - 7400:inst28|4~0 ; 1 ; 6 ;
+; - 7486:inst30|4 ; 1 ; 6 ;
+; B6 ; ; ;
+; - 7400:inst33|4~1 ; 1 ; 6 ;
+; - 7486:inst35|4~0 ; 1 ; 6 ;
+; A7 ; ; ;
+; - 7400:inst38|4~0 ; 0 ; 6 ;
+; - 7486:inst40|4 ; 0 ; 6 ;
+; B7 ; ; ;
+; - 7400:inst38|4~0 ; 1 ; 6 ;
+; - 7486:inst40|4 ; 1 ; 6 ;
++-------------------------+-------------------+---------+
+
+
++---------------------------------+
+; Non-Global High Fan-Out Signals ;
++------------------+--------------+
+; Name ; Fan-Out ;
++------------------+--------------+
+; A2 ; 4 ;
+; 7400:inst8|4~0 ; 4 ;
+; B2 ; 3 ;
+; CI ; 3 ;
+; A0 ; 3 ;
+; A4 ; 3 ;
+; B3 ; 3 ;
+; A3 ; 3 ;
+; A6 ; 3 ;
+; 7400:inst28|4~0 ; 3 ;
+; B7 ; 2 ;
+; A7 ; 2 ;
+; B6 ; 2 ;
+; B5 ; 2 ;
+; A5 ; 2 ;
+; B4 ; 2 ;
+; B1 ; 2 ;
+; A1 ; 2 ;
+; B0 ; 2 ;
+; 7400:inst33|4~1 ; 2 ;
+; 7400:inst33|4~0 ; 2 ;
+; 7400:inst23|4~9 ; 2 ;
+; 7400:inst18|4~0 ; 2 ;
+; 7400:inst23|4~8 ; 2 ;
+; 7400:inst13|4~1 ; 2 ;
+; 7400:inst13|4~0 ; 2 ;
+; 7400:inst3|4~1 ; 2 ;
+; 7400:inst3|4~0 ; 2 ;
+; 7400:inst23|4~10 ; 1 ;
+; 7486:inst35|4~0 ; 1 ;
+; 7486:inst30|4 ; 1 ;
+; 7486:inst25|4~0 ; 1 ;
+; 7486:inst20|4 ; 1 ;
+; 7486:inst15|4~0 ; 1 ;
+; 7486:inst10|4 ; 1 ;
+; 7486:inst5|4~0 ; 1 ;
+; 7486:inst40|4 ; 1 ;
+; 7400:inst38|4~0 ; 1 ;
++------------------+--------------+
+
+
++----------------------------------------------------+
+; Interconnect Usage Summary ;
++----------------------------+-----------------------+
+; Interconnect Resource Type ; Usage ;
++----------------------------+-----------------------+
+; Block interconnects ; 29 / 26,052 ( < 1 % ) ;
+; C16 interconnects ; 2 / 1,156 ( < 1 % ) ;
+; C4 interconnects ; 31 / 17,952 ( < 1 % ) ;
+; Direct links ; 2 / 26,052 ( < 1 % ) ;
+; Global clocks ; 0 / 8 ( 0 % ) ;
+; Local interconnects ; 10 / 8,256 ( < 1 % ) ;
+; R24 interconnects ; 3 / 1,020 ( < 1 % ) ;
+; R4 interconnects ; 18 / 22,440 ( < 1 % ) ;
++----------------------------+-----------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Logic Elements ;
++---------------------------------------------+-----------------------------+
+; Number of Logic Elements (Average = 10.50) ; Number of LABs (Total = 2) ;
++---------------------------------------------+-----------------------------+
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 0 ;
+; 4 ; 0 ;
+; 5 ; 1 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 0 ;
+; 9 ; 0 ;
+; 10 ; 0 ;
+; 11 ; 0 ;
+; 12 ; 0 ;
+; 13 ; 0 ;
+; 14 ; 0 ;
+; 15 ; 0 ;
+; 16 ; 1 ;
++---------------------------------------------+-----------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Signals Sourced ;
++----------------------------------------------+-----------------------------+
+; Number of Signals Sourced (Average = 10.50) ; Number of LABs (Total = 2) ;
++----------------------------------------------+-----------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 0 ;
+; 4 ; 0 ;
+; 5 ; 1 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 0 ;
+; 9 ; 0 ;
+; 10 ; 0 ;
+; 11 ; 0 ;
+; 12 ; 0 ;
+; 13 ; 0 ;
+; 14 ; 0 ;
+; 15 ; 0 ;
+; 16 ; 1 ;
++----------------------------------------------+-----------------------------+
+
+
++-------------------------------------------------------------------------------+
+; LAB Signals Sourced Out ;
++-------------------------------------------------+-----------------------------+
+; Number of Signals Sourced Out (Average = 5.00) ; Number of LABs (Total = 2) ;
++-------------------------------------------------+-----------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 1 ;
+; 4 ; 0 ;
+; 5 ; 0 ;
+; 6 ; 0 ;
+; 7 ; 1 ;
++-------------------------------------------------+-----------------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Distinct Inputs ;
++---------------------------------------------+-----------------------------+
+; Number of Distinct Inputs (Average = 9.00) ; Number of LABs (Total = 2) ;
++---------------------------------------------+-----------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 0 ;
+; 4 ; 0 ;
+; 5 ; 1 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 0 ;
+; 9 ; 0 ;
+; 10 ; 0 ;
+; 11 ; 0 ;
+; 12 ; 0 ;
+; 13 ; 1 ;
++---------------------------------------------+-----------------------------+
+
+
++-------------------------------------------------------------------------+
+; Fitter Device Options ;
++----------------------------------------------+--------------------------+
+; Option ; Setting ;
++----------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR) ; Off ;
+; Enable device-wide reset (DEV_CLRn) ; Off ;
+; Enable device-wide output enable (DEV_OE) ; Off ;
+; Enable INIT_DONE output ; Off ;
+; Configuration scheme ; Active Serial ;
+; Error detection CRC ; Off ;
+; nCEO ; As output driving ground ;
+; ASDO,nCSO ; As input tri-stated ;
+; Reserve all unused pins ; As output driving ground ;
+; Base pin-out file on sameframe device ; Off ;
++----------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions ;
++---------------------------+--------+
+; Setting ; Value ;
++---------------------------+--------+
+; Nominal Core Voltage ; 1.20 V ;
+; Low Junction Temperature ; 0 °C ;
+; High Junction Temperature ; 85 °C ;
++---------------------------+--------+
+
+
++------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing ;
++-----------------+----------------------+-------------------+
+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
++-----------------+----------------------+-------------------+
+
+
++----------------------------+
+; Advanced Data - General ;
++--------------------+-------+
+; Name ; Value ;
++--------------------+-------+
+; Status Code ; 0 ;
+; Desired User Slack ; 0 ;
+; Fit Attempts ; 1 ;
++--------------------+-------+
+
+
++---------------------------------------------------------------------------------+
+; Advanced Data - Placement Preparation ;
++------------------------------------------------------------------+--------------+
+; Name ; Value ;
++------------------------------------------------------------------+--------------+
+; Auto Fit Point 1 - Fit Attempt 1 ; ff ;
+; Mid Wire Use - Fit Attempt 1 ; 0 ;
+; Mid Slack - Fit Attempt 1 ; 2147483639 ;
+; Internal Atom Count - Fit Attempt 1 ; 22 ;
+; LE/ALM Count - Fit Attempt 1 ; 22 ;
+; LAB Count - Fit Attempt 1 ; 3 ;
+; Outputs per Lab - Fit Attempt 1 ; 3.333 ;
+; Inputs per LAB - Fit Attempt 1 ; 6.000 ;
+; Global Inputs per LAB - Fit Attempt 1 ; 0.000 ;
+; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:3 ;
+; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:3 ;
+; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:3 ;
+; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:3 ;
+; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:3 ;
+; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:3 ;
+; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:3 ;
+; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:3 ;
+; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:3 ;
+; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:3 ;
+; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:3 ;
+; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:3 ;
+; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;4:1;12:1 ;
+; LEs in Chains - Fit Attempt 1 ; 0 ;
+; LEs in Long Chains - Fit Attempt 1 ; 0 ;
+; LABs with Chains - Fit Attempt 1 ; 0 ;
+; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;
+; Time - Fit Attempt 1 ; 0 ;
++------------------------------------------------------------------+--------------+
+
+
++-------------------------------------------------+
+; Advanced Data - Placement ;
++------------------------------------+------------+
+; Name ; Value ;
++------------------------------------+------------+
+; Auto Fit Point 2 - Fit Attempt 1 ; ff ;
+; Auto Fit Point 5 - Fit Attempt 1 ; ff ;
+; Mid Wire Use - Fit Attempt 1 ; 0 ;
+; Mid Slack - Fit Attempt 1 ; 2147483639 ;
+; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
+; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
+; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
+; Auto Fit Point 5 - Fit Attempt 1 ; ff ;
+; Mid Wire Use - Fit Attempt 1 ; 0 ;
+; Mid Slack - Fit Attempt 1 ; 2147483639 ;
+; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
+; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
+; Auto Fit Point 6 - Fit Attempt 1 ; ff ;
+; Late Wire Use - Fit Attempt 1 ; 0 ;
+; Late Slack - Fit Attempt 1 ; 2147483639 ;
+; Peak Regional Wire - Fit Attempt 1 ; 0.000 ;
+; Auto Fit Point 7 - Fit Attempt 1 ; ff ;
+; Time - Fit Attempt 1 ; 0 ;
++------------------------------------+------------+
+
+
++--------------------------------------------------+
+; Advanced Data - Routing ;
++------------------------------------+-------------+
+; Name ; Value ;
++------------------------------------+-------------+
+; Early Slack - Fit Attempt 1 ; 2147483639 ;
+; Early Wire Use - Fit Attempt 1 ; 0 ;
+; Peak Regional Wire - Fit Attempt 1 ; 0 ;
+; Mid Slack - Fit Attempt 1 ; 2147483639 ;
+; Late Slack - Fit Attempt 1 ; -2147483648 ;
+; Late Wire Use - Fit Attempt 1 ; 0 ;
+; Time - Fit Attempt 1 ; 0 ;
++------------------------------------+-------------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info: *******************************************************************
+Info: Running Quartus II Fitter
+ Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+ Info: Processing started: Mon Mar 07 08:49:23 2022
+Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off adder -c adder
+Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info: Selected device EP2C8Q208C8 for design "adder"
+Info: Low junction temperature is 0 degrees C
+Info: High junction temperature is 85 degrees C
+Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+ Info: Device EP2C5Q208C8 is compatible
+ Info: Device EP2C5Q208I8 is compatible
+ Info: Device EP2C8Q208I8 is compatible
+Info: Fitter converted 3 user pins into dedicated programming pins
+ Info: Pin ~ASDO~ is reserved at location 1
+ Info: Pin ~nCSO~ is reserved at location 2
+ Info: Pin ~LVDS54p/nCEO~ is reserved at location 108
+Warning: No exact pin location assignment(s) for 26 pins of 26 total pins
+ Info: Pin CO not assigned to an exact location on the device
+ Info: Pin S7 not assigned to an exact location on the device
+ Info: Pin S0 not assigned to an exact location on the device
+ Info: Pin S1 not assigned to an exact location on the device
+ Info: Pin S2 not assigned to an exact location on the device
+ Info: Pin S3 not assigned to an exact location on the device
+ Info: Pin S4 not assigned to an exact location on the device
+ Info: Pin S5 not assigned to an exact location on the device
+ Info: Pin S6 not assigned to an exact location on the device
+ Info: Pin A6 not assigned to an exact location on the device
+ Info: Pin A3 not assigned to an exact location on the device
+ Info: Pin B3 not assigned to an exact location on the device
+ Info: Pin A4 not assigned to an exact location on the device
+ Info: Pin A2 not assigned to an exact location on the device
+ Info: Pin A0 not assigned to an exact location on the device
+ Info: Pin CI not assigned to an exact location on the device
+ Info: Pin B0 not assigned to an exact location on the device
+ Info: Pin A1 not assigned to an exact location on the device
+ Info: Pin B1 not assigned to an exact location on the device
+ Info: Pin B2 not assigned to an exact location on the device
+ Info: Pin B4 not assigned to an exact location on the device
+ Info: Pin A5 not assigned to an exact location on the device
+ Info: Pin B5 not assigned to an exact location on the device
+ Info: Pin B6 not assigned to an exact location on the device
+ Info: Pin A7 not assigned to an exact location on the device
+ Info: Pin B7 not assigned to an exact location on the device
+Info: Fitter is using the Classic Timing Analyzer
+Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
+Info: Starting register packing
+Info: Finished register packing
+ Extra Info: No registers were packed into other blocks
+Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+ Info: Number of I/O pins in group: 26 (unused VREF, 3.3V VCCIO, 17 input, 9 output, 0 bidirectional)
+ Info: I/O standards used: 3.3-V LVTTL.
+Info: I/O bank details before I/O pin placement
+ Info: Statistics of I/O banks
+ Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available
+ Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available
+ Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available
+ Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available
+Info: Fitter preparation operations ending: elapsed time is 00:00:00
+Info: Fitter placement preparation operations beginning
+Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info: Fitter placement operations beginning
+Info: Fitter placement was successful
+Info: Fitter placement operations ending: elapsed time is 00:00:00
+Info: Fitter routing operations beginning
+Info: Average interconnect usage is 0% of the available device resources
+ Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9
+Info: Fitter routing operations ending: elapsed time is 00:00:00
+Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
+ Info: Optimizations that may affect the design's routability were skipped
+ Info: Optimizations that may affect the design's timing were skipped
+Info: Started post-fitting delay annotation
+Warning: Found 9 output pins without output pin load capacitance assignment
+ Info: Pin "CO" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "S7" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "S0" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "S1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "S2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "S3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "S4" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "S5" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "S6" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+Info: Delay annotation completed successfully
+Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
+Info: Generated suppressed messages file D:/projects/quartus/adder/adder.fit.smsg
+Info: Quartus II Fitter was successful. 0 errors, 3 warnings
+ Info: Peak virtual memory: 305 megabytes
+ Info: Processing ended: Mon Mar 07 08:49:24 2022
+ Info: Elapsed time: 00:00:01
+ Info: Total CPU time (on all processors): 00:00:01
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in D:/projects/quartus/adder/adder.fit.smsg.
+
+
diff --git a/adder/adder.fit.smsg b/adder/adder.fit.smsg
new file mode 100644
index 0000000..14764e7
--- /dev/null
+++ b/adder/adder.fit.smsg
@@ -0,0 +1,6 @@
+Extra Info: Performing register packing on registers with non-logic cell location assignments
+Extra Info: Completed register packing on registers with non-logic cell location assignments
+Extra Info: Started Fast Input/Output/OE register processing
+Extra Info: Finished Fast Input/Output/OE register processing
+Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/adder/adder.fit.summary b/adder/adder.fit.summary
new file mode 100644
index 0000000..25f7342
--- /dev/null
+++ b/adder/adder.fit.summary
@@ -0,0 +1,16 @@
+Fitter Status : Successful - Mon Mar 07 08:49:24 2022
+Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
+Revision Name : adder
+Top-level Entity Name : adder
+Family : Cyclone II
+Device : EP2C8Q208C8
+Timing Models : Final
+Total logic elements : 21 / 8,256 ( < 1 % )
+ Total combinational functions : 21 / 8,256 ( < 1 % )
+ Dedicated logic registers : 0 / 8,256 ( 0 % )
+Total registers : 0
+Total pins : 26 / 138 ( 19 % )
+Total virtual pins : 0
+Total memory bits : 0 / 165,888 ( 0 % )
+Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % )
+Total PLLs : 0 / 2 ( 0 % )
diff --git a/adder/adder.flow.rpt b/adder/adder.flow.rpt
new file mode 100644
index 0000000..169a9be
--- /dev/null
+++ b/adder/adder.flow.rpt
@@ -0,0 +1,120 @@
+Flow report for adder
+Mon Mar 07 08:49:27 2022
+Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Flow Summary
+ 3. Flow Settings
+ 4. Flow Non-Default Global Settings
+ 5. Flow Elapsed Time
+ 6. Flow OS Summary
+ 7. Flow Log
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Flow Summary ;
++------------------------------------+----------------------------------------------+
+; Flow Status ; Successful - Mon Mar 07 08:49:27 2022 ;
+; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
+; Revision Name ; adder ;
+; Top-level Entity Name ; adder ;
+; Family ; Cyclone II ;
+; Device ; EP2C8Q208C8 ;
+; Timing Models ; Final ;
+; Met timing requirements ; Yes ;
+; Total logic elements ; 21 / 8,256 ( < 1 % ) ;
+; Total combinational functions ; 21 / 8,256 ( < 1 % ) ;
+; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ;
+; Total registers ; 0 ;
+; Total pins ; 26 / 138 ( 19 % ) ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 0 / 165,888 ( 0 % ) ;
+; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
+; Total PLLs ; 0 / 2 ( 0 % ) ;
++------------------------------------+----------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings ;
++-------------------+---------------------+
+; Option ; Setting ;
++-------------------+---------------------+
+; Start date & time ; 03/07/2022 08:49:22 ;
+; Main task ; Compilation ;
+; Revision Name ; adder ;
++-------------------+---------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings ;
++------------------------------------+---------------------------------+---------------+-------------+----------------+
+; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
++------------------------------------+---------------------------------+---------------+-------------+----------------+
+; COMPILER_SIGNATURE_ID ; 220283517943889.164661416219416 ; -- ; -- ; -- ;
+; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
+; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
+; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
+; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
+; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
++------------------------------------+---------------------------------+---------------+-------------+----------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time ;
++-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 245 MB ; 00:00:00 ;
+; Fitter ; 00:00:01 ; 1.0 ; 305 MB ; 00:00:01 ;
+; Assembler ; 00:00:01 ; 1.0 ; 242 MB ; 00:00:00 ;
+; Classic Timing Analyzer ; 00:00:01 ; 1.0 ; 198 MB ; 00:00:00 ;
+; Total ; 00:00:04 ; -- ; -- ; 00:00:01 ;
++-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++------------------------------------------------------------------------------------------+
+; Flow OS Summary ;
++-------------------------+------------------+---------------+------------+----------------+
+; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
++-------------------------+------------------+---------------+------------+----------------+
+; Analysis & Synthesis ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
+; Fitter ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
+; Assembler ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
+; Classic Timing Analyzer ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
++-------------------------+------------------+---------------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off adder -c adder
+quartus_fit --read_settings_files=off --write_settings_files=off adder -c adder
+quartus_asm --read_settings_files=off --write_settings_files=off adder -c adder
+quartus_tan --read_settings_files=off --write_settings_files=off adder -c adder --timing_analysis_only
+
+
+
diff --git a/adder/adder.map.rpt b/adder/adder.map.rpt
new file mode 100644
index 0000000..fc3c724
--- /dev/null
+++ b/adder/adder.map.rpt
@@ -0,0 +1,240 @@
+Analysis & Synthesis report for adder
+Mon Mar 07 08:49:22 2022
+Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Analysis & Synthesis Summary
+ 3. Analysis & Synthesis Settings
+ 4. Analysis & Synthesis Source Files Read
+ 5. Analysis & Synthesis Resource Usage Summary
+ 6. Analysis & Synthesis Resource Utilization by Entity
+ 7. General Register Statistics
+ 8. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary ;
++------------------------------------+----------------------------------------------+
+; Analysis & Synthesis Status ; Successful - Mon Mar 07 08:49:22 2022 ;
+; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
+; Revision Name ; adder ;
+; Top-level Entity Name ; adder ;
+; Family ; Cyclone II ;
+; Total logic elements ; 21 ;
+; Total combinational functions ; 21 ;
+; Dedicated logic registers ; 0 ;
+; Total registers ; 0 ;
+; Total pins ; 26 ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 0 ;
+; Embedded Multiplier 9-bit elements ; 0 ;
+; Total PLLs ; 0 ;
++------------------------------------+----------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings ;
++--------------------------------------------------------------+--------------------+--------------------+
+; Option ; Setting ; Default Value ;
++--------------------------------------------------------------+--------------------+--------------------+
+; Device ; EP2C8Q208C8 ; ;
+; Top-level entity name ; adder ; adder ;
+; Family name ; Cyclone II ; Stratix II ;
+; Use Generated Physical Constraints File ; Off ; ;
+; Use smart compilation ; Off ; Off ;
+; Restructure Multiplexers ; Auto ; Auto ;
+; Create Debugging Nodes for IP Cores ; Off ; Off ;
+; Preserve fewer node names ; On ; On ;
+; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
+; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
+; VHDL Version ; VHDL93 ; VHDL93 ;
+; State Machine Processing ; Auto ; Auto ;
+; Safe State Machine ; Off ; Off ;
+; Extract Verilog State Machines ; On ; On ;
+; Extract VHDL State Machines ; On ; On ;
+; Ignore Verilog initial constructs ; Off ; Off ;
+; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
+; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
+; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
+; Parallel Synthesis ; Off ; Off ;
+; DSP Block Balancing ; Auto ; Auto ;
+; NOT Gate Push-Back ; On ; On ;
+; Power-Up Don't Care ; On ; On ;
+; Remove Redundant Logic Cells ; Off ; Off ;
+; Remove Duplicate Registers ; On ; On ;
+; Ignore CARRY Buffers ; Off ; Off ;
+; Ignore CASCADE Buffers ; Off ; Off ;
+; Ignore GLOBAL Buffers ; Off ; Off ;
+; Ignore ROW GLOBAL Buffers ; Off ; Off ;
+; Ignore LCELL Buffers ; Off ; Off ;
+; Ignore SOFT Buffers ; On ; On ;
+; Limit AHDL Integers to 32 Bits ; Off ; Off ;
+; Optimization Technique ; Balanced ; Balanced ;
+; Carry Chain Length ; 70 ; 70 ;
+; Auto Carry Chains ; On ; On ;
+; Auto Open-Drain Pins ; On ; On ;
+; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
+; Auto ROM Replacement ; On ; On ;
+; Auto RAM Replacement ; On ; On ;
+; Auto Shift Register Replacement ; Auto ; Auto ;
+; Auto Clock Enable Replacement ; On ; On ;
+; Strict RAM Replacement ; Off ; Off ;
+; Allow Synchronous Control Signals ; On ; On ;
+; Force Use of Synchronous Clear Signals ; Off ; Off ;
+; Auto RAM to Logic Cell Conversion ; Off ; Off ;
+; Auto Resource Sharing ; Off ; Off ;
+; Allow Any RAM Size For Recognition ; Off ; Off ;
+; Allow Any ROM Size For Recognition ; Off ; Off ;
+; Allow Any Shift Register Size For Recognition ; Off ; Off ;
+; Use LogicLock Constraints during Resource Balancing ; On ; On ;
+; Ignore translate_off and synthesis_off directives ; Off ; Off ;
+; Timing-Driven Synthesis ; Off ; Off ;
+; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
+; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
+; Synchronization Register Chain Length ; 2 ; 2 ;
+; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
+; HDL message level ; Level2 ; Level2 ;
+; Suppress Register Optimization Related Messages ; Off ; Off ;
+; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Clock MUX Protection ; On ; On ;
+; Auto Gated Clock Conversion ; Off ; Off ;
+; Block Design Naming ; Auto ; Auto ;
+; SDC constraint protection ; Off ; Off ;
+; Synthesis Effort ; Auto ; Auto ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
+; Analysis & Synthesis Message Level ; Medium ; Medium ;
++--------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++----------------------------------+-----------------+------------------------------------+------------------------------------------------------------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
++----------------------------------+-----------------+------------------------------------+------------------------------------------------------------+
+; adder.bdf ; yes ; User Block Diagram/Schematic File ; D:/projects/quartus/adder/adder.bdf ;
+; 7400.bdf ; yes ; Megafunction ; d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf ;
+; 7486.bdf ; yes ; Megafunction ; d:/altera/90sp2/quartus/libraries/others/maxplus2/7486.bdf ;
++----------------------------------+-----------------+------------------------------------+------------------------------------------------------------+
+
+
++--------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary ;
++---------------------------------------------+----------------+
+; Resource ; Usage ;
++---------------------------------------------+----------------+
+; Estimated Total logic elements ; 21 ;
+; ; ;
+; Total combinational functions ; 21 ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 9 ;
+; -- 3 input functions ; 9 ;
+; -- <=2 input functions ; 3 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 21 ;
+; -- arithmetic mode ; 0 ;
+; ; ;
+; Total registers ; 0 ;
+; -- Dedicated logic registers ; 0 ;
+; -- I/O registers ; 0 ;
+; ; ;
+; I/O pins ; 26 ;
+; Maximum fan-out node ; 7400:inst8|4~0 ;
+; Maximum fan-out ; 4 ;
+; Total fan-out ; 78 ;
+; Average fan-out ; 1.66 ;
++---------------------------------------------+----------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
+; |adder ; 21 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 26 ; 0 ; |adder ; work ;
+; |7400:inst13| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7400:inst13 ; work ;
+; |7400:inst18| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7400:inst18 ; work ;
+; |7400:inst23| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7400:inst23 ; work ;
+; |7400:inst28| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7400:inst28 ; work ;
+; |7400:inst33| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7400:inst33 ; work ;
+; |7400:inst38| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7400:inst38 ; work ;
+; |7400:inst3| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7400:inst3 ; work ;
+; |7400:inst8| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7400:inst8 ; work ;
+; |7486:inst10| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7486:inst10 ; work ;
+; |7486:inst15| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7486:inst15 ; work ;
+; |7486:inst20| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7486:inst20 ; work ;
+; |7486:inst25| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7486:inst25 ; work ;
+; |7486:inst30| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7486:inst30 ; work ;
+; |7486:inst35| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7486:inst35 ; work ;
+; |7486:inst40| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7486:inst40 ; work ;
+; |7486:inst5| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7486:inst5 ; work ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics ;
++----------------------------------------------+-------+
+; Statistic ; Value ;
++----------------------------------------------+-------+
+; Total registers ; 0 ;
+; Number of registers using Synchronous Clear ; 0 ;
+; Number of registers using Synchronous Load ; 0 ;
+; Number of registers using Asynchronous Clear ; 0 ;
+; Number of registers using Asynchronous Load ; 0 ;
+; Number of registers using Clock Enable ; 0 ;
+; Number of registers using Preset ; 0 ;
++----------------------------------------------+-------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II Analysis & Synthesis
+ Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+ Info: Processing started: Mon Mar 07 08:49:21 2022
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adder -c adder
+Info: Found 1 design units, including 1 entities, in source file adder.bdf
+ Info: Found entity 1: adder
+Info: Elaborating entity "adder" for the top level hierarchy
+Info: Elaborating entity "7400" for hierarchy "7400:inst38"
+Info: Elaborated megafunction instantiation "7400:inst38"
+Info: Elaborating entity "7486" for hierarchy "7486:inst"
+Info: Elaborated megafunction instantiation "7486:inst"
+Info: Implemented 47 device resources after synthesis - the final resource count might be different
+ Info: Implemented 17 input pins
+ Info: Implemented 9 output pins
+ Info: Implemented 21 logic cells
+Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
+ Info: Peak virtual memory: 248 megabytes
+ Info: Processing ended: Mon Mar 07 08:49:22 2022
+ Info: Elapsed time: 00:00:01
+ Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/adder/adder.map.summary b/adder/adder.map.summary
new file mode 100644
index 0000000..a7a1b32
--- /dev/null
+++ b/adder/adder.map.summary
@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Mon Mar 07 08:49:22 2022
+Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
+Revision Name : adder
+Top-level Entity Name : adder
+Family : Cyclone II
+Total logic elements : 21
+ Total combinational functions : 21
+ Dedicated logic registers : 0
+Total registers : 0
+Total pins : 26
+Total virtual pins : 0
+Total memory bits : 0
+Embedded Multiplier 9-bit elements : 0
+Total PLLs : 0
diff --git a/adder/adder.pin b/adder/adder.pin
new file mode 100644
index 0000000..b5147e1
--- /dev/null
+++ b/adder/adder.pin
@@ -0,0 +1,278 @@
+ -- Copyright (C) 1991-2009 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions
+ -- and other software and tools, and its AMPP partner logic
+ -- functions, and any output files from any of the foregoing
+ -- (including device programming or simulation files), and any
+ -- associated documentation or information are expressly subject
+ -- to the terms and conditions of the Altera Program License
+ -- Subscription Agreement, Altera MegaCore Function License
+ -- Agreement, or other applicable license agreement, including,
+ -- without limitation, that your use is for the sole purpose of
+ -- programming logic devices manufactured by Altera and sold by
+ -- Altera or its authorized distributors. Please refer to the
+ -- applicable agreement for further details.
+ --
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC : No Connect. This pin has no internal connection to the device.
+ -- DNU : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
+ -- VCCIO : Dedicated power pin, which MUST be connected to VCC
+ -- of its bank.
+ -- Bank 1: 3.3V
+ -- Bank 2: 3.3V
+ -- Bank 3: 3.3V
+ -- Bank 4: 3.3V
+ -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ -- It can also be used to report unused dedicated pins. The connection
+ -- on the board for unused dedicated pins depends on whether this will
+ -- be used in a future design. One example is device migration. When
+ -- using device migration, refer to the device pin-tables. If it is a
+ -- GND pin in the pin table or if it will not be used in a future design
+ -- for another purpose the it MUST be connected to GND. If it is an unused
+ -- dedicated pin, then it can be connected to a valid signal on the board
+ -- (low, high, or toggling) if that signal is required for a different
+ -- revision of the design.
+ -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
+ -- This pin should be connected to GND. It may also be connected to a
+ -- valid signal on the board (low, high, or toggling) if that signal
+ -- is required for a different revision of the design.
+ -- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17),
+ -- connect each pin marked GND* either individually through a 10k Ohm resistor
+ -- to GND or tie all pins together and connect through a single 10k Ohm resistor
+ -- to GND.
+ -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND
+ -- or leave it unconnected.
+ -- RESERVED : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+CHIP "adder" ASSIGNED TO AN: EP2C8Q208C8
+
+Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
+-------------------------------------------------------------------------------------------------------------
+~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVTTL : : 1 : N
+~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVTTL : : 1 : N
+GND* : 3 : : : : 1 :
+GND* : 4 : : : : 1 :
+A7 : 5 : input : 3.3-V LVTTL : : 1 : N
+S7 : 6 : output : 3.3-V LVTTL : : 1 : N
+VCCIO1 : 7 : power : : 3.3V : 1 :
+GND* : 8 : : : : 1 :
+GND : 9 : gnd : : : :
+B6 : 10 : input : 3.3-V LVTTL : : 1 : N
+B7 : 11 : input : 3.3-V LVTTL : : 1 : N
+S6 : 12 : output : 3.3-V LVTTL : : 1 : N
+A6 : 13 : input : 3.3-V LVTTL : : 1 : N
+B5 : 14 : input : 3.3-V LVTTL : : 1 : N
+GND* : 15 : : : : 1 :
+TDO : 16 : output : : : 1 :
+TMS : 17 : input : : : 1 :
+TCK : 18 : input : : : 1 :
+TDI : 19 : input : : : 1 :
+DATA0 : 20 : input : : : 1 :
+DCLK : 21 : : : : 1 :
+nCE : 22 : : : : 1 :
+A2 : 23 : input : 3.3-V LVTTL : : 1 : N
+A0 : 24 : input : 3.3-V LVTTL : : 1 : N
+GND : 25 : gnd : : : :
+nCONFIG : 26 : : : : 1 :
+CI : 27 : input : 3.3-V LVTTL : : 1 : N
+B0 : 28 : input : 3.3-V LVTTL : : 1 : N
+VCCIO1 : 29 : power : : 3.3V : 1 :
+B2 : 30 : input : 3.3-V LVTTL : : 1 : N
+S3 : 31 : output : 3.3-V LVTTL : : 1 : N
+VCCINT : 32 : power : : 1.2V : :
+GND* : 33 : : : : 1 :
+S1 : 34 : output : 3.3-V LVTTL : : 1 : N
+S5 : 35 : output : 3.3-V LVTTL : : 1 : N
+GND : 36 : gnd : : : :
+S4 : 37 : output : 3.3-V LVTTL : : 1 : N
+GND : 38 : gnd : : : :
+B3 : 39 : input : 3.3-V LVTTL : : 1 : N
+A3 : 40 : input : 3.3-V LVTTL : : 1 : N
+A4 : 41 : input : 3.3-V LVTTL : : 1 : N
+VCCIO1 : 42 : power : : 3.3V : 1 :
+GND* : 43 : : : : 1 :
+GND* : 44 : : : : 1 :
+GND* : 45 : : : : 1 :
+GND* : 46 : : : : 1 :
+GND* : 47 : : : : 1 :
+GND* : 48 : : : : 1 :
+GND : 49 : gnd : : : :
+GND_PLL1 : 50 : gnd : : : :
+VCCD_PLL1 : 51 : power : : 1.2V : :
+GND_PLL1 : 52 : gnd : : : :
+VCCA_PLL1 : 53 : power : : 1.2V : :
+GNDA_PLL1 : 54 : gnd : : : :
+GND : 55 : gnd : : : :
+GND* : 56 : : : : 4 :
+A1 : 57 : input : 3.3-V LVTTL : : 4 : N
+CO : 58 : output : 3.3-V LVTTL : : 4 : N
+GND* : 59 : : : : 4 :
+B1 : 60 : input : 3.3-V LVTTL : : 4 : N
+GND* : 61 : : : : 4 :
+VCCIO4 : 62 : power : : 3.3V : 4 :
+GND* : 63 : : : : 4 :
+GND* : 64 : : : : 4 :
+GND : 65 : gnd : : : :
+VCCINT : 66 : power : : 1.2V : :
+GND* : 67 : : : : 4 :
+GND* : 68 : : : : 4 :
+GND* : 69 : : : : 4 :
+GND* : 70 : : : : 4 :
+VCCIO4 : 71 : power : : 3.3V : 4 :
+GND* : 72 : : : : 4 :
+GND : 73 : gnd : : : :
+GND* : 74 : : : : 4 :
+GND* : 75 : : : : 4 :
+GND* : 76 : : : : 4 :
+GND* : 77 : : : : 4 :
+GND : 78 : gnd : : : :
+VCCINT : 79 : power : : 1.2V : :
+GND* : 80 : : : : 4 :
+GND* : 81 : : : : 4 :
+GND* : 82 : : : : 4 :
+VCCIO4 : 83 : power : : 3.3V : 4 :
+GND* : 84 : : : : 4 :
+GND : 85 : gnd : : : :
+GND* : 86 : : : : 4 :
+GND* : 87 : : : : 4 :
+GND* : 88 : : : : 4 :
+GND* : 89 : : : : 4 :
+GND* : 90 : : : : 4 :
+VCCIO4 : 91 : power : : 3.3V : 4 :
+GND* : 92 : : : : 4 :
+GND : 93 : gnd : : : :
+GND* : 94 : : : : 4 :
+GND* : 95 : : : : 4 :
+GND* : 96 : : : : 4 :
+GND* : 97 : : : : 4 :
+VCCIO4 : 98 : power : : 3.3V : 4 :
+GND* : 99 : : : : 4 :
+GND : 100 : gnd : : : :
+GND* : 101 : : : : 4 :
+S0 : 102 : output : 3.3-V LVTTL : : 4 : N
+GND* : 103 : : : : 4 :
+GND* : 104 : : : : 4 :
+GND* : 105 : : : : 3 :
+GND* : 106 : : : : 3 :
+GND* : 107 : : : : 3 :
+~LVDS54p/nCEO~ : 108 : output : 3.3-V LVTTL : : 3 : N
+VCCIO3 : 109 : power : : 3.3V : 3 :
+GND* : 110 : : : : 3 :
+GND : 111 : gnd : : : :
+GND* : 112 : : : : 3 :
+GND* : 113 : : : : 3 :
+GND* : 114 : : : : 3 :
+GND* : 115 : : : : 3 :
+GND* : 116 : : : : 3 :
+GND* : 117 : : : : 3 :
+S2 : 118 : output : 3.3-V LVTTL : : 3 : N
+GND : 119 : gnd : : : :
+VCCINT : 120 : power : : 1.2V : :
+nSTATUS : 121 : : : : 3 :
+VCCIO3 : 122 : power : : 3.3V : 3 :
+CONF_DONE : 123 : : : : 3 :
+GND : 124 : gnd : : : :
+MSEL1 : 125 : : : : 3 :
+MSEL0 : 126 : : : : 3 :
+GND* : 127 : : : : 3 :
+GND* : 128 : : : : 3 :
+GND+ : 129 : : : : 3 :
+GND+ : 130 : : : : 3 :
+GND+ : 131 : : : : 3 :
+GND+ : 132 : : : : 3 :
+GND* : 133 : : : : 3 :
+GND* : 134 : : : : 3 :
+GND* : 135 : : : : 3 :
+VCCIO3 : 136 : power : : 3.3V : 3 :
+GND* : 137 : : : : 3 :
+GND* : 138 : : : : 3 :
+GND* : 139 : : : : 3 :
+GND : 140 : gnd : : : :
+GND* : 141 : : : : 3 :
+GND* : 142 : : : : 3 :
+GND* : 143 : : : : 3 :
+GND* : 144 : : : : 3 :
+GND* : 145 : : : : 3 :
+GND* : 146 : : : : 3 :
+GND* : 147 : : : : 3 :
+VCCIO3 : 148 : power : : 3.3V : 3 :
+GND* : 149 : : : : 3 :
+A5 : 150 : input : 3.3-V LVTTL : : 3 : N
+GND* : 151 : : : : 3 :
+GND* : 152 : : : : 3 :
+GND : 153 : gnd : : : :
+GND_PLL2 : 154 : gnd : : : :
+VCCD_PLL2 : 155 : power : : 1.2V : :
+GND_PLL2 : 156 : gnd : : : :
+VCCA_PLL2 : 157 : power : : 1.2V : :
+GNDA_PLL2 : 158 : gnd : : : :
+GND : 159 : gnd : : : :
+GND* : 160 : : : : 2 :
+GND* : 161 : : : : 2 :
+GND* : 162 : : : : 2 :
+GND* : 163 : : : : 2 :
+GND* : 164 : : : : 2 :
+GND* : 165 : : : : 2 :
+VCCIO2 : 166 : power : : 3.3V : 2 :
+GND : 167 : gnd : : : :
+GND* : 168 : : : : 2 :
+GND* : 169 : : : : 2 :
+GND* : 170 : : : : 2 :
+GND* : 171 : : : : 2 :
+VCCIO2 : 172 : power : : 3.3V : 2 :
+GND* : 173 : : : : 2 :
+GND : 174 : gnd : : : :
+GND* : 175 : : : : 2 :
+GND* : 176 : : : : 2 :
+GND : 177 : gnd : : : :
+VCCINT : 178 : power : : 1.2V : :
+GND* : 179 : : : : 2 :
+GND* : 180 : : : : 2 :
+GND* : 181 : : : : 2 :
+GND* : 182 : : : : 2 :
+VCCIO2 : 183 : power : : 3.3V : 2 :
+GND : 184 : gnd : : : :
+GND* : 185 : : : : 2 :
+GND : 186 : gnd : : : :
+GND* : 187 : : : : 2 :
+GND* : 188 : : : : 2 :
+GND* : 189 : : : : 2 :
+VCCINT : 190 : power : : 1.2V : :
+GND* : 191 : : : : 2 :
+GND* : 192 : : : : 2 :
+GND* : 193 : : : : 2 :
+VCCIO2 : 194 : power : : 3.3V : 2 :
+GND* : 195 : : : : 2 :
+GND : 196 : gnd : : : :
+GND* : 197 : : : : 2 :
+GND* : 198 : : : : 2 :
+GND* : 199 : : : : 2 :
+GND* : 200 : : : : 2 :
+GND* : 201 : : : : 2 :
+VCCIO2 : 202 : power : : 3.3V : 2 :
+GND* : 203 : : : : 2 :
+GND : 204 : gnd : : : :
+GND* : 205 : : : : 2 :
+GND* : 206 : : : : 2 :
+B4 : 207 : input : 3.3-V LVTTL : : 2 : N
+GND* : 208 : : : : 2 :
diff --git a/adder/adder.pof b/adder/adder.pof
new file mode 100644
index 0000000..29b3267
Binary files /dev/null and b/adder/adder.pof differ
diff --git a/adder/adder.qpf b/adder/adder.qpf
new file mode 100644
index 0000000..73b53ec
--- /dev/null
+++ b/adder/adder.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+# Date created = 08:48:37 March 07, 2022
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "9.0"
+DATE = "08:48:37 March 07, 2022"
+
+# Revisions
+
+PROJECT_REVISION = "adder"
diff --git a/adder/adder.qsf b/adder/adder.qsf
new file mode 100644
index 0000000..c55ed9d
--- /dev/null
+++ b/adder/adder.qsf
@@ -0,0 +1,53 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+# Date created = 08:48:37 March 07, 2022
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# adder_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone II"
+set_global_assignment -name DEVICE EP2C8Q208C8
+set_global_assignment -name TOP_LEVEL_ENTITY adder
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:48:37 MARCH 07, 2022"
+set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2"
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name BDF_FILE adder.bdf
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
\ No newline at end of file
diff --git a/adder/adder.sof b/adder/adder.sof
new file mode 100644
index 0000000..6cc9658
Binary files /dev/null and b/adder/adder.sof differ
diff --git a/adder/adder.tan.rpt b/adder/adder.tan.rpt
new file mode 100644
index 0000000..f0d5cc3
--- /dev/null
+++ b/adder/adder.tan.rpt
@@ -0,0 +1,228 @@
+Classic Timing Analyzer report for adder
+Mon Mar 07 08:49:27 2022
+Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Timing Analyzer Summary
+ 3. Timing Analyzer Settings
+ 4. Parallel Compilation
+ 5. tpd
+ 6. Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------------------------------------------+
+; Timing Analyzer Summary ;
++------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
+; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
++------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
+; Worst-case tpd ; N/A ; None ; 19.344 ns ; A1 ; CO ; -- ; -- ; 0 ;
+; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
++------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
+
+
++--------------------------------------------------------------------------------------------------------------------+
+; Timing Analyzer Settings ;
++---------------------------------------------------------------------+--------------------+------+----+-------------+
+; Option ; Setting ; From ; To ; Entity Name ;
++---------------------------------------------------------------------+--------------------+------+----+-------------+
+; Device Name ; EP2C8Q208C8 ; ; ; ;
+; Timing Models ; Final ; ; ; ;
+; Default hold multicycle ; Same as Multicycle ; ; ; ;
+; Cut paths between unrelated clock domains ; On ; ; ; ;
+; Cut off read during write signal paths ; On ; ; ; ;
+; Cut off feedback from I/O pins ; On ; ; ; ;
+; Report Combined Fast/Slow Timing ; Off ; ; ; ;
+; Ignore Clock Settings ; Off ; ; ; ;
+; Analyze latches as synchronous elements ; On ; ; ; ;
+; Enable Recovery/Removal analysis ; Off ; ; ; ;
+; Enable Clock Latency ; Off ; ; ; ;
+; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+; Minimum Core Junction Temperature ; 0 ; ; ; ;
+; Maximum Core Junction Temperature ; 85 ; ; ; ;
+; Number of source nodes to report per destination node ; 10 ; ; ; ;
+; Number of destination nodes to report ; 10 ; ; ; ;
+; Number of paths to report ; 200 ; ; ; ;
+; Report Minimum Timing Checks ; Off ; ; ; ;
+; Use Fast Timing Models ; Off ; ; ; ;
+; Report IO Paths Separately ; Off ; ; ; ;
+; Perform Multicorner Analysis ; On ; ; ; ;
+; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
+; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
+; Output I/O Timing Endpoint ; Near End ; ; ; ;
++---------------------------------------------------------------------+--------------------+------+----+-------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 4 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.00 ;
+; Maximum used ; 1 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; 1 processor ; 100.0% ;
+; 2-4 processors ; 0.0% ;
++----------------------------+-------------+
+
+
++---------------------------------------------------------+
+; tpd ;
++-------+-------------------+-----------------+------+----+
+; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
++-------+-------------------+-----------------+------+----+
+; N/A ; None ; 19.344 ns ; A1 ; CO ;
+; N/A ; None ; 19.220 ns ; B1 ; CO ;
+; N/A ; None ; 18.199 ns ; B2 ; CO ;
+; N/A ; None ; 18.173 ns ; A1 ; S7 ;
+; N/A ; None ; 18.049 ns ; B1 ; S7 ;
+; N/A ; None ; 17.501 ns ; A3 ; CO ;
+; N/A ; None ; 17.423 ns ; B3 ; CO ;
+; N/A ; None ; 17.266 ns ; B4 ; CO ;
+; N/A ; None ; 17.091 ns ; A5 ; CO ;
+; N/A ; None ; 17.075 ns ; A4 ; CO ;
+; N/A ; None ; 17.028 ns ; B2 ; S7 ;
+; N/A ; None ; 17.000 ns ; A1 ; S6 ;
+; N/A ; None ; 16.876 ns ; B1 ; S6 ;
+; N/A ; None ; 16.330 ns ; A3 ; S7 ;
+; N/A ; None ; 16.252 ns ; B3 ; S7 ;
+; N/A ; None ; 16.095 ns ; B4 ; S7 ;
+; N/A ; None ; 15.940 ns ; B5 ; CO ;
+; N/A ; None ; 15.920 ns ; A5 ; S7 ;
+; N/A ; None ; 15.904 ns ; A4 ; S7 ;
+; N/A ; None ; 15.855 ns ; B2 ; S6 ;
+; N/A ; None ; 15.259 ns ; A0 ; CO ;
+; N/A ; None ; 15.157 ns ; A3 ; S6 ;
+; N/A ; None ; 15.079 ns ; B3 ; S6 ;
+; N/A ; None ; 15.027 ns ; B0 ; CO ;
+; N/A ; None ; 14.922 ns ; B4 ; S6 ;
+; N/A ; None ; 14.769 ns ; B5 ; S7 ;
+; N/A ; None ; 14.762 ns ; CI ; CO ;
+; N/A ; None ; 14.759 ns ; A1 ; S5 ;
+; N/A ; None ; 14.747 ns ; A5 ; S6 ;
+; N/A ; None ; 14.731 ns ; A4 ; S6 ;
+; N/A ; None ; 14.635 ns ; B1 ; S5 ;
+; N/A ; None ; 14.560 ns ; A1 ; S2 ;
+; N/A ; None ; 14.436 ns ; B1 ; S2 ;
+; N/A ; None ; 14.088 ns ; A0 ; S7 ;
+; N/A ; None ; 14.087 ns ; A1 ; S4 ;
+; N/A ; None ; 13.963 ns ; B1 ; S4 ;
+; N/A ; None ; 13.856 ns ; B0 ; S7 ;
+; N/A ; None ; 13.695 ns ; A6 ; CO ;
+; N/A ; None ; 13.614 ns ; B2 ; S5 ;
+; N/A ; None ; 13.596 ns ; B5 ; S6 ;
+; N/A ; None ; 13.591 ns ; CI ; S7 ;
+; N/A ; None ; 13.448 ns ; A2 ; CO ;
+; N/A ; None ; 13.408 ns ; B2 ; S2 ;
+; N/A ; None ; 13.338 ns ; A1 ; S3 ;
+; N/A ; None ; 13.214 ns ; B1 ; S3 ;
+; N/A ; None ; 12.955 ns ; B6 ; CO ;
+; N/A ; None ; 12.942 ns ; B2 ; S4 ;
+; N/A ; None ; 12.916 ns ; A3 ; S5 ;
+; N/A ; None ; 12.915 ns ; A0 ; S6 ;
+; N/A ; None ; 12.838 ns ; B3 ; S5 ;
+; N/A ; None ; 12.683 ns ; B0 ; S6 ;
+; N/A ; None ; 12.681 ns ; B4 ; S5 ;
+; N/A ; None ; 12.613 ns ; B7 ; CO ;
+; N/A ; None ; 12.524 ns ; A6 ; S7 ;
+; N/A ; None ; 12.501 ns ; A5 ; S5 ;
+; N/A ; None ; 12.488 ns ; A4 ; S5 ;
+; N/A ; None ; 12.418 ns ; CI ; S6 ;
+; N/A ; None ; 12.408 ns ; A7 ; CO ;
+; N/A ; None ; 12.277 ns ; A2 ; S7 ;
+; N/A ; None ; 12.244 ns ; A3 ; S4 ;
+; N/A ; None ; 12.193 ns ; B2 ; S3 ;
+; N/A ; None ; 12.166 ns ; B3 ; S4 ;
+; N/A ; None ; 12.007 ns ; B4 ; S4 ;
+; N/A ; None ; 11.786 ns ; B6 ; S7 ;
+; N/A ; None ; 11.579 ns ; A1 ; S1 ;
+; N/A ; None ; 11.527 ns ; A4 ; S4 ;
+; N/A ; None ; 11.489 ns ; A3 ; S3 ;
+; N/A ; None ; 11.458 ns ; B1 ; S1 ;
+; N/A ; None ; 11.443 ns ; B7 ; S7 ;
+; N/A ; None ; 11.415 ns ; B3 ; S3 ;
+; N/A ; None ; 11.378 ns ; A6 ; S6 ;
+; N/A ; None ; 11.337 ns ; B5 ; S5 ;
+; N/A ; None ; 11.243 ns ; A7 ; S7 ;
+; N/A ; None ; 11.104 ns ; A2 ; S6 ;
+; N/A ; None ; 11.091 ns ; B6 ; S6 ;
+; N/A ; None ; 10.674 ns ; A0 ; S5 ;
+; N/A ; None ; 10.475 ns ; A0 ; S2 ;
+; N/A ; None ; 10.442 ns ; B0 ; S5 ;
+; N/A ; None ; 10.294 ns ; A0 ; S0 ;
+; N/A ; None ; 10.243 ns ; B0 ; S2 ;
+; N/A ; None ; 10.177 ns ; CI ; S5 ;
+; N/A ; None ; 10.065 ns ; B0 ; S0 ;
+; N/A ; None ; 10.002 ns ; A0 ; S4 ;
+; N/A ; None ; 9.978 ns ; CI ; S2 ;
+; N/A ; None ; 9.800 ns ; CI ; S0 ;
+; N/A ; None ; 9.770 ns ; B0 ; S4 ;
+; N/A ; None ; 9.505 ns ; CI ; S4 ;
+; N/A ; None ; 9.253 ns ; A0 ; S3 ;
+; N/A ; None ; 9.021 ns ; B0 ; S3 ;
+; N/A ; None ; 8.863 ns ; A2 ; S5 ;
+; N/A ; None ; 8.756 ns ; CI ; S3 ;
+; N/A ; None ; 8.661 ns ; A2 ; S2 ;
+; N/A ; None ; 8.191 ns ; A2 ; S4 ;
+; N/A ; None ; 7.490 ns ; A0 ; S1 ;
+; N/A ; None ; 7.442 ns ; A2 ; S3 ;
+; N/A ; None ; 7.258 ns ; B0 ; S1 ;
+; N/A ; None ; 6.993 ns ; CI ; S1 ;
++-------+-------------------+-----------------+------+----+
+
+
++--------------------------+
+; Timing Analyzer Messages ;
++--------------------------+
+Info: *******************************************************************
+Info: Running Quartus II Classic Timing Analyzer
+ Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+ Info: Processing started: Mon Mar 07 08:49:26 2022
+Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off adder -c adder --timing_analysis_only
+Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info: Longest tpd from source pin "A1" to destination pin "CO" is 19.344 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_57; Fanout = 2; PIN Node = 'A1'
+ Info: 2: + IC(6.202 ns) + CELL(0.651 ns) = 7.847 ns; Loc. = LCCOMB_X1_Y7_N12; Fanout = 4; COMB Node = '7400:inst8|4~0'
+ Info: 3: + IC(0.391 ns) + CELL(0.206 ns) = 8.444 ns; Loc. = LCCOMB_X1_Y7_N8; Fanout = 2; COMB Node = '7400:inst13|4~1'
+ Info: 4: + IC(0.387 ns) + CELL(0.370 ns) = 9.201 ns; Loc. = LCCOMB_X1_Y7_N4; Fanout = 2; COMB Node = '7400:inst18|4~0'
+ Info: 5: + IC(0.387 ns) + CELL(0.370 ns) = 9.958 ns; Loc. = LCCOMB_X1_Y7_N6; Fanout = 2; COMB Node = '7400:inst23|4~9'
+ Info: 6: + IC(0.412 ns) + CELL(0.650 ns) = 11.020 ns; Loc. = LCCOMB_X1_Y7_N0; Fanout = 3; COMB Node = '7400:inst28|4~0'
+ Info: 7: + IC(1.736 ns) + CELL(0.206 ns) = 12.962 ns; Loc. = LCCOMB_X1_Y15_N24; Fanout = 2; COMB Node = '7400:inst33|4~0'
+ Info: 8: + IC(0.396 ns) + CELL(0.651 ns) = 14.009 ns; Loc. = LCCOMB_X1_Y15_N4; Fanout = 1; COMB Node = '7400:inst38|4~0'
+ Info: 9: + IC(2.039 ns) + CELL(3.296 ns) = 19.344 ns; Loc. = PIN_58; Fanout = 0; PIN Node = 'CO'
+ Info: Total cell delay = 7.394 ns ( 38.22 % )
+ Info: Total interconnect delay = 11.950 ns ( 61.78 % )
+Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
+ Info: Peak virtual memory: 212 megabytes
+ Info: Processing ended: Mon Mar 07 08:49:27 2022
+ Info: Elapsed time: 00:00:01
+ Info: Total CPU time (on all processors): 00:00:00
+
+
diff --git a/adder/adder.tan.summary b/adder/adder.tan.summary
new file mode 100644
index 0000000..b333f61
--- /dev/null
+++ b/adder/adder.tan.summary
@@ -0,0 +1,26 @@
+--------------------------------------------------------------------------------------
+Timing Analyzer Summary
+--------------------------------------------------------------------------------------
+
+Type : Worst-case tpd
+Slack : N/A
+Required Time : None
+Actual Time : 19.344 ns
+From : A1
+To : CO
+From Clock : --
+To Clock : --
+Failed Paths : 0
+
+Type : Total number of failed paths
+Slack :
+Required Time :
+Actual Time :
+From :
+To :
+From Clock :
+To Clock :
+Failed Paths : 0
+
+--------------------------------------------------------------------------------------
+
diff --git a/adder/db/adder.(0).cnf.cdb b/adder/db/adder.(0).cnf.cdb
new file mode 100644
index 0000000..319fe50
Binary files /dev/null and b/adder/db/adder.(0).cnf.cdb differ
diff --git a/adder/db/adder.(0).cnf.hdb b/adder/db/adder.(0).cnf.hdb
new file mode 100644
index 0000000..bbab6ce
Binary files /dev/null and b/adder/db/adder.(0).cnf.hdb differ
diff --git a/adder/db/adder.(1).cnf.cdb b/adder/db/adder.(1).cnf.cdb
new file mode 100644
index 0000000..30a8556
Binary files /dev/null and b/adder/db/adder.(1).cnf.cdb differ
diff --git a/adder/db/adder.(1).cnf.hdb b/adder/db/adder.(1).cnf.hdb
new file mode 100644
index 0000000..4795141
Binary files /dev/null and b/adder/db/adder.(1).cnf.hdb differ
diff --git a/adder/db/adder.(2).cnf.cdb b/adder/db/adder.(2).cnf.cdb
new file mode 100644
index 0000000..7623026
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diff --git a/adder/db/adder.(2).cnf.hdb b/adder/db/adder.(2).cnf.hdb
new file mode 100644
index 0000000..6ee954e
Binary files /dev/null and b/adder/db/adder.(2).cnf.hdb differ
diff --git a/adder/db/adder.asm.qmsg b/adder/db/adder.asm.qmsg
new file mode 100644
index 0000000..18457b0
--- /dev/null
+++ b/adder/db/adder.asm.qmsg
@@ -0,0 +1,7 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 08:49:25 2022 " "Info: Processing started: Mon Mar 07 08:49:25 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off adder -c adder " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off adder -c adder" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
+{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "242 " "Info: Peak virtual memory: 242 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 08:49:26 2022 " "Info: Processing ended: Mon Mar 07 08:49:26 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/adder/db/adder.asm_labs.ddb b/adder/db/adder.asm_labs.ddb
new file mode 100644
index 0000000..94fd686
Binary files /dev/null and b/adder/db/adder.asm_labs.ddb differ
diff --git a/adder/db/adder.cbx.xml b/adder/db/adder.cbx.xml
new file mode 100644
index 0000000..37b7951
--- /dev/null
+++ b/adder/db/adder.cbx.xml
@@ -0,0 +1,5 @@
+
+
+
+
+
diff --git a/adder/db/adder.cmp.bpm b/adder/db/adder.cmp.bpm
new file mode 100644
index 0000000..ecf6a23
Binary files /dev/null and b/adder/db/adder.cmp.bpm differ
diff --git a/adder/db/adder.cmp.cdb b/adder/db/adder.cmp.cdb
new file mode 100644
index 0000000..d2b0603
Binary files /dev/null and b/adder/db/adder.cmp.cdb differ
diff --git a/adder/db/adder.cmp.ecobp b/adder/db/adder.cmp.ecobp
new file mode 100644
index 0000000..e05efff
Binary files /dev/null and b/adder/db/adder.cmp.ecobp differ
diff --git a/adder/db/adder.cmp.hdb b/adder/db/adder.cmp.hdb
new file mode 100644
index 0000000..d44f112
Binary files /dev/null and b/adder/db/adder.cmp.hdb differ
diff --git a/adder/db/adder.cmp.kpt b/adder/db/adder.cmp.kpt
new file mode 100644
index 0000000..f435f2c
--- /dev/null
+++ b/adder/db/adder.cmp.kpt
@@ -0,0 +1,10 @@
+
+
+
+
+
+
+
+
+
+
diff --git a/adder/db/adder.cmp.logdb b/adder/db/adder.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/adder/db/adder.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/adder/db/adder.cmp.rdb b/adder/db/adder.cmp.rdb
new file mode 100644
index 0000000..85303cd
Binary files /dev/null and b/adder/db/adder.cmp.rdb differ
diff --git a/adder/db/adder.cmp.tdb b/adder/db/adder.cmp.tdb
new file mode 100644
index 0000000..94dc2c0
Binary files /dev/null and b/adder/db/adder.cmp.tdb differ
diff --git a/adder/db/adder.cmp0.ddb b/adder/db/adder.cmp0.ddb
new file mode 100644
index 0000000..70cb394
Binary files /dev/null and b/adder/db/adder.cmp0.ddb differ
diff --git a/adder/db/adder.cmp2.ddb b/adder/db/adder.cmp2.ddb
new file mode 100644
index 0000000..0a3ce14
Binary files /dev/null and b/adder/db/adder.cmp2.ddb differ
diff --git a/adder/db/adder.cmp_merge.kpt b/adder/db/adder.cmp_merge.kpt
new file mode 100644
index 0000000..ad1741f
--- /dev/null
+++ b/adder/db/adder.cmp_merge.kpt
@@ -0,0 +1,10 @@
+
+
+
+
+
+
+
+
+
+
diff --git a/adder/db/adder.db_info b/adder/db/adder.db_info
new file mode 100644
index 0000000..90ca49d
--- /dev/null
+++ b/adder/db/adder.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+Version_Index = 167832322
+Creation_Time = Mon Mar 07 08:48:37 2022
diff --git a/adder/db/adder.eco.cdb b/adder/db/adder.eco.cdb
new file mode 100644
index 0000000..6612017
Binary files /dev/null and b/adder/db/adder.eco.cdb differ
diff --git a/adder/db/adder.fit.qmsg b/adder/db/adder.fit.qmsg
new file mode 100644
index 0000000..36253d3
--- /dev/null
+++ b/adder/db/adder.fit.qmsg
@@ -0,0 +1,39 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 08:49:23 2022 " "Info: Processing started: Mon Mar 07 08:49:23 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off adder -c adder " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off adder -c adder" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "IMPP_MPP_USER_DEVICE" "adder EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"adder\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "26 26 " "Warning: No exact pin location assignment(s) for 26 pins of 26 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CO " "Info: Pin CO not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { CO } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 32 536 712 48 "CO" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CO } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S7 " "Info: Pin S7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S7 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 64 536 712 80 "S7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S0 " "Info: Pin S0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S0 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 2120 536 712 2136 "S0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S1 " "Info: Pin S1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S1 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 1840 536 712 1856 "S1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S2 " "Info: Pin S2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S2 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 1544 536 712 1560 "S2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S3 " "Info: Pin S3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S3 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 1248 536 712 1264 "S3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S4 " "Info: Pin S4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S4 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 952 536 712 968 "S4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S5 " "Info: Pin S5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S5 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 656 536 712 672 "S5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S6 " "Info: Pin S6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { S6 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 360 536 712 376 "S6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { S6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A6 " "Info: Pin A6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A6 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 344 80 248 360 "A6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A3 " "Info: Pin A3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A3 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 1232 80 248 1248 "A3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B3 " "Info: Pin B3 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B3 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 1248 80 248 1264 "B3" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B3 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A4 " "Info: Pin A4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A4 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 936 80 248 952 "A4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A2 " "Info: Pin A2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A2 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 1528 80 248 1544 "A2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A0 " "Info: Pin A0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A0 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 2104 80 248 2120 "A0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CI " "Info: Pin CI not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { CI } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 2136 80 248 2152 "CI" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CI } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B0 " "Info: Pin B0 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B0 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 2120 80 248 2136 "B0" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B0 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A1 " "Info: Pin A1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A1 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 1824 80 248 1840 "A1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B1 " "Info: Pin B1 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B1 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 1840 80 248 1856 "B1" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B1 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B2 " "Info: Pin B2 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B2 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 1544 80 248 1560 "B2" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B2 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B4 " "Info: Pin B4 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B4 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 952 80 248 968 "B4" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B4 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A5 " "Info: Pin A5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A5 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 640 80 248 656 "A5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B5 " "Info: Pin B5 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B5 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 656 80 248 672 "B5" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B5 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B6 " "Info: Pin B6 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B6 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 360 80 248 376 "B6" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B6 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "A7 " "Info: Pin A7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { A7 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 48 80 248 64 "A7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "B7 " "Info: Pin B7 not assigned to an exact location on the device" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { B7 } } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 64 80 248 80 "B7" "" } } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { B7 } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
+{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
+{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "26 unused 3.3V 17 9 0 " "Info: Number of I/O pins in group: 26 (unused VREF, 3.3V VCCIO, 17 input, 9 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 2 30 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 35 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 34 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 36 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X10_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
+{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "9 " "Warning: Found 9 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "CO 0 " "Info: Pin \"CO\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S7 0 " "Info: Pin \"S7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S0 0 " "Info: Pin \"S0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S1 0 " "Info: Pin \"S1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S2 0 " "Info: Pin \"S2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S3 0 " "Info: Pin \"S3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S4 0 " "Info: Pin \"S4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S5 0 " "Info: Pin \"S5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "S6 0 " "Info: Pin \"S6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/adder/adder.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/adder/adder.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "305 " "Info: Peak virtual memory: 305 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 08:49:24 2022 " "Info: Processing ended: Mon Mar 07 08:49:24 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/adder/db/adder.hier_info b/adder/db/adder.hier_info
new file mode 100644
index 0000000..4f08f30
--- /dev/null
+++ b/adder/db/adder.hier_info
@@ -0,0 +1,286 @@
+|adder
+CO <= 7400:inst38.1
+A7 => 7400:inst39.3
+A7 => 7486:inst36.2
+B7 => 7400:inst39.2
+B7 => 7486:inst36.3
+A6 => 7400:inst34.3
+A6 => 7486:inst31.2
+B6 => 7400:inst34.2
+B6 => 7486:inst31.3
+A5 => 7400:inst29.3
+A5 => 7486:inst26.2
+B5 => 7400:inst29.2
+B5 => 7486:inst26.3
+A4 => 7400:inst24.3
+A4 => 7486:inst21.2
+B4 => 7400:inst24.2
+B4 => 7486:inst21.3
+A3 => 7400:inst19.3
+A3 => 7486:inst16.2
+B3 => 7400:inst19.2
+B3 => 7486:inst16.3
+A2 => 7400:inst14.3
+A2 => 7486:inst11.2
+B2 => 7400:inst14.2
+B2 => 7486:inst11.3
+A1 => 7400:inst9.3
+A1 => 7486:inst6.2
+B1 => 7400:inst9.2
+B1 => 7486:inst6.3
+A0 => 7400:inst4.3
+A0 => 7486:inst.2
+B0 => 7400:inst4.2
+B0 => 7486:inst.3
+CI => 7400:inst2.3
+CI => 7486:inst5.3
+S7 <= 7486:inst40.1
+S0 <= 7486:inst5.1
+S1 <= 7486:inst10.1
+S2 <= 7486:inst15.1
+S3 <= 7486:inst20.1
+S4 <= 7486:inst25.1
+S5 <= 7486:inst30.1
+S6 <= 7486:inst35.1
+
+
+|adder|7400:inst38
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7400:inst39
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7400:inst37
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7400:inst33
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7400:inst34
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7400:inst32
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7400:inst28
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7400:inst29
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7400:inst27
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7400:inst23
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7400:inst24
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7400:inst22
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7400:inst18
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7400:inst19
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7400:inst17
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7400:inst13
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7400:inst14
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7400:inst12
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7400:inst8
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7400:inst9
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7400:inst7
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7400:inst3
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7400:inst4
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7400:inst2
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7486:inst
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7486:inst6
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7486:inst11
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7486:inst16
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7486:inst21
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7486:inst26
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7486:inst31
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7486:inst36
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7486:inst40
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7486:inst5
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7486:inst10
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7486:inst15
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7486:inst20
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7486:inst25
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7486:inst30
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
+|adder|7486:inst35
+1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
+2 => 4.IN0
+3 => 4.IN1
+
+
diff --git a/adder/db/adder.hif b/adder/db/adder.hif
new file mode 100644
index 0000000..288d8b0
--- /dev/null
+++ b/adder/db/adder.hif
@@ -0,0 +1,120 @@
+Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+11
+936
+OFF
+OFF
+OFF
+ON
+ON
+ON
+FV_OFF
+Level2
+0
+0
+VRSM_ON
+VHSM_ON
+0
+-- Start Library Paths --
+-- End Library Paths --
+-- Start VHDL Libraries --
+-- End VHDL Libraries --
+# entity
+adder
+# storage
+db|adder.(0).cnf
+db|adder.(0).cnf
+# case_insensitive
+# source_file
+adder.bdf
+24315e582bd755b4b98eeb6d569ea2
+26
+# internal_option {
+BLOCK_DESIGN_NAMING
+AUTO
+}
+# hierarchies {
+|
+}
+# macro_sequence
+
+# end
+# entity
+7400
+# storage
+db|adder.(1).cnf
+db|adder.(1).cnf
+# case_insensitive
+# source_file
+..|..|..|altera|90sp2|quartus|libraries|others|maxplus2|7400.bdf
+2bbb3be4da5c8a854468ca6be3dac
+26
+# internal_option {
+BLOCK_DESIGN_NAMING
+AUTO
+}
+# hierarchies {
+7400:inst38
+7400:inst39
+7400:inst37
+7400:inst33
+7400:inst34
+7400:inst32
+7400:inst28
+7400:inst29
+7400:inst27
+7400:inst23
+7400:inst24
+7400:inst22
+7400:inst18
+7400:inst19
+7400:inst17
+7400:inst13
+7400:inst14
+7400:inst12
+7400:inst8
+7400:inst9
+7400:inst7
+7400:inst3
+7400:inst4
+7400:inst2
+}
+# macro_sequence
+
+# end
+# entity
+7486
+# storage
+db|adder.(2).cnf
+db|adder.(2).cnf
+# case_insensitive
+# source_file
+..|..|..|altera|90sp2|quartus|libraries|others|maxplus2|7486.bdf
+66760dceba984b0dca8067dd21fcf
+26
+# internal_option {
+BLOCK_DESIGN_NAMING
+AUTO
+}
+# hierarchies {
+7486:inst
+7486:inst6
+7486:inst11
+7486:inst16
+7486:inst21
+7486:inst26
+7486:inst31
+7486:inst36
+7486:inst40
+7486:inst5
+7486:inst10
+7486:inst15
+7486:inst20
+7486:inst25
+7486:inst30
+7486:inst35
+}
+# macro_sequence
+
+# end
+# complete
+
\ No newline at end of file
diff --git a/adder/db/adder.lpc.html b/adder/db/adder.lpc.html
new file mode 100644
index 0000000..fd4875d
--- /dev/null
+++ b/adder/db/adder.lpc.html
@@ -0,0 +1,18 @@
+
+
+| Hierarchy |
+Input |
+Constant Input |
+Unused Input |
+Floating Input |
+Output |
+Constant Output |
+Unused Output |
+Floating Output |
+Bidir |
+Constant Bidir |
+Unused Bidir |
+Input only Bidir |
+Output only Bidir |
+
+
diff --git a/adder/db/adder.lpc.rdb b/adder/db/adder.lpc.rdb
new file mode 100644
index 0000000..8bd163a
Binary files /dev/null and b/adder/db/adder.lpc.rdb differ
diff --git a/adder/db/adder.lpc.txt b/adder/db/adder.lpc.txt
new file mode 100644
index 0000000..a463804
--- /dev/null
+++ b/adder/db/adder.lpc.txt
@@ -0,0 +1,5 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/adder/db/adder.map.bpm b/adder/db/adder.map.bpm
new file mode 100644
index 0000000..069b60f
Binary files /dev/null and b/adder/db/adder.map.bpm differ
diff --git a/adder/db/adder.map.cdb b/adder/db/adder.map.cdb
new file mode 100644
index 0000000..ca140c2
Binary files /dev/null and b/adder/db/adder.map.cdb differ
diff --git a/adder/db/adder.map.ecobp b/adder/db/adder.map.ecobp
new file mode 100644
index 0000000..e05efff
Binary files /dev/null and b/adder/db/adder.map.ecobp differ
diff --git a/adder/db/adder.map.hdb b/adder/db/adder.map.hdb
new file mode 100644
index 0000000..7d682f8
Binary files /dev/null and b/adder/db/adder.map.hdb differ
diff --git a/adder/db/adder.map.kpt b/adder/db/adder.map.kpt
new file mode 100644
index 0000000..ef3dc47
--- /dev/null
+++ b/adder/db/adder.map.kpt
@@ -0,0 +1,10 @@
+
+
+
+
+
+
+
+
+
+
diff --git a/adder/db/adder.map.logdb b/adder/db/adder.map.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/adder/db/adder.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/adder/db/adder.map.qmsg b/adder/db/adder.map.qmsg
new file mode 100644
index 0000000..fb8e01f
--- /dev/null
+++ b/adder/db/adder.map.qmsg
@@ -0,0 +1,11 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 08:49:21 2022 " "Info: Processing started: Mon Mar 07 08:49:21 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off adder -c adder " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adder -c adder" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adder.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 adder " "Info: Found entity 1: adder" { } { { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_TOP" "adder " "Info: Elaborating entity \"adder\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7400 7400:inst38 " "Info: Elaborating entity \"7400\" for hierarchy \"7400:inst38\"" { } { { "adder.bdf" "inst38" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 184 432 496 224 "inst38" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_ELABORATION_HEADER" "7400:inst38 " "Info: Elaborated megafunction instantiation \"7400:inst38\"" { } { { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 184 432 496 224 "inst38" "" } } } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7486 7486:inst " "Info: Elaborating entity \"7486\" for hierarchy \"7486:inst\"" { } { { "adder.bdf" "inst" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 2096 304 368 2136 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_ELABORATION_HEADER" "7486:inst " "Info: Elaborated megafunction instantiation \"7486:inst\"" { } { { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 2096 304 368 2136 "inst" "" } } } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "47 " "Info: Implemented 47 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "17 " "Info: Implemented 17 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Info: Implemented 9 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "21 " "Info: Implemented 21 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "248 " "Info: Peak virtual memory: 248 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 08:49:22 2022 " "Info: Processing ended: Mon Mar 07 08:49:22 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/adder/db/adder.map_bb.cdb b/adder/db/adder.map_bb.cdb
new file mode 100644
index 0000000..1bf698d
Binary files /dev/null and b/adder/db/adder.map_bb.cdb differ
diff --git a/adder/db/adder.map_bb.hdb b/adder/db/adder.map_bb.hdb
new file mode 100644
index 0000000..084cebc
Binary files /dev/null and b/adder/db/adder.map_bb.hdb differ
diff --git a/adder/db/adder.map_bb.logdb b/adder/db/adder.map_bb.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/adder/db/adder.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/adder/db/adder.pre_map.cdb b/adder/db/adder.pre_map.cdb
new file mode 100644
index 0000000..5723a1e
Binary files /dev/null and b/adder/db/adder.pre_map.cdb differ
diff --git a/adder/db/adder.pre_map.hdb b/adder/db/adder.pre_map.hdb
new file mode 100644
index 0000000..b6c7246
Binary files /dev/null and b/adder/db/adder.pre_map.hdb differ
diff --git a/adder/db/adder.rtlv.hdb b/adder/db/adder.rtlv.hdb
new file mode 100644
index 0000000..d307cc4
Binary files /dev/null and b/adder/db/adder.rtlv.hdb differ
diff --git a/adder/db/adder.rtlv_sg.cdb b/adder/db/adder.rtlv_sg.cdb
new file mode 100644
index 0000000..f1be617
Binary files /dev/null and b/adder/db/adder.rtlv_sg.cdb differ
diff --git a/adder/db/adder.rtlv_sg_swap.cdb b/adder/db/adder.rtlv_sg_swap.cdb
new file mode 100644
index 0000000..7e46c61
Binary files /dev/null and b/adder/db/adder.rtlv_sg_swap.cdb differ
diff --git a/adder/db/adder.sgdiff.cdb b/adder/db/adder.sgdiff.cdb
new file mode 100644
index 0000000..1f4da8b
Binary files /dev/null and b/adder/db/adder.sgdiff.cdb differ
diff --git a/adder/db/adder.sgdiff.hdb b/adder/db/adder.sgdiff.hdb
new file mode 100644
index 0000000..12b22f8
Binary files /dev/null and b/adder/db/adder.sgdiff.hdb differ
diff --git a/adder/db/adder.sld_design_entry.sci b/adder/db/adder.sld_design_entry.sci
new file mode 100644
index 0000000..904d003
Binary files /dev/null and b/adder/db/adder.sld_design_entry.sci differ
diff --git a/adder/db/adder.sld_design_entry_dsc.sci b/adder/db/adder.sld_design_entry_dsc.sci
new file mode 100644
index 0000000..2000bdc
Binary files /dev/null and b/adder/db/adder.sld_design_entry_dsc.sci differ
diff --git a/adder/db/adder.syn_hier_info b/adder/db/adder.syn_hier_info
new file mode 100644
index 0000000..e69de29
diff --git a/adder/db/adder.tan.qmsg b/adder/db/adder.tan.qmsg
new file mode 100644
index 0000000..3fcee9e
--- /dev/null
+++ b/adder/db/adder.tan.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 08:49:26 2022 " "Info: Processing started: Mon Mar 07 08:49:26 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off adder -c adder --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off adder -c adder --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TPD_RESULT" "A1 CO 19.344 ns Longest " "Info: Longest tpd from source pin \"A1\" to destination pin \"CO\" is 19.344 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns A1 1 PIN PIN_57 2 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_57; Fanout = 2; PIN Node = 'A1'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A1 } "NODE_NAME" } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 1824 80 248 1840 "A1" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.202 ns) + CELL(0.651 ns) 7.847 ns 7400:inst8\|4~0 2 COMB LCCOMB_X1_Y7_N12 4 " "Info: 2: + IC(6.202 ns) + CELL(0.651 ns) = 7.847 ns; Loc. = LCCOMB_X1_Y7_N12; Fanout = 4; COMB Node = '7400:inst8\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.853 ns" { A1 7400:inst8|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.391 ns) + CELL(0.206 ns) 8.444 ns 7400:inst13\|4~1 3 COMB LCCOMB_X1_Y7_N8 2 " "Info: 3: + IC(0.391 ns) + CELL(0.206 ns) = 8.444 ns; Loc. = LCCOMB_X1_Y7_N8; Fanout = 2; COMB Node = '7400:inst13\|4~1'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.597 ns" { 7400:inst8|4~0 7400:inst13|4~1 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.387 ns) + CELL(0.370 ns) 9.201 ns 7400:inst18\|4~0 4 COMB LCCOMB_X1_Y7_N4 2 " "Info: 4: + IC(0.387 ns) + CELL(0.370 ns) = 9.201 ns; Loc. = LCCOMB_X1_Y7_N4; Fanout = 2; COMB Node = '7400:inst18\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.757 ns" { 7400:inst13|4~1 7400:inst18|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.387 ns) + CELL(0.370 ns) 9.958 ns 7400:inst23\|4~9 5 COMB LCCOMB_X1_Y7_N6 2 " "Info: 5: + IC(0.387 ns) + CELL(0.370 ns) = 9.958 ns; Loc. = LCCOMB_X1_Y7_N6; Fanout = 2; COMB Node = '7400:inst23\|4~9'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.757 ns" { 7400:inst18|4~0 7400:inst23|4~9 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.412 ns) + CELL(0.650 ns) 11.020 ns 7400:inst28\|4~0 6 COMB LCCOMB_X1_Y7_N0 3 " "Info: 6: + IC(0.412 ns) + CELL(0.650 ns) = 11.020 ns; Loc. = LCCOMB_X1_Y7_N0; Fanout = 3; COMB Node = '7400:inst28\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.062 ns" { 7400:inst23|4~9 7400:inst28|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.736 ns) + CELL(0.206 ns) 12.962 ns 7400:inst33\|4~0 7 COMB LCCOMB_X1_Y15_N24 2 " "Info: 7: + IC(1.736 ns) + CELL(0.206 ns) = 12.962 ns; Loc. = LCCOMB_X1_Y15_N24; Fanout = 2; COMB Node = '7400:inst33\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.942 ns" { 7400:inst28|4~0 7400:inst33|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.396 ns) + CELL(0.651 ns) 14.009 ns 7400:inst38\|4~0 8 COMB LCCOMB_X1_Y15_N4 1 " "Info: 8: + IC(0.396 ns) + CELL(0.651 ns) = 14.009 ns; Loc. = LCCOMB_X1_Y15_N4; Fanout = 1; COMB Node = '7400:inst38\|4~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.047 ns" { 7400:inst33|4~0 7400:inst38|4~0 } "NODE_NAME" } } { "7400.bdf" "" { Schematic "d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf" { { 160 288 352 200 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.039 ns) + CELL(3.296 ns) 19.344 ns CO 9 PIN PIN_58 0 " "Info: 9: + IC(2.039 ns) + CELL(3.296 ns) = 19.344 ns; Loc. = PIN_58; Fanout = 0; PIN Node = 'CO'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.335 ns" { 7400:inst38|4~0 CO } "NODE_NAME" } } { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 32 536 712 48 "CO" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.394 ns ( 38.22 % ) " "Info: Total cell delay = 7.394 ns ( 38.22 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "11.950 ns ( 61.78 % ) " "Info: Total interconnect delay = 11.950 ns ( 61.78 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "19.344 ns" { A1 7400:inst8|4~0 7400:inst13|4~1 7400:inst18|4~0 7400:inst23|4~9 7400:inst28|4~0 7400:inst33|4~0 7400:inst38|4~0 CO } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "19.344 ns" { A1 {} A1~combout {} 7400:inst8|4~0 {} 7400:inst13|4~1 {} 7400:inst18|4~0 {} 7400:inst23|4~9 {} 7400:inst28|4~0 {} 7400:inst33|4~0 {} 7400:inst38|4~0 {} CO {} } { 0.000ns 0.000ns 6.202ns 0.391ns 0.387ns 0.387ns 0.412ns 1.736ns 0.396ns 2.039ns } { 0.000ns 0.994ns 0.651ns 0.206ns 0.370ns 0.370ns 0.650ns 0.206ns 0.651ns 3.296ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 08:49:27 2022 " "Info: Processing ended: Mon Mar 07 08:49:27 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/adder/db/adder.tis_db_list.ddb b/adder/db/adder.tis_db_list.ddb
new file mode 100644
index 0000000..2a9a6ed
Binary files /dev/null and b/adder/db/adder.tis_db_list.ddb differ
diff --git a/adder/incremental_db/README b/adder/incremental_db/README
new file mode 100644
index 0000000..9f62dcd
--- /dev/null
+++ b/adder/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used. To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/adder/incremental_db/compiled_partitions/adder.root_partition.cmp.atm b/adder/incremental_db/compiled_partitions/adder.root_partition.cmp.atm
new file mode 100644
index 0000000..0a8e135
Binary files /dev/null and b/adder/incremental_db/compiled_partitions/adder.root_partition.cmp.atm differ
diff --git a/adder/incremental_db/compiled_partitions/adder.root_partition.cmp.dfp b/adder/incremental_db/compiled_partitions/adder.root_partition.cmp.dfp
new file mode 100644
index 0000000..b1c67d6
Binary files /dev/null and b/adder/incremental_db/compiled_partitions/adder.root_partition.cmp.dfp differ
diff --git a/adder/incremental_db/compiled_partitions/adder.root_partition.cmp.hdbx b/adder/incremental_db/compiled_partitions/adder.root_partition.cmp.hdbx
new file mode 100644
index 0000000..27ca53b
Binary files /dev/null and b/adder/incremental_db/compiled_partitions/adder.root_partition.cmp.hdbx differ
diff --git a/adder/incremental_db/compiled_partitions/adder.root_partition.cmp.kpt b/adder/incremental_db/compiled_partitions/adder.root_partition.cmp.kpt
new file mode 100644
index 0000000..c1e72d7
--- /dev/null
+++ b/adder/incremental_db/compiled_partitions/adder.root_partition.cmp.kpt
@@ -0,0 +1,10 @@
+
+
+
+
+
+
+
+
+
+
diff --git a/adder/incremental_db/compiled_partitions/adder.root_partition.cmp.logdb b/adder/incremental_db/compiled_partitions/adder.root_partition.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/adder/incremental_db/compiled_partitions/adder.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/adder/incremental_db/compiled_partitions/adder.root_partition.cmp.rcf b/adder/incremental_db/compiled_partitions/adder.root_partition.cmp.rcf
new file mode 100644
index 0000000..6d6acb5
Binary files /dev/null and b/adder/incremental_db/compiled_partitions/adder.root_partition.cmp.rcf differ
diff --git a/adder/incremental_db/compiled_partitions/adder.root_partition.map.atm b/adder/incremental_db/compiled_partitions/adder.root_partition.map.atm
new file mode 100644
index 0000000..929c37e
Binary files /dev/null and b/adder/incremental_db/compiled_partitions/adder.root_partition.map.atm differ
diff --git a/adder/incremental_db/compiled_partitions/adder.root_partition.map.dpi b/adder/incremental_db/compiled_partitions/adder.root_partition.map.dpi
new file mode 100644
index 0000000..4322234
Binary files /dev/null and b/adder/incremental_db/compiled_partitions/adder.root_partition.map.dpi differ
diff --git a/adder/incremental_db/compiled_partitions/adder.root_partition.map.hdbx b/adder/incremental_db/compiled_partitions/adder.root_partition.map.hdbx
new file mode 100644
index 0000000..9fc6925
Binary files /dev/null and b/adder/incremental_db/compiled_partitions/adder.root_partition.map.hdbx differ
diff --git a/adder/incremental_db/compiled_partitions/adder.root_partition.map.kpt b/adder/incremental_db/compiled_partitions/adder.root_partition.map.kpt
new file mode 100644
index 0000000..f84dabe
--- /dev/null
+++ b/adder/incremental_db/compiled_partitions/adder.root_partition.map.kpt
@@ -0,0 +1,10 @@
+
+
+
+
+
+
+
+
+
+