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更新八位移位器

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wzhqwq 2022-03-07 11:36:11 +08:00
父節點 09aded1db8
當前提交 fc6e8bc9f1
共有 66 個檔案被更改，包括 912 行新增 和 1062 行删除
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7
shifter_8b/db/prev_cmp_shifter_8b.asm.qmsg Normal file
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@ -0,0 +1,7 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:15:56 2022 " "Info: Processing started: Mon Mar 07 11:15:56 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "221 " "Info: Peak virtual memory: 221 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:15:57 2022 " "Info: Processing ended: Mon Mar 07 11:15:57 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

39
shifter_8b/db/prev_cmp_shifter_8b.fit.qmsg Normal file
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檔案差異因為一行或多行太長而無法顯示

10
shifter_8b/db/prev_cmp_shifter_8b.map.qmsg
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@ -1,7 +1,9 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:36:47 2022 " "Info: Processing started: Mon Mar 07 10:36:47 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:15:53 2022 " "Info: Processing started: Mon Mar 07 11:15:53 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 shifter_8b " "Info: Found entity 1: shifter_8b" { } { { "shifter_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 shifter_8b " "Info: Found entity 1: shifter_8b" { } { { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "shifter_8b " "Info: Elaborating entity \"shifter_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Error" "ESGN_ENTITY_IS_MISSING" "inst triple_selector_8b " "Error: Node instance \"inst\" instantiates undefined entity \"triple_selector_8b\"" { } { { "shifter_8b.bdf" "inst" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { { 32 488 584 512 "inst" "" } } } } } 0 0 "Node instance \"%1!s!\" instantiates undefined entity \"%2!s!\"" 0 0 "" 0 -1}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "246 " "Error: Peak virtual memory: 246 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Error" "EQEXE_END_BANNER_TIME" "Mon Mar 07 10:36:47 2022 " "Error: Processing ended: Mon Mar 07 10:36:47 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Error: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Error: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "triple_selector_8b.bdf 1 1 " "Warning: Using design file triple_selector_8b.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 triple_selector_8b " "Info: Found entity 1: triple_selector_8b" { } { { "triple_selector_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/triple_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "triple_selector_8b triple_selector_8b:inst " "Info: Elaborating entity \"triple_selector_8b\" for hierarchy \"triple_selector_8b:inst\"" { } { { "shifter_8b.bdf" "inst" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 32 488 584 512 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "33 " "Info: Implemented 33 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Info: Implemented 11 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "14 " "Info: Implemented 14 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "229 " "Info: Peak virtual memory: 229 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:15:53 2022 " "Info: Processing ended: Mon Mar 07 11:15:53 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

64
shifter_8b/db/prev_cmp_shifter_8b.qmsg
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檔案差異因為一行或多行太長而無法顯示

6
shifter_8b/db/prev_cmp_shifter_8b.tan.qmsg Normal file
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@ -0,0 +1,6 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:15:57 2022 " "Info: Processing started: Mon Mar 07 11:15:57 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 6 " "Info: Parallel compilation is enabled and will use 4 of the 6 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TPD_RESULT" "A6 Y7 13.413 ns Longest " "Info: Longest tpd from source pin \"A6\" to destination pin \"Y7\" is 13.413 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns A6 1 PIN PIN_67 3 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 3; PIN Node = 'A6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A6 } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 120 40 208 136 "A6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.895 ns) + CELL(0.624 ns) 8.513 ns triple_selector_8b:inst\|inst31 2 COMB LCCOMB_X1_Y5_N10 1 " "Info: 2: + IC(6.895 ns) + CELL(0.624 ns) = 8.513 ns; Loc. = LCCOMB_X1_Y5_N10; Fanout = 1; COMB Node = 'triple_selector_8b:inst\|inst31'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.519 ns" { A6 triple_selector_8b:inst|inst31 } "NODE_NAME" } } { "triple_selector_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/triple_selector_8b.bdf" { { 64 488 552 112 "inst31" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.604 ns) + CELL(3.296 ns) 13.413 ns Y7 3 PIN PIN_60 0 " "Info: 3: + IC(1.604 ns) + CELL(3.296 ns) = 13.413 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'Y7'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.900 ns" { triple_selector_8b:inst|inst31 Y7 } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 56 688 864 72 "Y7" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.914 ns ( 36.64 % ) " "Info: Total cell delay = 4.914 ns ( 36.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.499 ns ( 63.36 % ) " "Info: Total interconnect delay = 8.499 ns ( 63.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "13.413 ns" { A6 triple_selector_8b:inst|inst31 Y7 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "13.413 ns" { A6 {} A6~combout {} triple_selector_8b:inst|inst31 {} Y7 {} } { 0.000ns 0.000ns 6.895ns 1.604ns } { 0.000ns 0.994ns 0.624ns 3.296ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "191 " "Info: Peak virtual memory: 191 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:15:58 2022 " "Info: Processing ended: Mon Mar 07 11:15:58 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

二進制
shifter_8b/db/shifter_8b.(0).cnf.cdb
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未顯示二進位檔案。

二進制
shifter_8b/db/shifter_8b.(0).cnf.hdb
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未顯示二進位檔案。

二進制
shifter_8b/db/shifter_8b.(1).cnf.cdb
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未顯示二進位檔案。

二進制
shifter_8b/db/shifter_8b.(1).cnf.hdb
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未顯示二進位檔案。

0
shifter_8b/db/shifter_8b.cmp.bpm → shifter_8b/db/shifter_8b.ace_cmp.bpm
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0
shifter_8b/db/shifter_8b.cmp.cdb → shifter_8b/db/shifter_8b.ace_cmp.cdb
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二進制
shifter_8b/db/shifter_8b.ace_cmp.ecobp Normal file
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未顯示二進位檔案。

0
shifter_8b/db/shifter_8b.cmp.hdb → shifter_8b/db/shifter_8b.ace_cmp.hdb
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4
shifter_8b/db/shifter_8b.asm.qmsg
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@ -1,7 +1,7 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:37:43 2022 " "Info: Processing started: Mon Mar 07 10:37:43 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:15:56 2022 " "Info: Processing started: Mon Mar 07 11:15:56 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 10:37:44 2022 " "Info: Processing ended: Mon Mar 07 10:37:44 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "221 " "Info: Peak virtual memory: 221 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:15:57 2022 " "Info: Processing ended: Mon Mar 07 11:15:57 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

二進制
shifter_8b/db/shifter_8b.asm_labs.ddb
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未顯示二進位檔案。

1
shifter_8b/db/shifter_8b.cmp.logdb
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@ -1 +0,0 @@
v1

二進制
shifter_8b/db/shifter_8b.cmp.rdb
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未顯示二進位檔案。

二進制
shifter_8b/db/shifter_8b.cmp.tdb
查看文件

未顯示二進位檔案。

二進制
shifter_8b/db/shifter_8b.cmp0.ddb
查看文件

未顯示二進位檔案。

二進制
shifter_8b/db/shifter_8b.cmp2.ddb
查看文件

未顯示二進位檔案。

二進制
shifter_8b/db/shifter_8b.eco.cdb
查看文件

未顯示二進位檔案。

20
shifter_8b/db/shifter_8b.fit.qmsg
查看文件

檔案差異因為一行或多行太長而無法顯示

7
shifter_8b/db/shifter_8b.hier_info
查看文件

@ -5,8 +5,6 @@ A6 => triple_selector_8b:inst.B6
A6 => triple_selector_8b:inst.C5
A7 => triple_selector_8b:inst.B7
A7 => triple_selector_8b:inst.C6
A7 => inst1.IN1
R => triple_selector_8b:inst.C7
A5 => triple_selector_8b:inst.A6
A5 => triple_selector_8b:inst.B5
A5 => triple_selector_8b:inst.C4
@ -24,13 +22,9 @@ A1 => triple_selector_8b:inst.B1
A1 => triple_selector_8b:inst.C0
A0 => triple_selector_8b:inst.A1
A0 => triple_selector_8b:inst.B0
A0 => inst2.IN0
L => triple_selector_8b:inst.A0
LM => triple_selector_8b:inst.AY
LM => inst1.IN0
DM => triple_selector_8b:inst.BY
RM => triple_selector_8b:inst.CY
RM => inst2.IN1
Y1 <= triple_selector_8b:inst.Y1
Y2 <= triple_selector_8b:inst.Y2
Y3 <= triple_selector_8b:inst.Y3
@ -38,7 +32,6 @@ Y4 <= triple_selector_8b:inst.Y4
Y5 <= triple_selector_8b:inst.Y5
Y6 <= triple_selector_8b:inst.Y6
Y7 <= triple_selector_8b:inst.Y7
OF <= inst3.DB_MAX_OUTPUT_PORT_TYPE
|shifter_8b|triple_selector_8b:inst

4
shifter_8b/db/shifter_8b.hif
查看文件

@ -26,7 +26,7 @@ db|shifter_8b.(0).cnf
# case_insensitive
# source_file
shifter_8b.bdf
323ebfa5afd7389abf1fcd4efaf6de
d6db26b9c5f411a913f215ffd97edb7d
26
# internal_option {
BLOCK_DESIGN_NAMING
@ -46,7 +46,7 @@ db|shifter_8b.(1).cnf
# case_insensitive
# source_file
triple_selector_8b.bdf
91b7a41e9ebd47591ce44c4793a9f2e
faf397453d6830c2ec2358bb378770
26
# internal_option {
BLOCK_DESIGN_NAMING

10
shifter_8b/db/shifter_8b.lpc.html
查看文件

@ -18,13 +18,13 @@
<TR valign="middle">
<TD ALIGN="LEFT">inst</TD>
<TD ALIGN="LEFT">27</TD>
<TD ALIGN="LEFT">2</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">2</TD>
<TD ALIGN="LEFT">8</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">2</TD>
<TD ALIGN="LEFT">2</TD>
<TD ALIGN="LEFT">2</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>

二進制
shifter_8b/db/shifter_8b.lpc.rdb
查看文件

未顯示二進位檔案。

2
shifter_8b/db/shifter_8b.lpc.txt
查看文件

@ -3,5 +3,5 @@
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; inst ; 27 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst ; 27 ; 2 ; 0 ; 2 ; 8 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

二進制
shifter_8b/db/shifter_8b.map.bpm
查看文件

未顯示二進位檔案。

二進制
shifter_8b/db/shifter_8b.map.cdb
查看文件

未顯示二進位檔案。

二進制
shifter_8b/db/shifter_8b.map.hdb
查看文件

未顯示二進位檔案。

12
shifter_8b/db/shifter_8b.map.qmsg
查看文件

@ -1,9 +1,9 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:37:40 2022 " "Info: Processing started: Mon Mar 07 10:37:40 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:17:07 2022 " "Info: Processing started: Mon Mar 07 11:17:07 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 shifter_8b " "Info: Found entity 1: shifter_8b" { } { { "shifter_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 shifter_8b " "Info: Found entity 1: shifter_8b" { } { { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "shifter_8b " "Info: Elaborating entity \"shifter_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "triple_selector_8b.bdf 1 1 " "Warning: Using design file triple_selector_8b.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 triple_selector_8b " "Info: Found entity 1: triple_selector_8b" { } { { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/triple_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "triple_selector_8b triple_selector_8b:inst " "Info: Elaborating entity \"triple_selector_8b\" for hierarchy \"triple_selector_8b:inst\"" { } { { "shifter_8b.bdf" "inst" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { { 32 488 584 512 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "39 " "Info: Implemented 39 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "13 " "Info: Implemented 13 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Info: Implemented 9 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "17 " "Info: Implemented 17 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "249 " "Info: Peak virtual memory: 249 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 10:37:40 2022 " "Info: Processing ended: Mon Mar 07 10:37:40 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "triple_selector_8b.bdf 1 1 " "Warning: Using design file triple_selector_8b.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 triple_selector_8b " "Info: Found entity 1: triple_selector_8b" { } { { "triple_selector_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/triple_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "triple_selector_8b triple_selector_8b:inst " "Info: Elaborating entity \"triple_selector_8b\" for hierarchy \"triple_selector_8b:inst\"" { } { { "shifter_8b.bdf" "inst" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 32 488 584 512 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "33 " "Info: Implemented 33 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Info: Implemented 11 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "14 " "Info: Implemented 14 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "229 " "Info: Peak virtual memory: 229 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:17:07 2022 " "Info: Processing ended: Mon Mar 07 11:17:07 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

二進制
shifter_8b/db/shifter_8b.map_bb.cdb
查看文件

未顯示二進位檔案。

二進制
shifter_8b/db/shifter_8b.map_bb.hdb
查看文件

未顯示二進位檔案。

二進制
shifter_8b/db/shifter_8b.pre_map.cdb
查看文件

未顯示二進位檔案。

二進制
shifter_8b/db/shifter_8b.pre_map.hdb
查看文件

未顯示二進位檔案。

二進制
shifter_8b/db/shifter_8b.rtlv.hdb
查看文件

未顯示二進位檔案。

二進制
shifter_8b/db/shifter_8b.rtlv_sg.cdb
查看文件

未顯示二進位檔案。

二進制
shifter_8b/db/shifter_8b.rtlv_sg_swap.cdb
查看文件

未顯示二進位檔案。

二進制
shifter_8b/db/shifter_8b.sgdiff.cdb
查看文件

未顯示二進位檔案。

二進制
shifter_8b/db/shifter_8b.sgdiff.hdb
查看文件

未顯示二進位檔案。

二進制
shifter_8b/db/shifter_8b.sld_design_entry.sci
查看文件

未顯示二進位檔案。

8
shifter_8b/db/shifter_8b.tan.qmsg
查看文件

@ -1,6 +1,6 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:37:44 2022 " "Info: Processing started: Mon Mar 07 10:37:44 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:15:57 2022 " "Info: Processing started: Mon Mar 07 11:15:57 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TPD_RESULT" "DM Y7 13.320 ns Longest " "Info: Longest tpd from source pin \"DM\" to destination pin \"Y7\" is 13.320 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.985 ns) 0.985 ns DM 1 PIN PIN_35 8 " "Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_35; Fanout = 8; PIN Node = 'DM'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DM } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { { 456 40 208 472 "DM" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.057 ns) + CELL(0.650 ns) 7.692 ns triple_selector_8b:inst\|inst31~0 2 COMB LCCOMB_X1_Y14_N20 1 " "Info: 2: + IC(6.057 ns) + CELL(0.650 ns) = 7.692 ns; Loc. = LCCOMB_X1_Y14_N20; Fanout = 1; COMB Node = 'triple_selector_8b:inst\|inst31~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.707 ns" { DM triple_selector_8b:inst|inst31~0 } "NODE_NAME" } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/triple_selector_8b.bdf" { { 64 488 552 112 "inst31" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.286 ns) + CELL(0.319 ns) 9.297 ns triple_selector_8b:inst\|inst31 3 COMB LCCOMB_X1_Y9_N16 1 " "Info: 3: + IC(1.286 ns) + CELL(0.319 ns) = 9.297 ns; Loc. = LCCOMB_X1_Y9_N16; Fanout = 1; COMB Node = 'triple_selector_8b:inst\|inst31'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.605 ns" { triple_selector_8b:inst|inst31~0 triple_selector_8b:inst|inst31 } "NODE_NAME" } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/triple_selector_8b.bdf" { { 64 488 552 112 "inst31" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.927 ns) + CELL(3.096 ns) 13.320 ns Y7 4 PIN PIN_33 0 " "Info: 4: + IC(0.927 ns) + CELL(3.096 ns) = 13.320 ns; Loc. = PIN_33; Fanout = 0; PIN Node = 'Y7'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.023 ns" { triple_selector_8b:inst|inst31 Y7 } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { { 56 688 864 72 "Y7" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.050 ns ( 37.91 % ) " "Info: Total cell delay = 5.050 ns ( 37.91 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.270 ns ( 62.09 % ) " "Info: Total interconnect delay = 8.270 ns ( 62.09 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "13.320 ns" { DM triple_selector_8b:inst|inst31~0 triple_selector_8b:inst|inst31 Y7 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "13.320 ns" { DM {} DM~combout {} triple_selector_8b:inst|inst31~0 {} triple_selector_8b:inst|inst31 {} Y7 {} } { 0.000ns 0.000ns 6.057ns 1.286ns 0.927ns } { 0.000ns 0.985ns 0.650ns 0.319ns 3.096ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 10:37:44 2022 " "Info: Processing ended: Mon Mar 07 10:37:44 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 6 " "Info: Parallel compilation is enabled and will use 4 of the 6 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TPD_RESULT" "A6 Y7 13.413 ns Longest " "Info: Longest tpd from source pin \"A6\" to destination pin \"Y7\" is 13.413 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns A6 1 PIN PIN_67 3 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 3; PIN Node = 'A6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A6 } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 120 40 208 136 "A6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.895 ns) + CELL(0.624 ns) 8.513 ns triple_selector_8b:inst\|inst31 2 COMB LCCOMB_X1_Y5_N10 1 " "Info: 2: + IC(6.895 ns) + CELL(0.624 ns) = 8.513 ns; Loc. = LCCOMB_X1_Y5_N10; Fanout = 1; COMB Node = 'triple_selector_8b:inst\|inst31'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.519 ns" { A6 triple_selector_8b:inst|inst31 } "NODE_NAME" } } { "triple_selector_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/triple_selector_8b.bdf" { { 64 488 552 112 "inst31" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.604 ns) + CELL(3.296 ns) 13.413 ns Y7 3 PIN PIN_60 0 " "Info: 3: + IC(1.604 ns) + CELL(3.296 ns) = 13.413 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'Y7'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.900 ns" { triple_selector_8b:inst|inst31 Y7 } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 56 688 864 72 "Y7" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.914 ns ( 36.64 % ) " "Info: Total cell delay = 4.914 ns ( 36.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.499 ns ( 63.36 % ) " "Info: Total interconnect delay = 8.499 ns ( 63.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "13.413 ns" { A6 triple_selector_8b:inst|inst31 Y7 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "13.413 ns" { A6 {} A6~combout {} triple_selector_8b:inst|inst31 {} Y7 {} } { 0.000ns 0.000ns 6.895ns 1.604ns } { 0.000ns 0.994ns 0.624ns 3.296ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "191 " "Info: Peak virtual memory: 191 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:15:58 2022 " "Info: Processing ended: Mon Mar 07 11:15:58 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

二進制
shifter_8b/db/shifter_8b.tis_db_list.ddb
查看文件

未顯示二進位檔案。

二進制
shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.atm
查看文件

未顯示二進位檔案。

二進制
shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.hdbx
查看文件

未顯示二進位檔案。

二進制
shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.rcf
查看文件

未顯示二進位檔案。

二進制
shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.atm
查看文件

未顯示二進位檔案。

二進制
shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.dpi
查看文件

未顯示二進位檔案。

二進制
shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.hdbx
查看文件

未顯示二進位檔案。

70
shifter_8b/shifter_8b.asm.rpt
查看文件

@ -1,5 +1,5 @@
Assembler report for shifter_8b
Mon Mar 07 10:37:44 2022
Mon Mar 07 11:15:57 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@ -10,8 +10,8 @@ Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: D:/projects/quartus/shifter_8b/shifter_8b.sof
6. Assembler Device Options: D:/projects/quartus/shifter_8b/shifter_8b.pof
5. Assembler Device Options: D:/dev/quartus/shifter_8b/shifter_8b.sof
6. Assembler Device Options: D:/dev/quartus/shifter_8b/shifter_8b.pof
7. Assembler Messages
@ -38,7 +38,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Mon Mar 07 10:37:44 2022 ;
; Assembler Status ; Successful - Mon Mar 07 11:15:57 2022 ;
; Revision Name ; shifter_8b ;
; Top-level Entity Name ; shifter_8b ;
; Family ; Cyclone II ;
@ -76,37 +76,37 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+----------+---------------+
+-----------------------------------------------+
; Assembler Generated Files ;
+-----------------------------------------------+
; File Name ;
+-----------------------------------------------+
; D:/projects/quartus/shifter_8b/shifter_8b.sof ;
; D:/projects/quartus/shifter_8b/shifter_8b.pof ;
+-----------------------------------------------+
+------------------------------------------+
; Assembler Generated Files ;
+------------------------------------------+
; File Name ;
+------------------------------------------+
; D:/dev/quartus/shifter_8b/shifter_8b.sof ;
; D:/dev/quartus/shifter_8b/shifter_8b.pof ;
+------------------------------------------+
+-------------------------------------------------------------------------+
; Assembler Device Options: D:/projects/quartus/shifter_8b/shifter_8b.sof ;
+----------------+--------------------------------------------------------+
; Option ; Setting ;
+----------------+--------------------------------------------------------+
; Device ; EP2C8Q208C8 ;
; JTAG usercode ; 0xFFFFFFFF ;
; Checksum ; 0x000C7CD6 ;
+----------------+--------------------------------------------------------+
+--------------------------------------------------------------------+
; Assembler Device Options: D:/dev/quartus/shifter_8b/shifter_8b.sof ;
+----------------+---------------------------------------------------+
; Option ; Setting ;
+----------------+---------------------------------------------------+
; Device ; EP2C8Q208C8 ;
; JTAG usercode ; 0xFFFFFFFF ;
; Checksum ; 0x000C73F5 ;
+----------------+---------------------------------------------------+
+-------------------------------------------------------------------------+
; Assembler Device Options: D:/projects/quartus/shifter_8b/shifter_8b.pof ;
+--------------------+----------------------------------------------------+
; Option ; Setting ;
+--------------------+----------------------------------------------------+
; Device ; EPCS4 ;
; JTAG usercode ; 0x00000000 ;
; Checksum ; 0x06F093B0 ;
; Compression Ratio ; 3 ;
+--------------------+----------------------------------------------------+
+--------------------------------------------------------------------+
; Assembler Device Options: D:/dev/quartus/shifter_8b/shifter_8b.pof ;
+--------------------+-----------------------------------------------+
; Option ; Setting ;
+--------------------+-----------------------------------------------+
; Device ; EPCS4 ;
; JTAG usercode ; 0x00000000 ;
; Checksum ; 0x06F0A9BA ;
; Compression Ratio ; 3 ;
+--------------------+-----------------------------------------------+
+--------------------+
@ -115,15 +115,15 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Mon Mar 07 10:37:43 2022
Info: Processing started: Mon Mar 07 11:15:56 2022
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b
Info: Writing out detailed assembly data for power analysis
Info: Assembler is generating device programming files
Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 241 megabytes
Info: Processing ended: Mon Mar 07 10:37:44 2022
Info: Peak virtual memory: 221 megabytes
Info: Processing ended: Mon Mar 07 11:15:57 2022
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Info: Total CPU time (on all processors): 00:00:00

650
shifter_8b/shifter_8b.bdf
查看文件

@ -24,23 +24,7 @@ applicable agreement for further details.
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@ -56,7 +40,7 @@ applicable agreement for further details.
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@ -72,7 +56,7 @@ applicable agreement for further details.
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@ -88,7 +72,7 @@ applicable agreement for further details.
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@ -104,39 +88,7 @@ applicable agreement for further details.
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@ -152,7 +104,7 @@ applicable agreement for further details.
(input)
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@ -166,9 +118,25 @@ applicable agreement for further details.
)
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@ -184,7 +152,7 @@ applicable agreement for further details.
(input)
(rect 40 168 208 184)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "A5" (rect 5 0 17 12)(font "Arial" ))
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(pt 168 8)
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@ -200,7 +168,7 @@ applicable agreement for further details.
(input)
(rect 40 120 208 136)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "A6" (rect 5 0 17 12)(font "Arial" ))
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@ -216,7 +184,7 @@ applicable agreement for further details.
(input)
(rect 40 72 208 88)
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@ -356,117 +324,21 @@ applicable agreement for further details.
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@ -755,327 +627,239 @@ applicable agreement for further details.
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(junction (pt 312 400))

259
shifter_8b/shifter_8b.bsf
查看文件

@ -20,164 +20,157 @@ applicable agreement for further details.
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2
shifter_8b/shifter_8b.done
查看文件

@ -1 +1 @@
Mon Mar 07 10:37:45 2022
Mon Mar 07 11:17:08 2022

12
shifter_8b/shifter_8b.dpf Normal file
查看文件

@ -0,0 +1,12 @@
<?xml version="1.0" encoding="UTF-8"?>
<pin_planner>
<pin_info>
</pin_info>
<buses>
</buses>
<group_file_association>
</group_file_association>
<pin_planner_file_specifies>
</pin_planner_file_specifies>
</pin_planner>

425
shifter_8b/shifter_8b.fit.rpt
查看文件

@ -1,5 +1,5 @@
Fitter report for shifter_8b
Mon Mar 07 10:37:42 2022
Mon Mar 07 11:15:55 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@ -63,18 +63,18 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+----------------------------------------------+
; Fitter Status ; Successful - Mon Mar 07 10:37:42 2022 ;
; Fitter Status ; Successful - Mon Mar 07 11:15:55 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; shifter_8b ;
; Top-level Entity Name ; shifter_8b ;
; Family ; Cyclone II ;
; Device ; EP2C8Q208C8 ;
; Timing Models ; Final ;
; Total logic elements ; 17 / 8,256 ( < 1 % ) ;
; Total combinational functions ; 17 / 8,256 ( < 1 % ) ;
; Total logic elements ; 14 / 8,256 ( < 1 % ) ;
; Total combinational functions ; 14 / 8,256 ( < 1 % ) ;
; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 22 / 138 ( 16 % ) ;
; Total pins ; 19 / 138 ( 14 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 165,888 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
@ -137,7 +137,7 @@ applicable agreement for further details.
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Number detected on machine ; 6 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
@ -146,6 +146,7 @@ applicable agreement for further details.
; Usage by Processor ; % Time Used ;
; 1 processor ; 100.0% ;
; 2-4 processors ; < 0.1% ;
; 5-6 processors ; 0.0% ;
+----------------------------+-------------+
@ -155,8 +156,8 @@ applicable agreement for further details.
; Type ; Value ;
+-------------------------+--------------------+
; Placement ; ;
; -- Requested ; 0 / 39 ( 0.00 % ) ;
; -- Achieved ; 0 / 39 ( 0.00 % ) ;
; -- Requested ; 0 / 33 ( 0.00 % ) ;
; -- Achieved ; 0 / 33 ( 0.00 % ) ;
; ; ;
; Routing (by Connection) ; ;
; -- Requested ; 0 / 0 ( 0.00 % ) ;
@ -178,14 +179,14 @@ applicable agreement for further details.
+----------------+---------+-------------------+-------------------------+-------------------+
; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
+----------------+---------+-------------------+-------------------------+-------------------+
; Top ; 39 ; 0 ; N/A ; Source File ;
; Top ; 33 ; 0 ; N/A ; Source File ;
+----------------+---------+-------------------+-------------------------+-------------------+
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin.
The pin-out file can be found in D:/dev/quartus/shifter_8b/shifter_8b.pin.
+--------------------------------------------------------------------+
@ -193,29 +194,29 @@ The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin.
+---------------------------------------------+----------------------+
; Resource ; Usage ;
+---------------------------------------------+----------------------+
; Total logic elements ; 17 / 8,256 ( < 1 % ) ;
; -- Combinational with no register ; 17 ;
; Total logic elements ; 14 / 8,256 ( < 1 % ) ;
; -- Combinational with no register ; 14 ;
; -- Register only ; 0 ;
; -- Combinational with a register ; 0 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 9 ;
; -- 3 input functions ; 8 ;
; -- 4 input functions ; 8 ;
; -- 3 input functions ; 6 ;
; -- <=2 input functions ; 0 ;
; -- Register only ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 17 ;
; -- normal mode ; 14 ;
; -- arithmetic mode ; 0 ;
; ; ;
; Total registers* ; 0 / 8,646 ( 0 % ) ;
; -- Dedicated logic registers ; 0 / 8,256 ( 0 % ) ;
; -- I/O registers ; 0 / 390 ( 0 % ) ;
; ; ;
; Total LABs: partially or completely used ; 2 / 516 ( < 1 % ) ;
; Total LABs: partially or completely used ; 1 / 516 ( < 1 % ) ;
; User inserted logic elements ; 0 ;
; Virtual pins ; 0 ;
; I/O pins ; 22 / 138 ( 16 % ) ;
; I/O pins ; 19 / 138 ( 14 % ) ;
; -- Clock pins ; 2 / 4 ( 50 % ) ;
; Global signals ; 0 ;
; M4Ks ; 0 / 36 ( 0 % ) ;
@ -229,12 +230,12 @@ The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin.
; CRC blocks ; 0 / 1 ( 0 % ) ;
; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ;
; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ;
; Maximum fan-out node ; LM ;
; Maximum fan-out ; 9 ;
; Highest non-global fan-out signal ; LM ;
; Highest non-global fan-out ; 9 ;
; Total fan-out ; 69 ;
; Average fan-out ; 1.64 ;
; Maximum fan-out node ; DM ;
; Maximum fan-out ; 8 ;
; Highest non-global fan-out signal ; DM ;
; Highest non-global fan-out ; 8 ;
; Total fan-out ; 58 ;
; Average fan-out ; 1.61 ;
+---------------------------------------------+----------------------+
* Register count does not include registers inside RAM blocks or DSP blocks.
@ -245,19 +246,17 @@ The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin.
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; A0 ; 60 ; 4 ; 3 ; 0 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; A1 ; 23 ; 1 ; 0 ; 9 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; A2 ; 27 ; 1 ; 0 ; 9 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; A3 ; 28 ; 1 ; 0 ; 9 ; 3 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; A4 ; 4 ; 1 ; 0 ; 18 ; 3 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; A5 ; 8 ; 1 ; 0 ; 17 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; A6 ; 14 ; 1 ; 0 ; 14 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; A7 ; 15 ; 1 ; 0 ; 14 ; 3 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; DM ; 35 ; 1 ; 0 ; 7 ; 1 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; L ; 199 ; 2 ; 3 ; 19 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; LM ; 57 ; 4 ; 1 ; 0 ; 2 ; 9 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; R ; 30 ; 1 ; 0 ; 8 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; RM ; 24 ; 1 ; 0 ; 9 ; 1 ; 9 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; A0 ; 15 ; 1 ; 0 ; 14 ; 3 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; A1 ; 63 ; 4 ; 3 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; A2 ; 23 ; 1 ; 0 ; 9 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; A3 ; 24 ; 1 ; 0 ; 9 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; A4 ; 27 ; 1 ; 0 ; 9 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; A5 ; 28 ; 1 ; 0 ; 9 ; 3 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; A6 ; 67 ; 4 ; 9 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; A7 ; 13 ; 1 ; 0 ; 16 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; DM ; 205 ; 2 ; 1 ; 19 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; LM ; 30 ; 1 ; 0 ; 8 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; RM ; 35 ; 1 ; 0 ; 7 ; 1 ; 7 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
@ -266,15 +265,14 @@ The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin.
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; OF ; 40 ; 1 ; 0 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Y0 ; 31 ; 1 ; 0 ; 8 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Y1 ; 34 ; 1 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Y2 ; 12 ; 1 ; 0 ; 16 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Y3 ; 11 ; 1 ; 0 ; 16 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Y4 ; 208 ; 2 ; 1 ; 19 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Y5 ; 13 ; 1 ; 0 ; 16 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Y6 ; 5 ; 1 ; 0 ; 17 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Y7 ; 33 ; 1 ; 0 ; 8 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Y0 ; 48 ; 1 ; 0 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Y1 ; 40 ; 1 ; 0 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Y2 ; 33 ; 1 ; 0 ; 8 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Y3 ; 208 ; 2 ; 1 ; 19 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Y4 ; 34 ; 1 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Y5 ; 31 ; 1 ; 0 ; 8 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Y6 ; 39 ; 1 ; 0 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Y7 ; 60 ; 4 ; 3 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
@ -283,10 +281,10 @@ The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin.
+----------+------------------+---------------+--------------+
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
+----------+------------------+---------------+--------------+
; 1 ; 20 / 32 ( 63 % ) ; 3.3V ; -- ;
; 1 ; 16 / 32 ( 50 % ) ; 3.3V ; -- ;
; 2 ; 2 / 35 ( 6 % ) ; 3.3V ; -- ;
; 3 ; 1 / 35 ( 3 % ) ; 3.3V ; -- ;
; 4 ; 2 / 36 ( 6 % ) ; 3.3V ; -- ;
; 4 ; 3 / 36 ( 8 % ) ; 3.3V ; -- ;
+----------+------------------+---------------+--------------+
@ -298,18 +296,18 @@ The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin.
; 1 ; 0 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
; 2 ; 1 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
; 3 ; 2 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 4 ; 3 ; 1 ; A4 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 5 ; 4 ; 1 ; Y6 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 4 ; 3 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 5 ; 4 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 6 ; 5 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 8 ; 6 ; 1 ; A5 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 8 ; 6 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 10 ; 7 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 11 ; 8 ; 1 ; Y3 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 12 ; 9 ; 1 ; Y2 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 13 ; 10 ; 1 ; Y5 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 14 ; 18 ; 1 ; A6 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 15 ; 19 ; 1 ; A7 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 11 ; 8 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 12 ; 9 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 13 ; 10 ; 1 ; A7 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 14 ; 18 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 15 ; 19 ; 1 ; A0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
; 18 ; 22 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
@ -317,24 +315,24 @@ The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin.
; 20 ; 24 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ;
; 21 ; 25 ; 1 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ;
; 22 ; 26 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
; 23 ; 27 ; 1 ; A1 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 24 ; 28 ; 1 ; RM ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 23 ; 27 ; 1 ; A2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 24 ; 28 ; 1 ; A3 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 26 ; 29 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
; 27 ; 30 ; 1 ; A2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 28 ; 31 ; 1 ; A3 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 27 ; 30 ; 1 ; A4 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 28 ; 31 ; 1 ; A5 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 30 ; 32 ; 1 ; R ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 31 ; 33 ; 1 ; Y0 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 30 ; 32 ; 1 ; LM ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 31 ; 33 ; 1 ; Y5 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 33 ; 35 ; 1 ; Y7 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 34 ; 36 ; 1 ; Y1 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 35 ; 37 ; 1 ; DM ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 33 ; 35 ; 1 ; Y2 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 34 ; 36 ; 1 ; Y4 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 35 ; 37 ; 1 ; RM ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 37 ; 39 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 39 ; 43 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 40 ; 44 ; 1 ; OF ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 39 ; 43 ; 1 ; Y6 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 40 ; 44 ; 1 ; Y1 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 41 ; 45 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 42 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 43 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
@ -342,7 +340,7 @@ The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin.
; 45 ; 50 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 46 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 47 ; 52 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 48 ; 53 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 48 ; 53 ; 1 ; Y0 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 49 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 50 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
; 51 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
@ -351,17 +349,17 @@ The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin.
; 54 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
; 55 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 56 ; 54 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 57 ; 55 ; 4 ; LM ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 57 ; 55 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 58 ; 56 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 59 ; 57 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 60 ; 58 ; 4 ; A0 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 60 ; 58 ; 4 ; Y7 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 61 ; 59 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 63 ; 60 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 63 ; 60 ; 4 ; A1 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 64 ; 61 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 67 ; 69 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 67 ; 69 ; 4 ; A6 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 68 ; 70 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 69 ; 71 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 70 ; 74 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
@ -493,16 +491,16 @@ The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin.
; 196 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 197 ; 191 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 198 ; 192 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 199 ; 195 ; 2 ; L ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 199 ; 195 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 200 ; 196 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 201 ; 197 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 202 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 203 ; 198 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 204 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 205 ; 199 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 205 ; 199 ; 2 ; DM ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 206 ; 200 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 207 ; 201 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 208 ; 202 ; 2 ; Y4 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 208 ; 202 ; 2 ; Y3 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
@ -549,8 +547,8 @@ Note: User assignments will override these defaults. The user specified values a
+------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ;
+------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------+--------------+
; |shifter_8b ; 17 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 22 ; 0 ; 17 (1) ; 0 (0) ; 0 (0) ; |shifter_8b ; work ;
; |triple_selector_8b:inst| ; 16 (16) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (16) ; 0 (0) ; 0 (0) ; |shifter_8b|triple_selector_8b:inst ; work ;
; |shifter_8b ; 14 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 ; 0 ; 14 (0) ; 0 (0) ; 0 (0) ; |shifter_8b ; work ;
; |triple_selector_8b:inst| ; 14 (14) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 (14) ; 0 (0) ; 0 (0) ; |shifter_8b|triple_selector_8b:inst ; work ;
+------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@ -568,20 +566,17 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Y5 ; Output ; -- ; -- ; -- ; -- ;
; Y6 ; Output ; -- ; -- ; -- ; -- ;
; Y7 ; Output ; -- ; -- ; -- ; -- ;
; OF ; Output ; -- ; -- ; -- ; -- ;
; A0 ; Input ; 6 ; 6 ; -- ; -- ;
; L ; Input ; 6 ; 6 ; -- ; -- ;
; LM ; Input ; 6 ; 6 ; -- ; -- ;
; A1 ; Input ; 6 ; 6 ; -- ; -- ;
; RM ; Input ; 6 ; 6 ; -- ; -- ;
; DM ; Input ; 6 ; 6 ; -- ; -- ;
; A1 ; Input ; 0 ; 0 ; -- ; -- ;
; RM ; Input ; 0 ; 0 ; -- ; -- ;
; LM ; Input ; 6 ; 6 ; -- ; -- ;
; A2 ; Input ; 0 ; 0 ; -- ; -- ;
; A3 ; Input ; 0 ; 0 ; -- ; -- ;
; A4 ; Input ; 6 ; 6 ; -- ; -- ;
; A5 ; Input ; 6 ; 6 ; -- ; -- ;
; A4 ; Input ; 0 ; 0 ; -- ; -- ;
; A5 ; Input ; 0 ; 0 ; -- ; -- ;
; A6 ; Input ; 6 ; 6 ; -- ; -- ;
; A7 ; Input ; 6 ; 6 ; -- ; -- ;
; R ; Input ; 6 ; 6 ; -- ; -- ;
+------+----------+---------------+---------------+-----------------------+-----+
@ -591,51 +586,47 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
+-----------------------------------------+-------------------+---------+
; A0 ; ; ;
; - triple_selector_8b:inst|inst3~0 ; 1 ; 6 ;
; - triple_selector_8b:inst|inst3 ; 1 ; 6 ;
; - triple_selector_8b:inst|inst7~0 ; 1 ; 6 ;
; - inst3 ; 1 ; 6 ;
; L ; ; ;
; - triple_selector_8b:inst|inst3~0 ; 0 ; 6 ;
; LM ; ; ;
; - triple_selector_8b:inst|inst3~0 ; 1 ; 6 ;
; - triple_selector_8b:inst|inst7~0 ; 1 ; 6 ;
; - triple_selector_8b:inst|inst11~0 ; 1 ; 6 ;
; - triple_selector_8b:inst|inst15~0 ; 1 ; 6 ;
; - triple_selector_8b:inst|inst19~0 ; 1 ; 6 ;
; - triple_selector_8b:inst|inst23~0 ; 1 ; 6 ;
; - triple_selector_8b:inst|inst27~0 ; 1 ; 6 ;
; - triple_selector_8b:inst|inst31~0 ; 1 ; 6 ;
; - inst3 ; 1 ; 6 ;
; DM ; ; ;
; - triple_selector_8b:inst|inst3~0 ; 1 ; 6 ;
; - triple_selector_8b:inst|inst7~0 ; 1 ; 6 ;
; - triple_selector_8b:inst|inst11~0 ; 1 ; 6 ;
; - triple_selector_8b:inst|inst15~0 ; 1 ; 6 ;
; - triple_selector_8b:inst|inst19~0 ; 1 ; 6 ;
; - triple_selector_8b:inst|inst23~0 ; 1 ; 6 ;
; - triple_selector_8b:inst|inst27~0 ; 1 ; 6 ;
; - triple_selector_8b:inst|inst31~0 ; 1 ; 6 ;
; A1 ; ; ;
; - triple_selector_8b:inst|inst3 ; 0 ; 6 ;
; - triple_selector_8b:inst|inst7~0 ; 0 ; 6 ;
; - triple_selector_8b:inst|inst11~0 ; 0 ; 6 ;
; RM ; ; ;
; - triple_selector_8b:inst|inst3 ; 1 ; 6 ;
; - triple_selector_8b:inst|inst7 ; 1 ; 6 ;
; - triple_selector_8b:inst|inst11 ; 1 ; 6 ;
; - triple_selector_8b:inst|inst15 ; 1 ; 6 ;
; - triple_selector_8b:inst|inst19 ; 1 ; 6 ;
; - triple_selector_8b:inst|inst23 ; 1 ; 6 ;
; - triple_selector_8b:inst|inst27 ; 1 ; 6 ;
; DM ; ; ;
; - triple_selector_8b:inst|inst3 ; 0 ; 6 ;
; - triple_selector_8b:inst|inst7~0 ; 0 ; 6 ;
; - triple_selector_8b:inst|inst11~0 ; 0 ; 6 ;
; - triple_selector_8b:inst|inst15~0 ; 0 ; 6 ;
; - triple_selector_8b:inst|inst19~0 ; 0 ; 6 ;
; - triple_selector_8b:inst|inst23~0 ; 0 ; 6 ;
; - triple_selector_8b:inst|inst27~0 ; 0 ; 6 ;
; - triple_selector_8b:inst|inst31 ; 0 ; 6 ;
; LM ; ; ;
; - triple_selector_8b:inst|inst7~0 ; 0 ; 6 ;
; - triple_selector_8b:inst|inst11~0 ; 0 ; 6 ;
; - triple_selector_8b:inst|inst15~0 ; 0 ; 6 ;
; - triple_selector_8b:inst|inst19~0 ; 0 ; 6 ;
; - triple_selector_8b:inst|inst23~0 ; 0 ; 6 ;
; - triple_selector_8b:inst|inst27~0 ; 0 ; 6 ;
; - triple_selector_8b:inst|inst31 ; 0 ; 6 ;
; A2 ; ; ;
; A3 ; ; ;
; A4 ; ; ;
; - triple_selector_8b:inst|inst15 ; 1 ; 6 ;
; - triple_selector_8b:inst|inst19~0 ; 1 ; 6 ;
; - triple_selector_8b:inst|inst23~0 ; 1 ; 6 ;
; A5 ; ; ;
; - triple_selector_8b:inst|inst19 ; 0 ; 6 ;
; - triple_selector_8b:inst|inst23~0 ; 0 ; 6 ;
; - triple_selector_8b:inst|inst27~0 ; 0 ; 6 ;
; A6 ; ; ;
; - triple_selector_8b:inst|inst23 ; 1 ; 6 ;
; - triple_selector_8b:inst|inst23 ; 0 ; 6 ;
; - triple_selector_8b:inst|inst27~0 ; 0 ; 6 ;
; - triple_selector_8b:inst|inst31~0 ; 0 ; 6 ;
; - triple_selector_8b:inst|inst31 ; 0 ; 6 ;
; A7 ; ; ;
; - triple_selector_8b:inst|inst27 ; 1 ; 6 ;
; - triple_selector_8b:inst|inst31~0 ; 1 ; 6 ;
; - inst3 ; 1 ; 6 ;
; R ; ; ;
; - triple_selector_8b:inst|inst27 ; 0 ; 6 ;
; - triple_selector_8b:inst|inst31 ; 0 ; 6 ;
+-----------------------------------------+-------------------+---------+
@ -645,22 +636,18 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------+---------+
; Name ; Fan-Out ;
+----------------------------------+---------+
; RM ; 9 ;
; LM ; 9 ;
; DM ; 8 ;
; A7 ; 3 ;
; LM ; 7 ;
; RM ; 7 ;
; A6 ; 3 ;
; A5 ; 3 ;
; A4 ; 3 ;
; A3 ; 3 ;
; A2 ; 3 ;
; A1 ; 3 ;
; A0 ; 3 ;
; R ; 1 ;
; L ; 1 ;
; inst3 ; 1 ;
; A7 ; 2 ;
; A0 ; 2 ;
; triple_selector_8b:inst|inst31 ; 1 ;
; triple_selector_8b:inst|inst31~0 ; 1 ;
; triple_selector_8b:inst|inst27 ; 1 ;
; triple_selector_8b:inst|inst27~0 ; 1 ;
; triple_selector_8b:inst|inst23 ; 1 ;
@ -674,7 +661,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; triple_selector_8b:inst|inst7 ; 1 ;
; triple_selector_8b:inst|inst7~0 ; 1 ;
; triple_selector_8b:inst|inst3 ; 1 ;
; triple_selector_8b:inst|inst3~0 ; 1 ;
+----------------------------------+---------+
@ -683,48 +669,23 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------+-----------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+-----------------------+
; Block interconnects ; 26 / 26,052 ( < 1 % ) ;
; Block interconnects ; 19 / 26,052 ( < 1 % ) ;
; C16 interconnects ; 2 / 1,156 ( < 1 % ) ;
; C4 interconnects ; 30 / 17,952 ( < 1 % ) ;
; Direct links ; 0 / 26,052 ( 0 % ) ;
; C4 interconnects ; 24 / 17,952 ( < 1 % ) ;
; Direct links ; 2 / 26,052 ( < 1 % ) ;
; Global clocks ; 0 / 8 ( 0 % ) ;
; Local interconnects ; 7 / 8,256 ( < 1 % ) ;
; Local interconnects ; 6 / 8,256 ( < 1 % ) ;
; R24 interconnects ; 0 / 1,020 ( 0 % ) ;
; R4 interconnects ; 6 / 22,440 ( < 1 % ) ;
; R4 interconnects ; 4 / 22,440 ( < 1 % ) ;
+----------------------------+-----------------------+
+--------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements (Average = 8.50) ; Number of LABs (Total = 2) ;
+--------------------------------------------+-----------------------------+
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 1 ;
+--------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Signals Sourced ;
; LAB Logic Elements ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced (Average = 8.50) ; Number of LABs (Total = 2) ;
; Number of Logic Elements (Average = 14.00) ; Number of LABs (Total = 1) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
@ -737,49 +698,70 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 14 ; 1 ;
; 15 ; 0 ;
; 16 ; 1 ;
; 16 ; 0 ;
+---------------------------------------------+-----------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+----------------------------------------------+-----------------------------+
; Number of Signals Sourced (Average = 14.00) ; Number of LABs (Total = 1) ;
+----------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 1 ;
+----------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out (Average = 5.00) ; Number of LABs (Total = 2) ;
; Number of Signals Sourced Out (Average = 8.00) ; Number of LABs (Total = 1) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 1 ;
; 8 ; 1 ;
+-------------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs (Average = 7.50) ; Number of LABs (Total = 2) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 1 ;
+---------------------------------------------+-----------------------------+
+----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+-----------------------------+
; Number of Distinct Inputs (Average = 11.00) ; Number of LABs (Total = 1) ;
+----------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 1 ;
+----------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------+
@ -837,31 +819,30 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Auto Fit Point 1 - Fit Attempt 1 ; ff ;
; Mid Wire Use - Fit Attempt 1 ; 0 ;
; Mid Slack - Fit Attempt 1 ; 2147483639 ;
; Internal Atom Count - Fit Attempt 1 ; 18 ;
; LE/ALM Count - Fit Attempt 1 ; 18 ;
; LAB Count - Fit Attempt 1 ; 3 ;
; Outputs per Lab - Fit Attempt 1 ; 3.333 ;
; Inputs per LAB - Fit Attempt 1 ; 5.000 ;
; Internal Atom Count - Fit Attempt 1 ; 15 ;
; LE/ALM Count - Fit Attempt 1 ; 15 ;
; LAB Count - Fit Attempt 1 ; 2 ;
; Outputs per Lab - Fit Attempt 1 ; 4.000 ;
; Inputs per LAB - Fit Attempt 1 ; 5.500 ;
; Global Inputs per LAB - Fit Attempt 1 ; 0.000 ;
; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:3 ;
; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:3 ;
; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:3 ;
; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:3 ;
; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:3 ;
; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:3 ;
; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:3 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:3 ;
; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:3 ;
; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:3 ;
; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:3 ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:3 ;
; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:2 ;
; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1 ; 0:1;1:1 ;
; LEs in Chains - Fit Attempt 1 ; 0 ;
; LEs in Long Chains - Fit Attempt 1 ; 0 ;
; LABs with Chains - Fit Attempt 1 ; 0 ;
; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;
; Time - Fit Attempt 1 ; 0 ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016 ;
+------------------------------------------------------------------+------------+
@ -897,10 +878,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Name ; Value ;
+------------------------------------+-------------+
; Early Slack - Fit Attempt 1 ; 2147483639 ;
; Early Wire Use - Fit Attempt 1 ; 0 ;
; Peak Regional Wire - Fit Attempt 1 ; 1 ;
; Mid Slack - Fit Attempt 1 ; 2147483639 ;
; Late Slack - Fit Attempt 1 ; -2147483648 ;
; Early Wire Use - Fit Attempt 1 ; 0 ;
; Peak Regional Wire - Fit Attempt 1 ; 0 ;
; Late Wire Use - Fit Attempt 1 ; 0 ;
; Time - Fit Attempt 1 ; 0 ;
+------------------------------------+-------------+
@ -912,9 +893,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Mon Mar 07 10:37:41 2022
Info: Processing started: Mon Mar 07 11:15:54 2022
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Info: Parallel compilation is enabled and will use 4 of the 6 processors detected
Info: Selected device EP2C8Q208C8 for design "shifter_8b"
Info: Low junction temperature is 0 degrees C
Info: High junction temperature is 85 degrees C
@ -927,7 +908,7 @@ Info: Fitter converted 3 user pins into dedicated programming pins
Info: Pin ~ASDO~ is reserved at location 1
Info: Pin ~nCSO~ is reserved at location 2
Info: Pin ~LVDS54p/nCEO~ is reserved at location 108
Warning: No exact pin location assignment(s) for 22 pins of 22 total pins
Warning: No exact pin location assignment(s) for 19 pins of 19 total pins
Info: Pin Y0 not assigned to an exact location on the device
Info: Pin Y1 not assigned to an exact location on the device
Info: Pin Y2 not assigned to an exact location on the device
@ -936,27 +917,24 @@ Warning: No exact pin location assignment(s) for 22 pins of 22 total pins
Info: Pin Y5 not assigned to an exact location on the device
Info: Pin Y6 not assigned to an exact location on the device
Info: Pin Y7 not assigned to an exact location on the device
Info: Pin OF not assigned to an exact location on the device
Info: Pin A0 not assigned to an exact location on the device
Info: Pin L not assigned to an exact location on the device
Info: Pin LM not assigned to an exact location on the device
Info: Pin DM not assigned to an exact location on the device
Info: Pin A1 not assigned to an exact location on the device
Info: Pin RM not assigned to an exact location on the device
Info: Pin DM not assigned to an exact location on the device
Info: Pin LM not assigned to an exact location on the device
Info: Pin A2 not assigned to an exact location on the device
Info: Pin A3 not assigned to an exact location on the device
Info: Pin A4 not assigned to an exact location on the device
Info: Pin A5 not assigned to an exact location on the device
Info: Pin A6 not assigned to an exact location on the device
Info: Pin A7 not assigned to an exact location on the device
Info: Pin R not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Starting register packing
Info: Finished register packing
Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info: Number of I/O pins in group: 22 (unused VREF, 3.3V VCCIO, 13 input, 9 output, 0 bidirectional)
Info: Number of I/O pins in group: 19 (unused VREF, 3.3V VCCIO, 11 input, 8 output, 0 bidirectional)
Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
Info: Statistics of I/O banks
@ -964,7 +942,7 @@ Info: I/O bank details before I/O pin placement
Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available
Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available
Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available
Info: Fitter preparation operations ending: elapsed time is 00:00:01
Info: Fitter preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
@ -972,13 +950,13 @@ Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources
Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X10_Y19
Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 9 output pins without output pin load capacitance assignment
Warning: Found 8 output pins without output pin load capacitance assignment
Info: Pin "Y0" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "Y1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "Y2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
@ -987,13 +965,12 @@ Warning: Found 9 output pins without output pin load capacitance assignment
Info: Pin "Y5" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "Y6" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "Y7" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "OF" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Generated suppressed messages file D:/projects/quartus/shifter_8b/shifter_8b.fit.smsg
Info: Generated suppressed messages file D:/dev/quartus/shifter_8b/shifter_8b.fit.smsg
Info: Quartus II Fitter was successful. 0 errors, 3 warnings
Info: Peak virtual memory: 306 megabytes
Info: Processing ended: Mon Mar 07 10:37:42 2022
Info: Peak virtual memory: 286 megabytes
Info: Processing ended: Mon Mar 07 11:15:55 2022
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
@ -1001,6 +978,6 @@ Info: Quartus II Fitter was successful. 0 errors, 3 warnings
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in D:/projects/quartus/shifter_8b/shifter_8b.fit.smsg.
The suppressed messages can be found in D:/dev/quartus/shifter_8b/shifter_8b.fit.smsg.

8
shifter_8b/shifter_8b.fit.summary
查看文件

@ -1,15 +1,15 @@
Fitter Status : Successful - Mon Mar 07 10:37:42 2022
Fitter Status : Successful - Mon Mar 07 11:15:55 2022
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : shifter_8b
Top-level Entity Name : shifter_8b
Family : Cyclone II
Device : EP2C8Q208C8
Timing Models : Final
Total logic elements : 17 / 8,256 ( < 1 % )
Total combinational functions : 17 / 8,256 ( < 1 % )
Total logic elements : 14 / 8,256 ( < 1 % )
Total combinational functions : 14 / 8,256 ( < 1 % )
Dedicated logic registers : 0 / 8,256 ( 0 % )
Total registers : 0
Total pins : 22 / 138 ( 16 % )
Total pins : 19 / 138 ( 14 % )
Total virtual pins : 0
Total memory bits : 0 / 165,888 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % )

86
shifter_8b/shifter_8b.flow.rpt
查看文件

@ -1,5 +1,5 @@
Flow report for shifter_8b
Mon Mar 07 10:37:44 2022
Mon Mar 07 11:17:07 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@ -38,23 +38,23 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+----------------------------------------------+
; Flow Status ; Successful - Mon Mar 07 10:37:44 2022 ;
; Flow Status ; Successful - Mon Mar 07 11:17:07 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; shifter_8b ;
; Top-level Entity Name ; shifter_8b ;
; Family ; Cyclone II ;
; Device ; EP2C8Q208C8 ;
; Timing Models ; Final ;
; Met timing requirements ; Yes ;
; Total logic elements ; 17 / 8,256 ( < 1 % ) ;
; Total combinational functions ; 17 / 8,256 ( < 1 % ) ;
; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ;
; Met timing requirements ; N/A ;
; Total logic elements ; 14 ;
; Total combinational functions ; 14 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 22 / 138 ( 16 % ) ;
; Total pins ; 19 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 165,888 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
; Total PLLs ; 0 / 2 ( 0 % ) ;
; Total memory bits ; 0 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
+------------------------------------+----------------------------------------------+
@ -63,58 +63,50 @@ applicable agreement for further details.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 03/07/2022 10:37:40 ;
; Start date & time ; 03/07/2022 11:17:07 ;
; Main task ; Compilation ;
; Revision Name ; shifter_8b ;
+-------------------+---------------------+
+---------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+------------------------------------+---------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+------------------------------------+---------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 220283517943889.164662066022984 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
+------------------------------------+---------------------------------+---------------+-------------+----------------+
+------------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+------------------------------------+------------------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+------------------------------------+------------------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 136411542855513.164662302732708 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; MISC_FILE ; D:/dev/quartus/shifter_8b/shifter_8b.dpf ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
+------------------------------------+------------------------------------------+---------------+-------------+----------------+
+-----------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 245 MB ; 00:00:00 ;
; Fitter ; 00:00:01 ; 1.0 ; 306 MB ; 00:00:01 ;
; Assembler ; 00:00:01 ; 1.0 ; 241 MB ; 00:00:00 ;
; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 198 MB ; 00:00:00 ;
; Total ; 00:00:02 ; -- ; -- ; 00:00:01 ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 226 MB ; 00:00:00 ;
; Total ; 00:00:00 ; -- ; -- ; 00:00:00 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
+------------------------------------------------------------------------------------------+
; Flow OS Summary ;
+-------------------------+------------------+---------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+-------------------------+------------------+---------------+------------+----------------+
; Analysis & Synthesis ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
; Fitter ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
; Assembler ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
; Classic Timing Analyzer ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
+-------------------------+------------------+---------------+------------+----------------+
+---------------------------------------------------------------------------------------+
; Flow OS Summary ;
+----------------------+------------------+---------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+------------------+---------------+------------+----------------+
; Analysis & Synthesis ; DESKTOP-G0CBSMT ; Windows Vista ; 6.2 ; x86_64 ;
+----------------------+------------------+---------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b
quartus_fit --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b
quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b
quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only

64
shifter_8b/shifter_8b.map.rpt
查看文件

@ -1,5 +1,5 @@
Analysis & Synthesis report for shifter_8b
Mon Mar 07 10:37:40 2022
Mon Mar 07 11:17:07 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@ -39,16 +39,16 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Mar 07 10:37:40 2022 ;
; Analysis & Synthesis Status ; Successful - Mon Mar 07 11:17:07 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; shifter_8b ;
; Top-level Entity Name ; shifter_8b ;
; Family ; Cyclone II ;
; Total logic elements ; 17 ;
; Total combinational functions ; 17 ;
; Total logic elements ; 14 ;
; Total combinational functions ; 14 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 22 ;
; Total pins ; 19 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Embedded Multiplier 9-bit elements ; 0 ;
@ -131,14 +131,14 @@ applicable agreement for further details.
+--------------------------------------------------------------+--------------------+--------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------------+-------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------------+-------------------------------------------------------+
; shifter_8b.bdf ; yes ; User Block Diagram/Schematic File ; D:/projects/quartus/shifter_8b/shifter_8b.bdf ;
; triple_selector_8b.bdf ; yes ; Auto-Found Block Diagram/Schematic File ; D:/projects/quartus/shifter_8b/triple_selector_8b.bdf ;
+----------------------------------+-----------------+------------------------------------------+-------------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------------+--------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------------+--------------------------------------------------+
; shifter_8b.bdf ; yes ; User Block Diagram/Schematic File ; D:/dev/quartus/shifter_8b/shifter_8b.bdf ;
; triple_selector_8b.bdf ; yes ; Auto-Found Block Diagram/Schematic File ; D:/dev/quartus/shifter_8b/triple_selector_8b.bdf ;
+----------------------------------+-----------------+------------------------------------------+--------------------------------------------------+
+-----------------------------------------------------+
@ -146,27 +146,27 @@ applicable agreement for further details.
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements ; 17 ;
; Estimated Total logic elements ; 14 ;
; ; ;
; Total combinational functions ; 17 ;
; Total combinational functions ; 14 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 9 ;
; -- 3 input functions ; 8 ;
; -- 4 input functions ; 8 ;
; -- 3 input functions ; 6 ;
; -- <=2 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 17 ;
; -- normal mode ; 14 ;
; -- arithmetic mode ; 0 ;
; ; ;
; Total registers ; 0 ;
; -- Dedicated logic registers ; 0 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 22 ;
; Maximum fan-out node ; LM ;
; Maximum fan-out ; 9 ;
; Total fan-out ; 69 ;
; Average fan-out ; 1.77 ;
; I/O pins ; 19 ;
; Maximum fan-out node ; DM ;
; Maximum fan-out ; 8 ;
; Total fan-out ; 58 ;
; Average fan-out ; 1.76 ;
+---------------------------------------------+-------+
@ -175,8 +175,8 @@ applicable agreement for further details.
+------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------+--------------+
; |shifter_8b ; 17 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 22 ; 0 ; |shifter_8b ; work ;
; |triple_selector_8b:inst| ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |shifter_8b|triple_selector_8b:inst ; work ;
; |shifter_8b ; 14 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 19 ; 0 ; |shifter_8b ; work ;
; |triple_selector_8b:inst| ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |shifter_8b|triple_selector_8b:inst ; work ;
+------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@ -202,7 +202,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Mon Mar 07 10:37:40 2022
Info: Processing started: Mon Mar 07 11:17:07 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b
Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf
Info: Found entity 1: shifter_8b
@ -210,13 +210,13 @@ Info: Elaborating entity "shifter_8b" for the top level hierarchy
Warning: Using design file triple_selector_8b.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: triple_selector_8b
Info: Elaborating entity "triple_selector_8b" for hierarchy "triple_selector_8b:inst"
Info: Implemented 39 device resources after synthesis - the final resource count might be different
Info: Implemented 13 input pins
Info: Implemented 9 output pins
Info: Implemented 17 logic cells
Info: Implemented 33 device resources after synthesis - the final resource count might be different
Info: Implemented 11 input pins
Info: Implemented 8 output pins
Info: Implemented 14 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Peak virtual memory: 249 megabytes
Info: Processing ended: Mon Mar 07 10:37:40 2022
Info: Peak virtual memory: 229 megabytes
Info: Processing ended: Mon Mar 07 11:17:07 2022
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00

8
shifter_8b/shifter_8b.map.summary
查看文件

@ -1,13 +1,13 @@
Analysis & Synthesis Status : Successful - Mon Mar 07 10:37:40 2022
Analysis & Synthesis Status : Successful - Mon Mar 07 11:17:07 2022
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : shifter_8b
Top-level Entity Name : shifter_8b
Family : Cyclone II
Total logic elements : 17
Total combinational functions : 17
Total logic elements : 14
Total combinational functions : 14
Dedicated logic registers : 0
Total registers : 0
Total pins : 22
Total pins : 19
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0

54
shifter_8b/shifter_8b.pin
查看文件

@ -71,18 +71,18 @@ Pin Name/Usage : Location : Dir. : I/O Standard : Voltage
~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVTTL : : 1 : N
~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVTTL : : 1 : N
GND* : 3 : : : : 1 :
A4 : 4 : input : 3.3-V LVTTL : : 1 : N
Y6 : 5 : output : 3.3-V LVTTL : : 1 : N
GND* : 4 : : : : 1 :
GND* : 5 : : : : 1 :
GND* : 6 : : : : 1 :
VCCIO1 : 7 : power : : 3.3V : 1 :
A5 : 8 : input : 3.3-V LVTTL : : 1 : N
GND* : 8 : : : : 1 :
GND : 9 : gnd : : : :
GND* : 10 : : : : 1 :
Y3 : 11 : output : 3.3-V LVTTL : : 1 : N
Y2 : 12 : output : 3.3-V LVTTL : : 1 : N
Y5 : 13 : output : 3.3-V LVTTL : : 1 : N
A6 : 14 : input : 3.3-V LVTTL : : 1 : N
A7 : 15 : input : 3.3-V LVTTL : : 1 : N
GND* : 11 : : : : 1 :
GND* : 12 : : : : 1 :
A7 : 13 : input : 3.3-V LVTTL : : 1 : N
GND* : 14 : : : : 1 :
A0 : 15 : input : 3.3-V LVTTL : : 1 : N
TDO : 16 : output : : : 1 :
TMS : 17 : input : : : 1 :
TCK : 18 : input : : : 1 :
@ -90,24 +90,24 @@ TDI : 19 : input : :
DATA0 : 20 : input : : : 1 :
DCLK : 21 : : : : 1 :
nCE : 22 : : : : 1 :
A1 : 23 : input : 3.3-V LVTTL : : 1 : N
RM : 24 : input : 3.3-V LVTTL : : 1 : N
A2 : 23 : input : 3.3-V LVTTL : : 1 : N
A3 : 24 : input : 3.3-V LVTTL : : 1 : N
GND : 25 : gnd : : : :
nCONFIG : 26 : : : : 1 :
A2 : 27 : input : 3.3-V LVTTL : : 1 : N
A3 : 28 : input : 3.3-V LVTTL : : 1 : N
A4 : 27 : input : 3.3-V LVTTL : : 1 : N
A5 : 28 : input : 3.3-V LVTTL : : 1 : N
VCCIO1 : 29 : power : : 3.3V : 1 :
R : 30 : input : 3.3-V LVTTL : : 1 : N
Y0 : 31 : output : 3.3-V LVTTL : : 1 : N
LM : 30 : input : 3.3-V LVTTL : : 1 : N
Y5 : 31 : output : 3.3-V LVTTL : : 1 : N
VCCINT : 32 : power : : 1.2V : :
Y7 : 33 : output : 3.3-V LVTTL : : 1 : N
Y1 : 34 : output : 3.3-V LVTTL : : 1 : N
DM : 35 : input : 3.3-V LVTTL : : 1 : N
Y2 : 33 : output : 3.3-V LVTTL : : 1 : N
Y4 : 34 : output : 3.3-V LVTTL : : 1 : N
RM : 35 : input : 3.3-V LVTTL : : 1 : N
GND : 36 : gnd : : : :
GND* : 37 : : : : 1 :
GND : 38 : gnd : : : :
GND* : 39 : : : : 1 :
OF : 40 : output : 3.3-V LVTTL : : 1 : N
Y6 : 39 : output : 3.3-V LVTTL : : 1 : N
Y1 : 40 : output : 3.3-V LVTTL : : 1 : N
GND* : 41 : : : : 1 :
VCCIO1 : 42 : power : : 3.3V : 1 :
GND* : 43 : : : : 1 :
@ -115,7 +115,7 @@ GND* : 44 : : :
GND* : 45 : : : : 1 :
GND* : 46 : : : : 1 :
GND* : 47 : : : : 1 :
GND* : 48 : : : : 1 :
Y0 : 48 : output : 3.3-V LVTTL : : 1 : N
GND : 49 : gnd : : : :
GND_PLL1 : 50 : gnd : : : :
VCCD_PLL1 : 51 : power : : 1.2V : :
@ -124,17 +124,17 @@ VCCA_PLL1 : 53 : power : : 1.2V
GNDA_PLL1 : 54 : gnd : : : :
GND : 55 : gnd : : : :
GND* : 56 : : : : 4 :
LM : 57 : input : 3.3-V LVTTL : : 4 : N
GND* : 57 : : : : 4 :
GND* : 58 : : : : 4 :
GND* : 59 : : : : 4 :
A0 : 60 : input : 3.3-V LVTTL : : 4 : N
Y7 : 60 : output : 3.3-V LVTTL : : 4 : N
GND* : 61 : : : : 4 :
VCCIO4 : 62 : power : : 3.3V : 4 :
GND* : 63 : : : : 4 :
A1 : 63 : input : 3.3-V LVTTL : : 4 : N
GND* : 64 : : : : 4 :
GND : 65 : gnd : : : :
VCCINT : 66 : power : : 1.2V : :
GND* : 67 : : : : 4 :
A6 : 67 : input : 3.3-V LVTTL : : 4 : N
GND* : 68 : : : : 4 :
GND* : 69 : : : : 4 :
GND* : 70 : : : : 4 :
@ -266,13 +266,13 @@ GND* : 195 : : :
GND : 196 : gnd : : : :
GND* : 197 : : : : 2 :
GND* : 198 : : : : 2 :
L : 199 : input : 3.3-V LVTTL : : 2 : N
GND* : 199 : : : : 2 :
GND* : 200 : : : : 2 :
GND* : 201 : : : : 2 :
VCCIO2 : 202 : power : : 3.3V : 2 :
GND* : 203 : : : : 2 :
GND : 204 : gnd : : : :
GND* : 205 : : : : 2 :
DM : 205 : input : 3.3-V LVTTL : : 2 : N
GND* : 206 : : : : 2 :
GND* : 207 : : : : 2 :
Y4 : 208 : output : 3.3-V LVTTL : : 2 : N
Y3 : 208 : output : 3.3-V LVTTL : : 2 : N

二進制
shifter_8b/shifter_8b.pof
查看文件

未顯示二進位檔案。

3
shifter_8b/shifter_8b.qsf
查看文件

@ -50,4 +50,5 @@ set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name MISC_FILE "D:/dev/quartus/shifter_8b/shifter_8b.dpf"

二進制
shifter_8b/shifter_8b.sof
查看文件

未顯示二進位檔案。

127
shifter_8b/shifter_8b.tan.rpt
查看文件

@ -1,5 +1,5 @@
Classic Timing Analyzer report for shifter_8b
Mon Mar 07 10:37:44 2022
Mon Mar 07 11:15:57 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@ -39,7 +39,7 @@ applicable agreement for further details.
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 13.320 ns ; DM ; Y7 ; -- ; -- ; 0 ;
; Worst-case tpd ; N/A ; None ; 13.413 ns ; A6 ; Y7 ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
@ -81,7 +81,7 @@ applicable agreement for further details.
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Number detected on machine ; 6 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
@ -89,7 +89,7 @@ applicable agreement for further details.
; ; ;
; Usage by Processor ; % Time Used ;
; 1 processor ; 100.0% ;
; 2-4 processors ; 0.0% ;
; 2-6 processors ; 0.0% ;
+----------------------------+-------------+
@ -98,58 +98,50 @@ applicable agreement for further details.
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A ; None ; 13.320 ns ; DM ; Y7 ;
; N/A ; None ; 13.225 ns ; DM ; Y4 ;
; N/A ; None ; 13.207 ns ; LM ; Y7 ;
; N/A ; None ; 13.153 ns ; LM ; Y0 ;
; N/A ; None ; 13.128 ns ; LM ; Y4 ;
; N/A ; None ; 13.029 ns ; A0 ; Y1 ;
; N/A ; None ; 13.020 ns ; DM ; Y1 ;
; N/A ; None ; 12.918 ns ; LM ; Y1 ;
; N/A ; None ; 12.906 ns ; A4 ; Y4 ;
; N/A ; None ; 12.900 ns ; DM ; Y2 ;
; N/A ; None ; 12.874 ns ; A0 ; OF ;
; N/A ; None ; 12.848 ns ; A0 ; Y0 ;
; N/A ; None ; 12.834 ns ; DM ; Y0 ;
; N/A ; None ; 12.817 ns ; L ; Y0 ;
; N/A ; None ; 12.816 ns ; LM ; Y6 ;
; N/A ; None ; 12.787 ns ; LM ; Y2 ;
; N/A ; None ; 12.752 ns ; LM ; Y5 ;
; N/A ; None ; 12.542 ns ; A7 ; Y7 ;
; N/A ; None ; 12.524 ns ; DM ; Y3 ;
; N/A ; None ; 12.450 ns ; LM ; OF ;
; N/A ; None ; 12.431 ns ; LM ; Y3 ;
; N/A ; None ; 12.272 ns ; A6 ; Y7 ;
; N/A ; None ; 12.211 ns ; A5 ; Y6 ;
; N/A ; None ; 12.184 ns ; A4 ; Y5 ;
; N/A ; None ; 12.155 ns ; A5 ; Y5 ;
; N/A ; None ; 12.007 ns ; DM ; Y6 ;
; N/A ; None ; 11.961 ns ; A5 ; Y4 ;
; N/A ; None ; 11.952 ns ; DM ; Y5 ;
; N/A ; None ; 11.780 ns ; A7 ; OF ;
; N/A ; None ; 11.520 ns ; A4 ; Y3 ;
; N/A ; None ; 11.436 ns ; A6 ; Y6 ;
; N/A ; None ; 11.309 ns ; R ; Y7 ;
; N/A ; None ; 11.123 ns ; A6 ; Y5 ;
; N/A ; None ; 11.097 ns ; A7 ; Y6 ;
; N/A ; None ; 8.432 ns ; A1 ; Y1 ;
; N/A ; None ; 8.391 ns ; A3 ; Y4 ;
; N/A ; None ; 8.283 ns ; A2 ; Y2 ;
; N/A ; None ; 8.057 ns ; A1 ; Y2 ;
; N/A ; None ; 7.922 ns ; A2 ; Y3 ;
; N/A ; None ; 7.852 ns ; A2 ; Y1 ;
; N/A ; None ; 7.752 ns ; RM ; OF ;
; N/A ; None ; 7.697 ns ; A3 ; Y3 ;
; N/A ; None ; 7.656 ns ; RM ; Y1 ;
; N/A ; None ; 7.645 ns ; RM ; Y0 ;
; N/A ; None ; 7.558 ns ; A1 ; Y0 ;
; N/A ; None ; 7.441 ns ; RM ; Y4 ;
; N/A ; None ; 7.348 ns ; RM ; Y3 ;
; N/A ; None ; 7.270 ns ; A3 ; Y2 ;
; N/A ; None ; 7.067 ns ; RM ; Y5 ;
; N/A ; None ; 7.062 ns ; RM ; Y6 ;
; N/A ; None ; 7.054 ns ; RM ; Y2 ;
; N/A ; None ; 5.826 ns ; RM ; Y7 ;
; N/A ; None ; 13.413 ns ; A6 ; Y7 ;
; N/A ; None ; 13.008 ns ; A7 ; Y7 ;
; N/A ; None ; 12.993 ns ; DM ; Y3 ;
; N/A ; None ; 12.852 ns ; A1 ; Y2 ;
; N/A ; None ; 12.792 ns ; A6 ; Y6 ;
; N/A ; None ; 12.781 ns ; DM ; Y4 ;
; N/A ; None ; 12.737 ns ; DM ; Y5 ;
; N/A ; None ; 12.544 ns ; LM ; Y3 ;
; N/A ; None ; 12.476 ns ; DM ; Y7 ;
; N/A ; None ; 12.455 ns ; A1 ; Y0 ;
; N/A ; None ; 12.428 ns ; A1 ; Y1 ;
; N/A ; None ; 12.419 ns ; A0 ; Y0 ;
; N/A ; None ; 12.394 ns ; A0 ; Y1 ;
; N/A ; None ; 12.311 ns ; DM ; Y2 ;
; N/A ; None ; 12.292 ns ; LM ; Y5 ;
; N/A ; None ; 12.248 ns ; A6 ; Y5 ;
; N/A ; None ; 12.029 ns ; LM ; Y7 ;
; N/A ; None ; 11.943 ns ; RM ; Y3 ;
; N/A ; None ; 11.911 ns ; DM ; Y0 ;
; N/A ; None ; 11.884 ns ; DM ; Y1 ;
; N/A ; None ; 11.864 ns ; LM ; Y2 ;
; N/A ; None ; 11.859 ns ; LM ; Y4 ;
; N/A ; None ; 11.855 ns ; DM ; Y6 ;
; N/A ; None ; 11.827 ns ; A7 ; Y6 ;
; N/A ; None ; 11.433 ns ; LM ; Y1 ;
; N/A ; None ; 11.432 ns ; RM ; Y0 ;
; N/A ; None ; 11.404 ns ; LM ; Y6 ;
; N/A ; None ; 11.258 ns ; RM ; Y2 ;
; N/A ; None ; 11.254 ns ; RM ; Y5 ;
; N/A ; None ; 11.249 ns ; RM ; Y4 ;
; N/A ; None ; 10.823 ns ; RM ; Y1 ;
; N/A ; None ; 10.804 ns ; RM ; Y6 ;
; N/A ; None ; 8.265 ns ; A2 ; Y3 ;
; N/A ; None ; 8.237 ns ; A3 ; Y3 ;
; N/A ; None ; 8.014 ns ; A5 ; Y5 ;
; N/A ; None ; 7.942 ns ; A4 ; Y5 ;
; N/A ; None ; 7.635 ns ; A4 ; Y3 ;
; N/A ; None ; 7.583 ns ; A2 ; Y2 ;
; N/A ; None ; 7.551 ns ; A3 ; Y4 ;
; N/A ; None ; 7.136 ns ; A5 ; Y6 ;
; N/A ; None ; 7.085 ns ; A4 ; Y4 ;
; N/A ; None ; 7.014 ns ; A5 ; Y4 ;
; N/A ; None ; 6.993 ns ; A3 ; Y2 ;
; N/A ; None ; 6.585 ns ; A2 ; Y1 ;
+-------+-------------------+-----------------+------+----+
@ -159,20 +151,19 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Mon Mar 07 10:37:44 2022
Info: Processing started: Mon Mar 07 11:15:57 2022
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Info: Longest tpd from source pin "DM" to destination pin "Y7" is 13.320 ns
Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_35; Fanout = 8; PIN Node = 'DM'
Info: 2: + IC(6.057 ns) + CELL(0.650 ns) = 7.692 ns; Loc. = LCCOMB_X1_Y14_N20; Fanout = 1; COMB Node = 'triple_selector_8b:inst|inst31~0'
Info: 3: + IC(1.286 ns) + CELL(0.319 ns) = 9.297 ns; Loc. = LCCOMB_X1_Y9_N16; Fanout = 1; COMB Node = 'triple_selector_8b:inst|inst31'
Info: 4: + IC(0.927 ns) + CELL(3.096 ns) = 13.320 ns; Loc. = PIN_33; Fanout = 0; PIN Node = 'Y7'
Info: Total cell delay = 5.050 ns ( 37.91 % )
Info: Total interconnect delay = 8.270 ns ( 62.09 % )
Info: Parallel compilation is enabled and will use 4 of the 6 processors detected
Info: Longest tpd from source pin "A6" to destination pin "Y7" is 13.413 ns
Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 3; PIN Node = 'A6'
Info: 2: + IC(6.895 ns) + CELL(0.624 ns) = 8.513 ns; Loc. = LCCOMB_X1_Y5_N10; Fanout = 1; COMB Node = 'triple_selector_8b:inst|inst31'
Info: 3: + IC(1.604 ns) + CELL(3.296 ns) = 13.413 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'Y7'
Info: Total cell delay = 4.914 ns ( 36.64 % )
Info: Total interconnect delay = 8.499 ns ( 63.36 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 212 megabytes
Info: Processing ended: Mon Mar 07 10:37:44 2022
Info: Elapsed time: 00:00:00
Info: Peak virtual memory: 191 megabytes
Info: Processing ended: Mon Mar 07 11:15:58 2022
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:00

4
shifter_8b/shifter_8b.tan.summary
查看文件

@ -5,8 +5,8 @@ Timing Analyzer Summary
Type : Worst-case tpd
Slack : N/A
Required Time : None
Actual Time : 13.320 ns
From : DM
Actual Time : 13.413 ns
From : A6
To : Y7
From Clock : --
To Clock : --

8
shifter_8b/triple_selector_8b.bdf
查看文件

@ -2084,10 +2084,6 @@ applicable agreement for further details.
(pt 384 96)
(pt 488 96)
)
(connector
(pt 552 88)
(pt 600 88)
)
(connector
(pt 296 32)
(pt 184 32)
@ -2224,6 +2220,10 @@ applicable agreement for further details.
(pt 224 1152)
(pt 224 1368)
)
(connector
(pt 600 88)
(pt 552 88)
)
(junction (pt 272 192))
(junction (pt 272 336))
(junction (pt 272 480))