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67cdfe3059
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为ALU添加了无符号加法
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2022-04-10 20:22:26 +08:00 |
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3a0ca117b2
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更新了表
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2022-04-10 19:02:06 +08:00 |
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07a47340ea
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修正MDR命名歧义
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2022-04-10 18:14:00 +08:00 |
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0ac3169c22
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适配excel表内容、编写两条指令
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2022-04-10 17:38:31 +08:00 |
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a8f8d38a4f
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给ALU加上了一堆运算，重新规划了微操作位置，调整ALU单元位置
不再使用左移后加符号位的方式，采用左右串入进位的方式实现双精度左右移。
添加了逻辑与。
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2022-04-10 11:26:28 +08:00 |
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0e20a26d0d
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公式完工了
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2022-04-09 10:31:26 +08:00 |
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58d88c6b02
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将原有ALU寄存器逻辑改为2-4译码
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2022-04-08 20:56:40 +08:00 |
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777435b2de
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将CU纠正为微地址形成组件，进一步完善电路图标注
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2022-04-08 19:32:30 +08:00 |
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3dd900ff87
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添加了引脚定义
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2022-04-08 17:06:24 +08:00 |
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90b419379b
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修正CU的输入，完成整体设计，再次调整总电路
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2022-04-08 14:14:26 +08:00 |
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3b4f090ab4
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完成CU，然后再次调整总电路
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2022-04-08 11:01:52 +08:00 |
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57923355f8
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进一步压缩空间
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2022-04-08 09:20:00 +08:00 |
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902e3a3fb2
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完成MDR，然后挪了挪组件
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2022-04-07 22:34:50 +08:00 |
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5805be0c50
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update xlsx
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2022-04-07 17:35:45 +08:00 |
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1ed0e02f8e
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ALU的CP选择
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2022-04-07 17:35:27 +08:00 |
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cb7280f66f
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Merge branch 'master' of https://git.sduonline.cn/juzheng/quartus
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2022-04-07 17:20:54 +08:00 |
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0710801e99
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CP选择装置
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2022-04-07 17:20:49 +08:00 |
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b8750847dc
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优化ALU结构
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2022-04-07 17:08:33 +08:00 |
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461d5caad4
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fix JX selector
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2022-04-07 16:59:52 +08:00 |
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647f444488
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update register group in machine
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2022-04-07 16:54:37 +08:00 |
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2fef99c3ac
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Merge branch 'master' of https://git.sduonline.cn/juzheng/quartus
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2022-04-07 16:47:41 +08:00 |
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11bfd0c1e6
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修改寄存器组
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2022-04-07 16:47:37 +08:00 |
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3a4e6787ed
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忽略office的临时文件
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2022-04-07 16:21:36 +08:00 |
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e9de2bc8a9
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Merge branch 'master' of https://git.sduonline.cn/juzheng/quartus
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2022-04-07 16:18:57 +08:00 |
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a30b0494ef
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添加8位四选一选择器
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2022-04-07 16:18:53 +08:00 |
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36d5bedf8f
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Merge branch 'master' of https://git.sduonline.cn/juzheng/quartus
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2022-04-07 15:50:45 +08:00 |
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85c641f4cf
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添加笔记
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2022-04-07 15:50:30 +08:00 |
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fc3da88f19
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完善B寄存器的功能，删去A寄存器的组合逻辑思路，完成程序状态字的判断电路
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2022-04-07 15:40:25 +08:00 |
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69262dc207
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添加输入分组的三选一符号
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2022-04-07 15:35:09 +08:00 |
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1bdd55d75f
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upgrade single adder to ALU with adder & shifter
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2022-04-01 09:59:39 +08:00 |
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6d6bce4487
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完善微指令内容
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2022-03-31 22:34:12 +08:00 |
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2063d476b9
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啥都没干哼哼
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2022-03-31 17:35:05 +08:00 |
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68e10b4fd1
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优化ALU电路结构
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2022-03-31 17:27:15 +08:00 |
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00bbf8b267
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add 24_decoder
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2022-03-31 15:11:28 +08:00 |
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fc7e5d5807
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move asdf
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2022-03-30 08:41:24 +08:00 |
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6b95f93bc0
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update machine
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2022-03-29 17:10:33 +08:00 |
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cf71b49ea6
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create machine_alpha
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2022-03-29 16:52:11 +08:00 |
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f589e4fc86
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add register_8b_premium
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2022-03-29 16:34:13 +08:00 |
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2dd691bf99
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add register 4x
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2022-03-29 15:02:17 +08:00 |
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da8478ff9a
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rename for machine_alpha
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2022-03-29 14:38:35 +08:00 |
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wzh
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4df19e69b9
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change CPRn pin
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2022-03-24 18:36:24 +08:00 |
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ff09c80b84
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assign pins & add debug output
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2022-03-24 17:01:43 +08:00 |
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2124929b45
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Add NOT gate on CPs
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2022-03-24 16:24:00 +08:00 |
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78337c6f7a
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Add PC_uIR and uRDN
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2022-03-24 14:25:56 +08:00 |
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a8dd3f0217
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Finish uPC and whole design of RAM project
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2022-03-21 16:15:14 +08:00 |
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e5315fad02
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Finish RAM project without setting uPC and pin settings
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2022-03-17 21:19:47 +08:00 |
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eceb1b13d4
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set up project of start_circuit and copy it to ram project
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2022-03-17 20:27:34 +08:00 |
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978edd39d6
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add start_circuit
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2022-03-17 20:16:00 +08:00 |
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96a90da2bc
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create microprogram_ram
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2022-03-17 20:06:56 +08:00 |
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13b88836ec
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add register 8b with switch
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2022-03-17 19:25:16 +08:00 |
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