Classic Timing Analyzer report for register_8b Mon Mar 07 09:09:57 2022 Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Timing Analyzer Summary 3. Timing Analyzer Settings 4. Clock Settings Summary 5. Parallel Compilation 6. tsu 7. tco 8. th 9. Timing Analyzer Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2009 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +---------------------------------------------------------------------------------------------------------------------------+ ; Timing Analyzer Summary ; +------------------------------+-------+---------------+-------------+-------+-------+------------+----------+--------------+ ; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; +------------------------------+-------+---------------+-------------+-------+-------+------------+----------+--------------+ ; Worst-case tsu ; N/A ; None ; 4.872 ns ; D3 ; inst5 ; -- ; CP ; 0 ; ; Worst-case tco ; N/A ; None ; 8.228 ns ; inst3 ; Q5 ; CP ; -- ; 0 ; ; Worst-case th ; N/A ; None ; 0.406 ns ; D1 ; inst7 ; -- ; CP ; 0 ; ; Total number of failed paths ; ; ; ; ; ; ; ; 0 ; +------------------------------+-------+---------------+-------------+-------+-------+------------+----------+--------------+ +--------------------------------------------------------------------------------------------------------------------+ ; Timing Analyzer Settings ; +---------------------------------------------------------------------+--------------------+------+----+-------------+ ; Option ; Setting ; From ; To ; Entity Name ; +---------------------------------------------------------------------+--------------------+------+----+-------------+ ; Device Name ; EP2C8Q208C8 ; ; ; ; ; Timing Models ; Final ; ; ; ; ; Default hold multicycle ; Same as Multicycle ; ; ; ; ; Cut paths between unrelated clock domains ; On ; ; ; ; ; Cut off read during write signal paths ; On ; ; ; ; ; Cut off feedback from I/O pins ; On ; ; ; ; ; Report Combined Fast/Slow Timing ; Off ; ; ; ; ; Ignore Clock Settings ; Off ; ; ; ; ; Analyze latches as synchronous elements ; On ; ; ; ; ; Enable Recovery/Removal analysis ; Off ; ; ; ; ; Enable Clock Latency ; Off ; ; ; ; ; Use TimeQuest Timing Analyzer ; Off ; ; ; ; ; Minimum Core Junction Temperature ; 0 ; ; ; ; ; Maximum Core Junction Temperature ; 85 ; ; ; ; ; Number of source nodes to report per destination node ; 10 ; ; ; ; ; Number of destination nodes to report ; 10 ; ; ; ; ; Number of paths to report ; 200 ; ; ; ; ; Report Minimum Timing Checks ; Off ; ; ; ; ; Use Fast Timing Models ; Off ; ; ; ; ; Report IO Paths Separately ; Off ; ; ; ; ; Perform Multicorner Analysis ; On ; ; ; ; ; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ; ; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ; ; Output I/O Timing Endpoint ; Near End ; ; ; ; +---------------------------------------------------------------------+--------------------+------+----+-------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Clock Settings Summary ; +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ ; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ; +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ ; CP ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ; +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ +------------------------------------------+ ; Parallel Compilation ; +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ ; Number detected on machine ; 4 ; ; Maximum allowed ; 4 ; ; ; ; ; Average used ; 1.00 ; ; Maximum used ; 1 ; ; ; ; ; Usage by Processor ; % Time Used ; ; 1 processor ; 100.0% ; ; 2-4 processors ; 0.0% ; +----------------------------+-------------+ +-------------------------------------------------------------+ ; tsu ; +-------+--------------+------------+------+-------+----------+ ; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ; +-------+--------------+------------+------+-------+----------+ ; N/A ; None ; 4.872 ns ; D3 ; inst5 ; CP ; ; N/A ; None ; 4.693 ns ; D0 ; inst8 ; CP ; ; N/A ; None ; 4.628 ns ; D4 ; inst4 ; CP ; ; N/A ; None ; 4.577 ns ; D6 ; inst2 ; CP ; ; N/A ; None ; 4.264 ns ; D5 ; inst3 ; CP ; ; N/A ; None ; 4.007 ns ; D7 ; inst ; CP ; ; N/A ; None ; 1.029 ns ; D2 ; inst6 ; CP ; ; N/A ; None ; -0.140 ns ; D1 ; inst7 ; CP ; +-------+--------------+------------+------+-------+----------+ +-------------------------------------------------------------+ ; tco ; +-------+--------------+------------+-------+----+------------+ ; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ; +-------+--------------+------------+-------+----+------------+ ; N/A ; None ; 8.228 ns ; inst3 ; Q5 ; CP ; ; N/A ; None ; 8.096 ns ; inst2 ; Q6 ; CP ; ; N/A ; None ; 7.981 ns ; inst4 ; Q4 ; CP ; ; N/A ; None ; 7.359 ns ; inst6 ; Q2 ; CP ; ; N/A ; None ; 7.354 ns ; inst ; Q7 ; CP ; ; N/A ; None ; 7.258 ns ; inst5 ; Q3 ; CP ; ; N/A ; None ; 6.982 ns ; inst8 ; Q0 ; CP ; ; N/A ; None ; 6.969 ns ; inst7 ; Q1 ; CP ; +-------+--------------+------------+-------+----+------------+ +-------------------------------------------------------------------+ ; th ; +---------------+-------------+-----------+------+-------+----------+ ; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ; +---------------+-------------+-----------+------+-------+----------+ ; N/A ; None ; 0.406 ns ; D1 ; inst7 ; CP ; ; N/A ; None ; -0.763 ns ; D2 ; inst6 ; CP ; ; N/A ; None ; -3.741 ns ; D7 ; inst ; CP ; ; N/A ; None ; -3.998 ns ; D5 ; inst3 ; CP ; ; N/A ; None ; -4.311 ns ; D6 ; inst2 ; CP ; ; N/A ; None ; -4.362 ns ; D4 ; inst4 ; CP ; ; N/A ; None ; -4.427 ns ; D0 ; inst8 ; CP ; ; N/A ; None ; -4.606 ns ; D3 ; inst5 ; CP ; +---------------+-------------+-----------+------+-------+----------+ +--------------------------+ ; Timing Analyzer Messages ; +--------------------------+ Info: ******************************************************************* Info: Running Quartus II Classic Timing Analyzer Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition Info: Processing started: Mon Mar 07 09:09:57 2022 Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off register_8b -c register_8b --timing_analysis_only Info: Parallel compilation is enabled and will use 4 of the 4 processors detected Warning: Found pins functioning as undefined clocks and/or memory enables Info: Assuming node "CP" is an undefined clock Info: No valid register-to-register data paths exist for clock "CP" Info: tsu for register "inst5" (data pin = "D3", clock pin = "CP") is 4.872 ns Info: + Longest pin to register delay is 7.782 ns Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_96; Fanout = 1; PIN Node = 'D3' Info: 2: + IC(6.338 ns) + CELL(0.460 ns) = 7.782 ns; Loc. = LCFF_X32_Y15_N17; Fanout = 1; REG Node = 'inst5' Info: Total cell delay = 1.444 ns ( 18.56 % ) Info: Total interconnect delay = 6.338 ns ( 81.44 % ) Info: + Micro setup delay of destination is -0.040 ns Info: - Shortest clock path from clock "CP" to destination register is 2.870 ns Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CP' Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CP~clkctrl' Info: 3: + IC(0.925 ns) + CELL(0.666 ns) = 2.870 ns; Loc. = LCFF_X32_Y15_N17; Fanout = 1; REG Node = 'inst5' Info: Total cell delay = 1.806 ns ( 62.93 % ) Info: Total interconnect delay = 1.064 ns ( 37.07 % ) Info: tco from clock "CP" to destination pin "Q5" through register "inst3" is 8.228 ns Info: + Longest clock path from clock "CP" to source register is 2.879 ns Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CP' Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CP~clkctrl' Info: 3: + IC(0.934 ns) + CELL(0.666 ns) = 2.879 ns; Loc. = LCFF_X12_Y2_N9; Fanout = 1; REG Node = 'inst3' Info: Total cell delay = 1.806 ns ( 62.73 % ) Info: Total interconnect delay = 1.073 ns ( 37.27 % ) Info: + Micro clock to output delay of source is 0.304 ns Info: + Longest register to pin delay is 5.045 ns Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y2_N9; Fanout = 1; REG Node = 'inst3' Info: 2: + IC(1.765 ns) + CELL(3.280 ns) = 5.045 ns; Loc. = PIN_47; Fanout = 0; PIN Node = 'Q5' Info: Total cell delay = 3.280 ns ( 65.01 % ) Info: Total interconnect delay = 1.765 ns ( 34.99 % ) Info: th for register "inst7" (data pin = "D1", clock pin = "CP") is 0.406 ns Info: + Longest clock path from clock "CP" to destination register is 2.855 ns Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CP' Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CP~clkctrl' Info: 3: + IC(0.910 ns) + CELL(0.666 ns) = 2.855 ns; Loc. = LCFF_X1_Y14_N17; Fanout = 1; REG Node = 'inst7' Info: Total cell delay = 1.806 ns ( 63.26 % ) Info: Total interconnect delay = 1.049 ns ( 36.74 % ) Info: + Micro hold delay of destination is 0.306 ns Info: - Shortest pin to register delay is 2.755 ns Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_28; Fanout = 1; PIN Node = 'D1' Info: 2: + IC(1.301 ns) + CELL(0.206 ns) = 2.647 ns; Loc. = LCCOMB_X1_Y14_N16; Fanout = 1; COMB Node = 'inst7~feeder' Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 2.755 ns; Loc. = LCFF_X1_Y14_N17; Fanout = 1; REG Node = 'inst7' Info: Total cell delay = 1.454 ns ( 52.78 % ) Info: Total interconnect delay = 1.301 ns ( 47.22 % ) Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning Info: Peak virtual memory: 212 megabytes Info: Processing ended: Mon Mar 07 09:09:57 2022 Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:00