Classic Timing Analyzer report for shifter_8b Thu Mar 10 14:51:56 2022 Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Timing Analyzer Summary 3. Timing Analyzer Settings 4. Parallel Compilation 5. tpd 6. Timing Analyzer Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2009 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +-----------------------------------------------------------------------------------------------------------------------+ ; Timing Analyzer Summary ; +------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ ; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; +------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ ; Worst-case tpd ; N/A ; None ; 15.646 ns ; LM ; Y6 ; -- ; -- ; 0 ; ; Total number of failed paths ; ; ; ; ; ; ; ; 0 ; +------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ +--------------------------------------------------------------------------------------------------------------------+ ; Timing Analyzer Settings ; +---------------------------------------------------------------------+--------------------+------+----+-------------+ ; Option ; Setting ; From ; To ; Entity Name ; +---------------------------------------------------------------------+--------------------+------+----+-------------+ ; Device Name ; EP2C8Q208C8 ; ; ; ; ; Timing Models ; Final ; ; ; ; ; Default hold multicycle ; Same as Multicycle ; ; ; ; ; Cut paths between unrelated clock domains ; On ; ; ; ; ; Cut off read during write signal paths ; On ; ; ; ; ; Cut off feedback from I/O pins ; On ; ; ; ; ; Report Combined Fast/Slow Timing ; Off ; ; ; ; ; Ignore Clock Settings ; Off ; ; ; ; ; Analyze latches as synchronous elements ; On ; ; ; ; ; Enable Recovery/Removal analysis ; Off ; ; ; ; ; Enable Clock Latency ; Off ; ; ; ; ; Use TimeQuest Timing Analyzer ; Off ; ; ; ; ; Minimum Core Junction Temperature ; 0 ; ; ; ; ; Maximum Core Junction Temperature ; 85 ; ; ; ; ; Number of source nodes to report per destination node ; 10 ; ; ; ; ; Number of destination nodes to report ; 10 ; ; ; ; ; Number of paths to report ; 200 ; ; ; ; ; Report Minimum Timing Checks ; Off ; ; ; ; ; Use Fast Timing Models ; Off ; ; ; ; ; Report IO Paths Separately ; Off ; ; ; ; ; Perform Multicorner Analysis ; On ; ; ; ; ; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ; ; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ; ; Output I/O Timing Endpoint ; Near End ; ; ; ; +---------------------------------------------------------------------+--------------------+------+----+-------------+ +------------------------------------------+ ; Parallel Compilation ; +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ ; Number detected on machine ; 6 ; ; Maximum allowed ; 4 ; ; ; ; ; Average used ; 1.00 ; ; Maximum used ; 1 ; ; ; ; ; Usage by Processor ; % Time Used ; ; 1 processor ; 100.0% ; ; 2-6 processors ; 0.0% ; +----------------------------+-------------+ +---------------------------------------------------------+ ; tpd ; +-------+-------------------+-----------------+------+----+ ; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ; +-------+-------------------+-----------------+------+----+ ; N/A ; None ; 15.646 ns ; LM ; Y6 ; ; N/A ; None ; 15.635 ns ; DM ; Y4 ; ; N/A ; None ; 15.562 ns ; LM ; Y4 ; ; N/A ; None ; 15.337 ns ; A6 ; Y6 ; ; N/A ; None ; 15.239 ns ; DM ; Y6 ; ; N/A ; None ; 15.230 ns ; DM ; Y0 ; ; N/A ; None ; 15.217 ns ; DM ; Y5 ; ; N/A ; None ; 15.211 ns ; DM ; Y1 ; ; N/A ; None ; 15.186 ns ; DM ; Y2 ; ; N/A ; None ; 15.161 ns ; LM ; Y0 ; ; N/A ; None ; 15.148 ns ; LM ; Y5 ; ; N/A ; None ; 15.141 ns ; LM ; Y1 ; ; N/A ; None ; 15.115 ns ; LM ; Y2 ; ; N/A ; None ; 14.955 ns ; L ; Y0 ; ; N/A ; None ; 14.954 ns ; A3 ; Y4 ; ; N/A ; None ; 14.878 ns ; LM ; Y7 ; ; N/A ; None ; 14.829 ns ; A6 ; Y7 ; ; N/A ; None ; 14.828 ns ; A7 ; Y7 ; ; N/A ; None ; 14.763 ns ; A4 ; Y4 ; ; N/A ; None ; 14.737 ns ; A0 ; Y0 ; ; N/A ; None ; 14.726 ns ; DM ; Y7 ; ; N/A ; None ; 14.719 ns ; A0 ; Y1 ; ; N/A ; None ; 14.714 ns ; A5 ; Y6 ; ; N/A ; None ; 14.704 ns ; DM ; Y3 ; ; N/A ; None ; 14.631 ns ; LM ; Y3 ; ; N/A ; None ; 14.548 ns ; A2 ; Y2 ; ; N/A ; None ; 14.509 ns ; A1 ; Y1 ; ; N/A ; None ; 14.487 ns ; A1 ; Y2 ; ; N/A ; None ; 14.397 ns ; R ; Y7 ; ; N/A ; None ; 14.391 ns ; RM ; Y6 ; ; N/A ; None ; 14.373 ns ; RM ; Y4 ; ; N/A ; None ; 14.365 ns ; RM ; Y7 ; ; N/A ; None ; 14.346 ns ; A4 ; Y5 ; ; N/A ; None ; 14.300 ns ; A7 ; Y6 ; ; N/A ; None ; 14.259 ns ; RM ; Y1 ; ; N/A ; None ; 14.215 ns ; A5 ; Y5 ; ; N/A ; None ; 14.066 ns ; A2 ; Y3 ; ; N/A ; None ; 14.002 ns ; RM ; Y5 ; ; N/A ; None ; 13.950 ns ; A5 ; Y4 ; ; N/A ; None ; 13.923 ns ; RM ; Y2 ; ; N/A ; None ; 13.902 ns ; RM ; Y0 ; ; N/A ; None ; 13.836 ns ; A3 ; Y3 ; ; N/A ; None ; 13.818 ns ; A3 ; Y2 ; ; N/A ; None ; 13.589 ns ; A2 ; Y1 ; ; N/A ; None ; 13.485 ns ; A6 ; Y5 ; ; N/A ; None ; 13.479 ns ; A1 ; Y0 ; ; N/A ; None ; 13.437 ns ; RM ; Y3 ; ; N/A ; None ; 12.844 ns ; A4 ; Y3 ; +-------+-------------------+-----------------+------+----+ +--------------------------+ ; Timing Analyzer Messages ; +--------------------------+ Info: ******************************************************************* Info: Running Quartus II Classic Timing Analyzer Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition Info: Processing started: Thu Mar 10 14:51:56 2022 Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only Info: Parallel compilation is enabled and will use 4 of the 6 processors detected Info: Longest tpd from source pin "LM" to destination pin "Y6" is 15.646 ns Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_69; Fanout = 8; PIN Node = 'LM' Info: 2: + IC(6.993 ns) + CELL(0.624 ns) = 8.611 ns; Loc. = LCCOMB_X21_Y10_N24; Fanout = 1; COMB Node = 'triple_selector_8b:inst|inst27~0' Info: 3: + IC(0.395 ns) + CELL(0.651 ns) = 9.657 ns; Loc. = LCCOMB_X21_Y10_N18; Fanout = 1; COMB Node = 'triple_selector_8b:inst|inst27' Info: 4: + IC(2.873 ns) + CELL(3.116 ns) = 15.646 ns; Loc. = PIN_149; Fanout = 0; PIN Node = 'Y6' Info: Total cell delay = 5.385 ns ( 34.42 % ) Info: Total interconnect delay = 10.261 ns ( 65.58 % ) Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings Info: Peak virtual memory: 191 megabytes Info: Processing ended: Thu Mar 10 14:51:56 2022 Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:00