215 行
14 KiB
Plaintext
215 行
14 KiB
Plaintext
Classic Timing Analyzer report for register_8b
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Tue Mar 08 15:08:53 2022
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Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Timing Analyzer Summary
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3. Timing Analyzer Settings
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4. Clock Settings Summary
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5. Parallel Compilation
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6. tsu
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7. tco
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8. th
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9. Timing Analyzer Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2009 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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applicable agreement for further details.
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+---------------------------------------------------------------------------------------------------------------------------+
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; Timing Analyzer Summary ;
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+------------------------------+-------+---------------+-------------+-------+-------+------------+----------+--------------+
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; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
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+------------------------------+-------+---------------+-------------+-------+-------+------------+----------+--------------+
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; Worst-case tsu ; N/A ; None ; 3.273 ns ; D0 ; inst8 ; -- ; CP ; 0 ;
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; Worst-case tco ; N/A ; None ; 11.227 ns ; inst3 ; Q5 ; CP ; -- ; 0 ;
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; Worst-case th ; N/A ; None ; -2.294 ns ; D5 ; inst3 ; -- ; CP ; 0 ;
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; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
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+------------------------------+-------+---------------+-------------+-------+-------+------------+----------+--------------+
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+--------------------------------------------------------------------------------------------------------------------+
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; Timing Analyzer Settings ;
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+---------------------------------------------------------------------+--------------------+------+----+-------------+
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; Option ; Setting ; From ; To ; Entity Name ;
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+---------------------------------------------------------------------+--------------------+------+----+-------------+
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; Device Name ; EP2C8Q208C8 ; ; ; ;
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; Timing Models ; Final ; ; ; ;
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; Default hold multicycle ; Same as Multicycle ; ; ; ;
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; Cut paths between unrelated clock domains ; On ; ; ; ;
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; Cut off read during write signal paths ; On ; ; ; ;
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; Cut off feedback from I/O pins ; On ; ; ; ;
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; Report Combined Fast/Slow Timing ; Off ; ; ; ;
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; Ignore Clock Settings ; Off ; ; ; ;
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; Analyze latches as synchronous elements ; On ; ; ; ;
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; Enable Recovery/Removal analysis ; Off ; ; ; ;
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; Enable Clock Latency ; Off ; ; ; ;
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; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
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; Minimum Core Junction Temperature ; 0 ; ; ; ;
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; Maximum Core Junction Temperature ; 85 ; ; ; ;
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; Number of source nodes to report per destination node ; 10 ; ; ; ;
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; Number of destination nodes to report ; 10 ; ; ; ;
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; Number of paths to report ; 200 ; ; ; ;
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; Report Minimum Timing Checks ; Off ; ; ; ;
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; Use Fast Timing Models ; Off ; ; ; ;
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; Report IO Paths Separately ; Off ; ; ; ;
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; Perform Multicorner Analysis ; On ; ; ; ;
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; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
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; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
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; Output I/O Timing Endpoint ; Near End ; ; ; ;
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+---------------------------------------------------------------------+--------------------+------+----+-------------+
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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Clock Settings Summary ;
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+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
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; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
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+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
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; CP ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
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+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
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+------------------------------------------+
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; Parallel Compilation ;
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+----------------------------+-------------+
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; Processors ; Number ;
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+----------------------------+-------------+
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; Number detected on machine ; 4 ;
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; Maximum allowed ; 4 ;
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; ; ;
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; Average used ; 1.00 ;
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; Maximum used ; 1 ;
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; ; ;
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; Usage by Processor ; % Time Used ;
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; 1 processor ; 100.0% ;
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; 2-4 processors ; 0.0% ;
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+----------------------------+-------------+
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+-------------------------------------------------------------+
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; tsu ;
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+-------+--------------+------------+------+-------+----------+
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; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
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+-------+--------------+------------+------+-------+----------+
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; N/A ; None ; 3.273 ns ; D0 ; inst8 ; CP ;
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; N/A ; None ; 2.730 ns ; D3 ; inst5 ; CP ;
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; N/A ; None ; 2.724 ns ; D7 ; inst ; CP ;
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; N/A ; None ; 2.599 ns ; D1 ; inst7 ; CP ;
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; N/A ; None ; 2.597 ns ; D2 ; inst6 ; CP ;
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; N/A ; None ; 2.569 ns ; D6 ; inst2 ; CP ;
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; N/A ; None ; 2.567 ns ; D4 ; inst4 ; CP ;
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; N/A ; None ; 2.560 ns ; D5 ; inst3 ; CP ;
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+-------+--------------+------------+------+-------+----------+
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+-------------------------------------------------------------+
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; tco ;
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+-------+--------------+------------+-------+----+------------+
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; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
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+-------+--------------+------------+-------+----+------------+
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; N/A ; None ; 11.227 ns ; inst3 ; Q5 ; CP ;
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; N/A ; None ; 11.226 ns ; inst2 ; Q6 ; CP ;
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; N/A ; None ; 11.174 ns ; inst5 ; Q3 ; CP ;
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; N/A ; None ; 11.161 ns ; inst4 ; Q4 ; CP ;
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; N/A ; None ; 11.157 ns ; inst ; Q7 ; CP ;
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; N/A ; None ; 10.809 ns ; inst8 ; Q0 ; CP ;
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; N/A ; None ; 10.781 ns ; inst7 ; Q1 ; CP ;
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; N/A ; None ; 10.767 ns ; inst6 ; Q2 ; CP ;
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+-------+--------------+------------+-------+----+------------+
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+-------------------------------------------------------------------+
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; th ;
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+---------------+-------------+-----------+------+-------+----------+
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; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
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+---------------+-------------+-----------+------+-------+----------+
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; N/A ; None ; -2.294 ns ; D5 ; inst3 ; CP ;
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; N/A ; None ; -2.301 ns ; D4 ; inst4 ; CP ;
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; N/A ; None ; -2.303 ns ; D6 ; inst2 ; CP ;
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; N/A ; None ; -2.331 ns ; D2 ; inst6 ; CP ;
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; N/A ; None ; -2.333 ns ; D1 ; inst7 ; CP ;
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; N/A ; None ; -2.458 ns ; D7 ; inst ; CP ;
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; N/A ; None ; -2.464 ns ; D3 ; inst5 ; CP ;
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; N/A ; None ; -3.007 ns ; D0 ; inst8 ; CP ;
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+---------------+-------------+-----------+------+-------+----------+
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+--------------------------+
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; Timing Analyzer Messages ;
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+--------------------------+
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Info: *******************************************************************
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Info: Running Quartus II Classic Timing Analyzer
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Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
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Info: Processing started: Tue Mar 08 15:08:53 2022
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Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off register_8b -c register_8b --timing_analysis_only
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Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
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Warning: Found pins functioning as undefined clocks and/or memory enables
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Info: Assuming node "CP" is an undefined clock
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Info: No valid register-to-register data paths exist for clock "CP"
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Info: tsu for register "inst8" (data pin = "D0", clock pin = "CP") is 3.273 ns
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Info: + Longest pin to register delay is 7.692 ns
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Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_77; Fanout = 1; PIN Node = 'D0'
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Info: 2: + IC(6.404 ns) + CELL(0.206 ns) = 7.584 ns; Loc. = LCCOMB_X25_Y1_N22; Fanout = 1; COMB Node = 'inst8~feeder'
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Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.692 ns; Loc. = LCFF_X25_Y1_N23; Fanout = 1; REG Node = 'inst8'
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Info: Total cell delay = 1.288 ns ( 16.74 % )
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Info: Total interconnect delay = 6.404 ns ( 83.26 % )
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Info: + Micro setup delay of destination is -0.040 ns
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Info: - Shortest clock path from clock "CP" to destination register is 4.379 ns
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Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'
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Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N23; Fanout = 1; REG Node = 'inst8'
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Info: Total cell delay = 1.660 ns ( 37.91 % )
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Info: Total interconnect delay = 2.719 ns ( 62.09 % )
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Info: tco from clock "CP" to destination pin "Q5" through register "inst3" is 11.227 ns
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Info: + Longest clock path from clock "CP" to source register is 4.379 ns
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Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'
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Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'
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Info: Total cell delay = 1.660 ns ( 37.91 % )
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Info: Total interconnect delay = 2.719 ns ( 62.09 % )
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Info: + Micro clock to output delay of source is 0.304 ns
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Info: + Longest register to pin delay is 6.544 ns
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Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'
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Info: 2: + IC(3.428 ns) + CELL(3.116 ns) = 6.544 ns; Loc. = PIN_147; Fanout = 0; PIN Node = 'Q5'
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Info: Total cell delay = 3.116 ns ( 47.62 % )
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Info: Total interconnect delay = 3.428 ns ( 52.38 % )
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Info: th for register "inst3" (data pin = "D5", clock pin = "CP") is -2.294 ns
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Info: + Longest clock path from clock "CP" to destination register is 4.379 ns
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Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'
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Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'
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Info: Total cell delay = 1.660 ns ( 37.91 % )
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Info: Total interconnect delay = 2.719 ns ( 62.09 % )
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Info: + Micro hold delay of destination is 0.306 ns
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Info: - Shortest pin to register delay is 6.979 ns
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Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_86; Fanout = 1; PIN Node = 'D5'
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Info: 2: + IC(5.701 ns) + CELL(0.206 ns) = 6.871 ns; Loc. = LCCOMB_X25_Y1_N28; Fanout = 1; COMB Node = 'inst3~feeder'
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Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 6.979 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'
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Info: Total cell delay = 1.278 ns ( 18.31 % )
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Info: Total interconnect delay = 5.701 ns ( 81.69 % )
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Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
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Info: Peak virtual memory: 212 megabytes
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Info: Processing ended: Tue Mar 08 15:08:53 2022
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Info: Elapsed time: 00:00:00
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Info: Total CPU time (on all processors): 00:00:00
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