86 行
3.9 KiB
Plaintext
86 行
3.9 KiB
Plaintext
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2009 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II
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# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
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# Date created = 19:33:16 May 18, 2022
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# test_MDR_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone II"
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set_global_assignment -name DEVICE EP2C8Q208C8
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set_global_assignment -name TOP_LEVEL_ENTITY test_MDR
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:33:16 MAY 18, 2022"
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set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2"
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set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
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set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
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set_global_assignment -name BDF_FILE test_MDR.bdf
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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set_location_assignment PIN_69 -to 1BUS2MDR
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set_location_assignment PIN_77 -to Z0
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set_location_assignment PIN_80 -to Z1
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set_location_assignment PIN_81 -to Z2
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set_location_assignment PIN_82 -to Z3
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set_location_assignment PIN_84 -to Z4
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set_location_assignment PIN_86 -to Z5
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set_location_assignment PIN_87 -to Z6
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set_location_assignment PIN_88 -to Z7
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set_location_assignment PIN_142 -to MDR0
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set_location_assignment PIN_143 -to MDR1
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set_location_assignment PIN_144 -to MDR2
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set_location_assignment PIN_145 -to MDR3
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set_location_assignment PIN_146 -to MDR4
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set_location_assignment PIN_147 -to MDR5
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set_location_assignment PIN_149 -to MDR6
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set_location_assignment PIN_150 -to MDR7
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set_location_assignment PIN_168 -to RAM0
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set_location_assignment PIN_169 -to RAM1
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set_location_assignment PIN_170 -to RAM2
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set_location_assignment PIN_171 -to RAM3
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set_location_assignment PIN_173 -to RAM4
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set_location_assignment PIN_175 -to RAM5
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set_location_assignment PIN_176 -to RAM6
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set_location_assignment PIN_179 -to RAM7
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set_global_assignment -name MISC_FILE "D:/projects/quartus/test_MDR/test_MDR.dpf"
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set_location_assignment PIN_68 -to CLR
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set_location_assignment PIN_67 -to CP
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set_location_assignment PIN_70 -to RD
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set_location_assignment PIN_72 -to WR
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set_location_assignment PIN_63 -to RD_N
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set_location_assignment PIN_64 -to WR_N |