150 行
9.3 KiB
Plaintext
150 行
9.3 KiB
Plaintext
Classic Timing Analyzer report for 38_decoder
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Tue Mar 08 15:12:42 2022
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Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Timing Analyzer Summary
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3. Timing Analyzer Settings
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4. Parallel Compilation
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5. tpd
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6. Timing Analyzer Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2009 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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applicable agreement for further details.
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+-----------------------------------------------------------------------------------------------------------------------+
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; Timing Analyzer Summary ;
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+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
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; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
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+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
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; Worst-case tpd ; N/A ; None ; 13.172 ns ; I2 ; Y4 ; -- ; -- ; 0 ;
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; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
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+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
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+--------------------------------------------------------------------------------------------------------------------+
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; Timing Analyzer Settings ;
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+---------------------------------------------------------------------+--------------------+------+----+-------------+
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; Option ; Setting ; From ; To ; Entity Name ;
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+---------------------------------------------------------------------+--------------------+------+----+-------------+
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; Device Name ; EP2C8Q208C8 ; ; ; ;
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; Timing Models ; Final ; ; ; ;
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; Default hold multicycle ; Same as Multicycle ; ; ; ;
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; Cut paths between unrelated clock domains ; On ; ; ; ;
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; Cut off read during write signal paths ; On ; ; ; ;
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; Cut off feedback from I/O pins ; On ; ; ; ;
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; Report Combined Fast/Slow Timing ; Off ; ; ; ;
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; Ignore Clock Settings ; Off ; ; ; ;
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; Analyze latches as synchronous elements ; On ; ; ; ;
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; Enable Recovery/Removal analysis ; Off ; ; ; ;
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; Enable Clock Latency ; Off ; ; ; ;
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; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
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; Minimum Core Junction Temperature ; 0 ; ; ; ;
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; Maximum Core Junction Temperature ; 85 ; ; ; ;
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; Number of source nodes to report per destination node ; 10 ; ; ; ;
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; Number of destination nodes to report ; 10 ; ; ; ;
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; Number of paths to report ; 200 ; ; ; ;
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; Report Minimum Timing Checks ; Off ; ; ; ;
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; Use Fast Timing Models ; Off ; ; ; ;
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; Report IO Paths Separately ; Off ; ; ; ;
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; Perform Multicorner Analysis ; On ; ; ; ;
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; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
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; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
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; Output I/O Timing Endpoint ; Near End ; ; ; ;
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+---------------------------------------------------------------------+--------------------+------+----+-------------+
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+------------------------------------------+
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; Parallel Compilation ;
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+----------------------------+-------------+
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; Processors ; Number ;
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+----------------------------+-------------+
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; Number detected on machine ; 4 ;
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; Maximum allowed ; 4 ;
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; ; ;
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; Average used ; 1.00 ;
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; Maximum used ; 1 ;
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; ; ;
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; Usage by Processor ; % Time Used ;
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; 1 processor ; 100.0% ;
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; 2-4 processors ; 0.0% ;
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+----------------------------+-------------+
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+---------------------------------------------------------+
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; tpd ;
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+-------+-------------------+-----------------+------+----+
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; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
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+-------+-------------------+-----------------+------+----+
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; N/A ; None ; 13.172 ns ; I2 ; Y4 ;
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; N/A ; None ; 13.161 ns ; I2 ; Y6 ;
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; N/A ; None ; 13.141 ns ; I2 ; Y5 ;
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; N/A ; None ; 13.095 ns ; I2 ; Y7 ;
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; N/A ; None ; 13.009 ns ; I2 ; Y3 ;
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; N/A ; None ; 12.995 ns ; I2 ; Y0 ;
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; N/A ; None ; 12.674 ns ; I1 ; Y6 ;
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; N/A ; None ; 12.658 ns ; I0 ; Y5 ;
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; N/A ; None ; 12.658 ns ; I1 ; Y4 ;
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; N/A ; None ; 12.648 ns ; I1 ; Y3 ;
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; N/A ; None ; 12.647 ns ; I2 ; Y1 ;
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; N/A ; None ; 12.636 ns ; I0 ; Y3 ;
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; N/A ; None ; 12.623 ns ; I1 ; Y7 ;
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; N/A ; None ; 12.619 ns ; I0 ; Y7 ;
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; N/A ; None ; 12.614 ns ; I0 ; Y4 ;
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; N/A ; None ; 12.612 ns ; I1 ; Y5 ;
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; N/A ; None ; 12.594 ns ; I0 ; Y6 ;
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; N/A ; None ; 12.580 ns ; I1 ; Y0 ;
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; N/A ; None ; 12.560 ns ; I2 ; Y2 ;
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; N/A ; None ; 12.535 ns ; I0 ; Y0 ;
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; N/A ; None ; 12.270 ns ; I0 ; Y1 ;
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; N/A ; None ; 12.241 ns ; I1 ; Y1 ;
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; N/A ; None ; 12.201 ns ; I1 ; Y2 ;
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; N/A ; None ; 12.104 ns ; I0 ; Y2 ;
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+-------+-------------------+-----------------+------+----+
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+--------------------------+
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; Timing Analyzer Messages ;
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+--------------------------+
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Info: *******************************************************************
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Info: Running Quartus II Classic Timing Analyzer
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Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
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Info: Processing started: Tue Mar 08 15:12:42 2022
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Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off 38_decoder -c 38_decoder --timing_analysis_only
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Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
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Info: Longest tpd from source pin "I2" to destination pin "Y4" is 13.172 ns
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Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_81; Fanout = 8; PIN Node = 'I2'
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Info: 2: + IC(7.387 ns) + CELL(0.651 ns) = 9.012 ns; Loc. = LCCOMB_X33_Y13_N2; Fanout = 1; COMB Node = 'inst10~5'
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Info: 3: + IC(1.054 ns) + CELL(3.106 ns) = 13.172 ns; Loc. = PIN_146; Fanout = 0; PIN Node = 'Y4'
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Info: Total cell delay = 4.731 ns ( 35.92 % )
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Info: Total interconnect delay = 8.441 ns ( 64.08 % )
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Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
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Info: Peak virtual memory: 212 megabytes
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Info: Processing ended: Tue Mar 08 15:12:42 2022
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Info: Elapsed time: 00:00:00
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Info: Total CPU time (on all processors): 00:00:00
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