11 行
21 KiB
Plaintext
11 行
21 KiB
Plaintext
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:08:53 2022 " "Info: Processing started: Tue Mar 08 15:08:53 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off register_8b -c register_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off register_8b -c register_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CP " "Info: Assuming node \"CP\" is an undefined clock" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } { "d:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CP" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
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{ "Info" "ITAN_NO_REG2REG_EXIST" "CP " "Info: No valid register-to-register data paths exist for clock \"CP\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0 -1}
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{ "Info" "ITDB_TSU_RESULT" "inst8 D0 CP 3.273 ns register " "Info: tsu for register \"inst8\" (data pin = \"D0\", clock pin = \"CP\") is 3.273 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.692 ns + Longest pin register " "Info: + Longest pin to register delay is 7.692 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns D0 1 PIN PIN_77 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_77; Fanout = 1; PIN Node = 'D0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { D0 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 752 32 200 768 "D0" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.404 ns) + CELL(0.206 ns) 7.584 ns inst8~feeder 2 COMB LCCOMB_X25_Y1_N22 1 " "Info: 2: + IC(6.404 ns) + CELL(0.206 ns) = 7.584 ns; Loc. = LCCOMB_X25_Y1_N22; Fanout = 1; COMB Node = 'inst8~feeder'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.610 ns" { D0 inst8~feeder } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 736 344 408 816 "inst8" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.692 ns inst8 3 REG LCFF_X25_Y1_N23 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.692 ns; Loc. = LCFF_X25_Y1_N23; Fanout = 1; REG Node = 'inst8'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { inst8~feeder inst8 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 736 344 408 816 "inst8" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.288 ns ( 16.74 % ) " "Info: Total cell delay = 1.288 ns ( 16.74 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.404 ns ( 83.26 % ) " "Info: Total interconnect delay = 6.404 ns ( 83.26 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.692 ns" { D0 inst8~feeder inst8 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "7.692 ns" { D0 {} D0~combout {} inst8~feeder {} inst8 {} } { 0.000ns 0.000ns 6.404ns 0.000ns } { 0.000ns 0.974ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 736 344 408 816 "inst8" "" } } } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CP destination 4.379 ns - Shortest register " "Info: - Shortest clock path from clock \"CP\" to destination register is 4.379 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns CP 1 CLK PIN_67 8 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CP } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.719 ns) + CELL(0.666 ns) 4.379 ns inst8 2 REG LCFF_X25_Y1_N23 1 " "Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N23; Fanout = 1; REG Node = 'inst8'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.385 ns" { CP inst8 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 736 344 408 816 "inst8" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 37.91 % ) " "Info: Total cell delay = 1.660 ns ( 37.91 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.719 ns ( 62.09 % ) " "Info: Total interconnect delay = 2.719 ns ( 62.09 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst8 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst8 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.692 ns" { D0 inst8~feeder inst8 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "7.692 ns" { D0 {} D0~combout {} inst8~feeder {} inst8 {} } { 0.000ns 0.000ns 6.404ns 0.000ns } { 0.000ns 0.974ns 0.206ns 0.108ns } "" } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst8 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst8 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
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{ "Info" "ITDB_FULL_TCO_RESULT" "CP Q5 inst3 11.227 ns register " "Info: tco from clock \"CP\" to destination pin \"Q5\" through register \"inst3\" is 11.227 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CP source 4.379 ns + Longest register " "Info: + Longest clock path from clock \"CP\" to source register is 4.379 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns CP 1 CLK PIN_67 8 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CP } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.719 ns) + CELL(0.666 ns) 4.379 ns inst3 2 REG LCFF_X25_Y1_N29 1 " "Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.385 ns" { CP inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 37.91 % ) " "Info: Total cell delay = 1.660 ns ( 37.91 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.719 ns ( 62.09 % ) " "Info: Total interconnect delay = 2.719 ns ( 62.09 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst3 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.544 ns + Longest register pin " "Info: + Longest register to pin delay is 6.544 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst3 1 REG LCFF_X25_Y1_N29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.428 ns) + CELL(3.116 ns) 6.544 ns Q5 2 PIN PIN_147 0 " "Info: 2: + IC(3.428 ns) + CELL(3.116 ns) = 6.544 ns; Loc. = PIN_147; Fanout = 0; PIN Node = 'Q5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.544 ns" { inst3 Q5 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 272 464 640 288 "Q5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.116 ns ( 47.62 % ) " "Info: Total cell delay = 3.116 ns ( 47.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.428 ns ( 52.38 % ) " "Info: Total interconnect delay = 3.428 ns ( 52.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.544 ns" { inst3 Q5 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.544 ns" { inst3 {} Q5 {} } { 0.000ns 3.428ns } { 0.000ns 3.116ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst3 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.544 ns" { inst3 Q5 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.544 ns" { inst3 {} Q5 {} } { 0.000ns 3.428ns } { 0.000ns 3.116ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
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{ "Info" "ITDB_TH_RESULT" "inst3 D5 CP -2.294 ns register " "Info: th for register \"inst3\" (data pin = \"D5\", clock pin = \"CP\") is -2.294 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CP destination 4.379 ns + Longest register " "Info: + Longest clock path from clock \"CP\" to destination register is 4.379 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns CP 1 CLK PIN_67 8 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CP } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 40 32 200 56 "CP" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.719 ns) + CELL(0.666 ns) 4.379 ns inst3 2 REG LCFF_X25_Y1_N29 1 " "Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.385 ns" { CP inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 37.91 % ) " "Info: Total cell delay = 1.660 ns ( 37.91 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.719 ns ( 62.09 % ) " "Info: Total interconnect delay = 2.719 ns ( 62.09 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst3 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" { } { { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.979 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.979 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.964 ns) 0.964 ns D5 1 PIN PIN_86 1 " "Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_86; Fanout = 1; PIN Node = 'D5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { D5 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 272 32 200 288 "D5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.701 ns) + CELL(0.206 ns) 6.871 ns inst3~feeder 2 COMB LCCOMB_X25_Y1_N28 1 " "Info: 2: + IC(5.701 ns) + CELL(0.206 ns) = 6.871 ns; Loc. = LCCOMB_X25_Y1_N28; Fanout = 1; COMB Node = 'inst3~feeder'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.907 ns" { D5 inst3~feeder } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 6.979 ns inst3 3 REG LCFF_X25_Y1_N29 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 6.979 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { inst3~feeder inst3 } "NODE_NAME" } } { "register_8b.bdf" "" { Schematic "D:/projects/quartus/register_8b/register_8b.bdf" { { 256 344 408 336 "inst3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.278 ns ( 18.31 % ) " "Info: Total cell delay = 1.278 ns ( 18.31 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.701 ns ( 81.69 % ) " "Info: Total interconnect delay = 5.701 ns ( 81.69 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.979 ns" { D5 inst3~feeder inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.979 ns" { D5 {} D5~combout {} inst3~feeder {} inst3 {} } { 0.000ns 0.000ns 5.701ns 0.000ns } { 0.000ns 0.964ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.379 ns" { CP inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "4.379 ns" { CP {} CP~combout {} inst3 {} } { 0.000ns 0.000ns 2.719ns } { 0.000ns 0.994ns 0.666ns } "" } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.979 ns" { D5 inst3~feeder inst3 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "6.979 ns" { D5 {} D5~combout {} inst3~feeder {} inst3 {} } { 0.000ns 0.000ns 5.701ns 0.000ns } { 0.000ns 0.964ns 0.206ns 0.108ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
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{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:08:53 2022 " "Info: Processing ended: Tue Mar 08 15:08:53 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
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