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為double_selector_8b指定引腳

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juzeon 2022-03-07 11:23:35 +08:00
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10
README.md
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8位数据选择器（二选一）。
引脚分配：
```
K0~K7: a0~a7
K8~K15: b0~b7
K16: AY
K17: BY
LR0~LR7: Y0~Y7
```
### register_8b
8位寄存器。

4
double_selector_8b/db/double_selector_8b.asm.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:07:55 2022 " "Info: Processing started: Mon Mar 07 11:07:55 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:22:46 2022 " "Info: Processing started: Mon Mar 07 11:22:46 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:07:56 2022 " "Info: Processing ended: Mon Mar 07 11:07:56 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:22:46 2022 " "Info: Processing ended: Mon Mar 07 11:22:46 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

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double_selector_8b/db/double_selector_8b.asm_labs.ddb
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double_selector_8b/db/double_selector_8b.cmp.bpm
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double_selector_8b/db/double_selector_8b.cmp.cdb
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double_selector_8b/db/double_selector_8b.cmp.hdb
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double_selector_8b/db/double_selector_8b.cmp.rdb
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double_selector_8b/db/double_selector_8b.cmp.tdb
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double_selector_8b/db/double_selector_8b.cmp0.ddb
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double_selector_8b/db/double_selector_8b.cmp2.ddb
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double_selector_8b/db/double_selector_8b.fit.qmsg
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double_selector_8b/db/double_selector_8b.map.bpm
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double_selector_8b/db/double_selector_8b.map.cdb
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double_selector_8b/db/double_selector_8b.map.hdb
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double_selector_8b/db/double_selector_8b.map.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:07:52 2022 " "Info: Processing started: Mon Mar 07 11:07:52 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:22:43 2022 " "Info: Processing started: Mon Mar 07 11:22:43 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off double_selector_8b -c double_selector_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off double_selector_8b -c double_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "double_selector_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file double_selector_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 double_selector_8b " "Info: Found entity 1: double_selector_8b" { } { { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "double_selector_8b " "Info: Elaborating entity \"double_selector_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "34 " "Info: Implemented 34 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "18 " "Info: Implemented 18 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "248 " "Info: Peak virtual memory: 248 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:07:53 2022 " "Info: Processing ended: Mon Mar 07 11:07:53 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:22:43 2022 " "Info: Processing ended: Mon Mar 07 11:22:43 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

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double_selector_8b/db/double_selector_8b.map_bb.cdb
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double_selector_8b/db/double_selector_8b.map_bb.hdb
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double_selector_8b/db/double_selector_8b.pre_map.cdb
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double_selector_8b/db/double_selector_8b.pre_map.hdb
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double_selector_8b/db/double_selector_8b.rtlv.hdb
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double_selector_8b/db/double_selector_8b.rtlv_sg.cdb
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double_selector_8b/db/double_selector_8b.sgdiff.cdb
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double_selector_8b/db/double_selector_8b.sgdiff.hdb
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double_selector_8b/db/double_selector_8b.tan.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:07:57 2022 " "Info: Processing started: Mon Mar 07 11:07:57 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:22:47 2022 " "Info: Processing started: Mon Mar 07 11:22:47 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TPD_RESULT" "b5 Y5 12.694 ns Longest " "Info: Longest tpd from source pin \"b5\" to destination pin \"Y5\" is 12.694 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns b5 1 PIN PIN_45 1 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_45; Fanout = 1; PIN Node = 'b5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b5 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 640 64 232 656 "b5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.147 ns) + CELL(0.624 ns) 7.766 ns inst6 2 COMB LCCOMB_X1_Y9_N26 1 " "Info: 2: + IC(6.147 ns) + CELL(0.624 ns) = 7.766 ns; Loc. = LCCOMB_X1_Y9_N26; Fanout = 1; COMB Node = 'inst6'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.771 ns" { b5 inst6 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 336 664 728 384 "inst6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.642 ns) + CELL(3.286 ns) 12.694 ns Y5 3 PIN PIN_208 0 " "Info: 3: + IC(1.642 ns) + CELL(3.286 ns) = 12.694 ns; Loc. = PIN_208; Fanout = 0; PIN Node = 'Y5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.928 ns" { inst6 Y5 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 352 816 992 368 "Y5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.905 ns ( 38.64 % ) " "Info: Total cell delay = 4.905 ns ( 38.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "7.789 ns ( 61.36 % ) " "Info: Total interconnect delay = 7.789 ns ( 61.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "12.694 ns" { b5 inst6 Y5 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "12.694 ns" { b5 {} b5~combout {} inst6 {} Y5 {} } { 0.000ns 0.000ns 6.147ns 1.642ns } { 0.000ns 0.995ns 0.624ns 3.286ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:07:57 2022 " "Info: Processing ended: Mon Mar 07 11:07:57 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TPD_RESULT" "b6 Y6 14.785 ns Longest " "Info: Longest tpd from source pin \"b6\" to destination pin \"Y6\" is 14.785 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns b6 1 PIN PIN_75 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_75; Fanout = 1; PIN Node = 'b6'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b6 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 664 64 232 680 "b6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.679 ns) + CELL(0.651 ns) 8.304 ns inst7 2 COMB LCCOMB_X25_Y2_N12 1 " "Info: 2: + IC(6.679 ns) + CELL(0.651 ns) = 8.304 ns; Loc. = LCCOMB_X25_Y2_N12; Fanout = 1; COMB Node = 'inst7'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.330 ns" { b6 inst7 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 392 664 728 440 "inst7" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.365 ns) + CELL(3.116 ns) 14.785 ns Y6 3 PIN PIN_149 0 " "Info: 3: + IC(3.365 ns) + CELL(3.116 ns) = 14.785 ns; Loc. = PIN_149; Fanout = 0; PIN Node = 'Y6'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.481 ns" { inst7 Y6 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 408 816 992 424 "Y6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.741 ns ( 32.07 % ) " "Info: Total cell delay = 4.741 ns ( 32.07 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "10.044 ns ( 67.93 % ) " "Info: Total interconnect delay = 10.044 ns ( 67.93 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "14.785 ns" { b6 inst7 Y6 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "14.785 ns" { b6 {} b6~combout {} inst7 {} Y6 {} } { 0.000ns 0.000ns 6.679ns 3.365ns } { 0.000ns 0.974ns 0.651ns 3.116ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:22:47 2022 " "Info: Processing ended: Mon Mar 07 11:22:47 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

6
double_selector_8b/db/double_selector_8b.tmw_info Normal file
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@ -0,0 +1,6 @@
start_full_compilation:s:00:00:05
start_analysis_synthesis:s:00:00:01-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:02-start_full_compilation
start_assembler:s:00:00:01-start_full_compilation
start_timing_analyzer:s:00:00:01-start_full_compilation

7
double_selector_8b/db/prev_cmp_double_selector_8b.asm.qmsg Normal file
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@ -0,0 +1,7 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:20:35 2022 " "Info: Processing started: Mon Mar 07 11:20:35 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:20:36 2022 " "Info: Processing ended: Mon Mar 07 11:20:36 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

36
double_selector_8b/db/prev_cmp_double_selector_8b.fit.qmsg Normal file
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@ -0,0 +1,36 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:20:34 2022 " "Info: Processing started: Mon Mar 07 11:20:34 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "IMPP_MPP_USER_DEVICE" "double_selector_8b EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"double_selector_8b\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y0 X34_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X34_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y0 0 " "Info: Pin \"Y0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y1 0 " "Info: Pin \"Y1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y2 0 " "Info: Pin \"Y2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y3 0 " "Info: Pin \"Y3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y4 0 " "Info: Pin \"Y4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y5 0 " "Info: Pin \"Y5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y6 0 " "Info: Pin \"Y6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y7 0 " "Info: Pin \"Y7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/double_selector_8b/double_selector_8b.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/double_selector_8b/double_selector_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "306 " "Info: Peak virtual memory: 306 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:20:35 2022 " "Info: Processing ended: Mon Mar 07 11:20:35 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

7
double_selector_8b/db/prev_cmp_double_selector_8b.map.qmsg Normal file
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@ -0,0 +1,7 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:20:32 2022 " "Info: Processing started: Mon Mar 07 11:20:32 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off double_selector_8b -c double_selector_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off double_selector_8b -c double_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "double_selector_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file double_selector_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 double_selector_8b " "Info: Found entity 1: double_selector_8b" { } { { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "double_selector_8b " "Info: Elaborating entity \"double_selector_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "34 " "Info: Implemented 34 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "18 " "Info: Implemented 18 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:20:33 2022 " "Info: Processing ended: Mon Mar 07 11:20:33 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

57
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:20:32 2022 " "Info: Processing started: Mon Mar 07 11:20:32 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off double_selector_8b -c double_selector_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off double_selector_8b -c double_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "double_selector_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file double_selector_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 double_selector_8b " "Info: Found entity 1: double_selector_8b" { } { { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "double_selector_8b " "Info: Elaborating entity \"double_selector_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "34 " "Info: Implemented 34 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "18 " "Info: Implemented 18 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:20:33 2022 " "Info: Processing ended: Mon Mar 07 11:20:33 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:20:34 2022 " "Info: Processing started: Mon Mar 07 11:20:34 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "IMPP_MPP_USER_DEVICE" "double_selector_8b EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"double_selector_8b\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y0 X34_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X34_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y0 0 " "Info: Pin \"Y0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y1 0 " "Info: Pin \"Y1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y2 0 " "Info: Pin \"Y2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y3 0 " "Info: Pin \"Y3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y4 0 " "Info: Pin \"Y4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y5 0 " "Info: Pin \"Y5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y6 0 " "Info: Pin \"Y6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y7 0 " "Info: Pin \"Y7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/double_selector_8b/double_selector_8b.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/double_selector_8b/double_selector_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "306 " "Info: Peak virtual memory: 306 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:20:35 2022 " "Info: Processing ended: Mon Mar 07 11:20:35 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:20:35 2022 " "Info: Processing started: Mon Mar 07 11:20:35 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:20:36 2022 " "Info: Processing ended: Mon Mar 07 11:20:36 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:20:37 2022 " "Info: Processing started: Mon Mar 07 11:20:37 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TPD_RESULT" "b6 Y6 14.785 ns Longest " "Info: Longest tpd from source pin \"b6\" to destination pin \"Y6\" is 14.785 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns b6 1 PIN PIN_75 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_75; Fanout = 1; PIN Node = 'b6'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b6 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 664 64 232 680 "b6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.679 ns) + CELL(0.651 ns) 8.304 ns inst7 2 COMB LCCOMB_X25_Y2_N12 1 " "Info: 2: + IC(6.679 ns) + CELL(0.651 ns) = 8.304 ns; Loc. = LCCOMB_X25_Y2_N12; Fanout = 1; COMB Node = 'inst7'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.330 ns" { b6 inst7 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 392 664 728 440 "inst7" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.365 ns) + CELL(3.116 ns) 14.785 ns Y6 3 PIN PIN_149 0 " "Info: 3: + IC(3.365 ns) + CELL(3.116 ns) = 14.785 ns; Loc. = PIN_149; Fanout = 0; PIN Node = 'Y6'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.481 ns" { inst7 Y6 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 408 816 992 424 "Y6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.741 ns ( 32.07 % ) " "Info: Total cell delay = 4.741 ns ( 32.07 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "10.044 ns ( 67.93 % ) " "Info: Total interconnect delay = 10.044 ns ( 67.93 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "14.785 ns" { b6 inst7 Y6 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "14.785 ns" { b6 {} b6~combout {} inst7 {} Y6 {} } { 0.000ns 0.000ns 6.679ns 3.365ns } { 0.000ns 0.974ns 0.651ns 3.116ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:20:37 2022 " "Info: Processing ended: Mon Mar 07 11:20:37 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 2 s " "Info: Quartus II Full Compilation was successful. 0 errors, 2 warnings" { } { } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

6
double_selector_8b/db/prev_cmp_double_selector_8b.tan.qmsg Normal file
查看文件

@ -0,0 +1,6 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:20:37 2022 " "Info: Processing started: Mon Mar 07 11:20:37 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TPD_RESULT" "b6 Y6 14.785 ns Longest " "Info: Longest tpd from source pin \"b6\" to destination pin \"Y6\" is 14.785 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns b6 1 PIN PIN_75 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_75; Fanout = 1; PIN Node = 'b6'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b6 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 664 64 232 680 "b6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.679 ns) + CELL(0.651 ns) 8.304 ns inst7 2 COMB LCCOMB_X25_Y2_N12 1 " "Info: 2: + IC(6.679 ns) + CELL(0.651 ns) = 8.304 ns; Loc. = LCCOMB_X25_Y2_N12; Fanout = 1; COMB Node = 'inst7'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.330 ns" { b6 inst7 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 392 664 728 440 "inst7" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.365 ns) + CELL(3.116 ns) 14.785 ns Y6 3 PIN PIN_149 0 " "Info: 3: + IC(3.365 ns) + CELL(3.116 ns) = 14.785 ns; Loc. = PIN_149; Fanout = 0; PIN Node = 'Y6'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.481 ns" { inst7 Y6 } "NODE_NAME" } } { "double_selector_8b.bdf" "" { Schematic "D:/projects/quartus/double_selector_8b/double_selector_8b.bdf" { { 408 816 992 424 "Y6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.741 ns ( 32.07 % ) " "Info: Total cell delay = 4.741 ns ( 32.07 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "10.044 ns ( 67.93 % ) " "Info: Total interconnect delay = 10.044 ns ( 67.93 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "14.785 ns" { b6 inst7 Y6 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "14.785 ns" { b6 {} b6~combout {} inst7 {} Y6 {} } { 0.000ns 0.000ns 6.679ns 3.365ns } { 0.000ns 0.974ns 0.651ns 3.116ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:20:37 2022 " "Info: Processing ended: Mon Mar 07 11:20:37 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

16
double_selector_8b/double_selector_8b.asm.rpt
查看文件

@ -1,5 +1,5 @@
Assembler report for double_selector_8b
Mon Mar 07 11:07:56 2022
Mon Mar 07 11:22:46 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@ -38,7 +38,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Mon Mar 07 11:07:56 2022 ;
; Assembler Status ; Successful - Mon Mar 07 11:22:46 2022 ;
; Revision Name ; double_selector_8b ;
; Top-level Entity Name ; double_selector_8b ;
; Family ; Cyclone II ;
@ -93,7 +93,7 @@ applicable agreement for further details.
+----------------+------------------------------------------------------------------------+
; Device ; EP2C8Q208C8 ;
; JTAG usercode ; 0xFFFFFFFF ;
; Checksum ; 0x000C6B76 ;
; Checksum ; 0x000C2319 ;
+----------------+------------------------------------------------------------------------+
@ -104,7 +104,7 @@ applicable agreement for further details.
+--------------------+--------------------------------------------------------------------+
; Device ; EPCS4 ;
; JTAG usercode ; 0x00000000 ;
; Checksum ; 0x06F07E62 ;
; Checksum ; 0x06EFE4CF ;
; Compression Ratio ; 3 ;
+--------------------+--------------------------------------------------------------------+
@ -115,15 +115,15 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Mon Mar 07 11:07:55 2022
Info: Processing started: Mon Mar 07 11:22:46 2022
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b
Info: Writing out detailed assembly data for power analysis
Info: Assembler is generating device programming files
Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 241 megabytes
Info: Processing ended: Mon Mar 07 11:07:56 2022
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Info: Processing ended: Mon Mar 07 11:22:46 2022
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00

2
double_selector_8b/double_selector_8b.done
查看文件

@ -1 +1 @@
Mon Mar 07 11:07:57 2022
Mon Mar 07 11:22:47 2022

12
double_selector_8b/double_selector_8b.dpf Normal file
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@ -0,0 +1,12 @@
<?xml version="1.0" encoding="UTF-8"?>
<pin_planner>
<pin_info>
</pin_info>
<buses>
</buses>
<group_file_association>
</group_file_association>
<pin_planner_file_specifies>
</pin_planner_file_specifies>
</pin_planner>

434
double_selector_8b/double_selector_8b.fit.rpt
查看文件

@ -1,5 +1,5 @@
Fitter report for double_selector_8b
Mon Mar 07 11:07:55 2022
Mon Mar 07 11:22:45 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@ -63,7 +63,7 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+----------------------------------------------+
; Fitter Status ; Successful - Mon Mar 07 11:07:54 2022 ;
; Fitter Status ; Successful - Mon Mar 07 11:22:45 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; double_selector_8b ;
; Top-level Entity Name ; double_selector_8b ;
@ -91,6 +91,7 @@ applicable agreement for further details.
; Minimum Core Junction Temperature ; 0 ; ;
; Maximum Core Junction Temperature ; 85 ; ;
; Fit Attempts to Skip ; 0 ; 0.0 ;
; Device I/O Standard ; 3.3-V LVTTL ; ;
; Use smart compilation ; Off ; Off ;
; Use TimeQuest Timing Analyzer ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
@ -216,7 +217,7 @@ The pin-out file can be found in D:/projects/quartus/double_selector_8b/double_s
; User inserted logic elements ; 0 ;
; Virtual pins ; 0 ;
; I/O pins ; 26 / 138 ( 19 % ) ;
; -- Clock pins ; 2 / 4 ( 50 % ) ;
; -- Clock pins ; 1 / 4 ( 25 % ) ;
; Global signals ; 0 ;
; M4Ks ; 0 / 36 ( 0 % ) ;
; Total block memory bits ; 0 / 165,888 ( 0 % ) ;
@ -245,24 +246,24 @@ The pin-out file can be found in D:/projects/quartus/double_selector_8b/double_s
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; AY ; 56 ; 4 ; 1 ; 0 ; 3 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; BY ; 44 ; 1 ; 0 ; 3 ; 1 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; a0 ; 39 ; 1 ; 0 ; 5 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; a1 ; 37 ; 1 ; 0 ; 6 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; a2 ; 24 ; 1 ; 0 ; 9 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; a3 ; 28 ; 1 ; 0 ; 9 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; a4 ; 12 ; 1 ; 0 ; 16 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; a5 ; 31 ; 1 ; 0 ; 8 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; a6 ; 34 ; 1 ; 0 ; 7 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; a7 ; 3 ; 1 ; 0 ; 18 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; b0 ; 40 ; 1 ; 0 ; 5 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; b1 ; 23 ; 1 ; 0 ; 9 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; b2 ; 27 ; 1 ; 0 ; 9 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; b3 ; 59 ; 4 ; 1 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; b4 ; 41 ; 1 ; 0 ; 4 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; b5 ; 45 ; 1 ; 0 ; 3 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; b6 ; 57 ; 4 ; 1 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; b7 ; 33 ; 1 ; 0 ; 8 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; AY ; 23 ; 1 ; 0 ; 9 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
; BY ; 24 ; 1 ; 0 ; 9 ; 1 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
; a0 ; 77 ; 4 ; 18 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
; a1 ; 80 ; 4 ; 23 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
; a2 ; 81 ; 4 ; 23 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
; a3 ; 82 ; 4 ; 23 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
; a4 ; 84 ; 4 ; 25 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
; a5 ; 86 ; 4 ; 25 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
; a6 ; 87 ; 4 ; 25 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
; a7 ; 88 ; 4 ; 25 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
; b0 ; 67 ; 4 ; 9 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
; b1 ; 68 ; 4 ; 12 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
; b2 ; 69 ; 4 ; 12 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
; b3 ; 70 ; 4 ; 14 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
; b4 ; 72 ; 4 ; 16 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
; b5 ; 74 ; 4 ; 16 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
; b6 ; 75 ; 4 ; 16 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
; b7 ; 76 ; 4 ; 18 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
@ -271,14 +272,14 @@ The pin-out file can be found in D:/projects/quartus/double_selector_8b/double_s
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; Y0 ; 58 ; 4 ; 1 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Y1 ; 35 ; 1 ; 0 ; 7 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Y2 ; 14 ; 1 ; 0 ; 14 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Y3 ; 15 ; 1 ; 0 ; 14 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Y4 ; 10 ; 1 ; 0 ; 17 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Y5 ; 208 ; 2 ; 1 ; 19 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Y6 ; 30 ; 1 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Y7 ; 48 ; 1 ; 0 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
; Y0 ; 142 ; 3 ; 34 ; 12 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
; Y1 ; 143 ; 3 ; 34 ; 13 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
; Y2 ; 144 ; 3 ; 34 ; 13 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
; Y3 ; 145 ; 3 ; 34 ; 14 ; 4 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
; Y4 ; 146 ; 3 ; 34 ; 15 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
; Y5 ; 147 ; 3 ; 34 ; 15 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
; Y6 ; 149 ; 3 ; 34 ; 16 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
; Y7 ; 150 ; 3 ; 34 ; 16 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 0 pF ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
@ -287,10 +288,10 @@ The pin-out file can be found in D:/projects/quartus/double_selector_8b/double_s
+----------+------------------+---------------+--------------+
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
+----------+------------------+---------------+--------------+
; 1 ; 23 / 32 ( 72 % ) ; 3.3V ; -- ;
; 2 ; 1 / 35 ( 3 % ) ; 3.3V ; -- ;
; 3 ; 1 / 35 ( 3 % ) ; 3.3V ; -- ;
; 4 ; 4 / 36 ( 11 % ) ; 3.3V ; -- ;
; 1 ; 4 / 32 ( 13 % ) ; 3.3V ; -- ;
; 2 ; 0 / 35 ( 0 % ) ; 3.3V ; -- ;
; 3 ; 9 / 35 ( 26 % ) ; 3.3V ; -- ;
; 4 ; 16 / 36 ( 44 % ) ; 3.3V ; -- ;
+----------+------------------+---------------+--------------+
@ -301,19 +302,19 @@ The pin-out file can be found in D:/projects/quartus/double_selector_8b/double_s
+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; 1 ; 0 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
; 2 ; 1 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
; 3 ; 2 ; 1 ; a7 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 4 ; 3 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 5 ; 4 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 6 ; 5 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 3 ; 2 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 4 ; 3 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 5 ; 4 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 6 ; 5 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 8 ; 6 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 8 ; 6 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 10 ; 7 ; 1 ; Y4 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 11 ; 8 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 12 ; 9 ; 1 ; a4 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 13 ; 10 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 14 ; 18 ; 1 ; Y2 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 15 ; 19 ; 1 ; Y3 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 10 ; 7 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 11 ; 8 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 12 ; 9 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 13 ; 10 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 14 ; 18 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 15 ; 19 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
; 18 ; 22 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
@ -321,32 +322,32 @@ The pin-out file can be found in D:/projects/quartus/double_selector_8b/double_s
; 20 ; 24 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ;
; 21 ; 25 ; 1 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ;
; 22 ; 26 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
; 23 ; 27 ; 1 ; b1 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 24 ; 28 ; 1 ; a2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 23 ; 27 ; 1 ; AY ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 24 ; 28 ; 1 ; BY ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 26 ; 29 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
; 27 ; 30 ; 1 ; b2 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 28 ; 31 ; 1 ; a3 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 27 ; 30 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 28 ; 31 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 30 ; 32 ; 1 ; Y6 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 31 ; 33 ; 1 ; a5 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 30 ; 32 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 31 ; 33 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 33 ; 35 ; 1 ; b7 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 34 ; 36 ; 1 ; a6 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 35 ; 37 ; 1 ; Y1 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 33 ; 35 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 34 ; 36 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 35 ; 37 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 37 ; 39 ; 1 ; a1 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 37 ; 39 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 39 ; 43 ; 1 ; a0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 40 ; 44 ; 1 ; b0 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 41 ; 45 ; 1 ; b4 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 39 ; 43 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 40 ; 44 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 41 ; 45 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 42 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 43 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 44 ; 49 ; 1 ; BY ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 45 ; 50 ; 1 ; b5 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 46 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 47 ; 52 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 48 ; 53 ; 1 ; Y7 ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 43 ; 48 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 44 ; 49 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 45 ; 50 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 46 ; 51 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 47 ; 52 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 48 ; 53 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 49 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 50 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
; 51 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
@ -354,69 +355,69 @@ The pin-out file can be found in D:/projects/quartus/double_selector_8b/double_s
; 53 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 54 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
; 55 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 56 ; 54 ; 4 ; AY ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 57 ; 55 ; 4 ; b6 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 58 ; 56 ; 4 ; Y0 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 59 ; 57 ; 4 ; b3 ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 60 ; 58 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 61 ; 59 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 56 ; 54 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 57 ; 55 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 58 ; 56 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 59 ; 57 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 60 ; 58 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 61 ; 59 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 63 ; 60 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 64 ; 61 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 63 ; 60 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 64 ; 61 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 67 ; 69 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 68 ; 70 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 69 ; 71 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 70 ; 74 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 67 ; 69 ; 4 ; b0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 68 ; 70 ; 4 ; b1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 69 ; 71 ; 4 ; b2 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 70 ; 74 ; 4 ; b3 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 71 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 72 ; 75 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 72 ; 75 ; 4 ; b4 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 74 ; 76 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 75 ; 77 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 76 ; 78 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 77 ; 79 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 74 ; 76 ; 4 ; b5 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 75 ; 77 ; 4 ; b6 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 76 ; 78 ; 4 ; b7 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 77 ; 79 ; 4 ; a0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 80 ; 82 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 81 ; 83 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 82 ; 84 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 80 ; 82 ; 4 ; a1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 81 ; 83 ; 4 ; a2 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 82 ; 84 ; 4 ; a3 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 83 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 84 ; 85 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 84 ; 85 ; 4 ; a4 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 85 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 86 ; 86 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 87 ; 87 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 88 ; 88 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 89 ; 89 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 90 ; 90 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 86 ; 86 ; 4 ; a5 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 87 ; 87 ; 4 ; a6 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 88 ; 88 ; 4 ; a7 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 89 ; 89 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 90 ; 90 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 91 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 92 ; 91 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 92 ; 91 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 94 ; 92 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 95 ; 93 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 96 ; 94 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 97 ; 95 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 94 ; 92 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 95 ; 93 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 96 ; 94 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 97 ; 95 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 98 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 99 ; 96 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 99 ; 96 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 100 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 101 ; 97 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 102 ; 98 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 103 ; 99 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 104 ; 100 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 105 ; 101 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 106 ; 102 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 107 ; 105 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 101 ; 97 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 102 ; 98 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 103 ; 99 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 104 ; 100 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 105 ; 101 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 106 ; 102 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 107 ; 105 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 108 ; 106 ; 3 ; ~LVDS54p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 109 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 110 ; 107 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 110 ; 107 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 111 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 112 ; 108 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 113 ; 109 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 114 ; 110 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 115 ; 112 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 116 ; 113 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 117 ; 114 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 118 ; 117 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 112 ; 108 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 113 ; 109 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 114 ; 110 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 115 ; 112 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 116 ; 113 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 117 ; 114 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 118 ; 117 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 119 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 120 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 121 ; 121 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
@ -425,32 +426,32 @@ The pin-out file can be found in D:/projects/quartus/double_selector_8b/double_s
; 124 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 125 ; 123 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
; 126 ; 124 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
; 127 ; 125 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 128 ; 126 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 127 ; 125 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 128 ; 126 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 129 ; 127 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 130 ; 128 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 131 ; 129 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 132 ; 130 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
; 133 ; 131 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 134 ; 132 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 135 ; 133 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 133 ; 131 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 134 ; 132 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 135 ; 133 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 136 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 137 ; 134 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 138 ; 135 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 139 ; 136 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 137 ; 134 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 138 ; 135 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 139 ; 136 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 141 ; 137 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 142 ; 138 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 143 ; 141 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 144 ; 142 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 145 ; 143 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 146 ; 149 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 147 ; 150 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 141 ; 137 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 142 ; 138 ; 3 ; Y0 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 143 ; 141 ; 3 ; Y1 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 144 ; 142 ; 3 ; Y2 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 145 ; 143 ; 3 ; Y3 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 146 ; 149 ; 3 ; Y4 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 147 ; 150 ; 3 ; Y5 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 148 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 149 ; 151 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 150 ; 152 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 151 ; 153 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 152 ; 154 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 149 ; 151 ; 3 ; Y6 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 150 ; 152 ; 3 ; Y7 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 151 ; 153 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 152 ; 154 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 153 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 154 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
; 155 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
@ -458,55 +459,55 @@ The pin-out file can be found in D:/projects/quartus/double_selector_8b/double_s
; 157 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 158 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
; 159 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 160 ; 155 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 161 ; 156 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 162 ; 157 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 163 ; 158 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 164 ; 159 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 165 ; 160 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 160 ; 155 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 161 ; 156 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 162 ; 157 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 163 ; 158 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 164 ; 159 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 165 ; 160 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 166 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 167 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 168 ; 161 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 169 ; 162 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 170 ; 163 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 171 ; 164 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 168 ; 161 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 169 ; 162 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 170 ; 163 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 171 ; 164 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 172 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 173 ; 165 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 173 ; 165 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 174 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 175 ; 168 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 176 ; 169 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 175 ; 168 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 176 ; 169 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 177 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 178 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 179 ; 173 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 180 ; 174 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 181 ; 175 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 182 ; 176 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 179 ; 173 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 180 ; 174 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 181 ; 175 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 182 ; 176 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 183 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 184 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 185 ; 180 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 185 ; 180 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 186 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 187 ; 181 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 188 ; 182 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 189 ; 183 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 187 ; 181 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 188 ; 182 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 189 ; 183 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 190 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
; 191 ; 184 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 192 ; 185 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 193 ; 186 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 191 ; 184 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 192 ; 185 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 193 ; 186 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 194 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 195 ; 187 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 195 ; 187 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 196 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 197 ; 191 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 198 ; 192 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 199 ; 195 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 200 ; 196 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 201 ; 197 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 197 ; 191 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 198 ; 192 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 199 ; 195 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 200 ; 196 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 201 ; 197 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 202 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 203 ; 198 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 203 ; 198 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 204 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 205 ; 199 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 206 ; 200 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 207 ; 201 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 208 ; 202 ; 2 ; Y5 ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 205 ; 199 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 206 ; 200 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 207 ; 201 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 208 ; 202 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
@ -573,13 +574,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Y7 ; Output ; -- ; -- ; -- ; -- ;
; b0 ; Input ; 6 ; 6 ; -- ; -- ;
; a0 ; Input ; 6 ; 6 ; -- ; -- ;
; AY ; Input ; 6 ; 6 ; -- ; -- ;
; BY ; Input ; 6 ; 6 ; -- ; -- ;
; AY ; Input ; 0 ; 0 ; -- ; -- ;
; BY ; Input ; 0 ; 0 ; -- ; -- ;
; a1 ; Input ; 6 ; 6 ; -- ; -- ;
; b1 ; Input ; 0 ; 0 ; -- ; -- ;
; a2 ; Input ; 0 ; 0 ; -- ; -- ;
; b2 ; Input ; 0 ; 0 ; -- ; -- ;
; a3 ; Input ; 0 ; 0 ; -- ; -- ;
; b1 ; Input ; 6 ; 6 ; -- ; -- ;
; a2 ; Input ; 6 ; 6 ; -- ; -- ;
; b2 ; Input ; 6 ; 6 ; -- ; -- ;
; a3 ; Input ; 6 ; 6 ; -- ; -- ;
; b3 ; Input ; 6 ; 6 ; -- ; -- ;
; a4 ; Input ; 6 ; 6 ; -- ; -- ;
; b4 ; Input ; 6 ; 6 ; -- ; -- ;
@ -598,47 +599,35 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
+---------------------+-------------------+---------+
; b0 ; ; ;
; - inst1 ; 1 ; 6 ;
; - inst1 ; 0 ; 6 ;
; a0 ; ; ;
; - inst1 ; 0 ; 6 ;
; AY ; ; ;
; - inst1 ; 0 ; 6 ;
; - inst2 ; 0 ; 6 ;
; - inst3 ; 0 ; 6 ;
; - inst4 ; 0 ; 6 ;
; - inst5 ; 0 ; 6 ;
; - inst6 ; 0 ; 6 ;
; - inst7 ; 0 ; 6 ;
; - inst8 ; 0 ; 6 ;
; BY ; ; ;
; - inst1 ; 1 ; 6 ;
; - inst2 ; 1 ; 6 ;
; - inst3 ; 1 ; 6 ;
; - inst4 ; 1 ; 6 ;
; - inst5 ; 1 ; 6 ;
; - inst6 ; 1 ; 6 ;
; - inst7 ; 1 ; 6 ;
; - inst8 ; 1 ; 6 ;
; a1 ; ; ;
; - inst2 ; 0 ; 6 ;
; b1 ; ; ;
; - inst2 ; 0 ; 6 ;
; a2 ; ; ;
; - inst3 ; 0 ; 6 ;
; b2 ; ; ;
; - inst3 ; 0 ; 6 ;
; a3 ; ; ;
; b3 ; ; ;
; - inst4 ; 0 ; 6 ;
; b3 ; ; ;
; - inst4 ; 1 ; 6 ;
; a4 ; ; ;
; - inst5 ; 0 ; 6 ;
; b4 ; ; ;
; - inst5 ; 1 ; 6 ;
; - inst5 ; 0 ; 6 ;
; a5 ; ; ;
; - inst6 ; 0 ; 6 ;
; b5 ; ; ;
; - inst6 ; 1 ; 6 ;
; - inst6 ; 0 ; 6 ;
; a6 ; ; ;
; - inst7 ; 0 ; 6 ;
; b6 ; ; ;
; - inst7 ; 1 ; 6 ;
; - inst7 ; 0 ; 6 ;
; a7 ; ; ;
; - inst8 ; 0 ; 6 ;
; b7 ; ; ;
@ -686,13 +675,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Interconnect Resource Type ; Usage ;
+----------------------------+-----------------------+
; Block interconnects ; 26 / 26,052 ( < 1 % ) ;
; C16 interconnects ; 3 / 1,156 ( < 1 % ) ;
; C4 interconnects ; 35 / 17,952 ( < 1 % ) ;
; C16 interconnects ; 7 / 1,156 ( < 1 % ) ;
; C4 interconnects ; 42 / 17,952 ( < 1 % ) ;
; Direct links ; 0 / 26,052 ( 0 % ) ;
; Global clocks ; 0 / 8 ( 0 % ) ;
; Local interconnects ; 0 / 8,256 ( 0 % ) ;
; R24 interconnects ; 0 / 1,020 ( 0 % ) ;
; R4 interconnects ; 3 / 22,440 ( < 1 % ) ;
; R24 interconnects ; 9 / 1,020 ( < 1 % ) ;
; R4 interconnects ; 33 / 22,440 ( < 1 % ) ;
+----------------------------+-----------------------+
@ -794,7 +783,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Error detection CRC ; Off ;
; nCEO ; As output driving ground ;
; ASDO,nCSO ; As input tri-stated ;
; Reserve all unused pins ; As output driving ground ;
; Reserve all unused pins ; As input tri-stated ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+--------------------------+
@ -869,6 +858,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Name ; Value ;
+------------------------------------+------------+
; Auto Fit Point 2 - Fit Attempt 1 ; ff ;
; Early Wire Use - Fit Attempt 1 ; 0 ;
; Early Slack - Fit Attempt 1 ; 2147483639 ;
; Auto Fit Point 5 - Fit Attempt 1 ; ff ;
; Mid Wire Use - Fit Attempt 1 ; 0 ;
; Mid Slack - Fit Attempt 1 ; 2147483639 ;
@ -896,7 +887,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+------------------------------------+-------------+
; Early Slack - Fit Attempt 1 ; 2147483639 ;
; Early Wire Use - Fit Attempt 1 ; 0 ;
; Peak Regional Wire - Fit Attempt 1 ; 0 ;
; Peak Regional Wire - Fit Attempt 1 ; 1 ;
; Mid Slack - Fit Attempt 1 ; 2147483639 ;
; Late Slack - Fit Attempt 1 ; -2147483648 ;
; Late Wire Use - Fit Attempt 1 ; 0 ;
@ -910,7 +901,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Mon Mar 07 11:07:53 2022
Info: Processing started: Mon Mar 07 11:22:44 2022
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Info: Selected device EP2C8Q208C8 for design "double_selector_8b"
@ -925,47 +916,11 @@ Info: Fitter converted 3 user pins into dedicated programming pins
Info: Pin ~ASDO~ is reserved at location 1
Info: Pin ~nCSO~ is reserved at location 2
Info: Pin ~LVDS54p/nCEO~ is reserved at location 108
Warning: No exact pin location assignment(s) for 26 pins of 26 total pins
Info: Pin Y0 not assigned to an exact location on the device
Info: Pin Y1 not assigned to an exact location on the device
Info: Pin Y2 not assigned to an exact location on the device
Info: Pin Y3 not assigned to an exact location on the device
Info: Pin Y4 not assigned to an exact location on the device
Info: Pin Y5 not assigned to an exact location on the device
Info: Pin Y6 not assigned to an exact location on the device
Info: Pin Y7 not assigned to an exact location on the device
Info: Pin b0 not assigned to an exact location on the device
Info: Pin a0 not assigned to an exact location on the device
Info: Pin AY not assigned to an exact location on the device
Info: Pin BY not assigned to an exact location on the device
Info: Pin a1 not assigned to an exact location on the device
Info: Pin b1 not assigned to an exact location on the device
Info: Pin a2 not assigned to an exact location on the device
Info: Pin b2 not assigned to an exact location on the device
Info: Pin a3 not assigned to an exact location on the device
Info: Pin b3 not assigned to an exact location on the device
Info: Pin a4 not assigned to an exact location on the device
Info: Pin b4 not assigned to an exact location on the device
Info: Pin a5 not assigned to an exact location on the device
Info: Pin b5 not assigned to an exact location on the device
Info: Pin a6 not assigned to an exact location on the device
Info: Pin b6 not assigned to an exact location on the device
Info: Pin a7 not assigned to an exact location on the device
Info: Pin b7 not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Starting register packing
Info: Finished register packing
Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info: Number of I/O pins in group: 26 (unused VREF, 3.3V VCCIO, 18 input, 8 output, 0 bidirectional)
Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available
Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available
Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins available
Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins available
Info: Fitter preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
@ -974,7 +929,7 @@ Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources
Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y9
Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X34_Y9
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
@ -990,12 +945,11 @@ Warning: Found 8 output pins without output pin load capacitance assignment
Info: Pin "Y6" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "Y7" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Generated suppressed messages file D:/projects/quartus/double_selector_8b/double_selector_8b.fit.smsg
Info: Quartus II Fitter was successful. 0 errors, 3 warnings
Info: Peak virtual memory: 306 megabytes
Info: Processing ended: Mon Mar 07 11:07:55 2022
Info: Elapsed time: 00:00:02
Info: Quartus II Fitter was successful. 0 errors, 1 warning
Info: Peak virtual memory: 307 megabytes
Info: Processing ended: Mon Mar 07 11:22:45 2022
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01

2
double_selector_8b/double_selector_8b.fit.summary
查看文件

@ -1,4 +1,4 @@
Fitter Status : Successful - Mon Mar 07 11:07:54 2022
Fitter Status : Successful - Mon Mar 07 11:22:45 2022
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : double_selector_8b
Top-level Entity Name : double_selector_8b

39
double_selector_8b/double_selector_8b.flow.rpt
查看文件

@ -1,5 +1,5 @@
Flow report for double_selector_8b
Mon Mar 07 11:07:57 2022
Mon Mar 07 11:22:47 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@ -38,7 +38,7 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+----------------------------------------------+
; Flow Status ; Successful - Mon Mar 07 11:07:57 2022 ;
; Flow Status ; Successful - Mon Mar 07 11:22:47 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; double_selector_8b ;
; Top-level Entity Name ; double_selector_8b ;
@ -63,24 +63,25 @@ applicable agreement for further details.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 03/07/2022 11:07:53 ;
; Start date & time ; 03/07/2022 11:22:43 ;
; Main task ; Compilation ;
; Revision Name ; double_selector_8b ;
+-------------------+---------------------+
+---------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+------------------------------------+---------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+------------------------------------+---------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 220283517943889.164662247222660 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
+------------------------------------+---------------------------------+---------------+-------------+----------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+------------------------------------+---------------------------------------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+------------------------------------+---------------------------------------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 220283517943889.164662336312624 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; MISC_FILE ; D:/projects/quartus/double_selector_8b/double_selector_8b.dpf ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
+------------------------------------+---------------------------------------------------------------+---------------+-------------+----------------+
+-----------------------------------------------------------------------------------------------------------------------------+
@ -88,11 +89,11 @@ applicable agreement for further details.
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 245 MB ; 00:00:00 ;
; Fitter ; 00:00:01 ; 1.0 ; 306 MB ; 00:00:01 ;
; Assembler ; 00:00:01 ; 1.0 ; 241 MB ; 00:00:00 ;
; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 246 MB ; 00:00:00 ;
; Fitter ; 00:00:01 ; 1.0 ; 307 MB ; 00:00:01 ;
; Assembler ; 00:00:00 ; 1.0 ; 241 MB ; 00:00:00 ;
; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 198 MB ; 00:00:00 ;
; Total ; 00:00:03 ; -- ; -- ; 00:00:01 ;
; Total ; 00:00:01 ; -- ; -- ; 00:00:01 ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+

12
double_selector_8b/double_selector_8b.map.rpt
查看文件

@ -1,5 +1,5 @@
Analysis & Synthesis report for double_selector_8b
Mon Mar 07 11:07:53 2022
Mon Mar 07 11:22:43 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@ -39,7 +39,7 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Mar 07 11:07:53 2022 ;
; Analysis & Synthesis Status ; Successful - Mon Mar 07 11:22:43 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; double_selector_8b ;
; Top-level Entity Name ; double_selector_8b ;
@ -200,7 +200,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Mon Mar 07 11:07:52 2022
Info: Processing started: Mon Mar 07 11:22:43 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off double_selector_8b -c double_selector_8b
Info: Found 1 design units, including 1 entities, in source file double_selector_8b.bdf
Info: Found entity 1: double_selector_8b
@ -210,9 +210,9 @@ Info: Implemented 34 device resources after synthesis - the final resource count
Info: Implemented 8 output pins
Info: Implemented 8 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 248 megabytes
Info: Processing ended: Mon Mar 07 11:07:53 2022
Info: Elapsed time: 00:00:01
Info: Peak virtual memory: 250 megabytes
Info: Processing ended: Mon Mar 07 11:22:43 2022
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00

2
double_selector_8b/double_selector_8b.map.summary
查看文件

@ -1,4 +1,4 @@
Analysis & Synthesis Status : Successful - Mon Mar 07 11:07:53 2022
Analysis & Synthesis Status : Successful - Mon Mar 07 11:22:43 2022
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : double_selector_8b
Top-level Entity Name : double_selector_8b

262
double_selector_8b/double_selector_8b.pin
查看文件

@ -70,19 +70,19 @@ Pin Name/Usage : Location : Dir. : I/O Standard : Voltage
-------------------------------------------------------------------------------------------------------------
~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVTTL : : 1 : N
~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVTTL : : 1 : N
a7 : 3 : input : 3.3-V LVTTL : : 1 : N
GND* : 4 : : : : 1 :
GND* : 5 : : : : 1 :
GND* : 6 : : : : 1 :
RESERVED_INPUT : 3 : : : : 1 :
RESERVED_INPUT : 4 : : : : 1 :
RESERVED_INPUT : 5 : : : : 1 :
RESERVED_INPUT : 6 : : : : 1 :
VCCIO1 : 7 : power : : 3.3V : 1 :
GND* : 8 : : : : 1 :
RESERVED_INPUT : 8 : : : : 1 :
GND : 9 : gnd : : : :
Y4 : 10 : output : 3.3-V LVTTL : : 1 : N
GND* : 11 : : : : 1 :
a4 : 12 : input : 3.3-V LVTTL : : 1 : N
GND* : 13 : : : : 1 :
Y2 : 14 : output : 3.3-V LVTTL : : 1 : N
Y3 : 15 : output : 3.3-V LVTTL : : 1 : N
RESERVED_INPUT : 10 : : : : 1 :
RESERVED_INPUT : 11 : : : : 1 :
RESERVED_INPUT : 12 : : : : 1 :
RESERVED_INPUT : 13 : : : : 1 :
RESERVED_INPUT : 14 : : : : 1 :
RESERVED_INPUT : 15 : : : : 1 :
TDO : 16 : output : : : 1 :
TMS : 17 : input : : : 1 :
TCK : 18 : input : : : 1 :
@ -90,32 +90,32 @@ TDI : 19 : input : :
DATA0 : 20 : input : : : 1 :
DCLK : 21 : : : : 1 :
nCE : 22 : : : : 1 :
b1 : 23 : input : 3.3-V LVTTL : : 1 : N
a2 : 24 : input : 3.3-V LVTTL : : 1 : N
AY : 23 : input : 3.3-V LVTTL : : 1 : Y
BY : 24 : input : 3.3-V LVTTL : : 1 : Y
GND : 25 : gnd : : : :
nCONFIG : 26 : : : : 1 :
b2 : 27 : input : 3.3-V LVTTL : : 1 : N
a3 : 28 : input : 3.3-V LVTTL : : 1 : N
GND+ : 27 : : : : 1 :
GND+ : 28 : : : : 1 :
VCCIO1 : 29 : power : : 3.3V : 1 :
Y6 : 30 : output : 3.3-V LVTTL : : 1 : N
a5 : 31 : input : 3.3-V LVTTL : : 1 : N
RESERVED_INPUT : 30 : : : : 1 :
RESERVED_INPUT : 31 : : : : 1 :
VCCINT : 32 : power : : 1.2V : :
b7 : 33 : input : 3.3-V LVTTL : : 1 : N
a6 : 34 : input : 3.3-V LVTTL : : 1 : N
Y1 : 35 : output : 3.3-V LVTTL : : 1 : N
RESERVED_INPUT : 33 : : : : 1 :
RESERVED_INPUT : 34 : : : : 1 :
RESERVED_INPUT : 35 : : : : 1 :
GND : 36 : gnd : : : :
a1 : 37 : input : 3.3-V LVTTL : : 1 : N
RESERVED_INPUT : 37 : : : : 1 :
GND : 38 : gnd : : : :
a0 : 39 : input : 3.3-V LVTTL : : 1 : N
b0 : 40 : input : 3.3-V LVTTL : : 1 : N
b4 : 41 : input : 3.3-V LVTTL : : 1 : N
RESERVED_INPUT : 39 : : : : 1 :
RESERVED_INPUT : 40 : : : : 1 :
RESERVED_INPUT : 41 : : : : 1 :
VCCIO1 : 42 : power : : 3.3V : 1 :
GND* : 43 : : : : 1 :
BY : 44 : input : 3.3-V LVTTL : : 1 : N
b5 : 45 : input : 3.3-V LVTTL : : 1 : N
GND* : 46 : : : : 1 :
GND* : 47 : : : : 1 :
Y7 : 48 : output : 3.3-V LVTTL : : 1 : N
RESERVED_INPUT : 43 : : : : 1 :
RESERVED_INPUT : 44 : : : : 1 :
RESERVED_INPUT : 45 : : : : 1 :
RESERVED_INPUT : 46 : : : : 1 :
RESERVED_INPUT : 47 : : : : 1 :
RESERVED_INPUT : 48 : : : : 1 :
GND : 49 : gnd : : : :
GND_PLL1 : 50 : gnd : : : :
VCCD_PLL1 : 51 : power : : 1.2V : :
@ -123,69 +123,69 @@ GND_PLL1 : 52 : gnd : :
VCCA_PLL1 : 53 : power : : 1.2V : :
GNDA_PLL1 : 54 : gnd : : : :
GND : 55 : gnd : : : :
AY : 56 : input : 3.3-V LVTTL : : 4 : N
b6 : 57 : input : 3.3-V LVTTL : : 4 : N
Y0 : 58 : output : 3.3-V LVTTL : : 4 : N
b3 : 59 : input : 3.3-V LVTTL : : 4 : N
GND* : 60 : : : : 4 :
GND* : 61 : : : : 4 :
RESERVED_INPUT : 56 : : : : 4 :
RESERVED_INPUT : 57 : : : : 4 :
RESERVED_INPUT : 58 : : : : 4 :
RESERVED_INPUT : 59 : : : : 4 :
RESERVED_INPUT : 60 : : : : 4 :
RESERVED_INPUT : 61 : : : : 4 :
VCCIO4 : 62 : power : : 3.3V : 4 :
GND* : 63 : : : : 4 :
GND* : 64 : : : : 4 :
RESERVED_INPUT : 63 : : : : 4 :
RESERVED_INPUT : 64 : : : : 4 :
GND : 65 : gnd : : : :
VCCINT : 66 : power : : 1.2V : :
GND* : 67 : : : : 4 :
GND* : 68 : : : : 4 :
GND* : 69 : : : : 4 :
GND* : 70 : : : : 4 :
b0 : 67 : input : 3.3-V LVTTL : : 4 : Y
b1 : 68 : input : 3.3-V LVTTL : : 4 : Y
b2 : 69 : input : 3.3-V LVTTL : : 4 : Y
b3 : 70 : input : 3.3-V LVTTL : : 4 : Y
VCCIO4 : 71 : power : : 3.3V : 4 :
GND* : 72 : : : : 4 :
b4 : 72 : input : 3.3-V LVTTL : : 4 : Y
GND : 73 : gnd : : : :
GND* : 74 : : : : 4 :
GND* : 75 : : : : 4 :
GND* : 76 : : : : 4 :
GND* : 77 : : : : 4 :
b5 : 74 : input : 3.3-V LVTTL : : 4 : Y
b6 : 75 : input : 3.3-V LVTTL : : 4 : Y
b7 : 76 : input : 3.3-V LVTTL : : 4 : Y
a0 : 77 : input : 3.3-V LVTTL : : 4 : Y
GND : 78 : gnd : : : :
VCCINT : 79 : power : : 1.2V : :
GND* : 80 : : : : 4 :
GND* : 81 : : : : 4 :
GND* : 82 : : : : 4 :
a1 : 80 : input : 3.3-V LVTTL : : 4 : Y
a2 : 81 : input : 3.3-V LVTTL : : 4 : Y
a3 : 82 : input : 3.3-V LVTTL : : 4 : Y
VCCIO4 : 83 : power : : 3.3V : 4 :
GND* : 84 : : : : 4 :
a4 : 84 : input : 3.3-V LVTTL : : 4 : Y
GND : 85 : gnd : : : :
GND* : 86 : : : : 4 :
GND* : 87 : : : : 4 :
GND* : 88 : : : : 4 :
GND* : 89 : : : : 4 :
GND* : 90 : : : : 4 :
a5 : 86 : input : 3.3-V LVTTL : : 4 : Y
a6 : 87 : input : 3.3-V LVTTL : : 4 : Y
a7 : 88 : input : 3.3-V LVTTL : : 4 : Y
RESERVED_INPUT : 89 : : : : 4 :
RESERVED_INPUT : 90 : : : : 4 :
VCCIO4 : 91 : power : : 3.3V : 4 :
GND* : 92 : : : : 4 :
RESERVED_INPUT : 92 : : : : 4 :
GND : 93 : gnd : : : :
GND* : 94 : : : : 4 :
GND* : 95 : : : : 4 :
GND* : 96 : : : : 4 :
GND* : 97 : : : : 4 :
RESERVED_INPUT : 94 : : : : 4 :
RESERVED_INPUT : 95 : : : : 4 :
RESERVED_INPUT : 96 : : : : 4 :
RESERVED_INPUT : 97 : : : : 4 :
VCCIO4 : 98 : power : : 3.3V : 4 :
GND* : 99 : : : : 4 :
RESERVED_INPUT : 99 : : : : 4 :
GND : 100 : gnd : : : :
GND* : 101 : : : : 4 :
GND* : 102 : : : : 4 :
GND* : 103 : : : : 4 :
GND* : 104 : : : : 4 :
GND* : 105 : : : : 3 :
GND* : 106 : : : : 3 :
GND* : 107 : : : : 3 :
RESERVED_INPUT : 101 : : : : 4 :
RESERVED_INPUT : 102 : : : : 4 :
RESERVED_INPUT : 103 : : : : 4 :
RESERVED_INPUT : 104 : : : : 4 :
RESERVED_INPUT : 105 : : : : 3 :
RESERVED_INPUT : 106 : : : : 3 :
RESERVED_INPUT : 107 : : : : 3 :
~LVDS54p/nCEO~ : 108 : output : 3.3-V LVTTL : : 3 : N
VCCIO3 : 109 : power : : 3.3V : 3 :
GND* : 110 : : : : 3 :
RESERVED_INPUT : 110 : : : : 3 :
GND : 111 : gnd : : : :
GND* : 112 : : : : 3 :
GND* : 113 : : : : 3 :
GND* : 114 : : : : 3 :
GND* : 115 : : : : 3 :
GND* : 116 : : : : 3 :
GND* : 117 : : : : 3 :
GND* : 118 : : : : 3 :
RESERVED_INPUT : 112 : : : : 3 :
RESERVED_INPUT : 113 : : : : 3 :
RESERVED_INPUT : 114 : : : : 3 :
RESERVED_INPUT : 115 : : : : 3 :
RESERVED_INPUT : 116 : : : : 3 :
RESERVED_INPUT : 117 : : : : 3 :
RESERVED_INPUT : 118 : : : : 3 :
GND : 119 : gnd : : : :
VCCINT : 120 : power : : 1.2V : :
nSTATUS : 121 : : : : 3 :
@ -194,32 +194,32 @@ CONF_DONE : 123 : : :
GND : 124 : gnd : : : :
MSEL1 : 125 : : : : 3 :
MSEL0 : 126 : : : : 3 :
GND* : 127 : : : : 3 :
GND* : 128 : : : : 3 :
RESERVED_INPUT : 127 : : : : 3 :
RESERVED_INPUT : 128 : : : : 3 :
GND+ : 129 : : : : 3 :
GND+ : 130 : : : : 3 :
GND+ : 131 : : : : 3 :
GND+ : 132 : : : : 3 :
GND* : 133 : : : : 3 :
GND* : 134 : : : : 3 :
GND* : 135 : : : : 3 :
RESERVED_INPUT : 133 : : : : 3 :
RESERVED_INPUT : 134 : : : : 3 :
RESERVED_INPUT : 135 : : : : 3 :
VCCIO3 : 136 : power : : 3.3V : 3 :
GND* : 137 : : : : 3 :
GND* : 138 : : : : 3 :
GND* : 139 : : : : 3 :
RESERVED_INPUT : 137 : : : : 3 :
RESERVED_INPUT : 138 : : : : 3 :
RESERVED_INPUT : 139 : : : : 3 :
GND : 140 : gnd : : : :
GND* : 141 : : : : 3 :
GND* : 142 : : : : 3 :
GND* : 143 : : : : 3 :
GND* : 144 : : : : 3 :
GND* : 145 : : : : 3 :
GND* : 146 : : : : 3 :
GND* : 147 : : : : 3 :
RESERVED_INPUT : 141 : : : : 3 :
Y0 : 142 : output : 3.3-V LVTTL : : 3 : Y
Y1 : 143 : output : 3.3-V LVTTL : : 3 : Y
Y2 : 144 : output : 3.3-V LVTTL : : 3 : Y
Y3 : 145 : output : 3.3-V LVTTL : : 3 : Y
Y4 : 146 : output : 3.3-V LVTTL : : 3 : Y
Y5 : 147 : output : 3.3-V LVTTL : : 3 : Y
VCCIO3 : 148 : power : : 3.3V : 3 :
GND* : 149 : : : : 3 :
GND* : 150 : : : : 3 :
GND* : 151 : : : : 3 :
GND* : 152 : : : : 3 :
Y6 : 149 : output : 3.3-V LVTTL : : 3 : Y
Y7 : 150 : output : 3.3-V LVTTL : : 3 : Y
RESERVED_INPUT : 151 : : : : 3 :
RESERVED_INPUT : 152 : : : : 3 :
GND : 153 : gnd : : : :
GND_PLL2 : 154 : gnd : : : :
VCCD_PLL2 : 155 : power : : 1.2V : :
@ -227,52 +227,52 @@ GND_PLL2 : 156 : gnd : :
VCCA_PLL2 : 157 : power : : 1.2V : :
GNDA_PLL2 : 158 : gnd : : : :
GND : 159 : gnd : : : :
GND* : 160 : : : : 2 :
GND* : 161 : : : : 2 :
GND* : 162 : : : : 2 :
GND* : 163 : : : : 2 :
GND* : 164 : : : : 2 :
GND* : 165 : : : : 2 :
RESERVED_INPUT : 160 : : : : 2 :
RESERVED_INPUT : 161 : : : : 2 :
RESERVED_INPUT : 162 : : : : 2 :
RESERVED_INPUT : 163 : : : : 2 :
RESERVED_INPUT : 164 : : : : 2 :
RESERVED_INPUT : 165 : : : : 2 :
VCCIO2 : 166 : power : : 3.3V : 2 :
GND : 167 : gnd : : : :
GND* : 168 : : : : 2 :
GND* : 169 : : : : 2 :
GND* : 170 : : : : 2 :
GND* : 171 : : : : 2 :
RESERVED_INPUT : 168 : : : : 2 :
RESERVED_INPUT : 169 : : : : 2 :
RESERVED_INPUT : 170 : : : : 2 :
RESERVED_INPUT : 171 : : : : 2 :
VCCIO2 : 172 : power : : 3.3V : 2 :
GND* : 173 : : : : 2 :
RESERVED_INPUT : 173 : : : : 2 :
GND : 174 : gnd : : : :
GND* : 175 : : : : 2 :
GND* : 176 : : : : 2 :
RESERVED_INPUT : 175 : : : : 2 :
RESERVED_INPUT : 176 : : : : 2 :
GND : 177 : gnd : : : :
VCCINT : 178 : power : : 1.2V : :
GND* : 179 : : : : 2 :
GND* : 180 : : : : 2 :
GND* : 181 : : : : 2 :
GND* : 182 : : : : 2 :
RESERVED_INPUT : 179 : : : : 2 :
RESERVED_INPUT : 180 : : : : 2 :
RESERVED_INPUT : 181 : : : : 2 :
RESERVED_INPUT : 182 : : : : 2 :
VCCIO2 : 183 : power : : 3.3V : 2 :
GND : 184 : gnd : : : :
GND* : 185 : : : : 2 :
RESERVED_INPUT : 185 : : : : 2 :
GND : 186 : gnd : : : :
GND* : 187 : : : : 2 :
GND* : 188 : : : : 2 :
GND* : 189 : : : : 2 :
RESERVED_INPUT : 187 : : : : 2 :
RESERVED_INPUT : 188 : : : : 2 :
RESERVED_INPUT : 189 : : : : 2 :
VCCINT : 190 : power : : 1.2V : :
GND* : 191 : : : : 2 :
GND* : 192 : : : : 2 :
GND* : 193 : : : : 2 :
RESERVED_INPUT : 191 : : : : 2 :
RESERVED_INPUT : 192 : : : : 2 :
RESERVED_INPUT : 193 : : : : 2 :
VCCIO2 : 194 : power : : 3.3V : 2 :
GND* : 195 : : : : 2 :
RESERVED_INPUT : 195 : : : : 2 :
GND : 196 : gnd : : : :
GND* : 197 : : : : 2 :
GND* : 198 : : : : 2 :
GND* : 199 : : : : 2 :
GND* : 200 : : : : 2 :
GND* : 201 : : : : 2 :
RESERVED_INPUT : 197 : : : : 2 :
RESERVED_INPUT : 198 : : : : 2 :
RESERVED_INPUT : 199 : : : : 2 :
RESERVED_INPUT : 200 : : : : 2 :
RESERVED_INPUT : 201 : : : : 2 :
VCCIO2 : 202 : power : : 3.3V : 2 :
GND* : 203 : : : : 2 :
RESERVED_INPUT : 203 : : : : 2 :
GND : 204 : gnd : : : :
GND* : 205 : : : : 2 :
GND* : 206 : : : : 2 :
GND* : 207 : : : : 2 :
Y5 : 208 : output : 3.3-V LVTTL : : 2 : N
RESERVED_INPUT : 205 : : : : 2 :
RESERVED_INPUT : 206 : : : : 2 :
RESERVED_INPUT : 207 : : : : 2 :
RESERVED_INPUT : 208 : : : : 2 :

二進制
double_selector_8b/double_selector_8b.pof
查看文件

未顯示二進位檔案。

32
double_selector_8b/double_selector_8b.qsf
查看文件

@ -50,4 +50,34 @@ set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_77 -to a0
set_location_assignment PIN_80 -to a1
set_location_assignment PIN_81 -to a2
set_location_assignment PIN_82 -to a3
set_location_assignment PIN_84 -to a4
set_location_assignment PIN_86 -to a5
set_location_assignment PIN_87 -to a6
set_location_assignment PIN_88 -to a7
set_location_assignment PIN_67 -to b0
set_location_assignment PIN_68 -to b1
set_location_assignment PIN_69 -to b2
set_location_assignment PIN_70 -to b3
set_location_assignment PIN_72 -to b4
set_location_assignment PIN_74 -to b5
set_location_assignment PIN_75 -to b6
set_location_assignment PIN_76 -to b7
set_location_assignment PIN_23 -to AY
set_location_assignment PIN_24 -to BY
set_location_assignment PIN_142 -to Y0
set_location_assignment PIN_143 -to Y1
set_location_assignment PIN_144 -to Y2
set_location_assignment PIN_145 -to Y3
set_location_assignment PIN_146 -to Y4
set_location_assignment PIN_147 -to Y5
set_location_assignment PIN_149 -to Y6
set_location_assignment PIN_150 -to Y7
set_global_assignment -name MISC_FILE "D:/projects/quartus/double_selector_8b/double_selector_8b.dpf"
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"

二進制
double_selector_8b/double_selector_8b.sof
查看文件

未顯示二進位檔案。

84
double_selector_8b/double_selector_8b.tan.rpt
查看文件

@ -1,5 +1,5 @@
Classic Timing Analyzer report for double_selector_8b
Mon Mar 07 11:07:57 2022
Mon Mar 07 11:22:47 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@ -39,7 +39,7 @@ applicable agreement for further details.
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 12.694 ns ; b5 ; Y5 ; -- ; -- ; 0 ;
; Worst-case tpd ; N/A ; None ; 14.785 ns ; b6 ; Y6 ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
@ -98,38 +98,38 @@ applicable agreement for further details.
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A ; None ; 12.694 ns ; b5 ; Y5 ;
; N/A ; None ; 12.565 ns ; BY ; Y7 ;
; N/A ; None ; 12.553 ns ; BY ; Y0 ;
; N/A ; None ; 12.543 ns ; a7 ; Y7 ;
; N/A ; None ; 12.522 ns ; AY ; Y0 ;
; N/A ; None ; 12.477 ns ; BY ; Y5 ;
; N/A ; None ; 12.469 ns ; a4 ; Y4 ;
; N/A ; None ; 12.451 ns ; AY ; Y5 ;
; N/A ; None ; 12.396 ns ; b3 ; Y3 ;
; N/A ; None ; 12.360 ns ; a0 ; Y0 ;
; N/A ; None ; 12.298 ns ; b0 ; Y0 ;
; N/A ; None ; 12.293 ns ; AY ; Y7 ;
; N/A ; None ; 12.239 ns ; a5 ; Y5 ;
; N/A ; None ; 12.214 ns ; b4 ; Y4 ;
; N/A ; None ; 12.099 ns ; AY ; Y1 ;
; N/A ; None ; 12.083 ns ; b7 ; Y7 ;
; N/A ; None ; 12.036 ns ; BY ; Y2 ;
; N/A ; None ; 12.035 ns ; BY ; Y4 ;
; N/A ; None ; 12.030 ns ; BY ; Y3 ;
; N/A ; None ; 12.014 ns ; AY ; Y4 ;
; N/A ; None ; 12.010 ns ; AY ; Y2 ;
; N/A ; None ; 11.998 ns ; AY ; Y3 ;
; N/A ; None ; 11.941 ns ; b6 ; Y6 ;
; N/A ; None ; 11.823 ns ; a1 ; Y1 ;
; N/A ; None ; 11.701 ns ; BY ; Y1 ;
; N/A ; None ; 11.697 ns ; BY ; Y6 ;
; N/A ; None ; 11.670 ns ; AY ; Y6 ;
; N/A ; None ; 11.480 ns ; a6 ; Y6 ;
; N/A ; None ; 6.818 ns ; a3 ; Y3 ;
; N/A ; None ; 6.817 ns ; b2 ; Y2 ;
; N/A ; None ; 6.775 ns ; a2 ; Y2 ;
; N/A ; None ; 6.079 ns ; b1 ; Y1 ;
; N/A ; None ; 14.785 ns ; b6 ; Y6 ;
; N/A ; None ; 14.732 ns ; b5 ; Y5 ;
; N/A ; None ; 14.623 ns ; b0 ; Y0 ;
; N/A ; None ; 14.408 ns ; b4 ; Y4 ;
; N/A ; None ; 14.174 ns ; b1 ; Y1 ;
; N/A ; None ; 14.155 ns ; b7 ; Y7 ;
; N/A ; None ; 14.070 ns ; b2 ; Y2 ;
; N/A ; None ; 14.007 ns ; b3 ; Y3 ;
; N/A ; None ; 13.636 ns ; a0 ; Y0 ;
; N/A ; None ; 13.392 ns ; a6 ; Y6 ;
; N/A ; None ; 13.327 ns ; a5 ; Y5 ;
; N/A ; None ; 13.142 ns ; a3 ; Y3 ;
; N/A ; None ; 13.132 ns ; a2 ; Y2 ;
; N/A ; None ; 12.984 ns ; a7 ; Y7 ;
; N/A ; None ; 12.917 ns ; a4 ; Y4 ;
; N/A ; None ; 12.863 ns ; a1 ; Y1 ;
; N/A ; None ; 10.926 ns ; AY ; Y6 ;
; N/A ; None ; 10.880 ns ; AY ; Y5 ;
; N/A ; None ; 10.740 ns ; BY ; Y6 ;
; N/A ; None ; 10.694 ns ; BY ; Y5 ;
; N/A ; None ; 10.632 ns ; BY ; Y3 ;
; N/A ; None ; 10.630 ns ; BY ; Y2 ;
; N/A ; None ; 10.571 ns ; BY ; Y1 ;
; N/A ; None ; 10.534 ns ; AY ; Y7 ;
; N/A ; None ; 10.528 ns ; AY ; Y3 ;
; N/A ; None ; 10.506 ns ; AY ; Y2 ;
; N/A ; None ; 10.484 ns ; AY ; Y0 ;
; N/A ; None ; 10.463 ns ; AY ; Y4 ;
; N/A ; None ; 10.459 ns ; AY ; Y1 ;
; N/A ; None ; 10.346 ns ; BY ; Y7 ;
; N/A ; None ; 10.288 ns ; BY ; Y4 ;
; N/A ; None ; 10.285 ns ; BY ; Y0 ;
+-------+-------------------+-----------------+------+----+
@ -139,18 +139,18 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Mon Mar 07 11:07:57 2022
Info: Processing started: Mon Mar 07 11:22:47 2022
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off double_selector_8b -c double_selector_8b --timing_analysis_only
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Info: Longest tpd from source pin "b5" to destination pin "Y5" is 12.694 ns
Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_45; Fanout = 1; PIN Node = 'b5'
Info: 2: + IC(6.147 ns) + CELL(0.624 ns) = 7.766 ns; Loc. = LCCOMB_X1_Y9_N26; Fanout = 1; COMB Node = 'inst6'
Info: 3: + IC(1.642 ns) + CELL(3.286 ns) = 12.694 ns; Loc. = PIN_208; Fanout = 0; PIN Node = 'Y5'
Info: Total cell delay = 4.905 ns ( 38.64 % )
Info: Total interconnect delay = 7.789 ns ( 61.36 % )
Info: Longest tpd from source pin "b6" to destination pin "Y6" is 14.785 ns
Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_75; Fanout = 1; PIN Node = 'b6'
Info: 2: + IC(6.679 ns) + CELL(0.651 ns) = 8.304 ns; Loc. = LCCOMB_X25_Y2_N12; Fanout = 1; COMB Node = 'inst7'
Info: 3: + IC(3.365 ns) + CELL(3.116 ns) = 14.785 ns; Loc. = PIN_149; Fanout = 0; PIN Node = 'Y6'
Info: Total cell delay = 4.741 ns ( 32.07 % )
Info: Total interconnect delay = 10.044 ns ( 67.93 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 212 megabytes
Info: Processing ended: Mon Mar 07 11:07:57 2022
Info: Processing ended: Mon Mar 07 11:22:47 2022
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00

6
double_selector_8b/double_selector_8b.tan.summary
查看文件

@ -5,9 +5,9 @@ Timing Analyzer Summary
Type : Worst-case tpd
Slack : N/A
Required Time : None
Actual Time : 12.694 ns
From : b5
To : Y5
Actual Time : 14.785 ns
From : b6
To : Y6
From Clock : --
To Clock : --
Failed Paths : 0

二進制
double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.atm
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未顯示二進位檔案。

二進制
double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.hdbx
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未顯示二進位檔案。

二進制
double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.cmp.rcf
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未顯示二進位檔案。

二進制
double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.map.atm
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未顯示二進位檔案。

二進制
double_selector_8b/incremental_db/compiled_partitions/double_selector_8b.root_partition.map.hdbx
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未顯示二進位檔案。