为register 8b分配引脚
此提交包含在：
@@ -1,5 +1,5 @@
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Classic Timing Analyzer report for register_8b
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Mon Mar 07 09:09:57 2022
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Tue Mar 08 15:08:53 2022
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Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
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@@ -42,9 +42,9 @@ applicable agreement for further details.
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+------------------------------+-------+---------------+-------------+-------+-------+------------+----------+--------------+
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; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
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+------------------------------+-------+---------------+-------------+-------+-------+------------+----------+--------------+
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; Worst-case tsu ; N/A ; None ; 4.872 ns ; D3 ; inst5 ; -- ; CP ; 0 ;
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; Worst-case tco ; N/A ; None ; 8.228 ns ; inst3 ; Q5 ; CP ; -- ; 0 ;
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; Worst-case th ; N/A ; None ; 0.406 ns ; D1 ; inst7 ; -- ; CP ; 0 ;
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; Worst-case tsu ; N/A ; None ; 3.273 ns ; D0 ; inst8 ; -- ; CP ; 0 ;
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; Worst-case tco ; N/A ; None ; 11.227 ns ; inst3 ; Q5 ; CP ; -- ; 0 ;
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; Worst-case th ; N/A ; None ; -2.294 ns ; D5 ; inst3 ; -- ; CP ; 0 ;
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; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
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+------------------------------+-------+---------------+-------------+-------+-------+------------+----------+--------------+
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@@ -112,14 +112,14 @@ applicable agreement for further details.
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+-------+--------------+------------+------+-------+----------+
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; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
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+-------+--------------+------------+------+-------+----------+
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; N/A ; None ; 4.872 ns ; D3 ; inst5 ; CP ;
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; N/A ; None ; 4.693 ns ; D0 ; inst8 ; CP ;
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; N/A ; None ; 4.628 ns ; D4 ; inst4 ; CP ;
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; N/A ; None ; 4.577 ns ; D6 ; inst2 ; CP ;
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; N/A ; None ; 4.264 ns ; D5 ; inst3 ; CP ;
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; N/A ; None ; 4.007 ns ; D7 ; inst ; CP ;
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; N/A ; None ; 1.029 ns ; D2 ; inst6 ; CP ;
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; N/A ; None ; -0.140 ns ; D1 ; inst7 ; CP ;
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; N/A ; None ; 3.273 ns ; D0 ; inst8 ; CP ;
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; N/A ; None ; 2.730 ns ; D3 ; inst5 ; CP ;
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; N/A ; None ; 2.724 ns ; D7 ; inst ; CP ;
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; N/A ; None ; 2.599 ns ; D1 ; inst7 ; CP ;
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; N/A ; None ; 2.597 ns ; D2 ; inst6 ; CP ;
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; N/A ; None ; 2.569 ns ; D6 ; inst2 ; CP ;
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; N/A ; None ; 2.567 ns ; D4 ; inst4 ; CP ;
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; N/A ; None ; 2.560 ns ; D5 ; inst3 ; CP ;
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+-------+--------------+------------+------+-------+----------+
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@@ -128,14 +128,14 @@ applicable agreement for further details.
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+-------+--------------+------------+-------+----+------------+
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; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
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+-------+--------------+------------+-------+----+------------+
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; N/A ; None ; 8.228 ns ; inst3 ; Q5 ; CP ;
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; N/A ; None ; 8.096 ns ; inst2 ; Q6 ; CP ;
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; N/A ; None ; 7.981 ns ; inst4 ; Q4 ; CP ;
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; N/A ; None ; 7.359 ns ; inst6 ; Q2 ; CP ;
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; N/A ; None ; 7.354 ns ; inst ; Q7 ; CP ;
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; N/A ; None ; 7.258 ns ; inst5 ; Q3 ; CP ;
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; N/A ; None ; 6.982 ns ; inst8 ; Q0 ; CP ;
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; N/A ; None ; 6.969 ns ; inst7 ; Q1 ; CP ;
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; N/A ; None ; 11.227 ns ; inst3 ; Q5 ; CP ;
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; N/A ; None ; 11.226 ns ; inst2 ; Q6 ; CP ;
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; N/A ; None ; 11.174 ns ; inst5 ; Q3 ; CP ;
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; N/A ; None ; 11.161 ns ; inst4 ; Q4 ; CP ;
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; N/A ; None ; 11.157 ns ; inst ; Q7 ; CP ;
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; N/A ; None ; 10.809 ns ; inst8 ; Q0 ; CP ;
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; N/A ; None ; 10.781 ns ; inst7 ; Q1 ; CP ;
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; N/A ; None ; 10.767 ns ; inst6 ; Q2 ; CP ;
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+-------+--------------+------------+-------+----+------------+
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@@ -144,14 +144,14 @@ applicable agreement for further details.
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+---------------+-------------+-----------+------+-------+----------+
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; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
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+---------------+-------------+-----------+------+-------+----------+
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; N/A ; None ; 0.406 ns ; D1 ; inst7 ; CP ;
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; N/A ; None ; -0.763 ns ; D2 ; inst6 ; CP ;
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; N/A ; None ; -3.741 ns ; D7 ; inst ; CP ;
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; N/A ; None ; -3.998 ns ; D5 ; inst3 ; CP ;
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; N/A ; None ; -4.311 ns ; D6 ; inst2 ; CP ;
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; N/A ; None ; -4.362 ns ; D4 ; inst4 ; CP ;
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; N/A ; None ; -4.427 ns ; D0 ; inst8 ; CP ;
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; N/A ; None ; -4.606 ns ; D3 ; inst5 ; CP ;
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; N/A ; None ; -2.294 ns ; D5 ; inst3 ; CP ;
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; N/A ; None ; -2.301 ns ; D4 ; inst4 ; CP ;
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; N/A ; None ; -2.303 ns ; D6 ; inst2 ; CP ;
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; N/A ; None ; -2.331 ns ; D2 ; inst6 ; CP ;
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; N/A ; None ; -2.333 ns ; D1 ; inst7 ; CP ;
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; N/A ; None ; -2.458 ns ; D7 ; inst ; CP ;
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; N/A ; None ; -2.464 ns ; D3 ; inst5 ; CP ;
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; N/A ; None ; -3.007 ns ; D0 ; inst8 ; CP ;
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+---------------+-------------+-----------+------+-------+----------+
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@@ -161,55 +161,53 @@ applicable agreement for further details.
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Info: *******************************************************************
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Info: Running Quartus II Classic Timing Analyzer
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Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
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Info: Processing started: Mon Mar 07 09:09:57 2022
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Info: Processing started: Tue Mar 08 15:08:53 2022
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Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off register_8b -c register_8b --timing_analysis_only
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Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
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Warning: Found pins functioning as undefined clocks and/or memory enables
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Info: Assuming node "CP" is an undefined clock
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Info: No valid register-to-register data paths exist for clock "CP"
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Info: tsu for register "inst5" (data pin = "D3", clock pin = "CP") is 4.872 ns
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Info: + Longest pin to register delay is 7.782 ns
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Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_96; Fanout = 1; PIN Node = 'D3'
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Info: 2: + IC(6.338 ns) + CELL(0.460 ns) = 7.782 ns; Loc. = LCFF_X32_Y15_N17; Fanout = 1; REG Node = 'inst5'
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Info: Total cell delay = 1.444 ns ( 18.56 % )
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Info: Total interconnect delay = 6.338 ns ( 81.44 % )
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Info: tsu for register "inst8" (data pin = "D0", clock pin = "CP") is 3.273 ns
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Info: + Longest pin to register delay is 7.692 ns
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Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_77; Fanout = 1; PIN Node = 'D0'
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Info: 2: + IC(6.404 ns) + CELL(0.206 ns) = 7.584 ns; Loc. = LCCOMB_X25_Y1_N22; Fanout = 1; COMB Node = 'inst8~feeder'
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Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.692 ns; Loc. = LCFF_X25_Y1_N23; Fanout = 1; REG Node = 'inst8'
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Info: Total cell delay = 1.288 ns ( 16.74 % )
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Info: Total interconnect delay = 6.404 ns ( 83.26 % )
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Info: + Micro setup delay of destination is -0.040 ns
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Info: - Shortest clock path from clock "CP" to destination register is 2.870 ns
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Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CP'
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Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CP~clkctrl'
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Info: 3: + IC(0.925 ns) + CELL(0.666 ns) = 2.870 ns; Loc. = LCFF_X32_Y15_N17; Fanout = 1; REG Node = 'inst5'
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Info: Total cell delay = 1.806 ns ( 62.93 % )
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Info: Total interconnect delay = 1.064 ns ( 37.07 % )
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Info: tco from clock "CP" to destination pin "Q5" through register "inst3" is 8.228 ns
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Info: + Longest clock path from clock "CP" to source register is 2.879 ns
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Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CP'
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Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CP~clkctrl'
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Info: 3: + IC(0.934 ns) + CELL(0.666 ns) = 2.879 ns; Loc. = LCFF_X12_Y2_N9; Fanout = 1; REG Node = 'inst3'
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Info: Total cell delay = 1.806 ns ( 62.73 % )
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Info: Total interconnect delay = 1.073 ns ( 37.27 % )
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Info: - Shortest clock path from clock "CP" to destination register is 4.379 ns
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Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'
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Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N23; Fanout = 1; REG Node = 'inst8'
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Info: Total cell delay = 1.660 ns ( 37.91 % )
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Info: Total interconnect delay = 2.719 ns ( 62.09 % )
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Info: tco from clock "CP" to destination pin "Q5" through register "inst3" is 11.227 ns
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Info: + Longest clock path from clock "CP" to source register is 4.379 ns
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Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'
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Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'
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Info: Total cell delay = 1.660 ns ( 37.91 % )
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Info: Total interconnect delay = 2.719 ns ( 62.09 % )
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Info: + Micro clock to output delay of source is 0.304 ns
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Info: + Longest register to pin delay is 5.045 ns
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Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y2_N9; Fanout = 1; REG Node = 'inst3'
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Info: 2: + IC(1.765 ns) + CELL(3.280 ns) = 5.045 ns; Loc. = PIN_47; Fanout = 0; PIN Node = 'Q5'
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Info: Total cell delay = 3.280 ns ( 65.01 % )
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Info: Total interconnect delay = 1.765 ns ( 34.99 % )
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Info: th for register "inst7" (data pin = "D1", clock pin = "CP") is 0.406 ns
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Info: + Longest clock path from clock "CP" to destination register is 2.855 ns
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Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CP'
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Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CP~clkctrl'
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Info: 3: + IC(0.910 ns) + CELL(0.666 ns) = 2.855 ns; Loc. = LCFF_X1_Y14_N17; Fanout = 1; REG Node = 'inst7'
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Info: Total cell delay = 1.806 ns ( 63.26 % )
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Info: Total interconnect delay = 1.049 ns ( 36.74 % )
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Info: + Longest register to pin delay is 6.544 ns
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Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'
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Info: 2: + IC(3.428 ns) + CELL(3.116 ns) = 6.544 ns; Loc. = PIN_147; Fanout = 0; PIN Node = 'Q5'
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Info: Total cell delay = 3.116 ns ( 47.62 % )
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Info: Total interconnect delay = 3.428 ns ( 52.38 % )
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Info: th for register "inst3" (data pin = "D5", clock pin = "CP") is -2.294 ns
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Info: + Longest clock path from clock "CP" to destination register is 4.379 ns
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Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 8; CLK Node = 'CP'
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Info: 2: + IC(2.719 ns) + CELL(0.666 ns) = 4.379 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'
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Info: Total cell delay = 1.660 ns ( 37.91 % )
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Info: Total interconnect delay = 2.719 ns ( 62.09 % )
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Info: + Micro hold delay of destination is 0.306 ns
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Info: - Shortest pin to register delay is 2.755 ns
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Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_28; Fanout = 1; PIN Node = 'D1'
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Info: 2: + IC(1.301 ns) + CELL(0.206 ns) = 2.647 ns; Loc. = LCCOMB_X1_Y14_N16; Fanout = 1; COMB Node = 'inst7~feeder'
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Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 2.755 ns; Loc. = LCFF_X1_Y14_N17; Fanout = 1; REG Node = 'inst7'
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Info: Total cell delay = 1.454 ns ( 52.78 % )
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Info: Total interconnect delay = 1.301 ns ( 47.22 % )
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Info: - Shortest pin to register delay is 6.979 ns
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Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_86; Fanout = 1; PIN Node = 'D5'
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Info: 2: + IC(5.701 ns) + CELL(0.206 ns) = 6.871 ns; Loc. = LCCOMB_X25_Y1_N28; Fanout = 1; COMB Node = 'inst3~feeder'
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Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 6.979 ns; Loc. = LCFF_X25_Y1_N29; Fanout = 1; REG Node = 'inst3'
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Info: Total cell delay = 1.278 ns ( 18.31 % )
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Info: Total interconnect delay = 5.701 ns ( 81.69 % )
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Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
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Info: Peak virtual memory: 212 megabytes
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Info: Processing ended: Mon Mar 07 09:09:57 2022
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Info: Processing ended: Tue Mar 08 15:08:53 2022
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Info: Elapsed time: 00:00:00
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Info: Total CPU time (on all processors): 00:00:00
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