重新添加L和R引脚
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:15:56 2022 " "Info: Processing started: Mon Mar 07 11:15:56 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:17:18 2022 " "Info: Processing started: Tue Mar 08 15:17:18 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
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{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
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{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
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{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
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{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "221 " "Info: Peak virtual memory: 221 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:15:57 2022 " "Info: Processing ended: Mon Mar 07 11:15:57 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
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{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:17:18 2022 " "Info: Processing ended: Tue Mar 08 15:17:18 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
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檔案差異因為一行或多行太長而無法顯示
@ -1,9 +1,9 @@
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:17:07 2022 " "Info: Processing started: Mon Mar 07 11:17:07 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:17:15 2022 " "Info: Processing started: Tue Mar 08 15:17:15 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 shifter_8b " "Info: Found entity 1: shifter_8b" { } { { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 shifter_8b " "Info: Found entity 1: shifter_8b" { } { { "shifter_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
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{ "Info" "ISGN_START_ELABORATION_TOP" "shifter_8b " "Info: Elaborating entity \"shifter_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
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{ "Warning" "WSGN_SEARCH_FILE" "triple_selector_8b.bdf 1 1 " "Warning: Using design file triple_selector_8b.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 triple_selector_8b " "Info: Found entity 1: triple_selector_8b" { } { { "triple_selector_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/triple_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "triple_selector_8b triple_selector_8b:inst " "Info: Elaborating entity \"triple_selector_8b\" for hierarchy \"triple_selector_8b:inst\"" { } { { "shifter_8b.bdf" "inst" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 32 488 584 512 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
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{ "Warning" "WSGN_SEARCH_FILE" "triple_selector_8b.bdf 1 1 " "Warning: Using design file triple_selector_8b.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 triple_selector_8b " "Info: Found entity 1: triple_selector_8b" { } { { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/triple_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "triple_selector_8b triple_selector_8b:inst " "Info: Elaborating entity \"triple_selector_8b\" for hierarchy \"triple_selector_8b:inst\"" { } { { "shifter_8b.bdf" "inst" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { { 32 488 584 512 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
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{ "Info" "ICUT_CUT_TM_SUMMARY" "33 " "Info: Implemented 33 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Info: Implemented 11 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "14 " "Info: Implemented 14 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
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{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "229 " "Info: Peak virtual memory: 229 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:17:07 2022 " "Info: Processing ended: Mon Mar 07 11:17:07 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
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{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:17:15 2022 " "Info: Processing ended: Tue Mar 08 15:17:15 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
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@ -1,6 +1,6 @@
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 11:15:57 2022 " "Info: Processing started: Mon Mar 07 11:15:57 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:17:19 2022 " "Info: Processing started: Tue Mar 08 15:17:19 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 6 " "Info: Parallel compilation is enabled and will use 4 of the 6 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
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{ "Info" "ITDB_FULL_TPD_RESULT" "A6 Y7 13.413 ns Longest " "Info: Longest tpd from source pin \"A6\" to destination pin \"Y7\" is 13.413 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns A6 1 PIN PIN_67 3 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_67; Fanout = 3; PIN Node = 'A6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A6 } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 120 40 208 136 "A6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.895 ns) + CELL(0.624 ns) 8.513 ns triple_selector_8b:inst\|inst31 2 COMB LCCOMB_X1_Y5_N10 1 " "Info: 2: + IC(6.895 ns) + CELL(0.624 ns) = 8.513 ns; Loc. = LCCOMB_X1_Y5_N10; Fanout = 1; COMB Node = 'triple_selector_8b:inst\|inst31'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.519 ns" { A6 triple_selector_8b:inst|inst31 } "NODE_NAME" } } { "triple_selector_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/triple_selector_8b.bdf" { { 64 488 552 112 "inst31" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.604 ns) + CELL(3.296 ns) 13.413 ns Y7 3 PIN PIN_60 0 " "Info: 3: + IC(1.604 ns) + CELL(3.296 ns) = 13.413 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'Y7'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.900 ns" { triple_selector_8b:inst|inst31 Y7 } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 56 688 864 72 "Y7" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.914 ns ( 36.64 % ) " "Info: Total cell delay = 4.914 ns ( 36.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.499 ns ( 63.36 % ) " "Info: Total interconnect delay = 8.499 ns ( 63.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "13.413 ns" { A6 triple_selector_8b:inst|inst31 Y7 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "13.413 ns" { A6 {} A6~combout {} triple_selector_8b:inst|inst31 {} Y7 {} } { 0.000ns 0.000ns 6.895ns 1.604ns } { 0.000ns 0.994ns 0.624ns 3.296ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
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{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "191 " "Info: Peak virtual memory: 191 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 11:15:58 2022 " "Info: Processing ended: Mon Mar 07 11:15:58 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
|
||||
{ "Info" "ITDB_FULL_TPD_RESULT" "LM Y5 15.661 ns Longest " "Info: Longest tpd from source pin \"LM\" to destination pin \"Y5\" is 15.661 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns LM 1 PIN PIN_69 7 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_69; Fanout = 7; PIN Node = 'LM'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LM } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { { 456 40 208 472 "LM" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.879 ns) + CELL(0.650 ns) 8.523 ns triple_selector_8b:inst\|inst23~0 2 COMB LCCOMB_X26_Y1_N18 1 " "Info: 2: + IC(6.879 ns) + CELL(0.650 ns) = 8.523 ns; Loc. = LCCOMB_X26_Y1_N18; Fanout = 1; COMB Node = 'triple_selector_8b:inst\|inst23~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.529 ns" { LM triple_selector_8b:inst|inst23~0 } "NODE_NAME" } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/triple_selector_8b.bdf" { { 352 488 552 400 "inst23" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.370 ns) + CELL(0.624 ns) 9.517 ns triple_selector_8b:inst\|inst23 3 COMB LCCOMB_X26_Y1_N20 1 " "Info: 3: + IC(0.370 ns) + CELL(0.624 ns) = 9.517 ns; Loc. = LCCOMB_X26_Y1_N20; Fanout = 1; COMB Node = 'triple_selector_8b:inst\|inst23'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.994 ns" { triple_selector_8b:inst|inst23~0 triple_selector_8b:inst|inst23 } "NODE_NAME" } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/triple_selector_8b.bdf" { { 352 488 552 400 "inst23" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.028 ns) + CELL(3.116 ns) 15.661 ns Y5 4 PIN PIN_147 0 " "Info: 4: + IC(3.028 ns) + CELL(3.116 ns) = 15.661 ns; Loc. = PIN_147; Fanout = 0; PIN Node = 'Y5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.144 ns" { triple_selector_8b:inst|inst23 Y5 } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { { 88 688 864 104 "Y5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.384 ns ( 34.38 % ) " "Info: Total cell delay = 5.384 ns ( 34.38 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "10.277 ns ( 65.62 % ) " "Info: Total interconnect delay = 10.277 ns ( 65.62 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "15.661 ns" { LM triple_selector_8b:inst|inst23~0 triple_selector_8b:inst|inst23 Y5 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "15.661 ns" { LM {} LM~combout {} triple_selector_8b:inst|inst23~0 {} triple_selector_8b:inst|inst23 {} Y5 {} } { 0.000ns 0.000ns 6.879ns 0.370ns 3.028ns } { 0.000ns 0.994ns 0.650ns 0.624ns 3.116ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:17:19 2022 " "Info: Processing ended: Tue Mar 08 15:17:19 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
|
||||
|
||||
未顯示二進位檔案。
未顯示二進位檔案。
@ -1,7 +1,7 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:17:18 2022 " "Info: Processing started: Tue Mar 08 15:17:18 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 10 14:51:55 2022 " "Info: Processing started: Thu Mar 10 14:51:55 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
|
||||
{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:17:18 2022 " "Info: Processing ended: Tue Mar 08 15:17:18 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "221 " "Info: Peak virtual memory: 221 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 10 14:51:55 2022 " "Info: Processing ended: Thu Mar 10 14:51:55 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
|
||||
|
||||
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
@ -1,13 +1,14 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:17:16 2022 " "Info: Processing started: Tue Mar 08 15:17:16 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 10 14:51:52 2022 " "Info: Processing started: Thu Mar 10 14:51:52 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 6 " "Info: Parallel compilation is enabled and will use 4 of the 6 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
|
||||
{ "Info" "IMPP_MPP_USER_DEVICE" "shifter_8b EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"shifter_8b\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
|
||||
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
|
||||
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "d:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
|
||||
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
|
||||
{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "2 21 " "Warning: No exact pin location assignment(s) for 2 pins of 21 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "L " "Info: Pin L not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { L } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 600 40 208 616 "L" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { L } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "R " "Info: Pin R not assigned to an exact location on the device" { } { { "c:/altera/90sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90sp2/quartus/bin/pin_planner.ppl" { R } } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 648 40 208 664 "R" "" } } } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { R } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
|
||||
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
|
||||
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
|
||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
|
||||
@ -18,6 +19,8 @@
|
||||
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1}
|
||||
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1}
|
||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
|
||||
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "2 unused 3.3V 2 0 0 " "Info: Number of I/O pins in group: 2 (unused VREF, 3.3V VCCIO, 2 input, 0 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 2 30 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 35 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.3V 9 26 " "Info: I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 9 total pin(s) used -- 26 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 11 25 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 11 total pin(s) used -- 25 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
|
||||
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
|
||||
@ -25,11 +28,11 @@
|
||||
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y0 X34_Y9 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X34_Y9" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y10 X34_Y19 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y10 to location X34_Y19" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
|
||||
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
|
||||
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y0 0 " "Info: Pin \"Y0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y1 0 " "Info: Pin \"Y1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y2 0 " "Info: Pin \"Y2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y3 0 " "Info: Pin \"Y3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y4 0 " "Info: Pin \"Y4\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y5 0 " "Info: Pin \"Y5\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y6 0 " "Info: Pin \"Y6\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Y7 0 " "Info: Pin \"Y7\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
|
||||
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
|
||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/projects/quartus/shifter_8b/shifter_8b.fit.smsg " "Info: Generated suppressed messages file D:/projects/quartus/shifter_8b/shifter_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "306 " "Info: Peak virtual memory: 306 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:17:17 2022 " "Info: Processing ended: Tue Mar 08 15:17:17 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/dev/quartus/shifter_8b/shifter_8b.fit.smsg " "Info: Generated suppressed messages file D:/dev/quartus/shifter_8b/shifter_8b.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "285 " "Info: Peak virtual memory: 285 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 10 14:51:54 2022 " "Info: Processing ended: Thu Mar 10 14:51:54 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
|
||||
|
||||
@ -5,6 +5,7 @@ A6 => triple_selector_8b:inst.B6
|
||||
A6 => triple_selector_8b:inst.C5
|
||||
A7 => triple_selector_8b:inst.B7
|
||||
A7 => triple_selector_8b:inst.C6
|
||||
R => triple_selector_8b:inst.C7
|
||||
A5 => triple_selector_8b:inst.A6
|
||||
A5 => triple_selector_8b:inst.B5
|
||||
A5 => triple_selector_8b:inst.C4
|
||||
@ -22,6 +23,7 @@ A1 => triple_selector_8b:inst.B1
|
||||
A1 => triple_selector_8b:inst.C0
|
||||
A0 => triple_selector_8b:inst.A1
|
||||
A0 => triple_selector_8b:inst.B0
|
||||
L => triple_selector_8b:inst.A0
|
||||
LM => triple_selector_8b:inst.AY
|
||||
DM => triple_selector_8b:inst.BY
|
||||
RM => triple_selector_8b:inst.CY
|
||||
|
||||
@ -46,7 +46,7 @@ db|shifter_8b.(0).cnf
|
||||
# case_insensitive
|
||||
# source_file
|
||||
shifter_8b.bdf
|
||||
48c3dd91b772b04158a51fc34d535c
|
||||
14397f4ea413e68c8a371bb5b73c93a
|
||||
26
|
||||
# internal_option {
|
||||
BLOCK_DESIGN_NAMING
|
||||
|
||||
@ -18,13 +18,13 @@
|
||||
<TR valign="middle">
|
||||
<TD ALIGN="LEFT">inst</TD>
|
||||
<TD ALIGN="LEFT">27</TD>
|
||||
<TD ALIGN="LEFT">2</TD>
|
||||
<TD ALIGN="LEFT">0</TD>
|
||||
<TD ALIGN="LEFT">2</TD>
|
||||
<TD ALIGN="LEFT">0</TD>
|
||||
<TD ALIGN="LEFT">0</TD>
|
||||
<TD ALIGN="LEFT">8</TD>
|
||||
<TD ALIGN="LEFT">2</TD>
|
||||
<TD ALIGN="LEFT">2</TD>
|
||||
<TD ALIGN="LEFT">2</TD>
|
||||
<TD ALIGN="LEFT">0</TD>
|
||||
<TD ALIGN="LEFT">0</TD>
|
||||
<TD ALIGN="LEFT">0</TD>
|
||||
<TD ALIGN="LEFT">0</TD>
|
||||
<TD ALIGN="LEFT">0</TD>
|
||||
<TD ALIGN="LEFT">0</TD>
|
||||
|
||||
未顯示二進位檔案。
@ -3,5 +3,5 @@
|
||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
|
||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
; inst ; 27 ; 2 ; 0 ; 2 ; 8 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; inst ; 27 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
|
||||
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
@ -1,9 +1,9 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:17:15 2022 " "Info: Processing started: Tue Mar 08 15:17:15 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 10 14:51:50 2022 " "Info: Processing started: Thu Mar 10 14:51:50 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 shifter_8b " "Info: Found entity 1: shifter_8b" { } { { "shifter_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 shifter_8b " "Info: Found entity 1: shifter_8b" { } { { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "shifter_8b " "Info: Elaborating entity \"shifter_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
|
||||
{ "Warning" "WSGN_SEARCH_FILE" "triple_selector_8b.bdf 1 1 " "Warning: Using design file triple_selector_8b.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 triple_selector_8b " "Info: Found entity 1: triple_selector_8b" { } { { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/triple_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "triple_selector_8b triple_selector_8b:inst " "Info: Elaborating entity \"triple_selector_8b\" for hierarchy \"triple_selector_8b:inst\"" { } { { "shifter_8b.bdf" "inst" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { { 32 488 584 512 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "33 " "Info: Implemented 33 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Info: Implemented 11 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "14 " "Info: Implemented 14 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:17:15 2022 " "Info: Processing ended: Tue Mar 08 15:17:15 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
|
||||
{ "Warning" "WSGN_SEARCH_FILE" "triple_selector_8b.bdf 1 1 " "Warning: Using design file triple_selector_8b.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 triple_selector_8b " "Info: Found entity 1: triple_selector_8b" { } { { "triple_selector_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/triple_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "triple_selector_8b triple_selector_8b:inst " "Info: Elaborating entity \"triple_selector_8b\" for hierarchy \"triple_selector_8b:inst\"" { } { { "shifter_8b.bdf" "inst" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 32 488 584 512 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "37 " "Info: Implemented 37 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "13 " "Info: Implemented 13 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "16 " "Info: Implemented 16 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "229 " "Info: Peak virtual memory: 229 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 10 14:51:52 2022 " "Info: Processing ended: Thu Mar 10 14:51:52 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
|
||||
|
||||
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
未顯示二進位檔案。
@ -1,6 +1,6 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:17:19 2022 " "Info: Processing started: Tue Mar 08 15:17:19 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 10 14:51:56 2022 " "Info: Processing started: Thu Mar 10 14:51:56 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
|
||||
{ "Info" "ITDB_FULL_TPD_RESULT" "LM Y5 15.661 ns Longest " "Info: Longest tpd from source pin \"LM\" to destination pin \"Y5\" is 15.661 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns LM 1 PIN PIN_69 7 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_69; Fanout = 7; PIN Node = 'LM'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LM } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { { 456 40 208 472 "LM" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.879 ns) + CELL(0.650 ns) 8.523 ns triple_selector_8b:inst\|inst23~0 2 COMB LCCOMB_X26_Y1_N18 1 " "Info: 2: + IC(6.879 ns) + CELL(0.650 ns) = 8.523 ns; Loc. = LCCOMB_X26_Y1_N18; Fanout = 1; COMB Node = 'triple_selector_8b:inst\|inst23~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.529 ns" { LM triple_selector_8b:inst|inst23~0 } "NODE_NAME" } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/triple_selector_8b.bdf" { { 352 488 552 400 "inst23" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.370 ns) + CELL(0.624 ns) 9.517 ns triple_selector_8b:inst\|inst23 3 COMB LCCOMB_X26_Y1_N20 1 " "Info: 3: + IC(0.370 ns) + CELL(0.624 ns) = 9.517 ns; Loc. = LCCOMB_X26_Y1_N20; Fanout = 1; COMB Node = 'triple_selector_8b:inst\|inst23'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.994 ns" { triple_selector_8b:inst|inst23~0 triple_selector_8b:inst|inst23 } "NODE_NAME" } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/triple_selector_8b.bdf" { { 352 488 552 400 "inst23" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.028 ns) + CELL(3.116 ns) 15.661 ns Y5 4 PIN PIN_147 0 " "Info: 4: + IC(3.028 ns) + CELL(3.116 ns) = 15.661 ns; Loc. = PIN_147; Fanout = 0; PIN Node = 'Y5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.144 ns" { triple_selector_8b:inst|inst23 Y5 } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { { 88 688 864 104 "Y5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.384 ns ( 34.38 % ) " "Info: Total cell delay = 5.384 ns ( 34.38 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "10.277 ns ( 65.62 % ) " "Info: Total interconnect delay = 10.277 ns ( 65.62 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "15.661 ns" { LM triple_selector_8b:inst|inst23~0 triple_selector_8b:inst|inst23 Y5 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "15.661 ns" { LM {} LM~combout {} triple_selector_8b:inst|inst23~0 {} triple_selector_8b:inst|inst23 {} Y5 {} } { 0.000ns 0.000ns 6.879ns 0.370ns 3.028ns } { 0.000ns 0.994ns 0.650ns 0.624ns 3.116ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 15:17:19 2022 " "Info: Processing ended: Tue Mar 08 15:17:19 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 6 " "Info: Parallel compilation is enabled and will use 4 of the 6 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
|
||||
{ "Info" "ITDB_FULL_TPD_RESULT" "LM Y6 15.646 ns Longest " "Info: Longest tpd from source pin \"LM\" to destination pin \"Y6\" is 15.646 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns LM 1 PIN PIN_69 8 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_69; Fanout = 8; PIN Node = 'LM'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LM } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 456 40 208 472 "LM" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.993 ns) + CELL(0.624 ns) 8.611 ns triple_selector_8b:inst\|inst27~0 2 COMB LCCOMB_X21_Y10_N24 1 " "Info: 2: + IC(6.993 ns) + CELL(0.624 ns) = 8.611 ns; Loc. = LCCOMB_X21_Y10_N24; Fanout = 1; COMB Node = 'triple_selector_8b:inst\|inst27~0'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "7.617 ns" { LM triple_selector_8b:inst|inst27~0 } "NODE_NAME" } } { "triple_selector_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/triple_selector_8b.bdf" { { 208 488 552 256 "inst27" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.395 ns) + CELL(0.651 ns) 9.657 ns triple_selector_8b:inst\|inst27 3 COMB LCCOMB_X21_Y10_N18 1 " "Info: 3: + IC(0.395 ns) + CELL(0.651 ns) = 9.657 ns; Loc. = LCCOMB_X21_Y10_N18; Fanout = 1; COMB Node = 'triple_selector_8b:inst\|inst27'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.046 ns" { triple_selector_8b:inst|inst27~0 triple_selector_8b:inst|inst27 } "NODE_NAME" } } { "triple_selector_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/triple_selector_8b.bdf" { { 208 488 552 256 "inst27" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.873 ns) + CELL(3.116 ns) 15.646 ns Y6 4 PIN PIN_149 0 " "Info: 4: + IC(2.873 ns) + CELL(3.116 ns) = 15.646 ns; Loc. = PIN_149; Fanout = 0; PIN Node = 'Y6'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.989 ns" { triple_selector_8b:inst|inst27 Y6 } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/dev/quartus/shifter_8b/shifter_8b.bdf" { { 72 688 864 88 "Y6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.385 ns ( 34.42 % ) " "Info: Total cell delay = 5.385 ns ( 34.42 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "10.261 ns ( 65.58 % ) " "Info: Total interconnect delay = 10.261 ns ( 65.58 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "15.646 ns" { LM triple_selector_8b:inst|inst27~0 triple_selector_8b:inst|inst27 Y6 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "15.646 ns" { LM {} LM~combout {} triple_selector_8b:inst|inst27~0 {} triple_selector_8b:inst|inst27 {} Y6 {} } { 0.000ns 0.000ns 6.993ns 0.395ns 2.873ns } { 0.000ns 0.994ns 0.624ns 0.651ns 3.116ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "191 " "Info: Peak virtual memory: 191 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 10 14:51:56 2022 " "Info: Processing ended: Thu Mar 10 14:51:56 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
start_full_compilation:s:00:00:05
|
||||
start_full_compilation:s:00:00:07
|
||||
start_analysis_synthesis:s:00:00:02-start_full_compilation
|
||||
start_analysis_elaboration:s-start_full_compilation
|
||||
start_fitter:s:00:00:01-start_full_compilation
|
||||
start_fitter:s:00:00:02-start_full_compilation
|
||||
start_assembler:s:00:00:02-start_full_compilation
|
||||
start_timing_analyzer:s:00:00:00-start_full_compilation
|
||||
start_timing_analyzer:s:00:00:01-start_full_compilation
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
Assembler report for shifter_8b
|
||||
Tue Mar 08 15:17:18 2022
|
||||
Thu Mar 10 14:51:55 2022
|
||||
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
|
||||
|
||||
|
||||
@ -10,8 +10,8 @@ Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
|
||||
2. Assembler Summary
|
||||
3. Assembler Settings
|
||||
4. Assembler Generated Files
|
||||
5. Assembler Device Options: D:/projects/quartus/shifter_8b/shifter_8b.sof
|
||||
6. Assembler Device Options: D:/projects/quartus/shifter_8b/shifter_8b.pof
|
||||
5. Assembler Device Options: D:/dev/quartus/shifter_8b/shifter_8b.sof
|
||||
6. Assembler Device Options: D:/dev/quartus/shifter_8b/shifter_8b.pof
|
||||
7. Assembler Messages
|
||||
|
||||
|
||||
@ -38,7 +38,7 @@ applicable agreement for further details.
|
||||
+---------------------------------------------------------------+
|
||||
; Assembler Summary ;
|
||||
+-----------------------+---------------------------------------+
|
||||
; Assembler Status ; Successful - Tue Mar 08 15:17:18 2022 ;
|
||||
; Assembler Status ; Successful - Thu Mar 10 14:51:55 2022 ;
|
||||
; Revision Name ; shifter_8b ;
|
||||
; Top-level Entity Name ; shifter_8b ;
|
||||
; Family ; Cyclone II ;
|
||||
@ -76,37 +76,37 @@ applicable agreement for further details.
|
||||
+-----------------------------------------------------------------------------+----------+---------------+
|
||||
|
||||
|
||||
+-----------------------------------------------+
|
||||
; Assembler Generated Files ;
|
||||
+-----------------------------------------------+
|
||||
; File Name ;
|
||||
+-----------------------------------------------+
|
||||
; D:/projects/quartus/shifter_8b/shifter_8b.sof ;
|
||||
; D:/projects/quartus/shifter_8b/shifter_8b.pof ;
|
||||
+-----------------------------------------------+
|
||||
+------------------------------------------+
|
||||
; Assembler Generated Files ;
|
||||
+------------------------------------------+
|
||||
; File Name ;
|
||||
+------------------------------------------+
|
||||
; D:/dev/quartus/shifter_8b/shifter_8b.sof ;
|
||||
; D:/dev/quartus/shifter_8b/shifter_8b.pof ;
|
||||
+------------------------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------+
|
||||
; Assembler Device Options: D:/projects/quartus/shifter_8b/shifter_8b.sof ;
|
||||
+----------------+--------------------------------------------------------+
|
||||
; Option ; Setting ;
|
||||
+----------------+--------------------------------------------------------+
|
||||
; Device ; EP2C8Q208C8 ;
|
||||
; JTAG usercode ; 0xFFFFFFFF ;
|
||||
; Checksum ; 0x000C22C5 ;
|
||||
+----------------+--------------------------------------------------------+
|
||||
+--------------------------------------------------------------------+
|
||||
; Assembler Device Options: D:/dev/quartus/shifter_8b/shifter_8b.sof ;
|
||||
+----------------+---------------------------------------------------+
|
||||
; Option ; Setting ;
|
||||
+----------------+---------------------------------------------------+
|
||||
; Device ; EP2C8Q208C8 ;
|
||||
; JTAG usercode ; 0xFFFFFFFF ;
|
||||
; Checksum ; 0x000C2D71 ;
|
||||
+----------------+---------------------------------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------+
|
||||
; Assembler Device Options: D:/projects/quartus/shifter_8b/shifter_8b.pof ;
|
||||
+--------------------+----------------------------------------------------+
|
||||
; Option ; Setting ;
|
||||
+--------------------+----------------------------------------------------+
|
||||
; Device ; EPCS4 ;
|
||||
; JTAG usercode ; 0x00000000 ;
|
||||
; Checksum ; 0x06F00042 ;
|
||||
; Compression Ratio ; 3 ;
|
||||
+--------------------+----------------------------------------------------+
|
||||
+--------------------------------------------------------------------+
|
||||
; Assembler Device Options: D:/dev/quartus/shifter_8b/shifter_8b.pof ;
|
||||
+--------------------+-----------------------------------------------+
|
||||
; Option ; Setting ;
|
||||
+--------------------+-----------------------------------------------+
|
||||
; Device ; EPCS4 ;
|
||||
; JTAG usercode ; 0x00000000 ;
|
||||
; Checksum ; 0x06EFF64A ;
|
||||
; Compression Ratio ; 3 ;
|
||||
+--------------------+-----------------------------------------------+
|
||||
|
||||
|
||||
+--------------------+
|
||||
@ -115,15 +115,15 @@ applicable agreement for further details.
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II Assembler
|
||||
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
|
||||
Info: Processing started: Tue Mar 08 15:17:18 2022
|
||||
Info: Processing started: Thu Mar 10 14:51:55 2022
|
||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b
|
||||
Info: Writing out detailed assembly data for power analysis
|
||||
Info: Assembler is generating device programming files
|
||||
Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled
|
||||
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 241 megabytes
|
||||
Info: Processing ended: Tue Mar 08 15:17:18 2022
|
||||
Info: Peak virtual memory: 221 megabytes
|
||||
Info: Processing ended: Thu Mar 10 14:51:55 2022
|
||||
Info: Elapsed time: 00:00:00
|
||||
Info: Total CPU time (on all processors): 00:00:00
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
|
||||
|
||||
@ -35,6 +35,7 @@ applicable agreement for further details.
|
||||
(line (pt 117 12)(pt 121 8)(line_width 1))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
(annotation_block (location)(rect -8 424 40 440))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
@ -51,6 +52,7 @@ applicable agreement for further details.
|
||||
(line (pt 117 12)(pt 121 8)(line_width 1))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
(annotation_block (location)(rect -8 376 40 392))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
@ -67,6 +69,7 @@ applicable agreement for further details.
|
||||
(line (pt 117 12)(pt 121 8)(line_width 1))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
(annotation_block (location)(rect -8 328 40 344))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
@ -83,6 +86,7 @@ applicable agreement for further details.
|
||||
(line (pt 117 12)(pt 121 8)(line_width 1))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
(annotation_block (location)(rect -8 280 40 296))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
@ -99,6 +103,7 @@ applicable agreement for further details.
|
||||
(line (pt 117 12)(pt 121 8)(line_width 1))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
(annotation_block (location)(rect -8 232 40 248))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
@ -115,6 +120,7 @@ applicable agreement for further details.
|
||||
(line (pt 117 12)(pt 121 8)(line_width 1))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
(annotation_block (location)(rect -8 472 40 488))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
@ -131,6 +137,7 @@ applicable agreement for further details.
|
||||
(line (pt 117 12)(pt 121 8)(line_width 1))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
(annotation_block (location)(rect -8 520 40 536))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
@ -147,6 +154,7 @@ applicable agreement for further details.
|
||||
(line (pt 117 12)(pt 121 8)(line_width 1))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
(annotation_block (location)(rect -8 568 40 584))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
@ -163,6 +171,7 @@ applicable agreement for further details.
|
||||
(line (pt 117 12)(pt 121 8)(line_width 1))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
(annotation_block (location)(rect -8 184 40 200))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
@ -179,6 +188,7 @@ applicable agreement for further details.
|
||||
(line (pt 117 12)(pt 121 8)(line_width 1))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
(annotation_block (location)(rect -8 136 40 152))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
@ -195,6 +205,41 @@ applicable agreement for further details.
|
||||
(line (pt 117 12)(pt 121 8)(line_width 1))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
(annotation_block (location)(rect -8 88 40 104))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 40 600 208 616)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "L" (rect 5 0 10 12)(font "Arial" ))
|
||||
(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12)(line_width 1))
|
||||
(line (pt 92 4)(pt 117 4)(line_width 1))
|
||||
(line (pt 121 8)(pt 168 8)(line_width 1))
|
||||
(line (pt 92 12)(pt 92 4)(line_width 1))
|
||||
(line (pt 117 4)(pt 121 8)(line_width 1))
|
||||
(line (pt 117 12)(pt 121 8)(line_width 1))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
(annotation_block (location)(rect -8 616 40 632))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 40 648 208 664)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "R" (rect 5 0 13 12)(font "Arial" ))
|
||||
(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12)(line_width 1))
|
||||
(line (pt 92 4)(pt 117 4)(line_width 1))
|
||||
(line (pt 121 8)(pt 168 8)(line_width 1))
|
||||
(line (pt 92 12)(pt 92 4)(line_width 1))
|
||||
(line (pt 117 4)(pt 121 8)(line_width 1))
|
||||
(line (pt 117 12)(pt 121 8)(line_width 1))
|
||||
)
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
(annotation_block (location)(rect -8 664 40 680))
|
||||
)
|
||||
(pin
|
||||
(output)
|
||||
@ -211,6 +256,7 @@ applicable agreement for further details.
|
||||
(line (pt 82 8)(pt 78 12)(line_width 1))
|
||||
(line (pt 78 12)(pt 82 8)(line_width 1))
|
||||
)
|
||||
(annotation_block (location)(rect 864 184 920 200))
|
||||
)
|
||||
(pin
|
||||
(output)
|
||||
@ -227,6 +273,7 @@ applicable agreement for further details.
|
||||
(line (pt 82 8)(pt 78 12)(line_width 1))
|
||||
(line (pt 78 12)(pt 82 8)(line_width 1))
|
||||
)
|
||||
(annotation_block (location)(rect 864 168 920 184))
|
||||
)
|
||||
(pin
|
||||
(output)
|
||||
@ -243,6 +290,7 @@ applicable agreement for further details.
|
||||
(line (pt 82 8)(pt 78 12)(line_width 1))
|
||||
(line (pt 78 12)(pt 82 8)(line_width 1))
|
||||
)
|
||||
(annotation_block (location)(rect 864 152 920 168))
|
||||
)
|
||||
(pin
|
||||
(output)
|
||||
@ -259,6 +307,7 @@ applicable agreement for further details.
|
||||
(line (pt 82 8)(pt 78 12)(line_width 1))
|
||||
(line (pt 78 12)(pt 82 8)(line_width 1))
|
||||
)
|
||||
(annotation_block (location)(rect 864 136 920 152))
|
||||
)
|
||||
(pin
|
||||
(output)
|
||||
@ -275,6 +324,7 @@ applicable agreement for further details.
|
||||
(line (pt 82 8)(pt 78 12)(line_width 1))
|
||||
(line (pt 78 12)(pt 82 8)(line_width 1))
|
||||
)
|
||||
(annotation_block (location)(rect 864 120 920 136))
|
||||
)
|
||||
(pin
|
||||
(output)
|
||||
@ -291,6 +341,7 @@ applicable agreement for further details.
|
||||
(line (pt 82 8)(pt 78 12)(line_width 1))
|
||||
(line (pt 78 12)(pt 82 8)(line_width 1))
|
||||
)
|
||||
(annotation_block (location)(rect 864 104 920 120))
|
||||
)
|
||||
(pin
|
||||
(output)
|
||||
@ -307,6 +358,7 @@ applicable agreement for further details.
|
||||
(line (pt 82 8)(pt 78 12)(line_width 1))
|
||||
(line (pt 78 12)(pt 82 8)(line_width 1))
|
||||
)
|
||||
(annotation_block (location)(rect 864 88 920 104))
|
||||
)
|
||||
(pin
|
||||
(output)
|
||||
@ -323,23 +375,7 @@ applicable agreement for further details.
|
||||
(line (pt 82 8)(pt 78 12)(line_width 1))
|
||||
(line (pt 78 12)(pt 82 8)(line_width 1))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 296 496 328 528)
|
||||
(text "GND" (rect 8 16 29 26)(font "Arial" (font_size 6)))
|
||||
(text "inst1" (rect 3 21 26 33)(font "Arial" )(invisible))
|
||||
(port
|
||||
(pt 16 0)
|
||||
(output)
|
||||
(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
|
||||
(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 16 8)(pt 16 0)(line_width 1))
|
||||
)
|
||||
(drawing
|
||||
(line (pt 8 8)(pt 16 16)(line_width 1))
|
||||
(line (pt 16 16)(pt 24 8)(line_width 1))
|
||||
(line (pt 8 8)(pt 24 8)(line_width 1))
|
||||
)
|
||||
(annotation_block (location)(rect 864 72 920 88))
|
||||
)
|
||||
(symbol
|
||||
(rect 488 32 584 512)
|
||||
@ -802,22 +838,6 @@ applicable agreement for further details.
|
||||
(pt 360 80)
|
||||
(pt 488 80)
|
||||
)
|
||||
(connector
|
||||
(pt 488 96)
|
||||
(pt 312 96)
|
||||
)
|
||||
(connector
|
||||
(pt 488 400)
|
||||
(pt 312 400)
|
||||
)
|
||||
(connector
|
||||
(pt 312 96)
|
||||
(pt 312 400)
|
||||
)
|
||||
(connector
|
||||
(pt 312 400)
|
||||
(pt 312 496)
|
||||
)
|
||||
(connector
|
||||
(pt 488 480)
|
||||
(pt 288 480)
|
||||
@ -854,6 +874,30 @@ applicable agreement for further details.
|
||||
(pt 288 560)
|
||||
(pt 208 560)
|
||||
)
|
||||
(connector
|
||||
(pt 208 656)
|
||||
(pt 304 656)
|
||||
)
|
||||
(connector
|
||||
(pt 304 96)
|
||||
(pt 304 656)
|
||||
)
|
||||
(connector
|
||||
(pt 304 96)
|
||||
(pt 488 96)
|
||||
)
|
||||
(connector
|
||||
(pt 488 400)
|
||||
(pt 320 400)
|
||||
)
|
||||
(connector
|
||||
(pt 320 608)
|
||||
(pt 320 400)
|
||||
)
|
||||
(connector
|
||||
(pt 208 608)
|
||||
(pt 320 608)
|
||||
)
|
||||
(junction (pt 472 416))
|
||||
(junction (pt 456 368))
|
||||
(junction (pt 440 320))
|
||||
@ -862,4 +906,3 @@ applicable agreement for further details.
|
||||
(junction (pt 392 176))
|
||||
(junction (pt 376 128))
|
||||
(junction (pt 360 80))
|
||||
(junction (pt 312 400))
|
||||
|
||||
@ -1 +1 @@
|
||||
Tue Mar 08 15:17:19 2022
|
||||
Thu Mar 10 14:51:57 2022
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
Fitter report for shifter_8b
|
||||
Tue Mar 08 15:17:17 2022
|
||||
Thu Mar 10 14:51:54 2022
|
||||
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
|
||||
|
||||
|
||||
@ -63,18 +63,18 @@ applicable agreement for further details.
|
||||
+-----------------------------------------------------------------------------------+
|
||||
; Fitter Summary ;
|
||||
+------------------------------------+----------------------------------------------+
|
||||
; Fitter Status ; Successful - Tue Mar 08 15:17:17 2022 ;
|
||||
; Fitter Status ; Successful - Thu Mar 10 14:51:54 2022 ;
|
||||
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
|
||||
; Revision Name ; shifter_8b ;
|
||||
; Top-level Entity Name ; shifter_8b ;
|
||||
; Family ; Cyclone II ;
|
||||
; Device ; EP2C8Q208C8 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 14 / 8,256 ( < 1 % ) ;
|
||||
; Total combinational functions ; 14 / 8,256 ( < 1 % ) ;
|
||||
; Total logic elements ; 16 / 8,256 ( < 1 % ) ;
|
||||
; Total combinational functions ; 16 / 8,256 ( < 1 % ) ;
|
||||
; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ;
|
||||
; Total registers ; 0 ;
|
||||
; Total pins ; 19 / 138 ( 14 % ) ;
|
||||
; Total pins ; 21 / 138 ( 15 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; Total memory bits ; 0 / 165,888 ( 0 % ) ;
|
||||
; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
|
||||
@ -138,7 +138,7 @@ applicable agreement for further details.
|
||||
+----------------------------+-------------+
|
||||
; Processors ; Number ;
|
||||
+----------------------------+-------------+
|
||||
; Number detected on machine ; 4 ;
|
||||
; Number detected on machine ; 6 ;
|
||||
; Maximum allowed ; 4 ;
|
||||
; ; ;
|
||||
; Average used ; 1.00 ;
|
||||
@ -147,6 +147,7 @@ applicable agreement for further details.
|
||||
; Usage by Processor ; % Time Used ;
|
||||
; 1 processor ; 100.0% ;
|
||||
; 2-4 processors ; < 0.1% ;
|
||||
; 5-6 processors ; 0.0% ;
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
@ -156,8 +157,8 @@ applicable agreement for further details.
|
||||
; Type ; Value ;
|
||||
+-------------------------+--------------------+
|
||||
; Placement ; ;
|
||||
; -- Requested ; 0 / 33 ( 0.00 % ) ;
|
||||
; -- Achieved ; 0 / 33 ( 0.00 % ) ;
|
||||
; -- Requested ; 0 / 37 ( 0.00 % ) ;
|
||||
; -- Achieved ; 0 / 37 ( 0.00 % ) ;
|
||||
; ; ;
|
||||
; Routing (by Connection) ; ;
|
||||
; -- Requested ; 0 / 0 ( 0.00 % ) ;
|
||||
@ -179,14 +180,14 @@ applicable agreement for further details.
|
||||
+----------------+---------+-------------------+-------------------------+-------------------+
|
||||
; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
|
||||
+----------------+---------+-------------------+-------------------------+-------------------+
|
||||
; Top ; 33 ; 0 ; N/A ; Source File ;
|
||||
; Top ; 37 ; 0 ; N/A ; Source File ;
|
||||
+----------------+---------+-------------------+-------------------------+-------------------+
|
||||
|
||||
|
||||
+--------------+
|
||||
; Pin-Out File ;
|
||||
+--------------+
|
||||
The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin.
|
||||
The pin-out file can be found in D:/dev/quartus/shifter_8b/shifter_8b.pin.
|
||||
|
||||
|
||||
+--------------------------------------------------------------------+
|
||||
@ -194,19 +195,19 @@ The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin.
|
||||
+---------------------------------------------+----------------------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+----------------------+
|
||||
; Total logic elements ; 14 / 8,256 ( < 1 % ) ;
|
||||
; -- Combinational with no register ; 14 ;
|
||||
; Total logic elements ; 16 / 8,256 ( < 1 % ) ;
|
||||
; -- Combinational with no register ; 16 ;
|
||||
; -- Register only ; 0 ;
|
||||
; -- Combinational with a register ; 0 ;
|
||||
; ; ;
|
||||
; Logic element usage by number of LUT inputs ; ;
|
||||
; -- 4 input functions ; 8 ;
|
||||
; -- 3 input functions ; 6 ;
|
||||
; -- 3 input functions ; 8 ;
|
||||
; -- <=2 input functions ; 0 ;
|
||||
; -- Register only ; 0 ;
|
||||
; ; ;
|
||||
; Logic elements by mode ; ;
|
||||
; -- normal mode ; 14 ;
|
||||
; -- normal mode ; 16 ;
|
||||
; -- arithmetic mode ; 0 ;
|
||||
; ; ;
|
||||
; Total registers* ; 0 / 8,646 ( 0 % ) ;
|
||||
@ -216,7 +217,7 @@ The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin.
|
||||
; Total LABs: partially or completely used ; 1 / 516 ( < 1 % ) ;
|
||||
; User inserted logic elements ; 0 ;
|
||||
; Virtual pins ; 0 ;
|
||||
; I/O pins ; 19 / 138 ( 14 % ) ;
|
||||
; I/O pins ; 21 / 138 ( 15 % ) ;
|
||||
; -- Clock pins ; 0 / 4 ( 0 % ) ;
|
||||
; Global signals ; 0 ;
|
||||
; M4Ks ; 0 / 36 ( 0 % ) ;
|
||||
@ -230,12 +231,12 @@ The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin.
|
||||
; CRC blocks ; 0 / 1 ( 0 % ) ;
|
||||
; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ;
|
||||
; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ;
|
||||
; Maximum fan-out node ; DM ;
|
||||
; Maximum fan-out node ; LM ;
|
||||
; Maximum fan-out ; 8 ;
|
||||
; Highest non-global fan-out signal ; DM ;
|
||||
; Highest non-global fan-out signal ; LM ;
|
||||
; Highest non-global fan-out ; 8 ;
|
||||
; Total fan-out ; 58 ;
|
||||
; Average fan-out ; 1.61 ;
|
||||
; Total fan-out ; 64 ;
|
||||
; Average fan-out ; 1.60 ;
|
||||
+---------------------------------------------+----------------------+
|
||||
* Register count does not include registers inside RAM blocks or DSP blocks.
|
||||
|
||||
@ -255,8 +256,10 @@ The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin.
|
||||
; A6 ; 87 ; 4 ; 25 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
|
||||
; A7 ; 88 ; 4 ; 25 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
|
||||
; DM ; 68 ; 4 ; 12 ; 0 ; 1 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
|
||||
; LM ; 69 ; 4 ; 12 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
|
||||
; RM ; 67 ; 4 ; 9 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
|
||||
; L ; 92 ; 4 ; 28 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
|
||||
; LM ; 69 ; 4 ; 12 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
|
||||
; R ; 76 ; 4 ; 18 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
|
||||
; RM ; 67 ; 4 ; 9 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
|
||||
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
|
||||
|
||||
|
||||
@ -284,7 +287,7 @@ The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin.
|
||||
; 1 ; 2 / 32 ( 6 % ) ; 3.3V ; -- ;
|
||||
; 2 ; 0 / 35 ( 0 % ) ; 3.3V ; -- ;
|
||||
; 3 ; 9 / 35 ( 26 % ) ; 3.3V ; -- ;
|
||||
; 4 ; 11 / 36 ( 31 % ) ; 3.3V ; -- ;
|
||||
; 4 ; 13 / 36 ( 36 % ) ; 3.3V ; -- ;
|
||||
+----------+------------------+---------------+--------------+
|
||||
|
||||
|
||||
@ -368,7 +371,7 @@ The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin.
|
||||
; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; 74 ; 76 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
|
||||
; 75 ; 77 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
|
||||
; 76 ; 78 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
|
||||
; 76 ; 78 ; 4 ; R ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
|
||||
; 77 ; 79 ; 4 ; A0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
|
||||
; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||
@ -384,7 +387,7 @@ The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin.
|
||||
; 89 ; 89 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
|
||||
; 90 ; 90 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
|
||||
; 91 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
|
||||
; 92 ; 91 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
|
||||
; 92 ; 91 ; 4 ; L ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
|
||||
; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; 94 ; 92 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
|
||||
; 95 ; 93 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
|
||||
@ -547,8 +550,8 @@ Note: User assignments will override these defaults. The user specified values a
|
||||
+------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------+--------------+
|
||||
; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ;
|
||||
+------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------+--------------+
|
||||
; |shifter_8b ; 14 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 ; 0 ; 14 (0) ; 0 (0) ; 0 (0) ; |shifter_8b ; work ;
|
||||
; |triple_selector_8b:inst| ; 14 (14) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 (14) ; 0 (0) ; 0 (0) ; |shifter_8b|triple_selector_8b:inst ; work ;
|
||||
; |shifter_8b ; 16 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 21 ; 0 ; 16 (0) ; 0 (0) ; 0 (0) ; |shifter_8b ; work ;
|
||||
; |triple_selector_8b:inst| ; 16 (16) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (16) ; 0 (0) ; 0 (0) ; |shifter_8b|triple_selector_8b:inst ; work ;
|
||||
+------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------+--------------+
|
||||
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
||||
|
||||
@ -567,16 +570,18 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; Y6 ; Output ; -- ; -- ; -- ; -- ;
|
||||
; Y7 ; Output ; -- ; -- ; -- ; -- ;
|
||||
; A0 ; Input ; 6 ; 6 ; -- ; -- ;
|
||||
; L ; Input ; 6 ; 6 ; -- ; -- ;
|
||||
; LM ; Input ; 6 ; 6 ; -- ; -- ;
|
||||
; DM ; Input ; 6 ; 6 ; -- ; -- ;
|
||||
; A1 ; Input ; 6 ; 6 ; -- ; -- ;
|
||||
; RM ; Input ; 6 ; 6 ; -- ; -- ;
|
||||
; DM ; Input ; 6 ; 6 ; -- ; -- ;
|
||||
; LM ; Input ; 6 ; 6 ; -- ; -- ;
|
||||
; A2 ; Input ; 6 ; 6 ; -- ; -- ;
|
||||
; A3 ; Input ; 6 ; 6 ; -- ; -- ;
|
||||
; A4 ; Input ; 6 ; 6 ; -- ; -- ;
|
||||
; A5 ; Input ; 6 ; 6 ; -- ; -- ;
|
||||
; A6 ; Input ; 6 ; 6 ; -- ; -- ;
|
||||
; A7 ; Input ; 6 ; 6 ; -- ; -- ;
|
||||
; R ; Input ; 6 ; 6 ; -- ; -- ;
|
||||
+------+----------+---------------+---------------+-----------------------+-----+
|
||||
|
||||
|
||||
@ -586,37 +591,41 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
|
||||
+-----------------------------------------+-------------------+---------+
|
||||
; A0 ; ; ;
|
||||
; - triple_selector_8b:inst|inst3 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst7~0 ; 0 ; 6 ;
|
||||
; A1 ; ; ;
|
||||
; - triple_selector_8b:inst|inst3 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst7~0 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst11~0 ; 0 ; 6 ;
|
||||
; RM ; ; ;
|
||||
; - triple_selector_8b:inst|inst3 ; 1 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst7 ; 1 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst11 ; 1 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst15 ; 1 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst19 ; 1 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst23 ; 1 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst27 ; 1 ; 6 ;
|
||||
; DM ; ; ;
|
||||
; - triple_selector_8b:inst|inst3 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst7~0 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst11~0 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst15~0 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst19~0 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst23~0 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst27~0 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst31 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst3~0 ; 1 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst7~0 ; 1 ; 6 ;
|
||||
; L ; ; ;
|
||||
; - triple_selector_8b:inst|inst3~0 ; 0 ; 6 ;
|
||||
; LM ; ; ;
|
||||
; - triple_selector_8b:inst|inst3~0 ; 1 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst7~0 ; 1 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst11~0 ; 1 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst15~0 ; 1 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst19~0 ; 1 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst23~0 ; 1 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst27~0 ; 1 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst31 ; 1 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst31~0 ; 1 ; 6 ;
|
||||
; DM ; ; ;
|
||||
; - triple_selector_8b:inst|inst3~0 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst7~0 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst11~0 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst15~0 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst19~0 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst23~0 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst27~0 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst31~0 ; 0 ; 6 ;
|
||||
; A1 ; ; ;
|
||||
; - triple_selector_8b:inst|inst3 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst7~0 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst11~0 ; 0 ; 6 ;
|
||||
; RM ; ; ;
|
||||
; - triple_selector_8b:inst|inst3 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst7 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst11 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst15 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst19 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst23 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst27 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst31 ; 0 ; 6 ;
|
||||
; A2 ; ; ;
|
||||
; - triple_selector_8b:inst|inst7 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst11~0 ; 0 ; 6 ;
|
||||
@ -630,15 +639,17 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; - triple_selector_8b:inst|inst19~0 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst23~0 ; 0 ; 6 ;
|
||||
; A5 ; ; ;
|
||||
; - triple_selector_8b:inst|inst19 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst23~0 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst27~0 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst19 ; 1 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst23~0 ; 1 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst27~0 ; 1 ; 6 ;
|
||||
; A6 ; ; ;
|
||||
; - triple_selector_8b:inst|inst23 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst27~0 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst31 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst31~0 ; 0 ; 6 ;
|
||||
; A7 ; ; ;
|
||||
; - triple_selector_8b:inst|inst27 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst27 ; 1 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst31~0 ; 1 ; 6 ;
|
||||
; R ; ; ;
|
||||
; - triple_selector_8b:inst|inst31 ; 0 ; 6 ;
|
||||
+-----------------------------------------+-------------------+---------+
|
||||
|
||||
@ -648,9 +659,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+----------------------------------+---------+
|
||||
; Name ; Fan-Out ;
|
||||
+----------------------------------+---------+
|
||||
; RM ; 8 ;
|
||||
; DM ; 8 ;
|
||||
; LM ; 7 ;
|
||||
; RM ; 7 ;
|
||||
; LM ; 8 ;
|
||||
; A6 ; 3 ;
|
||||
; A5 ; 3 ;
|
||||
; A4 ; 3 ;
|
||||
@ -659,7 +670,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; A1 ; 3 ;
|
||||
; A7 ; 2 ;
|
||||
; A0 ; 2 ;
|
||||
; R ; 1 ;
|
||||
; L ; 1 ;
|
||||
; triple_selector_8b:inst|inst31 ; 1 ;
|
||||
; triple_selector_8b:inst|inst31~0 ; 1 ;
|
||||
; triple_selector_8b:inst|inst27 ; 1 ;
|
||||
; triple_selector_8b:inst|inst27~0 ; 1 ;
|
||||
; triple_selector_8b:inst|inst23 ; 1 ;
|
||||
@ -673,6 +687,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; triple_selector_8b:inst|inst7 ; 1 ;
|
||||
; triple_selector_8b:inst|inst7~0 ; 1 ;
|
||||
; triple_selector_8b:inst|inst3 ; 1 ;
|
||||
; triple_selector_8b:inst|inst3~0 ; 1 ;
|
||||
+----------------------------------+---------+
|
||||
|
||||
|
||||
@ -681,21 +696,21 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+----------------------------+-----------------------+
|
||||
; Interconnect Resource Type ; Usage ;
|
||||
+----------------------------+-----------------------+
|
||||
; Block interconnects ; 20 / 26,052 ( < 1 % ) ;
|
||||
; C16 interconnects ; 3 / 1,156 ( < 1 % ) ;
|
||||
; C4 interconnects ; 38 / 17,952 ( < 1 % ) ;
|
||||
; Block interconnects ; 23 / 26,052 ( < 1 % ) ;
|
||||
; C16 interconnects ; 16 / 1,156 ( 1 % ) ;
|
||||
; C4 interconnects ; 21 / 17,952 ( < 1 % ) ;
|
||||
; Direct links ; 0 / 26,052 ( 0 % ) ;
|
||||
; Global clocks ; 0 / 8 ( 0 % ) ;
|
||||
; Local interconnects ; 6 / 8,256 ( < 1 % ) ;
|
||||
; R24 interconnects ; 3 / 1,020 ( < 1 % ) ;
|
||||
; R4 interconnects ; 23 / 22,440 ( < 1 % ) ;
|
||||
; Local interconnects ; 8 / 8,256 ( < 1 % ) ;
|
||||
; R24 interconnects ; 6 / 1,020 ( < 1 % ) ;
|
||||
; R4 interconnects ; 37 / 22,440 ( < 1 % ) ;
|
||||
+----------------------------+-----------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------+
|
||||
; LAB Logic Elements ;
|
||||
+---------------------------------------------+-----------------------------+
|
||||
; Number of Logic Elements (Average = 14.00) ; Number of LABs (Total = 1) ;
|
||||
; Number of Logic Elements (Average = 16.00) ; Number of LABs (Total = 1) ;
|
||||
+---------------------------------------------+-----------------------------+
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 0 ;
|
||||
@ -710,16 +725,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; 11 ; 0 ;
|
||||
; 12 ; 0 ;
|
||||
; 13 ; 0 ;
|
||||
; 14 ; 1 ;
|
||||
; 14 ; 0 ;
|
||||
; 15 ; 0 ;
|
||||
; 16 ; 0 ;
|
||||
; 16 ; 1 ;
|
||||
+---------------------------------------------+-----------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced ;
|
||||
+----------------------------------------------+-----------------------------+
|
||||
; Number of Signals Sourced (Average = 14.00) ; Number of LABs (Total = 1) ;
|
||||
; Number of Signals Sourced (Average = 16.00) ; Number of LABs (Total = 1) ;
|
||||
+----------------------------------------------+-----------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
@ -735,7 +750,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; 11 ; 0 ;
|
||||
; 12 ; 0 ;
|
||||
; 13 ; 0 ;
|
||||
; 14 ; 1 ;
|
||||
; 14 ; 0 ;
|
||||
; 15 ; 0 ;
|
||||
; 16 ; 1 ;
|
||||
+----------------------------------------------+-----------------------------+
|
||||
|
||||
|
||||
@ -759,7 +776,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+----------------------------------------------------------------------------+
|
||||
; LAB Distinct Inputs ;
|
||||
+----------------------------------------------+-----------------------------+
|
||||
; Number of Distinct Inputs (Average = 11.00) ; Number of LABs (Total = 1) ;
|
||||
; Number of Distinct Inputs (Average = 13.00) ; Number of LABs (Total = 1) ;
|
||||
+----------------------------------------------+-----------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
@ -772,7 +789,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; 8 ; 0 ;
|
||||
; 9 ; 0 ;
|
||||
; 10 ; 0 ;
|
||||
; 11 ; 1 ;
|
||||
; 11 ; 0 ;
|
||||
; 12 ; 0 ;
|
||||
; 13 ; 1 ;
|
||||
+----------------------------------------------+-----------------------------+
|
||||
|
||||
|
||||
@ -831,11 +850,11 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; Auto Fit Point 1 - Fit Attempt 1 ; ff ;
|
||||
; Mid Wire Use - Fit Attempt 1 ; 0 ;
|
||||
; Mid Slack - Fit Attempt 1 ; 2147483639 ;
|
||||
; Internal Atom Count - Fit Attempt 1 ; 15 ;
|
||||
; LE/ALM Count - Fit Attempt 1 ; 15 ;
|
||||
; Internal Atom Count - Fit Attempt 1 ; 17 ;
|
||||
; LE/ALM Count - Fit Attempt 1 ; 17 ;
|
||||
; LAB Count - Fit Attempt 1 ; 2 ;
|
||||
; Outputs per Lab - Fit Attempt 1 ; 4.000 ;
|
||||
; Inputs per LAB - Fit Attempt 1 ; 5.500 ;
|
||||
; Inputs per LAB - Fit Attempt 1 ; 6.500 ;
|
||||
; Global Inputs per LAB - Fit Attempt 1 ; 0.000 ;
|
||||
; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:2 ;
|
||||
; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:2 ;
|
||||
@ -907,9 +926,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II Fitter
|
||||
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
|
||||
Info: Processing started: Tue Mar 08 15:17:16 2022
|
||||
Info: Processing started: Thu Mar 10 14:51:52 2022
|
||||
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b
|
||||
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
|
||||
Info: Parallel compilation is enabled and will use 4 of the 6 processors detected
|
||||
Info: Selected device EP2C8Q208C8 for design "shifter_8b"
|
||||
Info: Low junction temperature is 0 degrees C
|
||||
Info: High junction temperature is 85 degrees C
|
||||
@ -922,11 +941,23 @@ Info: Fitter converted 3 user pins into dedicated programming pins
|
||||
Info: Pin ~ASDO~ is reserved at location 1
|
||||
Info: Pin ~nCSO~ is reserved at location 2
|
||||
Info: Pin ~LVDS54p/nCEO~ is reserved at location 108
|
||||
Warning: No exact pin location assignment(s) for 2 pins of 21 total pins
|
||||
Info: Pin L not assigned to an exact location on the device
|
||||
Info: Pin R not assigned to an exact location on the device
|
||||
Info: Fitter is using the Classic Timing Analyzer
|
||||
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
|
||||
Info: Starting register packing
|
||||
Info: Finished register packing
|
||||
Extra Info: No registers were packed into other blocks
|
||||
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
|
||||
Info: Number of I/O pins in group: 2 (unused VREF, 3.3V VCCIO, 2 input, 0 output, 0 bidirectional)
|
||||
Info: I/O standards used: 3.3-V LVTTL.
|
||||
Info: I/O bank details before I/O pin placement
|
||||
Info: Statistics of I/O banks
|
||||
Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available
|
||||
Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available
|
||||
Info: I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 9 total pin(s) used -- 26 pins available
|
||||
Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 11 total pin(s) used -- 25 pins available
|
||||
Info: Fitter preparation operations ending: elapsed time is 00:00:00
|
||||
Info: Fitter placement preparation operations beginning
|
||||
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
|
||||
@ -935,7 +966,7 @@ Info: Fitter placement was successful
|
||||
Info: Fitter placement operations ending: elapsed time is 00:00:00
|
||||
Info: Fitter routing operations beginning
|
||||
Info: Average interconnect usage is 0% of the available device resources
|
||||
Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X34_Y9
|
||||
Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y10 to location X34_Y19
|
||||
Info: Fitter routing operations ending: elapsed time is 00:00:00
|
||||
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
|
||||
Info: Optimizations that may affect the design's routability were skipped
|
||||
@ -951,17 +982,17 @@ Warning: Found 8 output pins without output pin load capacitance assignment
|
||||
Info: Pin "Y6" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
||||
Info: Pin "Y7" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
||||
Info: Delay annotation completed successfully
|
||||
Info: Generated suppressed messages file D:/projects/quartus/shifter_8b/shifter_8b.fit.smsg
|
||||
Info: Quartus II Fitter was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 306 megabytes
|
||||
Info: Processing ended: Tue Mar 08 15:17:17 2022
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Generated suppressed messages file D:/dev/quartus/shifter_8b/shifter_8b.fit.smsg
|
||||
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
|
||||
Info: Peak virtual memory: 285 megabytes
|
||||
Info: Processing ended: Thu Mar 10 14:51:54 2022
|
||||
Info: Elapsed time: 00:00:02
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
|
||||
+----------------------------+
|
||||
; Fitter Suppressed Messages ;
|
||||
+----------------------------+
|
||||
The suppressed messages can be found in D:/projects/quartus/shifter_8b/shifter_8b.fit.smsg.
|
||||
The suppressed messages can be found in D:/dev/quartus/shifter_8b/shifter_8b.fit.smsg.
|
||||
|
||||
|
||||
|
||||
@ -1,15 +1,15 @@
|
||||
Fitter Status : Successful - Tue Mar 08 15:17:17 2022
|
||||
Fitter Status : Successful - Thu Mar 10 14:51:54 2022
|
||||
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
|
||||
Revision Name : shifter_8b
|
||||
Top-level Entity Name : shifter_8b
|
||||
Family : Cyclone II
|
||||
Device : EP2C8Q208C8
|
||||
Timing Models : Final
|
||||
Total logic elements : 14 / 8,256 ( < 1 % )
|
||||
Total combinational functions : 14 / 8,256 ( < 1 % )
|
||||
Total logic elements : 16 / 8,256 ( < 1 % )
|
||||
Total combinational functions : 16 / 8,256 ( < 1 % )
|
||||
Dedicated logic registers : 0 / 8,256 ( 0 % )
|
||||
Total registers : 0
|
||||
Total pins : 19 / 138 ( 14 % )
|
||||
Total pins : 21 / 138 ( 15 % )
|
||||
Total virtual pins : 0
|
||||
Total memory bits : 0 / 165,888 ( 0 % )
|
||||
Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % )
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
Flow report for shifter_8b
|
||||
Tue Mar 08 15:17:19 2022
|
||||
Thu Mar 10 14:51:56 2022
|
||||
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
|
||||
|
||||
|
||||
@ -38,7 +38,7 @@ applicable agreement for further details.
|
||||
+-----------------------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+------------------------------------+----------------------------------------------+
|
||||
; Flow Status ; Successful - Tue Mar 08 15:17:19 2022 ;
|
||||
; Flow Status ; Successful - Thu Mar 10 14:51:56 2022 ;
|
||||
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
|
||||
; Revision Name ; shifter_8b ;
|
||||
; Top-level Entity Name ; shifter_8b ;
|
||||
@ -46,11 +46,11 @@ applicable agreement for further details.
|
||||
; Device ; EP2C8Q208C8 ;
|
||||
; Timing Models ; Final ;
|
||||
; Met timing requirements ; Yes ;
|
||||
; Total logic elements ; 14 / 8,256 ( < 1 % ) ;
|
||||
; Total combinational functions ; 14 / 8,256 ( < 1 % ) ;
|
||||
; Total logic elements ; 16 / 8,256 ( < 1 % ) ;
|
||||
; Total combinational functions ; 16 / 8,256 ( < 1 % ) ;
|
||||
; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ;
|
||||
; Total registers ; 0 ;
|
||||
; Total pins ; 19 / 138 ( 14 % ) ;
|
||||
; Total pins ; 21 / 138 ( 15 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; Total memory bits ; 0 / 165,888 ( 0 % ) ;
|
||||
; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
|
||||
@ -63,7 +63,7 @@ applicable agreement for further details.
|
||||
+-------------------+---------------------+
|
||||
; Option ; Setting ;
|
||||
+-------------------+---------------------+
|
||||
; Start date & time ; 03/08/2022 15:17:15 ;
|
||||
; Start date & time ; 03/10/2022 14:51:51 ;
|
||||
; Main task ; Compilation ;
|
||||
; Revision Name ; shifter_8b ;
|
||||
+-------------------+---------------------+
|
||||
@ -74,7 +74,7 @@ applicable agreement for further details.
|
||||
+------------------------------------+-----------------------------------------------+---------------+-------------+----------------+
|
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||
+------------------------------------+-----------------------------------------------+---------------+-------------+----------------+
|
||||
; COMPILER_SIGNATURE_ID ; 220283517943889.164672383512820 ; -- ; -- ; -- ;
|
||||
; COMPILER_SIGNATURE_ID ; 136411542855513.164689511129872 ; -- ; -- ; -- ;
|
||||
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||||
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
||||
; MISC_FILE ; D:/dev/quartus/shifter_8b/shifter_8b.dpf ; -- ; -- ; -- ;
|
||||
@ -90,11 +90,11 @@ applicable agreement for further details.
|
||||
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 246 MB ; 00:00:00 ;
|
||||
; Fitter ; 00:00:01 ; 1.0 ; 306 MB ; 00:00:01 ;
|
||||
; Assembler ; 00:00:00 ; 1.0 ; 241 MB ; 00:00:00 ;
|
||||
; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 198 MB ; 00:00:00 ;
|
||||
; Total ; 00:00:01 ; -- ; -- ; 00:00:01 ;
|
||||
; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 226 MB ; 00:00:01 ;
|
||||
; Fitter ; 00:00:02 ; 1.0 ; 285 MB ; 00:00:01 ;
|
||||
; Assembler ; 00:00:00 ; 1.0 ; 221 MB ; 00:00:01 ;
|
||||
; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 177 MB ; 00:00:00 ;
|
||||
; Total ; 00:00:03 ; -- ; -- ; 00:00:03 ;
|
||||
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
|
||||
|
||||
@ -103,10 +103,10 @@ applicable agreement for further details.
|
||||
+-------------------------+------------------+---------------+------------+----------------+
|
||||
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
|
||||
+-------------------------+------------------+---------------+------------+----------------+
|
||||
; Analysis & Synthesis ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
|
||||
; Fitter ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
|
||||
; Assembler ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
|
||||
; Classic Timing Analyzer ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
|
||||
; Analysis & Synthesis ; DESKTOP-G0CBSMT ; Windows Vista ; 6.2 ; x86_64 ;
|
||||
; Fitter ; DESKTOP-G0CBSMT ; Windows Vista ; 6.2 ; x86_64 ;
|
||||
; Assembler ; DESKTOP-G0CBSMT ; Windows Vista ; 6.2 ; x86_64 ;
|
||||
; Classic Timing Analyzer ; DESKTOP-G0CBSMT ; Windows Vista ; 6.2 ; x86_64 ;
|
||||
+-------------------------+------------------+---------------+------------+----------------+
|
||||
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
Analysis & Synthesis report for shifter_8b
|
||||
Tue Mar 08 15:17:15 2022
|
||||
Thu Mar 10 14:51:51 2022
|
||||
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
|
||||
|
||||
|
||||
@ -39,16 +39,16 @@ applicable agreement for further details.
|
||||
+-----------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+------------------------------------+----------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Tue Mar 08 15:17:15 2022 ;
|
||||
; Analysis & Synthesis Status ; Successful - Thu Mar 10 14:51:51 2022 ;
|
||||
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
|
||||
; Revision Name ; shifter_8b ;
|
||||
; Top-level Entity Name ; shifter_8b ;
|
||||
; Family ; Cyclone II ;
|
||||
; Total logic elements ; 14 ;
|
||||
; Total combinational functions ; 14 ;
|
||||
; Total logic elements ; 16 ;
|
||||
; Total combinational functions ; 16 ;
|
||||
; Dedicated logic registers ; 0 ;
|
||||
; Total registers ; 0 ;
|
||||
; Total pins ; 19 ;
|
||||
; Total pins ; 21 ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; Total memory bits ; 0 ;
|
||||
; Embedded Multiplier 9-bit elements ; 0 ;
|
||||
@ -131,14 +131,14 @@ applicable agreement for further details.
|
||||
+--------------------------------------------------------------+--------------------+--------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Source Files Read ;
|
||||
+----------------------------------+-----------------+------------------------------------------+-------------------------------------------------------+
|
||||
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
|
||||
+----------------------------------+-----------------+------------------------------------------+-------------------------------------------------------+
|
||||
; shifter_8b.bdf ; yes ; User Block Diagram/Schematic File ; D:/projects/quartus/shifter_8b/shifter_8b.bdf ;
|
||||
; triple_selector_8b.bdf ; yes ; Auto-Found Block Diagram/Schematic File ; D:/projects/quartus/shifter_8b/triple_selector_8b.bdf ;
|
||||
+----------------------------------+-----------------+------------------------------------------+-------------------------------------------------------+
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Source Files Read ;
|
||||
+----------------------------------+-----------------+------------------------------------------+--------------------------------------------------+
|
||||
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
|
||||
+----------------------------------+-----------------+------------------------------------------+--------------------------------------------------+
|
||||
; shifter_8b.bdf ; yes ; User Block Diagram/Schematic File ; D:/dev/quartus/shifter_8b/shifter_8b.bdf ;
|
||||
; triple_selector_8b.bdf ; yes ; Auto-Found Block Diagram/Schematic File ; D:/dev/quartus/shifter_8b/triple_selector_8b.bdf ;
|
||||
+----------------------------------+-----------------+------------------------------------------+--------------------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------+
|
||||
@ -146,27 +146,27 @@ applicable agreement for further details.
|
||||
+---------------------------------------------+-------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+-------+
|
||||
; Estimated Total logic elements ; 14 ;
|
||||
; Estimated Total logic elements ; 16 ;
|
||||
; ; ;
|
||||
; Total combinational functions ; 14 ;
|
||||
; Total combinational functions ; 16 ;
|
||||
; Logic element usage by number of LUT inputs ; ;
|
||||
; -- 4 input functions ; 8 ;
|
||||
; -- 3 input functions ; 6 ;
|
||||
; -- 3 input functions ; 8 ;
|
||||
; -- <=2 input functions ; 0 ;
|
||||
; ; ;
|
||||
; Logic elements by mode ; ;
|
||||
; -- normal mode ; 14 ;
|
||||
; -- normal mode ; 16 ;
|
||||
; -- arithmetic mode ; 0 ;
|
||||
; ; ;
|
||||
; Total registers ; 0 ;
|
||||
; -- Dedicated logic registers ; 0 ;
|
||||
; -- I/O registers ; 0 ;
|
||||
; ; ;
|
||||
; I/O pins ; 19 ;
|
||||
; Maximum fan-out node ; DM ;
|
||||
; I/O pins ; 21 ;
|
||||
; Maximum fan-out node ; LM ;
|
||||
; Maximum fan-out ; 8 ;
|
||||
; Total fan-out ; 58 ;
|
||||
; Average fan-out ; 1.76 ;
|
||||
; Total fan-out ; 64 ;
|
||||
; Average fan-out ; 1.73 ;
|
||||
+---------------------------------------------+-------+
|
||||
|
||||
|
||||
@ -175,8 +175,8 @@ applicable agreement for further details.
|
||||
+------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------+--------------+
|
||||
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
|
||||
+------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------+--------------+
|
||||
; |shifter_8b ; 14 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 19 ; 0 ; |shifter_8b ; work ;
|
||||
; |triple_selector_8b:inst| ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |shifter_8b|triple_selector_8b:inst ; work ;
|
||||
; |shifter_8b ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 21 ; 0 ; |shifter_8b ; work ;
|
||||
; |triple_selector_8b:inst| ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |shifter_8b|triple_selector_8b:inst ; work ;
|
||||
+------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------+--------------+
|
||||
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
||||
|
||||
@ -202,7 +202,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II Analysis & Synthesis
|
||||
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
|
||||
Info: Processing started: Tue Mar 08 15:17:15 2022
|
||||
Info: Processing started: Thu Mar 10 14:51:50 2022
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b
|
||||
Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf
|
||||
Info: Found entity 1: shifter_8b
|
||||
@ -210,14 +210,14 @@ Info: Elaborating entity "shifter_8b" for the top level hierarchy
|
||||
Warning: Using design file triple_selector_8b.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
|
||||
Info: Found entity 1: triple_selector_8b
|
||||
Info: Elaborating entity "triple_selector_8b" for hierarchy "triple_selector_8b:inst"
|
||||
Info: Implemented 33 device resources after synthesis - the final resource count might be different
|
||||
Info: Implemented 11 input pins
|
||||
Info: Implemented 37 device resources after synthesis - the final resource count might be different
|
||||
Info: Implemented 13 input pins
|
||||
Info: Implemented 8 output pins
|
||||
Info: Implemented 14 logic cells
|
||||
Info: Implemented 16 logic cells
|
||||
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 250 megabytes
|
||||
Info: Processing ended: Tue Mar 08 15:17:15 2022
|
||||
Info: Elapsed time: 00:00:00
|
||||
Info: Total CPU time (on all processors): 00:00:00
|
||||
Info: Peak virtual memory: 229 megabytes
|
||||
Info: Processing ended: Thu Mar 10 14:51:52 2022
|
||||
Info: Elapsed time: 00:00:02
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
|
||||
|
||||
@ -1,13 +1,13 @@
|
||||
Analysis & Synthesis Status : Successful - Tue Mar 08 15:17:15 2022
|
||||
Analysis & Synthesis Status : Successful - Thu Mar 10 14:51:51 2022
|
||||
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
|
||||
Revision Name : shifter_8b
|
||||
Top-level Entity Name : shifter_8b
|
||||
Family : Cyclone II
|
||||
Total logic elements : 14
|
||||
Total combinational functions : 14
|
||||
Total logic elements : 16
|
||||
Total combinational functions : 16
|
||||
Dedicated logic registers : 0
|
||||
Total registers : 0
|
||||
Total pins : 19
|
||||
Total pins : 21
|
||||
Total virtual pins : 0
|
||||
Total memory bits : 0
|
||||
Embedded Multiplier 9-bit elements : 0
|
||||
|
||||
@ -143,7 +143,7 @@ RESERVED_INPUT : 72 : : :
|
||||
GND : 73 : gnd : : : :
|
||||
RESERVED_INPUT : 74 : : : : 4 :
|
||||
RESERVED_INPUT : 75 : : : : 4 :
|
||||
RESERVED_INPUT : 76 : : : : 4 :
|
||||
R : 76 : input : 3.3-V LVTTL : : 4 : N
|
||||
A0 : 77 : input : 3.3-V LVTTL : : 4 : Y
|
||||
GND : 78 : gnd : : : :
|
||||
VCCINT : 79 : power : : 1.2V : :
|
||||
@ -159,7 +159,7 @@ A7 : 88 : input : 3.3-V LVTTL :
|
||||
RESERVED_INPUT : 89 : : : : 4 :
|
||||
RESERVED_INPUT : 90 : : : : 4 :
|
||||
VCCIO4 : 91 : power : : 3.3V : 4 :
|
||||
RESERVED_INPUT : 92 : : : : 4 :
|
||||
L : 92 : input : 3.3-V LVTTL : : 4 : N
|
||||
GND : 93 : gnd : : : :
|
||||
RESERVED_INPUT : 94 : : : : 4 :
|
||||
RESERVED_INPUT : 95 : : : : 4 :
|
||||
|
||||
未顯示二進位檔案。
@ -74,4 +74,5 @@ set_location_assignment PIN_146 -to Y4
|
||||
set_location_assignment PIN_147 -to Y5
|
||||
set_location_assignment PIN_149 -to Y6
|
||||
set_location_assignment PIN_150 -to Y7
|
||||
set_global_assignment -name MISC_FILE "D:/projects/quartus/shifter_8b/shifter_8b.dpf"
|
||||
set_global_assignment -name MISC_FILE "D:/projects/quartus/shifter_8b/shifter_8b.dpf"
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
|
||||
@ -4,6 +4,10 @@ ptn_Child1=Frames
|
||||
ptn_Child1=ChildFrames
|
||||
[ProjectWorkspace.Frames.ChildFrames]
|
||||
ptn_Child1=Document-0
|
||||
ptn_Child2=Document-1
|
||||
ptn_Child3=Document-2
|
||||
ptn_Child4=Document-3
|
||||
ptn_Child5=Document-4
|
||||
[ProjectWorkspace.Frames.ChildFrames.Document-0]
|
||||
ptn_Child1=ViewFrame-0
|
||||
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
|
||||
@ -12,3 +16,19 @@ DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde}
|
||||
IsChildFrameDetached=False
|
||||
IsActiveChildFrame=True
|
||||
ptn_Child1=StateMap
|
||||
[ProjectWorkspace.Frames.ChildFrames.Document-1]
|
||||
ptn_Child1=ViewFrame-0
|
||||
[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0]
|
||||
DocPathName=triple_selector_8b.bdf
|
||||
DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde}
|
||||
IsChildFrameDetached=False
|
||||
IsActiveChildFrame=False
|
||||
ptn_Child1=StateMap
|
||||
[ProjectWorkspace.Frames.ChildFrames.Document-2]
|
||||
ptn_Child1=ViewFrame-0
|
||||
[ProjectWorkspace.Frames.ChildFrames.Document-2.ViewFrame-0]
|
||||
DocPathName=shifter_8b.bsf
|
||||
DocumentCLSID={7b19e8f4-2bbe-11d1-a082-0020affa5bde}
|
||||
IsChildFrameDetached=False
|
||||
IsActiveChildFrame=False
|
||||
ptn_Child1=StateMap
|
||||
|
||||
未顯示二進位檔案。
@ -1,5 +1,5 @@
|
||||
Classic Timing Analyzer report for shifter_8b
|
||||
Tue Mar 08 15:17:19 2022
|
||||
Thu Mar 10 14:51:56 2022
|
||||
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
|
||||
|
||||
|
||||
@ -39,7 +39,7 @@ applicable agreement for further details.
|
||||
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
|
||||
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
|
||||
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
|
||||
; Worst-case tpd ; N/A ; None ; 15.661 ns ; LM ; Y5 ; -- ; -- ; 0 ;
|
||||
; Worst-case tpd ; N/A ; None ; 15.646 ns ; LM ; Y6 ; -- ; -- ; 0 ;
|
||||
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
|
||||
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
|
||||
|
||||
@ -81,7 +81,7 @@ applicable agreement for further details.
|
||||
+----------------------------+-------------+
|
||||
; Processors ; Number ;
|
||||
+----------------------------+-------------+
|
||||
; Number detected on machine ; 4 ;
|
||||
; Number detected on machine ; 6 ;
|
||||
; Maximum allowed ; 4 ;
|
||||
; ; ;
|
||||
; Average used ; 1.00 ;
|
||||
@ -89,7 +89,7 @@ applicable agreement for further details.
|
||||
; ; ;
|
||||
; Usage by Processor ; % Time Used ;
|
||||
; 1 processor ; 100.0% ;
|
||||
; 2-4 processors ; 0.0% ;
|
||||
; 2-6 processors ; 0.0% ;
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
@ -98,50 +98,54 @@ applicable agreement for further details.
|
||||
+-------+-------------------+-----------------+------+----+
|
||||
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
|
||||
+-------+-------------------+-----------------+------+----+
|
||||
; N/A ; None ; 15.661 ns ; LM ; Y5 ;
|
||||
; N/A ; None ; 15.651 ns ; DM ; Y5 ;
|
||||
; N/A ; None ; 15.610 ns ; LM ; Y3 ;
|
||||
; N/A ; None ; 15.606 ns ; DM ; Y3 ;
|
||||
; N/A ; None ; 15.297 ns ; DM ; Y1 ;
|
||||
; N/A ; None ; 15.251 ns ; DM ; Y6 ;
|
||||
; N/A ; None ; 15.189 ns ; LM ; Y4 ;
|
||||
; N/A ; None ; 15.186 ns ; DM ; Y4 ;
|
||||
; N/A ; None ; 14.807 ns ; LM ; Y1 ;
|
||||
; N/A ; None ; 14.796 ns ; DM ; Y2 ;
|
||||
; N/A ; None ; 14.768 ns ; LM ; Y6 ;
|
||||
; N/A ; None ; 14.737 ns ; RM ; Y6 ;
|
||||
; N/A ; None ; 14.714 ns ; RM ; Y5 ;
|
||||
; N/A ; None ; 14.662 ns ; RM ; Y3 ;
|
||||
; N/A ; None ; 14.654 ns ; RM ; Y4 ;
|
||||
; N/A ; None ; 14.633 ns ; DM ; Y7 ;
|
||||
; N/A ; None ; 14.630 ns ; LM ; Y7 ;
|
||||
; N/A ; None ; 14.582 ns ; A0 ; Y1 ;
|
||||
; N/A ; None ; 14.517 ns ; A3 ; Y3 ;
|
||||
; N/A ; None ; 15.646 ns ; LM ; Y6 ;
|
||||
; N/A ; None ; 15.635 ns ; DM ; Y4 ;
|
||||
; N/A ; None ; 15.562 ns ; LM ; Y4 ;
|
||||
; N/A ; None ; 15.337 ns ; A6 ; Y6 ;
|
||||
; N/A ; None ; 15.239 ns ; DM ; Y6 ;
|
||||
; N/A ; None ; 15.230 ns ; DM ; Y0 ;
|
||||
; N/A ; None ; 15.217 ns ; DM ; Y5 ;
|
||||
; N/A ; None ; 15.211 ns ; DM ; Y1 ;
|
||||
; N/A ; None ; 15.186 ns ; DM ; Y2 ;
|
||||
; N/A ; None ; 15.161 ns ; LM ; Y0 ;
|
||||
; N/A ; None ; 15.148 ns ; LM ; Y5 ;
|
||||
; N/A ; None ; 15.141 ns ; LM ; Y1 ;
|
||||
; N/A ; None ; 15.115 ns ; LM ; Y2 ;
|
||||
; N/A ; None ; 14.955 ns ; L ; Y0 ;
|
||||
; N/A ; None ; 14.954 ns ; A3 ; Y4 ;
|
||||
; N/A ; None ; 14.878 ns ; LM ; Y7 ;
|
||||
; N/A ; None ; 14.829 ns ; A6 ; Y7 ;
|
||||
; N/A ; None ; 14.828 ns ; A7 ; Y7 ;
|
||||
; N/A ; None ; 14.763 ns ; A4 ; Y4 ;
|
||||
; N/A ; None ; 14.737 ns ; A0 ; Y0 ;
|
||||
; N/A ; None ; 14.726 ns ; DM ; Y7 ;
|
||||
; N/A ; None ; 14.719 ns ; A0 ; Y1 ;
|
||||
; N/A ; None ; 14.714 ns ; A5 ; Y6 ;
|
||||
; N/A ; None ; 14.704 ns ; DM ; Y3 ;
|
||||
; N/A ; None ; 14.631 ns ; LM ; Y3 ;
|
||||
; N/A ; None ; 14.548 ns ; A2 ; Y2 ;
|
||||
; N/A ; None ; 14.509 ns ; A1 ; Y1 ;
|
||||
; N/A ; None ; 14.410 ns ; A2 ; Y3 ;
|
||||
; N/A ; None ; 14.345 ns ; RM ; Y1 ;
|
||||
; N/A ; None ; 14.328 ns ; LM ; Y2 ;
|
||||
; N/A ; None ; 14.284 ns ; RM ; Y2 ;
|
||||
; N/A ; None ; 14.272 ns ; RM ; Y0 ;
|
||||
; N/A ; None ; 14.232 ns ; A5 ; Y5 ;
|
||||
; N/A ; None ; 14.231 ns ; DM ; Y0 ;
|
||||
; N/A ; None ; 14.156 ns ; A6 ; Y6 ;
|
||||
; N/A ; None ; 14.096 ns ; A3 ; Y4 ;
|
||||
; N/A ; None ; 14.080 ns ; A2 ; Y2 ;
|
||||
; N/A ; None ; 14.078 ns ; A4 ; Y5 ;
|
||||
; N/A ; None ; 13.824 ns ; A5 ; Y6 ;
|
||||
; N/A ; None ; 13.706 ns ; A1 ; Y2 ;
|
||||
; N/A ; None ; 13.606 ns ; A4 ; Y4 ;
|
||||
; N/A ; None ; 13.309 ns ; A0 ; Y0 ;
|
||||
; N/A ; None ; 13.231 ns ; A7 ; Y6 ;
|
||||
; N/A ; None ; 13.196 ns ; A5 ; Y4 ;
|
||||
; N/A ; None ; 13.181 ns ; A7 ; Y7 ;
|
||||
; N/A ; None ; 13.141 ns ; A1 ; Y0 ;
|
||||
; N/A ; None ; 13.137 ns ; A3 ; Y2 ;
|
||||
; N/A ; None ; 13.099 ns ; A2 ; Y1 ;
|
||||
; N/A ; None ; 13.098 ns ; A6 ; Y5 ;
|
||||
; N/A ; None ; 13.064 ns ; A6 ; Y7 ;
|
||||
; N/A ; None ; 13.036 ns ; A4 ; Y3 ;
|
||||
; N/A ; None ; 14.487 ns ; A1 ; Y2 ;
|
||||
; N/A ; None ; 14.397 ns ; R ; Y7 ;
|
||||
; N/A ; None ; 14.391 ns ; RM ; Y6 ;
|
||||
; N/A ; None ; 14.373 ns ; RM ; Y4 ;
|
||||
; N/A ; None ; 14.365 ns ; RM ; Y7 ;
|
||||
; N/A ; None ; 14.346 ns ; A4 ; Y5 ;
|
||||
; N/A ; None ; 14.300 ns ; A7 ; Y6 ;
|
||||
; N/A ; None ; 14.259 ns ; RM ; Y1 ;
|
||||
; N/A ; None ; 14.215 ns ; A5 ; Y5 ;
|
||||
; N/A ; None ; 14.066 ns ; A2 ; Y3 ;
|
||||
; N/A ; None ; 14.002 ns ; RM ; Y5 ;
|
||||
; N/A ; None ; 13.950 ns ; A5 ; Y4 ;
|
||||
; N/A ; None ; 13.923 ns ; RM ; Y2 ;
|
||||
; N/A ; None ; 13.902 ns ; RM ; Y0 ;
|
||||
; N/A ; None ; 13.836 ns ; A3 ; Y3 ;
|
||||
; N/A ; None ; 13.818 ns ; A3 ; Y2 ;
|
||||
; N/A ; None ; 13.589 ns ; A2 ; Y1 ;
|
||||
; N/A ; None ; 13.485 ns ; A6 ; Y5 ;
|
||||
; N/A ; None ; 13.479 ns ; A1 ; Y0 ;
|
||||
; N/A ; None ; 13.437 ns ; RM ; Y3 ;
|
||||
; N/A ; None ; 12.844 ns ; A4 ; Y3 ;
|
||||
+-------+-------------------+-----------------+------+----+
|
||||
|
||||
|
||||
@ -151,19 +155,19 @@ applicable agreement for further details.
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II Classic Timing Analyzer
|
||||
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
|
||||
Info: Processing started: Tue Mar 08 15:17:19 2022
|
||||
Info: Processing started: Thu Mar 10 14:51:56 2022
|
||||
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only
|
||||
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
|
||||
Info: Longest tpd from source pin "LM" to destination pin "Y5" is 15.661 ns
|
||||
Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_69; Fanout = 7; PIN Node = 'LM'
|
||||
Info: 2: + IC(6.879 ns) + CELL(0.650 ns) = 8.523 ns; Loc. = LCCOMB_X26_Y1_N18; Fanout = 1; COMB Node = 'triple_selector_8b:inst|inst23~0'
|
||||
Info: 3: + IC(0.370 ns) + CELL(0.624 ns) = 9.517 ns; Loc. = LCCOMB_X26_Y1_N20; Fanout = 1; COMB Node = 'triple_selector_8b:inst|inst23'
|
||||
Info: 4: + IC(3.028 ns) + CELL(3.116 ns) = 15.661 ns; Loc. = PIN_147; Fanout = 0; PIN Node = 'Y5'
|
||||
Info: Total cell delay = 5.384 ns ( 34.38 % )
|
||||
Info: Total interconnect delay = 10.277 ns ( 65.62 % )
|
||||
Info: Parallel compilation is enabled and will use 4 of the 6 processors detected
|
||||
Info: Longest tpd from source pin "LM" to destination pin "Y6" is 15.646 ns
|
||||
Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_69; Fanout = 8; PIN Node = 'LM'
|
||||
Info: 2: + IC(6.993 ns) + CELL(0.624 ns) = 8.611 ns; Loc. = LCCOMB_X21_Y10_N24; Fanout = 1; COMB Node = 'triple_selector_8b:inst|inst27~0'
|
||||
Info: 3: + IC(0.395 ns) + CELL(0.651 ns) = 9.657 ns; Loc. = LCCOMB_X21_Y10_N18; Fanout = 1; COMB Node = 'triple_selector_8b:inst|inst27'
|
||||
Info: 4: + IC(2.873 ns) + CELL(3.116 ns) = 15.646 ns; Loc. = PIN_149; Fanout = 0; PIN Node = 'Y6'
|
||||
Info: Total cell delay = 5.385 ns ( 34.42 % )
|
||||
Info: Total interconnect delay = 10.261 ns ( 65.58 % )
|
||||
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 212 megabytes
|
||||
Info: Processing ended: Tue Mar 08 15:17:19 2022
|
||||
Info: Peak virtual memory: 191 megabytes
|
||||
Info: Processing ended: Thu Mar 10 14:51:56 2022
|
||||
Info: Elapsed time: 00:00:00
|
||||
Info: Total CPU time (on all processors): 00:00:00
|
||||
|
||||
|
||||
@ -5,9 +5,9 @@ Timing Analyzer Summary
|
||||
Type : Worst-case tpd
|
||||
Slack : N/A
|
||||
Required Time : None
|
||||
Actual Time : 15.661 ns
|
||||
Actual Time : 15.646 ns
|
||||
From : LM
|
||||
To : Y5
|
||||
To : Y6
|
||||
From Clock : --
|
||||
To Clock : --
|
||||
Failed Paths : 0
|
||||
|
||||
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