重新添加L和R引脚
此提交包含在：
@@ -1,5 +1,5 @@
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Fitter report for shifter_8b
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Tue Mar 08 15:17:17 2022
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Thu Mar 10 14:51:54 2022
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Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
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@@ -63,18 +63,18 @@ applicable agreement for further details.
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+-----------------------------------------------------------------------------------+
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; Fitter Summary ;
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+------------------------------------+----------------------------------------------+
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; Fitter Status ; Successful - Tue Mar 08 15:17:17 2022 ;
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; Fitter Status ; Successful - Thu Mar 10 14:51:54 2022 ;
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; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
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; Revision Name ; shifter_8b ;
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; Top-level Entity Name ; shifter_8b ;
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; Family ; Cyclone II ;
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; Device ; EP2C8Q208C8 ;
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; Timing Models ; Final ;
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; Total logic elements ; 14 / 8,256 ( < 1 % ) ;
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; Total combinational functions ; 14 / 8,256 ( < 1 % ) ;
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; Total logic elements ; 16 / 8,256 ( < 1 % ) ;
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; Total combinational functions ; 16 / 8,256 ( < 1 % ) ;
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; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ;
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; Total registers ; 0 ;
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; Total pins ; 19 / 138 ( 14 % ) ;
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; Total pins ; 21 / 138 ( 15 % ) ;
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; Total virtual pins ; 0 ;
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; Total memory bits ; 0 / 165,888 ( 0 % ) ;
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; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
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@@ -138,7 +138,7 @@ applicable agreement for further details.
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+----------------------------+-------------+
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; Processors ; Number ;
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+----------------------------+-------------+
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; Number detected on machine ; 4 ;
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; Number detected on machine ; 6 ;
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; Maximum allowed ; 4 ;
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; ; ;
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; Average used ; 1.00 ;
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@@ -147,6 +147,7 @@ applicable agreement for further details.
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; Usage by Processor ; % Time Used ;
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; 1 processor ; 100.0% ;
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; 2-4 processors ; < 0.1% ;
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; 5-6 processors ; 0.0% ;
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+----------------------------+-------------+
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@@ -156,8 +157,8 @@ applicable agreement for further details.
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; Type ; Value ;
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+-------------------------+--------------------+
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; Placement ; ;
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; -- Requested ; 0 / 33 ( 0.00 % ) ;
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; -- Achieved ; 0 / 33 ( 0.00 % ) ;
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; -- Requested ; 0 / 37 ( 0.00 % ) ;
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; -- Achieved ; 0 / 37 ( 0.00 % ) ;
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; ; ;
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; Routing (by Connection) ; ;
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; -- Requested ; 0 / 0 ( 0.00 % ) ;
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@@ -179,14 +180,14 @@ applicable agreement for further details.
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+----------------+---------+-------------------+-------------------------+-------------------+
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; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
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+----------------+---------+-------------------+-------------------------+-------------------+
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; Top ; 33 ; 0 ; N/A ; Source File ;
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; Top ; 37 ; 0 ; N/A ; Source File ;
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+----------------+---------+-------------------+-------------------------+-------------------+
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+--------------+
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; Pin-Out File ;
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+--------------+
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The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin.
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The pin-out file can be found in D:/dev/quartus/shifter_8b/shifter_8b.pin.
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+--------------------------------------------------------------------+
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@@ -194,19 +195,19 @@ The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin.
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+---------------------------------------------+----------------------+
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; Resource ; Usage ;
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+---------------------------------------------+----------------------+
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; Total logic elements ; 14 / 8,256 ( < 1 % ) ;
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; -- Combinational with no register ; 14 ;
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; Total logic elements ; 16 / 8,256 ( < 1 % ) ;
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; -- Combinational with no register ; 16 ;
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; -- Register only ; 0 ;
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; -- Combinational with a register ; 0 ;
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; ; ;
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; Logic element usage by number of LUT inputs ; ;
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; -- 4 input functions ; 8 ;
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; -- 3 input functions ; 6 ;
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; -- 3 input functions ; 8 ;
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; -- <=2 input functions ; 0 ;
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; -- Register only ; 0 ;
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; ; ;
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; Logic elements by mode ; ;
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; -- normal mode ; 14 ;
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; -- normal mode ; 16 ;
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; -- arithmetic mode ; 0 ;
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; ; ;
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; Total registers* ; 0 / 8,646 ( 0 % ) ;
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@@ -216,7 +217,7 @@ The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin.
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; Total LABs: partially or completely used ; 1 / 516 ( < 1 % ) ;
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; User inserted logic elements ; 0 ;
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; Virtual pins ; 0 ;
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; I/O pins ; 19 / 138 ( 14 % ) ;
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; I/O pins ; 21 / 138 ( 15 % ) ;
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; -- Clock pins ; 0 / 4 ( 0 % ) ;
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; Global signals ; 0 ;
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; M4Ks ; 0 / 36 ( 0 % ) ;
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@@ -230,12 +231,12 @@ The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin.
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; CRC blocks ; 0 / 1 ( 0 % ) ;
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; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ;
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; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ;
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; Maximum fan-out node ; DM ;
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; Maximum fan-out node ; LM ;
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; Maximum fan-out ; 8 ;
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; Highest non-global fan-out signal ; DM ;
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; Highest non-global fan-out signal ; LM ;
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; Highest non-global fan-out ; 8 ;
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; Total fan-out ; 58 ;
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; Average fan-out ; 1.61 ;
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; Total fan-out ; 64 ;
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; Average fan-out ; 1.60 ;
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+---------------------------------------------+----------------------+
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* Register count does not include registers inside RAM blocks or DSP blocks.
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@@ -255,8 +256,10 @@ The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin.
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; A6 ; 87 ; 4 ; 25 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
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; A7 ; 88 ; 4 ; 25 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
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; DM ; 68 ; 4 ; 12 ; 0 ; 1 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
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; LM ; 69 ; 4 ; 12 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
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; RM ; 67 ; 4 ; 9 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
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; L ; 92 ; 4 ; 28 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
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; LM ; 69 ; 4 ; 12 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
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; R ; 76 ; 4 ; 18 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
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; RM ; 67 ; 4 ; 9 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ;
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+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
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@@ -284,7 +287,7 @@ The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin.
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; 1 ; 2 / 32 ( 6 % ) ; 3.3V ; -- ;
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; 2 ; 0 / 35 ( 0 % ) ; 3.3V ; -- ;
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; 3 ; 9 / 35 ( 26 % ) ; 3.3V ; -- ;
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; 4 ; 11 / 36 ( 31 % ) ; 3.3V ; -- ;
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; 4 ; 13 / 36 ( 36 % ) ; 3.3V ; -- ;
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+----------+------------------+---------------+--------------+
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@@ -368,7 +371,7 @@ The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin.
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; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; 74 ; 76 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
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; 75 ; 77 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
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; 76 ; 78 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
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; 76 ; 78 ; 4 ; R ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
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; 77 ; 79 ; 4 ; A0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
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; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
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@@ -384,7 +387,7 @@ The pin-out file can be found in D:/projects/quartus/shifter_8b/shifter_8b.pin.
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; 89 ; 89 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
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; 90 ; 90 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
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; 91 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
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; 92 ; 91 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
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; 92 ; 91 ; 4 ; L ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
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; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; 94 ; 92 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
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; 95 ; 93 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
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@@ -547,8 +550,8 @@ Note: User assignments will override these defaults. The user specified values a
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+------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------+--------------+
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; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ;
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+------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------+--------------+
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; |shifter_8b ; 14 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 ; 0 ; 14 (0) ; 0 (0) ; 0 (0) ; |shifter_8b ; work ;
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; |triple_selector_8b:inst| ; 14 (14) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 (14) ; 0 (0) ; 0 (0) ; |shifter_8b|triple_selector_8b:inst ; work ;
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; |shifter_8b ; 16 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 21 ; 0 ; 16 (0) ; 0 (0) ; 0 (0) ; |shifter_8b ; work ;
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; |triple_selector_8b:inst| ; 16 (16) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (16) ; 0 (0) ; 0 (0) ; |shifter_8b|triple_selector_8b:inst ; work ;
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+------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------+--------------+
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Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
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@@ -567,16 +570,18 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
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; Y6 ; Output ; -- ; -- ; -- ; -- ;
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; Y7 ; Output ; -- ; -- ; -- ; -- ;
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; A0 ; Input ; 6 ; 6 ; -- ; -- ;
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; L ; Input ; 6 ; 6 ; -- ; -- ;
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; LM ; Input ; 6 ; 6 ; -- ; -- ;
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; DM ; Input ; 6 ; 6 ; -- ; -- ;
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; A1 ; Input ; 6 ; 6 ; -- ; -- ;
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; RM ; Input ; 6 ; 6 ; -- ; -- ;
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; DM ; Input ; 6 ; 6 ; -- ; -- ;
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; LM ; Input ; 6 ; 6 ; -- ; -- ;
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; A2 ; Input ; 6 ; 6 ; -- ; -- ;
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; A3 ; Input ; 6 ; 6 ; -- ; -- ;
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; A4 ; Input ; 6 ; 6 ; -- ; -- ;
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; A5 ; Input ; 6 ; 6 ; -- ; -- ;
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; A6 ; Input ; 6 ; 6 ; -- ; -- ;
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; A7 ; Input ; 6 ; 6 ; -- ; -- ;
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; R ; Input ; 6 ; 6 ; -- ; -- ;
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+------+----------+---------------+---------------+-----------------------+-----+
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@@ -586,37 +591,41 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
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; Source Pin / Fanout ; Pad To Core Index ; Setting ;
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+-----------------------------------------+-------------------+---------+
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; A0 ; ; ;
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; - triple_selector_8b:inst|inst3 ; 0 ; 6 ;
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; - triple_selector_8b:inst|inst7~0 ; 0 ; 6 ;
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; A1 ; ; ;
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; - triple_selector_8b:inst|inst3 ; 0 ; 6 ;
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; - triple_selector_8b:inst|inst7~0 ; 0 ; 6 ;
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; - triple_selector_8b:inst|inst11~0 ; 0 ; 6 ;
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; RM ; ; ;
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; - triple_selector_8b:inst|inst3 ; 1 ; 6 ;
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; - triple_selector_8b:inst|inst7 ; 1 ; 6 ;
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; - triple_selector_8b:inst|inst11 ; 1 ; 6 ;
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; - triple_selector_8b:inst|inst15 ; 1 ; 6 ;
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; - triple_selector_8b:inst|inst19 ; 1 ; 6 ;
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; - triple_selector_8b:inst|inst23 ; 1 ; 6 ;
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; - triple_selector_8b:inst|inst27 ; 1 ; 6 ;
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; DM ; ; ;
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; - triple_selector_8b:inst|inst3 ; 0 ; 6 ;
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; - triple_selector_8b:inst|inst7~0 ; 0 ; 6 ;
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; - triple_selector_8b:inst|inst11~0 ; 0 ; 6 ;
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; - triple_selector_8b:inst|inst15~0 ; 0 ; 6 ;
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; - triple_selector_8b:inst|inst19~0 ; 0 ; 6 ;
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; - triple_selector_8b:inst|inst23~0 ; 0 ; 6 ;
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; - triple_selector_8b:inst|inst27~0 ; 0 ; 6 ;
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; - triple_selector_8b:inst|inst31 ; 0 ; 6 ;
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; - triple_selector_8b:inst|inst3~0 ; 1 ; 6 ;
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; - triple_selector_8b:inst|inst7~0 ; 1 ; 6 ;
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; L ; ; ;
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; - triple_selector_8b:inst|inst3~0 ; 0 ; 6 ;
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; LM ; ; ;
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; - triple_selector_8b:inst|inst3~0 ; 1 ; 6 ;
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; - triple_selector_8b:inst|inst7~0 ; 1 ; 6 ;
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; - triple_selector_8b:inst|inst11~0 ; 1 ; 6 ;
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; - triple_selector_8b:inst|inst15~0 ; 1 ; 6 ;
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; - triple_selector_8b:inst|inst19~0 ; 1 ; 6 ;
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; - triple_selector_8b:inst|inst23~0 ; 1 ; 6 ;
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; - triple_selector_8b:inst|inst27~0 ; 1 ; 6 ;
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; - triple_selector_8b:inst|inst31 ; 1 ; 6 ;
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; - triple_selector_8b:inst|inst31~0 ; 1 ; 6 ;
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; DM ; ; ;
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; - triple_selector_8b:inst|inst3~0 ; 0 ; 6 ;
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; - triple_selector_8b:inst|inst7~0 ; 0 ; 6 ;
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; - triple_selector_8b:inst|inst11~0 ; 0 ; 6 ;
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; - triple_selector_8b:inst|inst15~0 ; 0 ; 6 ;
|
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; - triple_selector_8b:inst|inst19~0 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst23~0 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst27~0 ; 0 ; 6 ;
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; - triple_selector_8b:inst|inst31~0 ; 0 ; 6 ;
|
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; A1 ; ; ;
|
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; - triple_selector_8b:inst|inst3 ; 0 ; 6 ;
|
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; - triple_selector_8b:inst|inst7~0 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst11~0 ; 0 ; 6 ;
|
||||
; RM ; ; ;
|
||||
; - triple_selector_8b:inst|inst3 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst7 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst11 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst15 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst19 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst23 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst27 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst31 ; 0 ; 6 ;
|
||||
; A2 ; ; ;
|
||||
; - triple_selector_8b:inst|inst7 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst11~0 ; 0 ; 6 ;
|
||||
@@ -630,15 +639,17 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; - triple_selector_8b:inst|inst19~0 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst23~0 ; 0 ; 6 ;
|
||||
; A5 ; ; ;
|
||||
; - triple_selector_8b:inst|inst19 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst23~0 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst27~0 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst19 ; 1 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst23~0 ; 1 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst27~0 ; 1 ; 6 ;
|
||||
; A6 ; ; ;
|
||||
; - triple_selector_8b:inst|inst23 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst27~0 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst31 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst31~0 ; 0 ; 6 ;
|
||||
; A7 ; ; ;
|
||||
; - triple_selector_8b:inst|inst27 ; 0 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst27 ; 1 ; 6 ;
|
||||
; - triple_selector_8b:inst|inst31~0 ; 1 ; 6 ;
|
||||
; R ; ; ;
|
||||
; - triple_selector_8b:inst|inst31 ; 0 ; 6 ;
|
||||
+-----------------------------------------+-------------------+---------+
|
||||
|
||||
@@ -648,9 +659,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+----------------------------------+---------+
|
||||
; Name ; Fan-Out ;
|
||||
+----------------------------------+---------+
|
||||
; RM ; 8 ;
|
||||
; DM ; 8 ;
|
||||
; LM ; 7 ;
|
||||
; RM ; 7 ;
|
||||
; LM ; 8 ;
|
||||
; A6 ; 3 ;
|
||||
; A5 ; 3 ;
|
||||
; A4 ; 3 ;
|
||||
@@ -659,7 +670,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; A1 ; 3 ;
|
||||
; A7 ; 2 ;
|
||||
; A0 ; 2 ;
|
||||
; R ; 1 ;
|
||||
; L ; 1 ;
|
||||
; triple_selector_8b:inst|inst31 ; 1 ;
|
||||
; triple_selector_8b:inst|inst31~0 ; 1 ;
|
||||
; triple_selector_8b:inst|inst27 ; 1 ;
|
||||
; triple_selector_8b:inst|inst27~0 ; 1 ;
|
||||
; triple_selector_8b:inst|inst23 ; 1 ;
|
||||
@@ -673,6 +687,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; triple_selector_8b:inst|inst7 ; 1 ;
|
||||
; triple_selector_8b:inst|inst7~0 ; 1 ;
|
||||
; triple_selector_8b:inst|inst3 ; 1 ;
|
||||
; triple_selector_8b:inst|inst3~0 ; 1 ;
|
||||
+----------------------------------+---------+
|
||||
|
||||
|
||||
@@ -681,21 +696,21 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+----------------------------+-----------------------+
|
||||
; Interconnect Resource Type ; Usage ;
|
||||
+----------------------------+-----------------------+
|
||||
; Block interconnects ; 20 / 26,052 ( < 1 % ) ;
|
||||
; C16 interconnects ; 3 / 1,156 ( < 1 % ) ;
|
||||
; C4 interconnects ; 38 / 17,952 ( < 1 % ) ;
|
||||
; Block interconnects ; 23 / 26,052 ( < 1 % ) ;
|
||||
; C16 interconnects ; 16 / 1,156 ( 1 % ) ;
|
||||
; C4 interconnects ; 21 / 17,952 ( < 1 % ) ;
|
||||
; Direct links ; 0 / 26,052 ( 0 % ) ;
|
||||
; Global clocks ; 0 / 8 ( 0 % ) ;
|
||||
; Local interconnects ; 6 / 8,256 ( < 1 % ) ;
|
||||
; R24 interconnects ; 3 / 1,020 ( < 1 % ) ;
|
||||
; R4 interconnects ; 23 / 22,440 ( < 1 % ) ;
|
||||
; Local interconnects ; 8 / 8,256 ( < 1 % ) ;
|
||||
; R24 interconnects ; 6 / 1,020 ( < 1 % ) ;
|
||||
; R4 interconnects ; 37 / 22,440 ( < 1 % ) ;
|
||||
+----------------------------+-----------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------+
|
||||
; LAB Logic Elements ;
|
||||
+---------------------------------------------+-----------------------------+
|
||||
; Number of Logic Elements (Average = 14.00) ; Number of LABs (Total = 1) ;
|
||||
; Number of Logic Elements (Average = 16.00) ; Number of LABs (Total = 1) ;
|
||||
+---------------------------------------------+-----------------------------+
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 0 ;
|
||||
@@ -710,16 +725,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; 11 ; 0 ;
|
||||
; 12 ; 0 ;
|
||||
; 13 ; 0 ;
|
||||
; 14 ; 1 ;
|
||||
; 14 ; 0 ;
|
||||
; 15 ; 0 ;
|
||||
; 16 ; 0 ;
|
||||
; 16 ; 1 ;
|
||||
+---------------------------------------------+-----------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced ;
|
||||
+----------------------------------------------+-----------------------------+
|
||||
; Number of Signals Sourced (Average = 14.00) ; Number of LABs (Total = 1) ;
|
||||
; Number of Signals Sourced (Average = 16.00) ; Number of LABs (Total = 1) ;
|
||||
+----------------------------------------------+-----------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
@@ -735,7 +750,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; 11 ; 0 ;
|
||||
; 12 ; 0 ;
|
||||
; 13 ; 0 ;
|
||||
; 14 ; 1 ;
|
||||
; 14 ; 0 ;
|
||||
; 15 ; 0 ;
|
||||
; 16 ; 1 ;
|
||||
+----------------------------------------------+-----------------------------+
|
||||
|
||||
|
||||
@@ -759,7 +776,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+----------------------------------------------------------------------------+
|
||||
; LAB Distinct Inputs ;
|
||||
+----------------------------------------------+-----------------------------+
|
||||
; Number of Distinct Inputs (Average = 11.00) ; Number of LABs (Total = 1) ;
|
||||
; Number of Distinct Inputs (Average = 13.00) ; Number of LABs (Total = 1) ;
|
||||
+----------------------------------------------+-----------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
@@ -772,7 +789,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; 8 ; 0 ;
|
||||
; 9 ; 0 ;
|
||||
; 10 ; 0 ;
|
||||
; 11 ; 1 ;
|
||||
; 11 ; 0 ;
|
||||
; 12 ; 0 ;
|
||||
; 13 ; 1 ;
|
||||
+----------------------------------------------+-----------------------------+
|
||||
|
||||
|
||||
@@ -831,11 +850,11 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; Auto Fit Point 1 - Fit Attempt 1 ; ff ;
|
||||
; Mid Wire Use - Fit Attempt 1 ; 0 ;
|
||||
; Mid Slack - Fit Attempt 1 ; 2147483639 ;
|
||||
; Internal Atom Count - Fit Attempt 1 ; 15 ;
|
||||
; LE/ALM Count - Fit Attempt 1 ; 15 ;
|
||||
; Internal Atom Count - Fit Attempt 1 ; 17 ;
|
||||
; LE/ALM Count - Fit Attempt 1 ; 17 ;
|
||||
; LAB Count - Fit Attempt 1 ; 2 ;
|
||||
; Outputs per Lab - Fit Attempt 1 ; 4.000 ;
|
||||
; Inputs per LAB - Fit Attempt 1 ; 5.500 ;
|
||||
; Inputs per LAB - Fit Attempt 1 ; 6.500 ;
|
||||
; Global Inputs per LAB - Fit Attempt 1 ; 0.000 ;
|
||||
; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:2 ;
|
||||
; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:2 ;
|
||||
@@ -907,9 +926,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus II Fitter
|
||||
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
|
||||
Info: Processing started: Tue Mar 08 15:17:16 2022
|
||||
Info: Processing started: Thu Mar 10 14:51:52 2022
|
||||
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b
|
||||
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
|
||||
Info: Parallel compilation is enabled and will use 4 of the 6 processors detected
|
||||
Info: Selected device EP2C8Q208C8 for design "shifter_8b"
|
||||
Info: Low junction temperature is 0 degrees C
|
||||
Info: High junction temperature is 85 degrees C
|
||||
@@ -922,11 +941,23 @@ Info: Fitter converted 3 user pins into dedicated programming pins
|
||||
Info: Pin ~ASDO~ is reserved at location 1
|
||||
Info: Pin ~nCSO~ is reserved at location 2
|
||||
Info: Pin ~LVDS54p/nCEO~ is reserved at location 108
|
||||
Warning: No exact pin location assignment(s) for 2 pins of 21 total pins
|
||||
Info: Pin L not assigned to an exact location on the device
|
||||
Info: Pin R not assigned to an exact location on the device
|
||||
Info: Fitter is using the Classic Timing Analyzer
|
||||
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
|
||||
Info: Starting register packing
|
||||
Info: Finished register packing
|
||||
Extra Info: No registers were packed into other blocks
|
||||
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
|
||||
Info: Number of I/O pins in group: 2 (unused VREF, 3.3V VCCIO, 2 input, 0 output, 0 bidirectional)
|
||||
Info: I/O standards used: 3.3-V LVTTL.
|
||||
Info: I/O bank details before I/O pin placement
|
||||
Info: Statistics of I/O banks
|
||||
Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 30 pins available
|
||||
Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available
|
||||
Info: I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 9 total pin(s) used -- 26 pins available
|
||||
Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 11 total pin(s) used -- 25 pins available
|
||||
Info: Fitter preparation operations ending: elapsed time is 00:00:00
|
||||
Info: Fitter placement preparation operations beginning
|
||||
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
|
||||
@@ -935,7 +966,7 @@ Info: Fitter placement was successful
|
||||
Info: Fitter placement operations ending: elapsed time is 00:00:00
|
||||
Info: Fitter routing operations beginning
|
||||
Info: Average interconnect usage is 0% of the available device resources
|
||||
Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X34_Y9
|
||||
Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y10 to location X34_Y19
|
||||
Info: Fitter routing operations ending: elapsed time is 00:00:00
|
||||
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
|
||||
Info: Optimizations that may affect the design's routability were skipped
|
||||
@@ -951,17 +982,17 @@ Warning: Found 8 output pins without output pin load capacitance assignment
|
||||
Info: Pin "Y6" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
||||
Info: Pin "Y7" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
|
||||
Info: Delay annotation completed successfully
|
||||
Info: Generated suppressed messages file D:/projects/quartus/shifter_8b/shifter_8b.fit.smsg
|
||||
Info: Quartus II Fitter was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 306 megabytes
|
||||
Info: Processing ended: Tue Mar 08 15:17:17 2022
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Generated suppressed messages file D:/dev/quartus/shifter_8b/shifter_8b.fit.smsg
|
||||
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
|
||||
Info: Peak virtual memory: 285 megabytes
|
||||
Info: Processing ended: Thu Mar 10 14:51:54 2022
|
||||
Info: Elapsed time: 00:00:02
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
|
||||
+----------------------------+
|
||||
; Fitter Suppressed Messages ;
|
||||
+----------------------------+
|
||||
The suppressed messages can be found in D:/projects/quartus/shifter_8b/shifter_8b.fit.smsg.
|
||||
The suppressed messages can be found in D:/dev/quartus/shifter_8b/shifter_8b.fit.smsg.
|
||||
|
||||
|
||||
|
||||
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