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重新添加L和R引脚

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wzhqwq
2022-03-10 14:58:16 +08:00
parent 558b1b3ead
commit a4c2c114cf
57 changed files with 421 additions and 321 deletions
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shifter_8b/shifter_8b.map.rpt
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@@ -1,5 +1,5 @@
Analysis & Synthesis report for shifter_8b
Tue Mar 08 15:17:15 2022
Thu Mar 10 14:51:51 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
@@ -39,16 +39,16 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Mar 08 15:17:15 2022 ;
; Analysis & Synthesis Status ; Successful - Thu Mar 10 14:51:51 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; shifter_8b ;
; Top-level Entity Name ; shifter_8b ;
; Family ; Cyclone II ;
; Total logic elements ; 14 ;
; Total combinational functions ; 14 ;
; Total logic elements ; 16 ;
; Total combinational functions ; 16 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 19 ;
; Total pins ; 21 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Embedded Multiplier 9-bit elements ; 0 ;
@@ -131,14 +131,14 @@ applicable agreement for further details.
+--------------------------------------------------------------+--------------------+--------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------------+-------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------------+-------------------------------------------------------+
; shifter_8b.bdf ; yes ; User Block Diagram/Schematic File ; D:/projects/quartus/shifter_8b/shifter_8b.bdf ;
; triple_selector_8b.bdf ; yes ; Auto-Found Block Diagram/Schematic File ; D:/projects/quartus/shifter_8b/triple_selector_8b.bdf ;
+----------------------------------+-----------------+------------------------------------------+-------------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------------+--------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------------+--------------------------------------------------+
; shifter_8b.bdf ; yes ; User Block Diagram/Schematic File ; D:/dev/quartus/shifter_8b/shifter_8b.bdf ;
; triple_selector_8b.bdf ; yes ; Auto-Found Block Diagram/Schematic File ; D:/dev/quartus/shifter_8b/triple_selector_8b.bdf ;
+----------------------------------+-----------------+------------------------------------------+--------------------------------------------------+
+-----------------------------------------------------+
@@ -146,27 +146,27 @@ applicable agreement for further details.
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements ; 14 ;
; Estimated Total logic elements ; 16 ;
; ; ;
; Total combinational functions ; 14 ;
; Total combinational functions ; 16 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 8 ;
; -- 3 input functions ; 6 ;
; -- 3 input functions ; 8 ;
; -- <=2 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 14 ;
; -- normal mode ; 16 ;
; -- arithmetic mode ; 0 ;
; ; ;
; Total registers ; 0 ;
; -- Dedicated logic registers ; 0 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 19 ;
; Maximum fan-out node ; DM ;
; I/O pins ; 21 ;
; Maximum fan-out node ; LM ;
; Maximum fan-out ; 8 ;
; Total fan-out ; 58 ;
; Average fan-out ; 1.76 ;
; Total fan-out ; 64 ;
; Average fan-out ; 1.73 ;
+---------------------------------------------+-------+
@@ -175,8 +175,8 @@ applicable agreement for further details.
+------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------+--------------+
; |shifter_8b ; 14 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 19 ; 0 ; |shifter_8b ; work ;
; |triple_selector_8b:inst| ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |shifter_8b|triple_selector_8b:inst ; work ;
; |shifter_8b ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 21 ; 0 ; |shifter_8b ; work ;
; |triple_selector_8b:inst| ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |shifter_8b|triple_selector_8b:inst ; work ;
+------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@@ -202,7 +202,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Tue Mar 08 15:17:15 2022
Info: Processing started: Thu Mar 10 14:51:50 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b
Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf
Info: Found entity 1: shifter_8b
@@ -210,14 +210,14 @@ Info: Elaborating entity "shifter_8b" for the top level hierarchy
Warning: Using design file triple_selector_8b.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: triple_selector_8b
Info: Elaborating entity "triple_selector_8b" for hierarchy "triple_selector_8b:inst"
Info: Implemented 33 device resources after synthesis - the final resource count might be different
Info: Implemented 11 input pins
Info: Implemented 37 device resources after synthesis - the final resource count might be different
Info: Implemented 13 input pins
Info: Implemented 8 output pins
Info: Implemented 14 logic cells
Info: Implemented 16 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Peak virtual memory: 250 megabytes
Info: Processing ended: Tue Mar 08 15:17:15 2022
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00
Info: Peak virtual memory: 229 megabytes
Info: Processing ended: Thu Mar 10 14:51:52 2022
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01