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add triple_selector_8b, shifter_8b

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juzeon 2022-03-07 10:41:24 +08:00
父節點 d39a6bc50a
當前提交 db64b867f6
共有 159 個檔案被更改，包括 11204 行新增 和 1 行删除
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10
README.md
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@ -16,4 +16,12 @@
### 38_decoder
3-8译码器。
3-8译码器。
### triple_selector_8b
8位数据选择器（三选一）。
### shifter_8b
8位数据移位器。

14
adder_8b/adder_8b.qws Normal file
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[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
[ProjectWorkspace.Frames.ChildFrames.Document-0]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
DocPathName=adder_8b.bdf
DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde}
IsChildFrameDetached=False
IsActiveChildFrame=True
ptn_Child1=StateMap

6
adder_8b/db/adder_8b.tmw_info Normal file
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start_full_compilation:s:00:00:06
start_analysis_synthesis:s:00:00:02-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:02-start_full_compilation
start_assembler:s:00:00:01-start_full_compilation
start_timing_analyzer:s:00:00:01-start_full_compilation

7
shifter_8b/db/prev_cmp_shifter_8b.map.qmsg Normal file
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:36:47 2022 " "Info: Processing started: Mon Mar 07 10:36:47 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 shifter_8b " "Info: Found entity 1: shifter_8b" { } { { "shifter_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "shifter_8b " "Info: Elaborating entity \"shifter_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Error" "ESGN_ENTITY_IS_MISSING" "inst triple_selector_8b " "Error: Node instance \"inst\" instantiates undefined entity \"triple_selector_8b\"" { } { { "shifter_8b.bdf" "inst" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { { 32 488 584 512 "inst" "" } } } } } 0 0 "Node instance \"%1!s!\" instantiates undefined entity \"%2!s!\"" 0 0 "" 0 -1}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "246 " "Error: Peak virtual memory: 246 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Error" "EQEXE_END_BANNER_TIME" "Mon Mar 07 10:36:47 2022 " "Error: Processing ended: Mon Mar 07 10:36:47 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Error: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Error: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

8
shifter_8b/db/prev_cmp_shifter_8b.qmsg Normal file
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:36:47 2022 " "Info: Processing started: Mon Mar 07 10:36:47 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 shifter_8b " "Info: Found entity 1: shifter_8b" { } { { "shifter_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "shifter_8b " "Info: Elaborating entity \"shifter_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Error" "ESGN_ENTITY_IS_MISSING" "inst triple_selector_8b " "Error: Node instance \"inst\" instantiates undefined entity \"triple_selector_8b\"" { } { { "shifter_8b.bdf" "inst" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { { 32 488 584 512 "inst" "" } } } } } 0 0 "Node instance \"%1!s!\" instantiates undefined entity \"%2!s!\"" 0 0 "" 0 -1}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "246 " "Error: Peak virtual memory: 246 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Error" "EQEXE_END_BANNER_TIME" "Mon Mar 07 10:36:47 2022 " "Error: Processing ended: Mon Mar 07 10:36:47 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Error: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Error: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 0 s " "Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings" { } { } 0 0 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

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shifter_8b/db/shifter_8b.(0).cnf.cdb Normal file
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未顯示二進位檔案。

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shifter_8b/db/shifter_8b.(0).cnf.hdb Normal file
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shifter_8b/db/shifter_8b.(1).cnf.cdb Normal file
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shifter_8b/db/shifter_8b.(1).cnf.hdb Normal file
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未顯示二進位檔案。

7
shifter_8b/db/shifter_8b.asm.qmsg Normal file
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:37:43 2022 " "Info: Processing started: Mon Mar 07 10:37:43 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 10:37:44 2022 " "Info: Processing ended: Mon Mar 07 10:37:44 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

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shifter_8b/db/shifter_8b.asm_labs.ddb Normal file
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5
shifter_8b/db/shifter_8b.cbx.xml Normal file
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<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="shifter_8b">
</PROJECT>
</LOG_ROOT>

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shifter_8b/db/shifter_8b.cmp.bpm Normal file
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shifter_8b/db/shifter_8b.cmp.cdb Normal file
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未顯示二進位檔案。

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shifter_8b/db/shifter_8b.cmp.ecobp Normal file
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shifter_8b/db/shifter_8b.cmp.hdb Normal file
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未顯示二進位檔案。

10
shifter_8b/db/shifter_8b.cmp.kpt Normal file
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<kpt_db name="shifter_8b.cmp" kpt_version="1.1">
<key_points_set type="reference" hier_sep="|">
</key_points_set>
<key_points_set type="transition" hier_sep="|">
</key_points_set>
<key_points_set type="transformed" hier_sep="|">
</key_points_set>
<transformations_set hier_sep="|">
</transformations_set>
</kpt_db>

1
shifter_8b/db/shifter_8b.cmp.logdb Normal file
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v1

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shifter_8b/db/shifter_8b.cmp.rdb Normal file
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shifter_8b/db/shifter_8b.cmp.tdb Normal file
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shifter_8b/db/shifter_8b.cmp0.ddb Normal file
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shifter_8b/db/shifter_8b.cmp2.ddb Normal file
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10
shifter_8b/db/shifter_8b.cmp_merge.kpt Normal file
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<kpt_db name="shifter_8b.cmp_merge" kpt_version="1.1">
<key_points_set type="reference" hier_sep="|">
</key_points_set>
<key_points_set type="transition" hier_sep="|">
</key_points_set>
<key_points_set type="transformed" hier_sep="|">
</key_points_set>
<transformations_set hier_sep="|">
</transformations_set>
</kpt_db>

3
shifter_8b/db/shifter_8b.db_info Normal file
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Quartus_Version = Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Version_Index = 167832322
Creation_Time = Mon Mar 07 10:34:26 2022

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shifter_8b/db/shifter_8b.eco.cdb Normal file
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39
shifter_8b/db/shifter_8b.fit.qmsg Normal file
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檔案差異因為一行或多行太長而無法顯示

102
shifter_8b/db/shifter_8b.hier_info Normal file
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|shifter_8b
Y0 <= triple_selector_8b:inst.Y0
A6 => triple_selector_8b:inst.A7
A6 => triple_selector_8b:inst.B6
A6 => triple_selector_8b:inst.C5
A7 => triple_selector_8b:inst.B7
A7 => triple_selector_8b:inst.C6
A7 => inst1.IN1
R => triple_selector_8b:inst.C7
A5 => triple_selector_8b:inst.A6
A5 => triple_selector_8b:inst.B5
A5 => triple_selector_8b:inst.C4
A4 => triple_selector_8b:inst.A5
A4 => triple_selector_8b:inst.B4
A4 => triple_selector_8b:inst.C3
A3 => triple_selector_8b:inst.A4
A3 => triple_selector_8b:inst.B3
A3 => triple_selector_8b:inst.C2
A2 => triple_selector_8b:inst.A3
A2 => triple_selector_8b:inst.B2
A2 => triple_selector_8b:inst.C1
A1 => triple_selector_8b:inst.A2
A1 => triple_selector_8b:inst.B1
A1 => triple_selector_8b:inst.C0
A0 => triple_selector_8b:inst.A1
A0 => triple_selector_8b:inst.B0
A0 => inst2.IN0
L => triple_selector_8b:inst.A0
LM => triple_selector_8b:inst.AY
LM => inst1.IN0
DM => triple_selector_8b:inst.BY
RM => triple_selector_8b:inst.CY
RM => inst2.IN1
Y1 <= triple_selector_8b:inst.Y1
Y2 <= triple_selector_8b:inst.Y2
Y3 <= triple_selector_8b:inst.Y3
Y4 <= triple_selector_8b:inst.Y4
Y5 <= triple_selector_8b:inst.Y5
Y6 <= triple_selector_8b:inst.Y6
Y7 <= triple_selector_8b:inst.Y7
OF <= inst3.DB_MAX_OUTPUT_PORT_TYPE
|shifter_8b|triple_selector_8b:inst
Y0 <= inst3.DB_MAX_OUTPUT_PORT_TYPE
B0 => inst1.IN0
BY => inst1.IN1
BY => inst5.IN1
BY => inst9.IN1
BY => inst13.IN1
BY => inst16.IN1
BY => inst21.IN1
BY => inst24.IN1
BY => inst29.IN1
C0 => inst2.IN0
CY => inst2.IN1
CY => inst6.IN1
CY => inst10.IN1
CY => inst14.IN1
CY => inst18.IN1
CY => inst22.IN1
CY => inst26.IN1
CY => inst30.IN1
A0 => inst.IN0
AY => inst.IN1
AY => inst4.IN1
AY => inst8.IN1
AY => inst12.IN1
AY => inst17.IN1
AY => inst20.IN1
AY => inst25.IN1
AY => inst28.IN1
Y1 <= inst7.DB_MAX_OUTPUT_PORT_TYPE
B1 => inst5.IN0
C1 => inst6.IN0
A1 => inst4.IN0
Y2 <= inst11.DB_MAX_OUTPUT_PORT_TYPE
B2 => inst9.IN0
C2 => inst10.IN0
A2 => inst8.IN0
Y3 <= inst15.DB_MAX_OUTPUT_PORT_TYPE
B3 => inst13.IN0
C3 => inst14.IN0
A3 => inst12.IN0
Y4 <= inst19.DB_MAX_OUTPUT_PORT_TYPE
B4 => inst16.IN0
C4 => inst18.IN0
A4 => inst17.IN0
Y5 <= inst23.DB_MAX_OUTPUT_PORT_TYPE
B5 => inst21.IN0
C5 => inst22.IN0
A5 => inst20.IN0
Y6 <= inst27.DB_MAX_OUTPUT_PORT_TYPE
B6 => inst24.IN0
C6 => inst26.IN0
A6 => inst25.IN0
Y7 <= inst31.DB_MAX_OUTPUT_PORT_TYPE
B7 => inst29.IN0
C7 => inst30.IN0
A7 => inst28.IN0

62
shifter_8b/db/shifter_8b.hif Normal file
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Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
11
936
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
shifter_8b
# storage
db|shifter_8b.(0).cnf
db|shifter_8b.(0).cnf
# case_insensitive
# source_file
shifter_8b.bdf
323ebfa5afd7389abf1fcd4efaf6de
26
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
|
}
# macro_sequence
# end
# entity
triple_selector_8b
# storage
db|shifter_8b.(1).cnf
db|shifter_8b.(1).cnf
# case_insensitive
# source_file
triple_selector_8b.bdf
91b7a41e9ebd47591ce44c4793a9f2e
26
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
triple_selector_8b:inst
}
# macro_sequence
# end
# complete

34
shifter_8b/db/shifter_8b.lpc.html Normal file
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<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">inst</TD>
<TD ALIGN="LEFT">27</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">8</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
</TABLE>

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shifter_8b/db/shifter_8b.lpc.rdb Normal file
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shifter_8b/db/shifter_8b.lpc.txt Normal file
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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; inst ; 27 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

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shifter_8b/db/shifter_8b.map.bpm Normal file
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未顯示二進位檔案。

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shifter_8b/db/shifter_8b.map.cdb Normal file
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未顯示二進位檔案。

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shifter_8b/db/shifter_8b.map.ecobp Normal file
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未顯示二進位檔案。

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shifter_8b/db/shifter_8b.map.hdb Normal file
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未顯示二進位檔案。

10
shifter_8b/db/shifter_8b.map.kpt Normal file
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<kpt_db name="shifter_8b.map" kpt_version="1.1">
<key_points_set type="reference" hier_sep="/">
</key_points_set>
<key_points_set type="transition" hier_sep="|">
</key_points_set>
<key_points_set type="transformed" hier_sep="|">
</key_points_set>
<transformations_set hier_sep="|">
</transformations_set>
</kpt_db>

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shifter_8b/db/shifter_8b.map.logdb Normal file
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shifter_8b/db/shifter_8b.map.qmsg Normal file
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:37:40 2022 " "Info: Processing started: Mon Mar 07 10:37:40 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter_8b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 shifter_8b " "Info: Found entity 1: shifter_8b" { } { { "shifter_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "shifter_8b " "Info: Elaborating entity \"shifter_8b\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "triple_selector_8b.bdf 1 1 " "Warning: Using design file triple_selector_8b.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 triple_selector_8b " "Info: Found entity 1: triple_selector_8b" { } { { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/triple_selector_8b.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "triple_selector_8b triple_selector_8b:inst " "Info: Elaborating entity \"triple_selector_8b\" for hierarchy \"triple_selector_8b:inst\"" { } { { "shifter_8b.bdf" "inst" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { { 32 488 584 512 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "39 " "Info: Implemented 39 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "13 " "Info: Implemented 13 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Info: Implemented 9 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "17 " "Info: Implemented 17 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "249 " "Info: Peak virtual memory: 249 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 10:37:40 2022 " "Info: Processing ended: Mon Mar 07 10:37:40 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

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shifter_8b/db/shifter_8b.syn_hier_info Normal file
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:37:44 2022 " "Info: Processing started: Mon Mar 07 10:37:44 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TPD_RESULT" "DM Y7 13.320 ns Longest " "Info: Longest tpd from source pin \"DM\" to destination pin \"Y7\" is 13.320 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.985 ns) 0.985 ns DM 1 PIN PIN_35 8 " "Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_35; Fanout = 8; PIN Node = 'DM'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DM } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { { 456 40 208 472 "DM" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.057 ns) + CELL(0.650 ns) 7.692 ns triple_selector_8b:inst\|inst31~0 2 COMB LCCOMB_X1_Y14_N20 1 " "Info: 2: + IC(6.057 ns) + CELL(0.650 ns) = 7.692 ns; Loc. = LCCOMB_X1_Y14_N20; Fanout = 1; COMB Node = 'triple_selector_8b:inst\|inst31~0'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.707 ns" { DM triple_selector_8b:inst|inst31~0 } "NODE_NAME" } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/triple_selector_8b.bdf" { { 64 488 552 112 "inst31" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.286 ns) + CELL(0.319 ns) 9.297 ns triple_selector_8b:inst\|inst31 3 COMB LCCOMB_X1_Y9_N16 1 " "Info: 3: + IC(1.286 ns) + CELL(0.319 ns) = 9.297 ns; Loc. = LCCOMB_X1_Y9_N16; Fanout = 1; COMB Node = 'triple_selector_8b:inst\|inst31'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.605 ns" { triple_selector_8b:inst|inst31~0 triple_selector_8b:inst|inst31 } "NODE_NAME" } } { "triple_selector_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/triple_selector_8b.bdf" { { 64 488 552 112 "inst31" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.927 ns) + CELL(3.096 ns) 13.320 ns Y7 4 PIN PIN_33 0 " "Info: 4: + IC(0.927 ns) + CELL(3.096 ns) = 13.320 ns; Loc. = PIN_33; Fanout = 0; PIN Node = 'Y7'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.023 ns" { triple_selector_8b:inst|inst31 Y7 } "NODE_NAME" } } { "shifter_8b.bdf" "" { Schematic "D:/projects/quartus/shifter_8b/shifter_8b.bdf" { { 56 688 864 72 "Y7" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.050 ns ( 37.91 % ) " "Info: Total cell delay = 5.050 ns ( 37.91 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.270 ns ( 62.09 % ) " "Info: Total interconnect delay = 8.270 ns ( 62.09 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "13.320 ns" { DM triple_selector_8b:inst|inst31~0 triple_selector_8b:inst|inst31 Y7 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "13.320 ns" { DM {} DM~combout {} triple_selector_8b:inst|inst31~0 {} triple_selector_8b:inst|inst31 {} Y7 {} } { 0.000ns 0.000ns 6.057ns 1.286ns 0.927ns } { 0.000ns 0.985ns 0.650ns 0.319ns 3.096ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 10:37:44 2022 " "Info: Processing ended: Mon Mar 07 10:37:44 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

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shifter_8b/db/shifter_8b.tis_db_list.ddb Normal file
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shifter_8b/incremental_db/README Normal file
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This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.

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shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.cmp.kpt Normal file
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<kpt_db name="root_partition" kpt_version="1.1">
<key_points_set type="reference" hier_sep="|">
</key_points_set>
<key_points_set type="transition" hier_sep="|">
</key_points_set>
<key_points_set type="transformed" hier_sep="|">
</key_points_set>
<transformations_set hier_sep="|">
</transformations_set>
</kpt_db>

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shifter_8b/incremental_db/compiled_partitions/shifter_8b.root_partition.map.kpt Normal file
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<kpt_db name="shifter_8b.map_bb" kpt_version="1.1">
<key_points_set type="reference" hier_sep="/">
</key_points_set>
<key_points_set type="transition" hier_sep="|">
</key_points_set>
<key_points_set type="transformed" hier_sep="|">
</key_points_set>
<transformations_set hier_sep="|">
</transformations_set>
</kpt_db>

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Assembler report for shifter_8b
Mon Mar 07 10:37:44 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: D:/projects/quartus/shifter_8b/shifter_8b.sof
6. Assembler Device Options: D:/projects/quartus/shifter_8b/shifter_8b.pof
7. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Mon Mar 07 10:37:44 2022 ;
; Revision Name ; shifter_8b ;
; Top-level Entity Name ; shifter_8b ;
; Family ; Cyclone II ;
; Device ; EP2C8Q208C8 ;
+-----------------------+---------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Assembler Settings ;
+-----------------------------------------------------------------------------+----------+---------------+
; Option ; Setting ; Default Value ;
+-----------------------------------------------------------------------------+----------+---------------+
; Use smart compilation ; Off ; Off ;
; Generate compressed bitstreams ; On ; On ;
; Compression mode ; Off ; Off ;
; Clock source for configuration device ; Internal ; Internal ;
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
; Divide clock frequency by ; 1 ; 1 ;
; Auto user code ; Off ; Off ;
; Use configuration device ; On ; On ;
; Configuration device ; Auto ; Auto ;
; Configuration device auto user code ; Off ; Off ;
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
; Hexadecimal Output File start address ; 0 ; 0 ;
; Hexadecimal Output File count direction ; Up ; Up ;
; Release clears before tri-states ; Off ; Off ;
; Auto-restart configuration after error ; On ; On ;
; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ;
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
+-----------------------------------------------------------------------------+----------+---------------+
+-----------------------------------------------+
; Assembler Generated Files ;
+-----------------------------------------------+
; File Name ;
+-----------------------------------------------+
; D:/projects/quartus/shifter_8b/shifter_8b.sof ;
; D:/projects/quartus/shifter_8b/shifter_8b.pof ;
+-----------------------------------------------+
+-------------------------------------------------------------------------+
; Assembler Device Options: D:/projects/quartus/shifter_8b/shifter_8b.sof ;
+----------------+--------------------------------------------------------+
; Option ; Setting ;
+----------------+--------------------------------------------------------+
; Device ; EP2C8Q208C8 ;
; JTAG usercode ; 0xFFFFFFFF ;
; Checksum ; 0x000C7CD6 ;
+----------------+--------------------------------------------------------+
+-------------------------------------------------------------------------+
; Assembler Device Options: D:/projects/quartus/shifter_8b/shifter_8b.pof ;
+--------------------+----------------------------------------------------+
; Option ; Setting ;
+--------------------+----------------------------------------------------+
; Device ; EPCS4 ;
; JTAG usercode ; 0x00000000 ;
; Checksum ; 0x06F093B0 ;
; Compression Ratio ; 3 ;
+--------------------+----------------------------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Mon Mar 07 10:37:43 2022
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b
Info: Writing out detailed assembly data for power analysis
Info: Assembler is generating device programming files
Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 241 megabytes
Info: Processing ended: Mon Mar 07 10:37:44 2022
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01

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shifter_8b/shifter_8b.bdf Normal file
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shifter_8b/shifter_8b.done Normal file
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Mon Mar 07 10:37:45 2022

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shifter_8b/shifter_8b.fit.rpt Normal file
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shifter_8b/shifter_8b.fit.smsg Normal file
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Extra Info: Performing register packing on registers with non-logic cell location assignments
Extra Info: Completed register packing on registers with non-logic cell location assignments
Extra Info: Started Fast Input/Output/OE register processing
Extra Info: Finished Fast Input/Output/OE register processing
Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks

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shifter_8b/shifter_8b.fit.summary Normal file
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Fitter Status : Successful - Mon Mar 07 10:37:42 2022
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : shifter_8b
Top-level Entity Name : shifter_8b
Family : Cyclone II
Device : EP2C8Q208C8
Timing Models : Final
Total logic elements : 17 / 8,256 ( < 1 % )
Total combinational functions : 17 / 8,256 ( < 1 % )
Dedicated logic registers : 0 / 8,256 ( 0 % )
Total registers : 0
Total pins : 22 / 138 ( 16 % )
Total virtual pins : 0
Total memory bits : 0 / 165,888 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )

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shifter_8b/shifter_8b.flow.rpt Normal file
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Flow report for shifter_8b
Mon Mar 07 10:37:44 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+----------------------------------------------+
; Flow Status ; Successful - Mon Mar 07 10:37:44 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; shifter_8b ;
; Top-level Entity Name ; shifter_8b ;
; Family ; Cyclone II ;
; Device ; EP2C8Q208C8 ;
; Timing Models ; Final ;
; Met timing requirements ; Yes ;
; Total logic elements ; 17 / 8,256 ( < 1 % ) ;
; Total combinational functions ; 17 / 8,256 ( < 1 % ) ;
; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 22 / 138 ( 16 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 165,888 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
; Total PLLs ; 0 / 2 ( 0 % ) ;
+------------------------------------+----------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 03/07/2022 10:37:40 ;
; Main task ; Compilation ;
; Revision Name ; shifter_8b ;
+-------------------+---------------------+
+---------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+------------------------------------+---------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+------------------------------------+---------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 220283517943889.164662066022984 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
+------------------------------------+---------------------------------+---------------+-------------+----------------+
+-----------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 245 MB ; 00:00:00 ;
; Fitter ; 00:00:01 ; 1.0 ; 306 MB ; 00:00:01 ;
; Assembler ; 00:00:01 ; 1.0 ; 241 MB ; 00:00:00 ;
; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 198 MB ; 00:00:00 ;
; Total ; 00:00:02 ; -- ; -- ; 00:00:01 ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+------------------------------------------------------------------------------------------+
; Flow OS Summary ;
+-------------------------+------------------+---------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+-------------------------+------------------+---------------+------------+----------------+
; Analysis & Synthesis ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
; Fitter ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
; Assembler ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
; Classic Timing Analyzer ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
+-------------------------+------------------+---------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b
quartus_fit --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b
quartus_asm --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b
quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only

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shifter_8b/shifter_8b.map.rpt Normal file
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Analysis & Synthesis report for shifter_8b
Mon Mar 07 10:37:40 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. General Register Statistics
8. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Mar 07 10:37:40 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; shifter_8b ;
; Top-level Entity Name ; shifter_8b ;
; Family ; Cyclone II ;
; Total logic elements ; 17 ;
; Total combinational functions ; 17 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 22 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
+------------------------------------+----------------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------+--------------------+--------------------+
; Device ; EP2C8Q208C8 ; ;
; Top-level entity name ; shifter_8b ; shifter_8b ;
; Family name ; Cyclone II ; Stratix II ;
; Use Generated Physical Constraints File ; Off ; ;
; Use smart compilation ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; Off ; Off ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
+--------------------------------------------------------------+--------------------+--------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------------+-------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------------+-------------------------------------------------------+
; shifter_8b.bdf ; yes ; User Block Diagram/Schematic File ; D:/projects/quartus/shifter_8b/shifter_8b.bdf ;
; triple_selector_8b.bdf ; yes ; Auto-Found Block Diagram/Schematic File ; D:/projects/quartus/shifter_8b/triple_selector_8b.bdf ;
+----------------------------------+-----------------+------------------------------------------+-------------------------------------------------------+
+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements ; 17 ;
; ; ;
; Total combinational functions ; 17 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 9 ;
; -- 3 input functions ; 8 ;
; -- <=2 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 17 ;
; -- arithmetic mode ; 0 ;
; ; ;
; Total registers ; 0 ;
; -- Dedicated logic registers ; 0 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 22 ;
; Maximum fan-out node ; LM ;
; Maximum fan-out ; 9 ;
; Total fan-out ; 69 ;
; Average fan-out ; 1.77 ;
+---------------------------------------------+-------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------+--------------+
; |shifter_8b ; 17 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 22 ; 0 ; |shifter_8b ; work ;
; |triple_selector_8b:inst| ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |shifter_8b|triple_selector_8b:inst ; work ;
+------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Mon Mar 07 10:37:40 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shifter_8b -c shifter_8b
Info: Found 1 design units, including 1 entities, in source file shifter_8b.bdf
Info: Found entity 1: shifter_8b
Info: Elaborating entity "shifter_8b" for the top level hierarchy
Warning: Using design file triple_selector_8b.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: triple_selector_8b
Info: Elaborating entity "triple_selector_8b" for hierarchy "triple_selector_8b:inst"
Info: Implemented 39 device resources after synthesis - the final resource count might be different
Info: Implemented 13 input pins
Info: Implemented 9 output pins
Info: Implemented 17 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Peak virtual memory: 249 megabytes
Info: Processing ended: Mon Mar 07 10:37:40 2022
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00

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Analysis & Synthesis Status : Successful - Mon Mar 07 10:37:40 2022
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : shifter_8b
Top-level Entity Name : shifter_8b
Family : Cyclone II
Total logic elements : 17
Total combinational functions : 17
Dedicated logic registers : 0
Total registers : 0
Total pins : 22
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0

278
shifter_8b/shifter_8b.pin Normal file
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-- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
-- Bank 2: 3.3V
-- Bank 3: 3.3V
-- Bank 4: 3.3V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17),
-- connect each pin marked GND* either individually through a 10k Ohm resistor
-- to GND or tie all pins together and connect through a single 10k Ohm resistor
-- to GND.
-- For non-transceiver I/O banks, connect each pin marked GND* directly to GND
-- or leave it unconnected.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
CHIP "shifter_8b" ASSIGNED TO AN: EP2C8Q208C8
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVTTL : : 1 : N
~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVTTL : : 1 : N
GND* : 3 : : : : 1 :
A4 : 4 : input : 3.3-V LVTTL : : 1 : N
Y6 : 5 : output : 3.3-V LVTTL : : 1 : N
GND* : 6 : : : : 1 :
VCCIO1 : 7 : power : : 3.3V : 1 :
A5 : 8 : input : 3.3-V LVTTL : : 1 : N
GND : 9 : gnd : : : :
GND* : 10 : : : : 1 :
Y3 : 11 : output : 3.3-V LVTTL : : 1 : N
Y2 : 12 : output : 3.3-V LVTTL : : 1 : N
Y5 : 13 : output : 3.3-V LVTTL : : 1 : N
A6 : 14 : input : 3.3-V LVTTL : : 1 : N
A7 : 15 : input : 3.3-V LVTTL : : 1 : N
TDO : 16 : output : : : 1 :
TMS : 17 : input : : : 1 :
TCK : 18 : input : : : 1 :
TDI : 19 : input : : : 1 :
DATA0 : 20 : input : : : 1 :
DCLK : 21 : : : : 1 :
nCE : 22 : : : : 1 :
A1 : 23 : input : 3.3-V LVTTL : : 1 : N
RM : 24 : input : 3.3-V LVTTL : : 1 : N
GND : 25 : gnd : : : :
nCONFIG : 26 : : : : 1 :
A2 : 27 : input : 3.3-V LVTTL : : 1 : N
A3 : 28 : input : 3.3-V LVTTL : : 1 : N
VCCIO1 : 29 : power : : 3.3V : 1 :
R : 30 : input : 3.3-V LVTTL : : 1 : N
Y0 : 31 : output : 3.3-V LVTTL : : 1 : N
VCCINT : 32 : power : : 1.2V : :
Y7 : 33 : output : 3.3-V LVTTL : : 1 : N
Y1 : 34 : output : 3.3-V LVTTL : : 1 : N
DM : 35 : input : 3.3-V LVTTL : : 1 : N
GND : 36 : gnd : : : :
GND* : 37 : : : : 1 :
GND : 38 : gnd : : : :
GND* : 39 : : : : 1 :
OF : 40 : output : 3.3-V LVTTL : : 1 : N
GND* : 41 : : : : 1 :
VCCIO1 : 42 : power : : 3.3V : 1 :
GND* : 43 : : : : 1 :
GND* : 44 : : : : 1 :
GND* : 45 : : : : 1 :
GND* : 46 : : : : 1 :
GND* : 47 : : : : 1 :
GND* : 48 : : : : 1 :
GND : 49 : gnd : : : :
GND_PLL1 : 50 : gnd : : : :
VCCD_PLL1 : 51 : power : : 1.2V : :
GND_PLL1 : 52 : gnd : : : :
VCCA_PLL1 : 53 : power : : 1.2V : :
GNDA_PLL1 : 54 : gnd : : : :
GND : 55 : gnd : : : :
GND* : 56 : : : : 4 :
LM : 57 : input : 3.3-V LVTTL : : 4 : N
GND* : 58 : : : : 4 :
GND* : 59 : : : : 4 :
A0 : 60 : input : 3.3-V LVTTL : : 4 : N
GND* : 61 : : : : 4 :
VCCIO4 : 62 : power : : 3.3V : 4 :
GND* : 63 : : : : 4 :
GND* : 64 : : : : 4 :
GND : 65 : gnd : : : :
VCCINT : 66 : power : : 1.2V : :
GND* : 67 : : : : 4 :
GND* : 68 : : : : 4 :
GND* : 69 : : : : 4 :
GND* : 70 : : : : 4 :
VCCIO4 : 71 : power : : 3.3V : 4 :
GND* : 72 : : : : 4 :
GND : 73 : gnd : : : :
GND* : 74 : : : : 4 :
GND* : 75 : : : : 4 :
GND* : 76 : : : : 4 :
GND* : 77 : : : : 4 :
GND : 78 : gnd : : : :
VCCINT : 79 : power : : 1.2V : :
GND* : 80 : : : : 4 :
GND* : 81 : : : : 4 :
GND* : 82 : : : : 4 :
VCCIO4 : 83 : power : : 3.3V : 4 :
GND* : 84 : : : : 4 :
GND : 85 : gnd : : : :
GND* : 86 : : : : 4 :
GND* : 87 : : : : 4 :
GND* : 88 : : : : 4 :
GND* : 89 : : : : 4 :
GND* : 90 : : : : 4 :
VCCIO4 : 91 : power : : 3.3V : 4 :
GND* : 92 : : : : 4 :
GND : 93 : gnd : : : :
GND* : 94 : : : : 4 :
GND* : 95 : : : : 4 :
GND* : 96 : : : : 4 :
GND* : 97 : : : : 4 :
VCCIO4 : 98 : power : : 3.3V : 4 :
GND* : 99 : : : : 4 :
GND : 100 : gnd : : : :
GND* : 101 : : : : 4 :
GND* : 102 : : : : 4 :
GND* : 103 : : : : 4 :
GND* : 104 : : : : 4 :
GND* : 105 : : : : 3 :
GND* : 106 : : : : 3 :
GND* : 107 : : : : 3 :
~LVDS54p/nCEO~ : 108 : output : 3.3-V LVTTL : : 3 : N
VCCIO3 : 109 : power : : 3.3V : 3 :
GND* : 110 : : : : 3 :
GND : 111 : gnd : : : :
GND* : 112 : : : : 3 :
GND* : 113 : : : : 3 :
GND* : 114 : : : : 3 :
GND* : 115 : : : : 3 :
GND* : 116 : : : : 3 :
GND* : 117 : : : : 3 :
GND* : 118 : : : : 3 :
GND : 119 : gnd : : : :
VCCINT : 120 : power : : 1.2V : :
nSTATUS : 121 : : : : 3 :
VCCIO3 : 122 : power : : 3.3V : 3 :
CONF_DONE : 123 : : : : 3 :
GND : 124 : gnd : : : :
MSEL1 : 125 : : : : 3 :
MSEL0 : 126 : : : : 3 :
GND* : 127 : : : : 3 :
GND* : 128 : : : : 3 :
GND+ : 129 : : : : 3 :
GND+ : 130 : : : : 3 :
GND+ : 131 : : : : 3 :
GND+ : 132 : : : : 3 :
GND* : 133 : : : : 3 :
GND* : 134 : : : : 3 :
GND* : 135 : : : : 3 :
VCCIO3 : 136 : power : : 3.3V : 3 :
GND* : 137 : : : : 3 :
GND* : 138 : : : : 3 :
GND* : 139 : : : : 3 :
GND : 140 : gnd : : : :
GND* : 141 : : : : 3 :
GND* : 142 : : : : 3 :
GND* : 143 : : : : 3 :
GND* : 144 : : : : 3 :
GND* : 145 : : : : 3 :
GND* : 146 : : : : 3 :
GND* : 147 : : : : 3 :
VCCIO3 : 148 : power : : 3.3V : 3 :
GND* : 149 : : : : 3 :
GND* : 150 : : : : 3 :
GND* : 151 : : : : 3 :
GND* : 152 : : : : 3 :
GND : 153 : gnd : : : :
GND_PLL2 : 154 : gnd : : : :
VCCD_PLL2 : 155 : power : : 1.2V : :
GND_PLL2 : 156 : gnd : : : :
VCCA_PLL2 : 157 : power : : 1.2V : :
GNDA_PLL2 : 158 : gnd : : : :
GND : 159 : gnd : : : :
GND* : 160 : : : : 2 :
GND* : 161 : : : : 2 :
GND* : 162 : : : : 2 :
GND* : 163 : : : : 2 :
GND* : 164 : : : : 2 :
GND* : 165 : : : : 2 :
VCCIO2 : 166 : power : : 3.3V : 2 :
GND : 167 : gnd : : : :
GND* : 168 : : : : 2 :
GND* : 169 : : : : 2 :
GND* : 170 : : : : 2 :
GND* : 171 : : : : 2 :
VCCIO2 : 172 : power : : 3.3V : 2 :
GND* : 173 : : : : 2 :
GND : 174 : gnd : : : :
GND* : 175 : : : : 2 :
GND* : 176 : : : : 2 :
GND : 177 : gnd : : : :
VCCINT : 178 : power : : 1.2V : :
GND* : 179 : : : : 2 :
GND* : 180 : : : : 2 :
GND* : 181 : : : : 2 :
GND* : 182 : : : : 2 :
VCCIO2 : 183 : power : : 3.3V : 2 :
GND : 184 : gnd : : : :
GND* : 185 : : : : 2 :
GND : 186 : gnd : : : :
GND* : 187 : : : : 2 :
GND* : 188 : : : : 2 :
GND* : 189 : : : : 2 :
VCCINT : 190 : power : : 1.2V : :
GND* : 191 : : : : 2 :
GND* : 192 : : : : 2 :
GND* : 193 : : : : 2 :
VCCIO2 : 194 : power : : 3.3V : 2 :
GND* : 195 : : : : 2 :
GND : 196 : gnd : : : :
GND* : 197 : : : : 2 :
GND* : 198 : : : : 2 :
L : 199 : input : 3.3-V LVTTL : : 2 : N
GND* : 200 : : : : 2 :
GND* : 201 : : : : 2 :
VCCIO2 : 202 : power : : 3.3V : 2 :
GND* : 203 : : : : 2 :
GND : 204 : gnd : : : :
GND* : 205 : : : : 2 :
GND* : 206 : : : : 2 :
GND* : 207 : : : : 2 :
Y4 : 208 : output : 3.3-V LVTTL : : 2 : N

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shifter_8b/shifter_8b.pof Normal file
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30
shifter_8b/shifter_8b.qpf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 10:34:26 March 07, 2022
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "9.0"
DATE = "10:34:26 March 07, 2022"
# Revisions
PROJECT_REVISION = "shifter_8b"

53
shifter_8b/shifter_8b.qsf Normal file
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@ -0,0 +1,53 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 10:34:26 March 07, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# shifter_8b_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C8Q208C8
set_global_assignment -name TOP_LEVEL_ENTITY shifter_8b
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:34:26 MARCH 07, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name BDF_FILE shifter_8b.bdf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"

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shifter_8b/shifter_8b.sof Normal file
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178
shifter_8b/shifter_8b.tan.rpt Normal file
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Classic Timing Analyzer report for shifter_8b
Mon Mar 07 10:37:44 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Parallel Compilation
5. tpd
6. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 13.320 ns ; DM ; Y7 ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C8Q208C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Minimum Core Junction Temperature ; 0 ; ; ; ;
; Maximum Core Junction Temperature ; 85 ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; On ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
; Output I/O Timing Endpoint ; Near End ; ; ; ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; 1 processor ; 100.0% ;
; 2-4 processors ; 0.0% ;
+----------------------------+-------------+
+---------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A ; None ; 13.320 ns ; DM ; Y7 ;
; N/A ; None ; 13.225 ns ; DM ; Y4 ;
; N/A ; None ; 13.207 ns ; LM ; Y7 ;
; N/A ; None ; 13.153 ns ; LM ; Y0 ;
; N/A ; None ; 13.128 ns ; LM ; Y4 ;
; N/A ; None ; 13.029 ns ; A0 ; Y1 ;
; N/A ; None ; 13.020 ns ; DM ; Y1 ;
; N/A ; None ; 12.918 ns ; LM ; Y1 ;
; N/A ; None ; 12.906 ns ; A4 ; Y4 ;
; N/A ; None ; 12.900 ns ; DM ; Y2 ;
; N/A ; None ; 12.874 ns ; A0 ; OF ;
; N/A ; None ; 12.848 ns ; A0 ; Y0 ;
; N/A ; None ; 12.834 ns ; DM ; Y0 ;
; N/A ; None ; 12.817 ns ; L ; Y0 ;
; N/A ; None ; 12.816 ns ; LM ; Y6 ;
; N/A ; None ; 12.787 ns ; LM ; Y2 ;
; N/A ; None ; 12.752 ns ; LM ; Y5 ;
; N/A ; None ; 12.542 ns ; A7 ; Y7 ;
; N/A ; None ; 12.524 ns ; DM ; Y3 ;
; N/A ; None ; 12.450 ns ; LM ; OF ;
; N/A ; None ; 12.431 ns ; LM ; Y3 ;
; N/A ; None ; 12.272 ns ; A6 ; Y7 ;
; N/A ; None ; 12.211 ns ; A5 ; Y6 ;
; N/A ; None ; 12.184 ns ; A4 ; Y5 ;
; N/A ; None ; 12.155 ns ; A5 ; Y5 ;
; N/A ; None ; 12.007 ns ; DM ; Y6 ;
; N/A ; None ; 11.961 ns ; A5 ; Y4 ;
; N/A ; None ; 11.952 ns ; DM ; Y5 ;
; N/A ; None ; 11.780 ns ; A7 ; OF ;
; N/A ; None ; 11.520 ns ; A4 ; Y3 ;
; N/A ; None ; 11.436 ns ; A6 ; Y6 ;
; N/A ; None ; 11.309 ns ; R ; Y7 ;
; N/A ; None ; 11.123 ns ; A6 ; Y5 ;
; N/A ; None ; 11.097 ns ; A7 ; Y6 ;
; N/A ; None ; 8.432 ns ; A1 ; Y1 ;
; N/A ; None ; 8.391 ns ; A3 ; Y4 ;
; N/A ; None ; 8.283 ns ; A2 ; Y2 ;
; N/A ; None ; 8.057 ns ; A1 ; Y2 ;
; N/A ; None ; 7.922 ns ; A2 ; Y3 ;
; N/A ; None ; 7.852 ns ; A2 ; Y1 ;
; N/A ; None ; 7.752 ns ; RM ; OF ;
; N/A ; None ; 7.697 ns ; A3 ; Y3 ;
; N/A ; None ; 7.656 ns ; RM ; Y1 ;
; N/A ; None ; 7.645 ns ; RM ; Y0 ;
; N/A ; None ; 7.558 ns ; A1 ; Y0 ;
; N/A ; None ; 7.441 ns ; RM ; Y4 ;
; N/A ; None ; 7.348 ns ; RM ; Y3 ;
; N/A ; None ; 7.270 ns ; A3 ; Y2 ;
; N/A ; None ; 7.067 ns ; RM ; Y5 ;
; N/A ; None ; 7.062 ns ; RM ; Y6 ;
; N/A ; None ; 7.054 ns ; RM ; Y2 ;
; N/A ; None ; 5.826 ns ; RM ; Y7 ;
+-------+-------------------+-----------------+------+----+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Mon Mar 07 10:37:44 2022
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Info: Longest tpd from source pin "DM" to destination pin "Y7" is 13.320 ns
Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_35; Fanout = 8; PIN Node = 'DM'
Info: 2: + IC(6.057 ns) + CELL(0.650 ns) = 7.692 ns; Loc. = LCCOMB_X1_Y14_N20; Fanout = 1; COMB Node = 'triple_selector_8b:inst|inst31~0'
Info: 3: + IC(1.286 ns) + CELL(0.319 ns) = 9.297 ns; Loc. = LCCOMB_X1_Y9_N16; Fanout = 1; COMB Node = 'triple_selector_8b:inst|inst31'
Info: 4: + IC(0.927 ns) + CELL(3.096 ns) = 13.320 ns; Loc. = PIN_33; Fanout = 0; PIN Node = 'Y7'
Info: Total cell delay = 5.050 ns ( 37.91 % )
Info: Total interconnect delay = 8.270 ns ( 62.09 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 212 megabytes
Info: Processing ended: Mon Mar 07 10:37:44 2022
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00

26
shifter_8b/shifter_8b.tan.summary Normal file
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--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------
Type : Worst-case tpd
Slack : N/A
Required Time : None
Actual Time : 13.320 ns
From : DM
To : Y7
From Clock : --
To Clock : --
Failed Paths : 0
Type : Total number of failed paths
Slack :
Required Time :
Actual Time :
From :
To :
From Clock :
To Clock :
Failed Paths : 0
--------------------------------------------------------------------------------------

2247
shifter_8b/triple_selector_8b.bdf Normal file
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檔案差異因為檔案過大而無法顯示 載入差異

274
shifter_8b/triple_selector_8b.bsf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 112 496)
(text "triple_selector_8b" (rect 5 0 106 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 464 25 476)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "A7" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "A7" (rect 21 27 37 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "B7" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "B7" (rect 21 43 36 57)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "C7" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "C7" (rect 21 59 36 73)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 0 80)
(input)
(text "A6" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "A6" (rect 21 75 37 89)(font "Arial" (font_size 8)))
(line (pt 0 80)(pt 16 80)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "B6" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "B6" (rect 21 91 36 105)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 16 96)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "C6" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "C6" (rect 21 107 36 121)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 16 112)(line_width 1))
)
(port
(pt 0 128)
(input)
(text "A5" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "A5" (rect 21 123 37 137)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 16 128)(line_width 1))
)
(port
(pt 0 144)
(input)
(text "B5" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "B5" (rect 21 139 36 153)(font "Arial" (font_size 8)))
(line (pt 0 144)(pt 16 144)(line_width 1))
)
(port
(pt 0 160)
(input)
(text "C5" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "C5" (rect 21 155 36 169)(font "Arial" (font_size 8)))
(line (pt 0 160)(pt 16 160)(line_width 1))
)
(port
(pt 0 176)
(input)
(text "A4" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "A4" (rect 21 171 37 185)(font "Arial" (font_size 8)))
(line (pt 0 176)(pt 16 176)(line_width 1))
)
(port
(pt 0 192)
(input)
(text "B4" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "B4" (rect 21 187 36 201)(font "Arial" (font_size 8)))
(line (pt 0 192)(pt 16 192)(line_width 1))
)
(port
(pt 0 208)
(input)
(text "C4" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "C4" (rect 21 203 36 217)(font "Arial" (font_size 8)))
(line (pt 0 208)(pt 16 208)(line_width 1))
)
(port
(pt 0 224)
(input)
(text "A3" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "A3" (rect 21 219 37 233)(font "Arial" (font_size 8)))
(line (pt 0 224)(pt 16 224)(line_width 1))
)
(port
(pt 0 240)
(input)
(text "B3" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "B3" (rect 21 235 36 249)(font "Arial" (font_size 8)))
(line (pt 0 240)(pt 16 240)(line_width 1))
)
(port
(pt 0 256)
(input)
(text "C3" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "C3" (rect 21 251 36 265)(font "Arial" (font_size 8)))
(line (pt 0 256)(pt 16 256)(line_width 1))
)
(port
(pt 0 272)
(input)
(text "A2" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "A2" (rect 21 267 37 281)(font "Arial" (font_size 8)))
(line (pt 0 272)(pt 16 272)(line_width 1))
)
(port
(pt 0 288)
(input)
(text "B2" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "B2" (rect 21 283 36 297)(font "Arial" (font_size 8)))
(line (pt 0 288)(pt 16 288)(line_width 1))
)
(port
(pt 0 304)
(input)
(text "C2" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "C2" (rect 21 299 36 313)(font "Arial" (font_size 8)))
(line (pt 0 304)(pt 16 304)(line_width 1))
)
(port
(pt 0 320)
(input)
(text "A1" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "A1" (rect 21 315 37 329)(font "Arial" (font_size 8)))
(line (pt 0 320)(pt 16 320)(line_width 1))
)
(port
(pt 0 336)
(input)
(text "B1" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "B1" (rect 21 331 36 345)(font "Arial" (font_size 8)))
(line (pt 0 336)(pt 16 336)(line_width 1))
)
(port
(pt 0 352)
(input)
(text "C1" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "C1" (rect 21 347 36 361)(font "Arial" (font_size 8)))
(line (pt 0 352)(pt 16 352)(line_width 1))
)
(port
(pt 0 368)
(input)
(text "A0" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "A0" (rect 21 363 37 377)(font "Arial" (font_size 8)))
(line (pt 0 368)(pt 16 368)(line_width 1))
)
(port
(pt 0 384)
(input)
(text "B0" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "B0" (rect 21 379 36 393)(font "Arial" (font_size 8)))
(line (pt 0 384)(pt 16 384)(line_width 1))
)
(port
(pt 0 400)
(input)
(text "C0" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "C0" (rect 21 395 36 409)(font "Arial" (font_size 8)))
(line (pt 0 400)(pt 16 400)(line_width 1))
)
(port
(pt 0 416)
(input)
(text "AY" (rect 0 0 18 14)(font "Arial" (font_size 8)))
(text "AY" (rect 21 411 39 425)(font "Arial" (font_size 8)))
(line (pt 0 416)(pt 16 416)(line_width 1))
)
(port
(pt 0 432)
(input)
(text "BY" (rect 0 0 17 14)(font "Arial" (font_size 8)))
(text "BY" (rect 21 427 38 441)(font "Arial" (font_size 8)))
(line (pt 0 432)(pt 16 432)(line_width 1))
)
(port
(pt 0 448)
(input)
(text "CY" (rect 0 0 17 14)(font "Arial" (font_size 8)))
(text "CY" (rect 21 443 38 457)(font "Arial" (font_size 8)))
(line (pt 0 448)(pt 16 448)(line_width 1))
)
(port
(pt 96 32)
(output)
(text "Y7" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "Y7" (rect 59 27 75 41)(font "Arial" (font_size 8)))
(line (pt 96 32)(pt 80 32)(line_width 1))
)
(port
(pt 96 48)
(output)
(text "Y6" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "Y6" (rect 59 43 75 57)(font "Arial" (font_size 8)))
(line (pt 96 48)(pt 80 48)(line_width 1))
)
(port
(pt 96 64)
(output)
(text "Y5" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "Y5" (rect 59 59 75 73)(font "Arial" (font_size 8)))
(line (pt 96 64)(pt 80 64)(line_width 1))
)
(port
(pt 96 80)
(output)
(text "Y4" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "Y4" (rect 59 75 75 89)(font "Arial" (font_size 8)))
(line (pt 96 80)(pt 80 80)(line_width 1))
)
(port
(pt 96 96)
(output)
(text "Y3" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "Y3" (rect 59 91 75 105)(font "Arial" (font_size 8)))
(line (pt 96 96)(pt 80 96)(line_width 1))
)
(port
(pt 96 112)
(output)
(text "Y2" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "Y2" (rect 59 107 75 121)(font "Arial" (font_size 8)))
(line (pt 96 112)(pt 80 112)(line_width 1))
)
(port
(pt 96 128)
(output)
(text "Y1" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "Y1" (rect 59 123 75 137)(font "Arial" (font_size 8)))
(line (pt 96 128)(pt 80 128)(line_width 1))
)
(port
(pt 96 144)
(output)
(text "Y0" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "Y0" (rect 59 139 75 153)(font "Arial" (font_size 8)))
(line (pt 96 144)(pt 80 144)(line_width 1))
)
(drawing
(rectangle (rect 16 16 80 464)(line_width 1))
)
)

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triple_selector_8b/db/triple_selector_8b.(0).cnf.cdb Normal file
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未顯示二進位檔案。

二進制
triple_selector_8b/db/triple_selector_8b.(0).cnf.hdb Normal file
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未顯示二進位檔案。

7
triple_selector_8b/db/triple_selector_8b.asm.qmsg Normal file
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 10:24:28 2022 " "Info: Processing started: Mon Mar 07 10:24:28 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off triple_selector_8b -c triple_selector_8b " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off triple_selector_8b -c triple_selector_8b" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "242 " "Info: Peak virtual memory: 242 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 10:24:29 2022 " "Info: Processing ended: Mon Mar 07 10:24:29 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

二進制
triple_selector_8b/db/triple_selector_8b.asm_labs.ddb Normal file
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未顯示二進位檔案。

5
triple_selector_8b/db/triple_selector_8b.cbx.xml Normal file
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<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="triple_selector_8b">
</PROJECT>
</LOG_ROOT>

二進制
triple_selector_8b/db/triple_selector_8b.cmp.bpm Normal file
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未顯示二進位檔案。

二進制
triple_selector_8b/db/triple_selector_8b.cmp.cdb Normal file
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未顯示二進位檔案。

二進制
triple_selector_8b/db/triple_selector_8b.cmp.ecobp Normal file
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未顯示二進位檔案。

二進制
triple_selector_8b/db/triple_selector_8b.cmp.hdb Normal file
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未顯示二進位檔案。

10
triple_selector_8b/db/triple_selector_8b.cmp.kpt Normal file
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<kpt_db name="triple_selector_8b.cmp" kpt_version="1.1">
<key_points_set type="reference" hier_sep="|">
</key_points_set>
<key_points_set type="transition" hier_sep="|">
</key_points_set>
<key_points_set type="transformed" hier_sep="|">
</key_points_set>
<transformations_set hier_sep="|">
</transformations_set>
</kpt_db>

1
triple_selector_8b/db/triple_selector_8b.cmp.logdb Normal file
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v1

二進制
triple_selector_8b/db/triple_selector_8b.cmp.rdb Normal file
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未顯示二進位檔案。

二進制
triple_selector_8b/db/triple_selector_8b.cmp.tdb Normal file
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未顯示二進位檔案。

二進制
triple_selector_8b/db/triple_selector_8b.cmp0.ddb Normal file
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未顯示二進位檔案。

二進制
triple_selector_8b/db/triple_selector_8b.cmp2.ddb Normal file
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未顯示二進位檔案。

10
triple_selector_8b/db/triple_selector_8b.cmp_merge.kpt Normal file
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<kpt_db name="triple_selector_8b.cmp_merge" kpt_version="1.1">
<key_points_set type="reference" hier_sep="|">
</key_points_set>
<key_points_set type="transition" hier_sep="|">
</key_points_set>
<key_points_set type="transformed" hier_sep="|">
</key_points_set>
<transformations_set hier_sep="|">
</transformations_set>
</kpt_db>

3
triple_selector_8b/db/triple_selector_8b.db_info Normal file
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Quartus_Version = Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Version_Index = 167832322
Creation_Time = Mon Mar 07 10:23:46 2022

二進制
triple_selector_8b/db/triple_selector_8b.eco.cdb Normal file
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未顯示二進位檔案。

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