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add 8位加法器

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juzeon 2022-03-07 08:54:33 +08:00
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129
adder/adder.asm.rpt Normal file
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Assembler report for adder
Mon Mar 07 08:49:26 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: D:/projects/quartus/adder/adder.sof
6. Assembler Device Options: D:/projects/quartus/adder/adder.pof
7. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Mon Mar 07 08:49:26 2022 ;
; Revision Name ; adder ;
; Top-level Entity Name ; adder ;
; Family ; Cyclone II ;
; Device ; EP2C8Q208C8 ;
+-----------------------+---------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Assembler Settings ;
+-----------------------------------------------------------------------------+----------+---------------+
; Option ; Setting ; Default Value ;
+-----------------------------------------------------------------------------+----------+---------------+
; Use smart compilation ; Off ; Off ;
; Generate compressed bitstreams ; On ; On ;
; Compression mode ; Off ; Off ;
; Clock source for configuration device ; Internal ; Internal ;
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
; Divide clock frequency by ; 1 ; 1 ;
; Auto user code ; Off ; Off ;
; Use configuration device ; On ; On ;
; Configuration device ; Auto ; Auto ;
; Configuration device auto user code ; Off ; Off ;
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
; Hexadecimal Output File start address ; 0 ; 0 ;
; Hexadecimal Output File count direction ; Up ; Up ;
; Release clears before tri-states ; Off ; Off ;
; Auto-restart configuration after error ; On ; On ;
; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ;
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
+-----------------------------------------------------------------------------+----------+---------------+
+-------------------------------------+
; Assembler Generated Files ;
+-------------------------------------+
; File Name ;
+-------------------------------------+
; D:/projects/quartus/adder/adder.sof ;
; D:/projects/quartus/adder/adder.pof ;
+-------------------------------------+
+---------------------------------------------------------------+
; Assembler Device Options: D:/projects/quartus/adder/adder.sof ;
+----------------+----------------------------------------------+
; Option ; Setting ;
+----------------+----------------------------------------------+
; Device ; EP2C8Q208C8 ;
; JTAG usercode ; 0xFFFFFFFF ;
; Checksum ; 0x000C8655 ;
+----------------+----------------------------------------------+
+---------------------------------------------------------------+
; Assembler Device Options: D:/projects/quartus/adder/adder.pof ;
+--------------------+------------------------------------------+
; Option ; Setting ;
+--------------------+------------------------------------------+
; Device ; EPCS4 ;
; JTAG usercode ; 0x00000000 ;
; Checksum ; 0x06F061B0 ;
; Compression Ratio ; 3 ;
+--------------------+------------------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Mon Mar 07 08:49:25 2022
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off adder -c adder
Info: Writing out detailed assembly data for power analysis
Info: Assembler is generating device programming files
Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 242 megabytes
Info: Processing ended: Mon Mar 07 08:49:26 2022
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:00

2906
adder/adder.bdf Normal file
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211
adder/adder.bsf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 112 336)
(text "adder" (rect 5 0 38 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 304 25 316)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "A7" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "A7" (rect 21 27 37 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "B7" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "B7" (rect 21 43 36 57)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "A6" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "A6" (rect 21 59 37 73)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 0 80)
(input)
(text "B6" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "B6" (rect 21 75 36 89)(font "Arial" (font_size 8)))
(line (pt 0 80)(pt 16 80)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "A5" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "A5" (rect 21 91 37 105)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 16 96)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "B5" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "B5" (rect 21 107 36 121)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 16 112)(line_width 1))
)
(port
(pt 0 128)
(input)
(text "A4" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "A4" (rect 21 123 37 137)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 16 128)(line_width 1))
)
(port
(pt 0 144)
(input)
(text "B4" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "B4" (rect 21 139 36 153)(font "Arial" (font_size 8)))
(line (pt 0 144)(pt 16 144)(line_width 1))
)
(port
(pt 0 160)
(input)
(text "A3" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "A3" (rect 21 155 37 169)(font "Arial" (font_size 8)))
(line (pt 0 160)(pt 16 160)(line_width 1))
)
(port
(pt 0 176)
(input)
(text "B3" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "B3" (rect 21 171 36 185)(font "Arial" (font_size 8)))
(line (pt 0 176)(pt 16 176)(line_width 1))
)
(port
(pt 0 192)
(input)
(text "A2" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "A2" (rect 21 187 37 201)(font "Arial" (font_size 8)))
(line (pt 0 192)(pt 16 192)(line_width 1))
)
(port
(pt 0 208)
(input)
(text "B2" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "B2" (rect 21 203 36 217)(font "Arial" (font_size 8)))
(line (pt 0 208)(pt 16 208)(line_width 1))
)
(port
(pt 0 224)
(input)
(text "A1" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "A1" (rect 21 219 37 233)(font "Arial" (font_size 8)))
(line (pt 0 224)(pt 16 224)(line_width 1))
)
(port
(pt 0 240)
(input)
(text "B1" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "B1" (rect 21 235 36 249)(font "Arial" (font_size 8)))
(line (pt 0 240)(pt 16 240)(line_width 1))
)
(port
(pt 0 256)
(input)
(text "A0" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "A0" (rect 21 251 37 265)(font "Arial" (font_size 8)))
(line (pt 0 256)(pt 16 256)(line_width 1))
)
(port
(pt 0 272)
(input)
(text "B0" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "B0" (rect 21 267 36 281)(font "Arial" (font_size 8)))
(line (pt 0 272)(pt 16 272)(line_width 1))
)
(port
(pt 0 288)
(input)
(text "CI" (rect 0 0 10 14)(font "Arial" (font_size 8)))
(text "CI" (rect 21 283 31 297)(font "Arial" (font_size 8)))
(line (pt 0 288)(pt 16 288)(line_width 1))
)
(port
(pt 96 32)
(output)
(text "CO" (rect 0 0 17 14)(font "Arial" (font_size 8)))
(text "CO" (rect 58 27 75 41)(font "Arial" (font_size 8)))
(line (pt 96 32)(pt 80 32)(line_width 1))
)
(port
(pt 96 48)
(output)
(text "S7" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "S7" (rect 60 43 75 57)(font "Arial" (font_size 8)))
(line (pt 96 48)(pt 80 48)(line_width 1))
)
(port
(pt 96 64)
(output)
(text "S6" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "S6" (rect 60 59 75 73)(font "Arial" (font_size 8)))
(line (pt 96 64)(pt 80 64)(line_width 1))
)
(port
(pt 96 80)
(output)
(text "S5" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "S5" (rect 60 75 75 89)(font "Arial" (font_size 8)))
(line (pt 96 80)(pt 80 80)(line_width 1))
)
(port
(pt 96 96)
(output)
(text "S4" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "S4" (rect 60 91 75 105)(font "Arial" (font_size 8)))
(line (pt 96 96)(pt 80 96)(line_width 1))
)
(port
(pt 96 112)
(output)
(text "S3" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "S3" (rect 60 107 75 121)(font "Arial" (font_size 8)))
(line (pt 96 112)(pt 80 112)(line_width 1))
)
(port
(pt 96 128)
(output)
(text "S2" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "S2" (rect 60 123 75 137)(font "Arial" (font_size 8)))
(line (pt 96 128)(pt 80 128)(line_width 1))
)
(port
(pt 96 144)
(output)
(text "S1" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "S1" (rect 60 139 75 153)(font "Arial" (font_size 8)))
(line (pt 96 144)(pt 80 144)(line_width 1))
)
(port
(pt 96 160)
(output)
(text "S0" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "S0" (rect 60 155 75 169)(font "Arial" (font_size 8)))
(line (pt 96 160)(pt 80 160)(line_width 1))
)
(drawing
(rectangle (rect 16 16 80 304)(line_width 1))
)
)

1
adder/adder.done Normal file
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Mon Mar 07 08:49:27 2022

1040
adder/adder.fit.rpt Normal file
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adder/adder.fit.smsg Normal file
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Extra Info: Performing register packing on registers with non-logic cell location assignments
Extra Info: Completed register packing on registers with non-logic cell location assignments
Extra Info: Started Fast Input/Output/OE register processing
Extra Info: Finished Fast Input/Output/OE register processing
Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks

16
adder/adder.fit.summary Normal file
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Fitter Status : Successful - Mon Mar 07 08:49:24 2022
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : adder
Top-level Entity Name : adder
Family : Cyclone II
Device : EP2C8Q208C8
Timing Models : Final
Total logic elements : 21 / 8,256 ( < 1 % )
Total combinational functions : 21 / 8,256 ( < 1 % )
Dedicated logic registers : 0 / 8,256 ( 0 % )
Total registers : 0
Total pins : 26 / 138 ( 19 % )
Total virtual pins : 0
Total memory bits : 0 / 165,888 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )

120
adder/adder.flow.rpt Normal file
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Flow report for adder
Mon Mar 07 08:49:27 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+----------------------------------------------+
; Flow Status ; Successful - Mon Mar 07 08:49:27 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; adder ;
; Top-level Entity Name ; adder ;
; Family ; Cyclone II ;
; Device ; EP2C8Q208C8 ;
; Timing Models ; Final ;
; Met timing requirements ; Yes ;
; Total logic elements ; 21 / 8,256 ( < 1 % ) ;
; Total combinational functions ; 21 / 8,256 ( < 1 % ) ;
; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 26 / 138 ( 19 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 165,888 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
; Total PLLs ; 0 / 2 ( 0 % ) ;
+------------------------------------+----------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 03/07/2022 08:49:22 ;
; Main task ; Compilation ;
; Revision Name ; adder ;
+-------------------+---------------------+
+---------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+------------------------------------+---------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+------------------------------------+---------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 220283517943889.164661416219416 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
+------------------------------------+---------------------------------+---------------+-------------+----------------+
+-----------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 245 MB ; 00:00:00 ;
; Fitter ; 00:00:01 ; 1.0 ; 305 MB ; 00:00:01 ;
; Assembler ; 00:00:01 ; 1.0 ; 242 MB ; 00:00:00 ;
; Classic Timing Analyzer ; 00:00:01 ; 1.0 ; 198 MB ; 00:00:00 ;
; Total ; 00:00:04 ; -- ; -- ; 00:00:01 ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+------------------------------------------------------------------------------------------+
; Flow OS Summary ;
+-------------------------+------------------+---------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+-------------------------+------------------+---------------+------------+----------------+
; Analysis & Synthesis ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
; Fitter ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
; Assembler ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
; Classic Timing Analyzer ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
+-------------------------+------------------+---------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off adder -c adder
quartus_fit --read_settings_files=off --write_settings_files=off adder -c adder
quartus_asm --read_settings_files=off --write_settings_files=off adder -c adder
quartus_tan --read_settings_files=off --write_settings_files=off adder -c adder --timing_analysis_only

240
adder/adder.map.rpt Normal file
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Analysis & Synthesis report for adder
Mon Mar 07 08:49:22 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. General Register Statistics
8. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Mar 07 08:49:22 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; adder ;
; Top-level Entity Name ; adder ;
; Family ; Cyclone II ;
; Total logic elements ; 21 ;
; Total combinational functions ; 21 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 26 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
+------------------------------------+----------------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------+--------------------+--------------------+
; Device ; EP2C8Q208C8 ; ;
; Top-level entity name ; adder ; adder ;
; Family name ; Cyclone II ; Stratix II ;
; Use Generated Physical Constraints File ; Off ; ;
; Use smart compilation ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; Off ; Off ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
+--------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------+
; adder.bdf ; yes ; User Block Diagram/Schematic File ; D:/projects/quartus/adder/adder.bdf ;
; 7400.bdf ; yes ; Megafunction ; d:/altera/90sp2/quartus/libraries/others/maxplus2/7400.bdf ;
; 7486.bdf ; yes ; Megafunction ; d:/altera/90sp2/quartus/libraries/others/maxplus2/7486.bdf ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------+
+--------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+----------------+
; Resource ; Usage ;
+---------------------------------------------+----------------+
; Estimated Total logic elements ; 21 ;
; ; ;
; Total combinational functions ; 21 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 9 ;
; -- 3 input functions ; 9 ;
; -- <=2 input functions ; 3 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 21 ;
; -- arithmetic mode ; 0 ;
; ; ;
; Total registers ; 0 ;
; -- Dedicated logic registers ; 0 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 26 ;
; Maximum fan-out node ; 7400:inst8|4~0 ;
; Maximum fan-out ; 4 ;
; Total fan-out ; 78 ;
; Average fan-out ; 1.66 ;
+---------------------------------------------+----------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |adder ; 21 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 26 ; 0 ; |adder ; work ;
; |7400:inst13| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7400:inst13 ; work ;
; |7400:inst18| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7400:inst18 ; work ;
; |7400:inst23| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7400:inst23 ; work ;
; |7400:inst28| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7400:inst28 ; work ;
; |7400:inst33| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7400:inst33 ; work ;
; |7400:inst38| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7400:inst38 ; work ;
; |7400:inst3| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7400:inst3 ; work ;
; |7400:inst8| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7400:inst8 ; work ;
; |7486:inst10| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7486:inst10 ; work ;
; |7486:inst15| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7486:inst15 ; work ;
; |7486:inst20| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7486:inst20 ; work ;
; |7486:inst25| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7486:inst25 ; work ;
; |7486:inst30| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7486:inst30 ; work ;
; |7486:inst35| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7486:inst35 ; work ;
; |7486:inst40| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7486:inst40 ; work ;
; |7486:inst5| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |adder|7486:inst5 ; work ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Mon Mar 07 08:49:21 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adder -c adder
Info: Found 1 design units, including 1 entities, in source file adder.bdf
Info: Found entity 1: adder
Info: Elaborating entity "adder" for the top level hierarchy
Info: Elaborating entity "7400" for hierarchy "7400:inst38"
Info: Elaborated megafunction instantiation "7400:inst38"
Info: Elaborating entity "7486" for hierarchy "7486:inst"
Info: Elaborated megafunction instantiation "7486:inst"
Info: Implemented 47 device resources after synthesis - the final resource count might be different
Info: Implemented 17 input pins
Info: Implemented 9 output pins
Info: Implemented 21 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 248 megabytes
Info: Processing ended: Mon Mar 07 08:49:22 2022
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01

14
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Analysis & Synthesis Status : Successful - Mon Mar 07 08:49:22 2022
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : adder
Top-level Entity Name : adder
Family : Cyclone II
Total logic elements : 21
Total combinational functions : 21
Dedicated logic registers : 0
Total registers : 0
Total pins : 26
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0

278
adder/adder.pin Normal file
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-- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
-- Bank 2: 3.3V
-- Bank 3: 3.3V
-- Bank 4: 3.3V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17),
-- connect each pin marked GND* either individually through a 10k Ohm resistor
-- to GND or tie all pins together and connect through a single 10k Ohm resistor
-- to GND.
-- For non-transceiver I/O banks, connect each pin marked GND* directly to GND
-- or leave it unconnected.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
CHIP "adder" ASSIGNED TO AN: EP2C8Q208C8
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVTTL : : 1 : N
~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVTTL : : 1 : N
GND* : 3 : : : : 1 :
GND* : 4 : : : : 1 :
A7 : 5 : input : 3.3-V LVTTL : : 1 : N
S7 : 6 : output : 3.3-V LVTTL : : 1 : N
VCCIO1 : 7 : power : : 3.3V : 1 :
GND* : 8 : : : : 1 :
GND : 9 : gnd : : : :
B6 : 10 : input : 3.3-V LVTTL : : 1 : N
B7 : 11 : input : 3.3-V LVTTL : : 1 : N
S6 : 12 : output : 3.3-V LVTTL : : 1 : N
A6 : 13 : input : 3.3-V LVTTL : : 1 : N
B5 : 14 : input : 3.3-V LVTTL : : 1 : N
GND* : 15 : : : : 1 :
TDO : 16 : output : : : 1 :
TMS : 17 : input : : : 1 :
TCK : 18 : input : : : 1 :
TDI : 19 : input : : : 1 :
DATA0 : 20 : input : : : 1 :
DCLK : 21 : : : : 1 :
nCE : 22 : : : : 1 :
A2 : 23 : input : 3.3-V LVTTL : : 1 : N
A0 : 24 : input : 3.3-V LVTTL : : 1 : N
GND : 25 : gnd : : : :
nCONFIG : 26 : : : : 1 :
CI : 27 : input : 3.3-V LVTTL : : 1 : N
B0 : 28 : input : 3.3-V LVTTL : : 1 : N
VCCIO1 : 29 : power : : 3.3V : 1 :
B2 : 30 : input : 3.3-V LVTTL : : 1 : N
S3 : 31 : output : 3.3-V LVTTL : : 1 : N
VCCINT : 32 : power : : 1.2V : :
GND* : 33 : : : : 1 :
S1 : 34 : output : 3.3-V LVTTL : : 1 : N
S5 : 35 : output : 3.3-V LVTTL : : 1 : N
GND : 36 : gnd : : : :
S4 : 37 : output : 3.3-V LVTTL : : 1 : N
GND : 38 : gnd : : : :
B3 : 39 : input : 3.3-V LVTTL : : 1 : N
A3 : 40 : input : 3.3-V LVTTL : : 1 : N
A4 : 41 : input : 3.3-V LVTTL : : 1 : N
VCCIO1 : 42 : power : : 3.3V : 1 :
GND* : 43 : : : : 1 :
GND* : 44 : : : : 1 :
GND* : 45 : : : : 1 :
GND* : 46 : : : : 1 :
GND* : 47 : : : : 1 :
GND* : 48 : : : : 1 :
GND : 49 : gnd : : : :
GND_PLL1 : 50 : gnd : : : :
VCCD_PLL1 : 51 : power : : 1.2V : :
GND_PLL1 : 52 : gnd : : : :
VCCA_PLL1 : 53 : power : : 1.2V : :
GNDA_PLL1 : 54 : gnd : : : :
GND : 55 : gnd : : : :
GND* : 56 : : : : 4 :
A1 : 57 : input : 3.3-V LVTTL : : 4 : N
CO : 58 : output : 3.3-V LVTTL : : 4 : N
GND* : 59 : : : : 4 :
B1 : 60 : input : 3.3-V LVTTL : : 4 : N
GND* : 61 : : : : 4 :
VCCIO4 : 62 : power : : 3.3V : 4 :
GND* : 63 : : : : 4 :
GND* : 64 : : : : 4 :
GND : 65 : gnd : : : :
VCCINT : 66 : power : : 1.2V : :
GND* : 67 : : : : 4 :
GND* : 68 : : : : 4 :
GND* : 69 : : : : 4 :
GND* : 70 : : : : 4 :
VCCIO4 : 71 : power : : 3.3V : 4 :
GND* : 72 : : : : 4 :
GND : 73 : gnd : : : :
GND* : 74 : : : : 4 :
GND* : 75 : : : : 4 :
GND* : 76 : : : : 4 :
GND* : 77 : : : : 4 :
GND : 78 : gnd : : : :
VCCINT : 79 : power : : 1.2V : :
GND* : 80 : : : : 4 :
GND* : 81 : : : : 4 :
GND* : 82 : : : : 4 :
VCCIO4 : 83 : power : : 3.3V : 4 :
GND* : 84 : : : : 4 :
GND : 85 : gnd : : : :
GND* : 86 : : : : 4 :
GND* : 87 : : : : 4 :
GND* : 88 : : : : 4 :
GND* : 89 : : : : 4 :
GND* : 90 : : : : 4 :
VCCIO4 : 91 : power : : 3.3V : 4 :
GND* : 92 : : : : 4 :
GND : 93 : gnd : : : :
GND* : 94 : : : : 4 :
GND* : 95 : : : : 4 :
GND* : 96 : : : : 4 :
GND* : 97 : : : : 4 :
VCCIO4 : 98 : power : : 3.3V : 4 :
GND* : 99 : : : : 4 :
GND : 100 : gnd : : : :
GND* : 101 : : : : 4 :
S0 : 102 : output : 3.3-V LVTTL : : 4 : N
GND* : 103 : : : : 4 :
GND* : 104 : : : : 4 :
GND* : 105 : : : : 3 :
GND* : 106 : : : : 3 :
GND* : 107 : : : : 3 :
~LVDS54p/nCEO~ : 108 : output : 3.3-V LVTTL : : 3 : N
VCCIO3 : 109 : power : : 3.3V : 3 :
GND* : 110 : : : : 3 :
GND : 111 : gnd : : : :
GND* : 112 : : : : 3 :
GND* : 113 : : : : 3 :
GND* : 114 : : : : 3 :
GND* : 115 : : : : 3 :
GND* : 116 : : : : 3 :
GND* : 117 : : : : 3 :
S2 : 118 : output : 3.3-V LVTTL : : 3 : N
GND : 119 : gnd : : : :
VCCINT : 120 : power : : 1.2V : :
nSTATUS : 121 : : : : 3 :
VCCIO3 : 122 : power : : 3.3V : 3 :
CONF_DONE : 123 : : : : 3 :
GND : 124 : gnd : : : :
MSEL1 : 125 : : : : 3 :
MSEL0 : 126 : : : : 3 :
GND* : 127 : : : : 3 :
GND* : 128 : : : : 3 :
GND+ : 129 : : : : 3 :
GND+ : 130 : : : : 3 :
GND+ : 131 : : : : 3 :
GND+ : 132 : : : : 3 :
GND* : 133 : : : : 3 :
GND* : 134 : : : : 3 :
GND* : 135 : : : : 3 :
VCCIO3 : 136 : power : : 3.3V : 3 :
GND* : 137 : : : : 3 :
GND* : 138 : : : : 3 :
GND* : 139 : : : : 3 :
GND : 140 : gnd : : : :
GND* : 141 : : : : 3 :
GND* : 142 : : : : 3 :
GND* : 143 : : : : 3 :
GND* : 144 : : : : 3 :
GND* : 145 : : : : 3 :
GND* : 146 : : : : 3 :
GND* : 147 : : : : 3 :
VCCIO3 : 148 : power : : 3.3V : 3 :
GND* : 149 : : : : 3 :
A5 : 150 : input : 3.3-V LVTTL : : 3 : N
GND* : 151 : : : : 3 :
GND* : 152 : : : : 3 :
GND : 153 : gnd : : : :
GND_PLL2 : 154 : gnd : : : :
VCCD_PLL2 : 155 : power : : 1.2V : :
GND_PLL2 : 156 : gnd : : : :
VCCA_PLL2 : 157 : power : : 1.2V : :
GNDA_PLL2 : 158 : gnd : : : :
GND : 159 : gnd : : : :
GND* : 160 : : : : 2 :
GND* : 161 : : : : 2 :
GND* : 162 : : : : 2 :
GND* : 163 : : : : 2 :
GND* : 164 : : : : 2 :
GND* : 165 : : : : 2 :
VCCIO2 : 166 : power : : 3.3V : 2 :
GND : 167 : gnd : : : :
GND* : 168 : : : : 2 :
GND* : 169 : : : : 2 :
GND* : 170 : : : : 2 :
GND* : 171 : : : : 2 :
VCCIO2 : 172 : power : : 3.3V : 2 :
GND* : 173 : : : : 2 :
GND : 174 : gnd : : : :
GND* : 175 : : : : 2 :
GND* : 176 : : : : 2 :
GND : 177 : gnd : : : :
VCCINT : 178 : power : : 1.2V : :
GND* : 179 : : : : 2 :
GND* : 180 : : : : 2 :
GND* : 181 : : : : 2 :
GND* : 182 : : : : 2 :
VCCIO2 : 183 : power : : 3.3V : 2 :
GND : 184 : gnd : : : :
GND* : 185 : : : : 2 :
GND : 186 : gnd : : : :
GND* : 187 : : : : 2 :
GND* : 188 : : : : 2 :
GND* : 189 : : : : 2 :
VCCINT : 190 : power : : 1.2V : :
GND* : 191 : : : : 2 :
GND* : 192 : : : : 2 :
GND* : 193 : : : : 2 :
VCCIO2 : 194 : power : : 3.3V : 2 :
GND* : 195 : : : : 2 :
GND : 196 : gnd : : : :
GND* : 197 : : : : 2 :
GND* : 198 : : : : 2 :
GND* : 199 : : : : 2 :
GND* : 200 : : : : 2 :
GND* : 201 : : : : 2 :
VCCIO2 : 202 : power : : 3.3V : 2 :
GND* : 203 : : : : 2 :
GND : 204 : gnd : : : :
GND* : 205 : : : : 2 :
GND* : 206 : : : : 2 :
B4 : 207 : input : 3.3-V LVTTL : : 2 : N
GND* : 208 : : : : 2 :

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adder/adder.pof Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 08:48:37 March 07, 2022
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "9.0"
DATE = "08:48:37 March 07, 2022"
# Revisions
PROJECT_REVISION = "adder"

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adder/adder.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 08:48:37 March 07, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# adder_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C8Q208C8
set_global_assignment -name TOP_LEVEL_ENTITY adder
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:48:37 MARCH 07, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name BDF_FILE adder.bdf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"

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adder/adder.sof Normal file
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adder/adder.tan.rpt Normal file
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Classic Timing Analyzer report for adder
Mon Mar 07 08:49:27 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Parallel Compilation
5. tpd
6. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 19.344 ns ; A1 ; CO ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C8Q208C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Minimum Core Junction Temperature ; 0 ; ; ; ;
; Maximum Core Junction Temperature ; 85 ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; On ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
; Output I/O Timing Endpoint ; Near End ; ; ; ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; 1 processor ; 100.0% ;
; 2-4 processors ; 0.0% ;
+----------------------------+-------------+
+---------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A ; None ; 19.344 ns ; A1 ; CO ;
; N/A ; None ; 19.220 ns ; B1 ; CO ;
; N/A ; None ; 18.199 ns ; B2 ; CO ;
; N/A ; None ; 18.173 ns ; A1 ; S7 ;
; N/A ; None ; 18.049 ns ; B1 ; S7 ;
; N/A ; None ; 17.501 ns ; A3 ; CO ;
; N/A ; None ; 17.423 ns ; B3 ; CO ;
; N/A ; None ; 17.266 ns ; B4 ; CO ;
; N/A ; None ; 17.091 ns ; A5 ; CO ;
; N/A ; None ; 17.075 ns ; A4 ; CO ;
; N/A ; None ; 17.028 ns ; B2 ; S7 ;
; N/A ; None ; 17.000 ns ; A1 ; S6 ;
; N/A ; None ; 16.876 ns ; B1 ; S6 ;
; N/A ; None ; 16.330 ns ; A3 ; S7 ;
; N/A ; None ; 16.252 ns ; B3 ; S7 ;
; N/A ; None ; 16.095 ns ; B4 ; S7 ;
; N/A ; None ; 15.940 ns ; B5 ; CO ;
; N/A ; None ; 15.920 ns ; A5 ; S7 ;
; N/A ; None ; 15.904 ns ; A4 ; S7 ;
; N/A ; None ; 15.855 ns ; B2 ; S6 ;
; N/A ; None ; 15.259 ns ; A0 ; CO ;
; N/A ; None ; 15.157 ns ; A3 ; S6 ;
; N/A ; None ; 15.079 ns ; B3 ; S6 ;
; N/A ; None ; 15.027 ns ; B0 ; CO ;
; N/A ; None ; 14.922 ns ; B4 ; S6 ;
; N/A ; None ; 14.769 ns ; B5 ; S7 ;
; N/A ; None ; 14.762 ns ; CI ; CO ;
; N/A ; None ; 14.759 ns ; A1 ; S5 ;
; N/A ; None ; 14.747 ns ; A5 ; S6 ;
; N/A ; None ; 14.731 ns ; A4 ; S6 ;
; N/A ; None ; 14.635 ns ; B1 ; S5 ;
; N/A ; None ; 14.560 ns ; A1 ; S2 ;
; N/A ; None ; 14.436 ns ; B1 ; S2 ;
; N/A ; None ; 14.088 ns ; A0 ; S7 ;
; N/A ; None ; 14.087 ns ; A1 ; S4 ;
; N/A ; None ; 13.963 ns ; B1 ; S4 ;
; N/A ; None ; 13.856 ns ; B0 ; S7 ;
; N/A ; None ; 13.695 ns ; A6 ; CO ;
; N/A ; None ; 13.614 ns ; B2 ; S5 ;
; N/A ; None ; 13.596 ns ; B5 ; S6 ;
; N/A ; None ; 13.591 ns ; CI ; S7 ;
; N/A ; None ; 13.448 ns ; A2 ; CO ;
; N/A ; None ; 13.408 ns ; B2 ; S2 ;
; N/A ; None ; 13.338 ns ; A1 ; S3 ;
; N/A ; None ; 13.214 ns ; B1 ; S3 ;
; N/A ; None ; 12.955 ns ; B6 ; CO ;
; N/A ; None ; 12.942 ns ; B2 ; S4 ;
; N/A ; None ; 12.916 ns ; A3 ; S5 ;
; N/A ; None ; 12.915 ns ; A0 ; S6 ;
; N/A ; None ; 12.838 ns ; B3 ; S5 ;
; N/A ; None ; 12.683 ns ; B0 ; S6 ;
; N/A ; None ; 12.681 ns ; B4 ; S5 ;
; N/A ; None ; 12.613 ns ; B7 ; CO ;
; N/A ; None ; 12.524 ns ; A6 ; S7 ;
; N/A ; None ; 12.501 ns ; A5 ; S5 ;
; N/A ; None ; 12.488 ns ; A4 ; S5 ;
; N/A ; None ; 12.418 ns ; CI ; S6 ;
; N/A ; None ; 12.408 ns ; A7 ; CO ;
; N/A ; None ; 12.277 ns ; A2 ; S7 ;
; N/A ; None ; 12.244 ns ; A3 ; S4 ;
; N/A ; None ; 12.193 ns ; B2 ; S3 ;
; N/A ; None ; 12.166 ns ; B3 ; S4 ;
; N/A ; None ; 12.007 ns ; B4 ; S4 ;
; N/A ; None ; 11.786 ns ; B6 ; S7 ;
; N/A ; None ; 11.579 ns ; A1 ; S1 ;
; N/A ; None ; 11.527 ns ; A4 ; S4 ;
; N/A ; None ; 11.489 ns ; A3 ; S3 ;
; N/A ; None ; 11.458 ns ; B1 ; S1 ;
; N/A ; None ; 11.443 ns ; B7 ; S7 ;
; N/A ; None ; 11.415 ns ; B3 ; S3 ;
; N/A ; None ; 11.378 ns ; A6 ; S6 ;
; N/A ; None ; 11.337 ns ; B5 ; S5 ;
; N/A ; None ; 11.243 ns ; A7 ; S7 ;
; N/A ; None ; 11.104 ns ; A2 ; S6 ;
; N/A ; None ; 11.091 ns ; B6 ; S6 ;
; N/A ; None ; 10.674 ns ; A0 ; S5 ;
; N/A ; None ; 10.475 ns ; A0 ; S2 ;
; N/A ; None ; 10.442 ns ; B0 ; S5 ;
; N/A ; None ; 10.294 ns ; A0 ; S0 ;
; N/A ; None ; 10.243 ns ; B0 ; S2 ;
; N/A ; None ; 10.177 ns ; CI ; S5 ;
; N/A ; None ; 10.065 ns ; B0 ; S0 ;
; N/A ; None ; 10.002 ns ; A0 ; S4 ;
; N/A ; None ; 9.978 ns ; CI ; S2 ;
; N/A ; None ; 9.800 ns ; CI ; S0 ;
; N/A ; None ; 9.770 ns ; B0 ; S4 ;
; N/A ; None ; 9.505 ns ; CI ; S4 ;
; N/A ; None ; 9.253 ns ; A0 ; S3 ;
; N/A ; None ; 9.021 ns ; B0 ; S3 ;
; N/A ; None ; 8.863 ns ; A2 ; S5 ;
; N/A ; None ; 8.756 ns ; CI ; S3 ;
; N/A ; None ; 8.661 ns ; A2 ; S2 ;
; N/A ; None ; 8.191 ns ; A2 ; S4 ;
; N/A ; None ; 7.490 ns ; A0 ; S1 ;
; N/A ; None ; 7.442 ns ; A2 ; S3 ;
; N/A ; None ; 7.258 ns ; B0 ; S1 ;
; N/A ; None ; 6.993 ns ; CI ; S1 ;
+-------+-------------------+-----------------+------+----+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Mon Mar 07 08:49:26 2022
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off adder -c adder --timing_analysis_only
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Info: Longest tpd from source pin "A1" to destination pin "CO" is 19.344 ns
Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_57; Fanout = 2; PIN Node = 'A1'
Info: 2: + IC(6.202 ns) + CELL(0.651 ns) = 7.847 ns; Loc. = LCCOMB_X1_Y7_N12; Fanout = 4; COMB Node = '7400:inst8|4~0'
Info: 3: + IC(0.391 ns) + CELL(0.206 ns) = 8.444 ns; Loc. = LCCOMB_X1_Y7_N8; Fanout = 2; COMB Node = '7400:inst13|4~1'
Info: 4: + IC(0.387 ns) + CELL(0.370 ns) = 9.201 ns; Loc. = LCCOMB_X1_Y7_N4; Fanout = 2; COMB Node = '7400:inst18|4~0'
Info: 5: + IC(0.387 ns) + CELL(0.370 ns) = 9.958 ns; Loc. = LCCOMB_X1_Y7_N6; Fanout = 2; COMB Node = '7400:inst23|4~9'
Info: 6: + IC(0.412 ns) + CELL(0.650 ns) = 11.020 ns; Loc. = LCCOMB_X1_Y7_N0; Fanout = 3; COMB Node = '7400:inst28|4~0'
Info: 7: + IC(1.736 ns) + CELL(0.206 ns) = 12.962 ns; Loc. = LCCOMB_X1_Y15_N24; Fanout = 2; COMB Node = '7400:inst33|4~0'
Info: 8: + IC(0.396 ns) + CELL(0.651 ns) = 14.009 ns; Loc. = LCCOMB_X1_Y15_N4; Fanout = 1; COMB Node = '7400:inst38|4~0'
Info: 9: + IC(2.039 ns) + CELL(3.296 ns) = 19.344 ns; Loc. = PIN_58; Fanout = 0; PIN Node = 'CO'
Info: Total cell delay = 7.394 ns ( 38.22 % )
Info: Total interconnect delay = 11.950 ns ( 61.78 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 212 megabytes
Info: Processing ended: Mon Mar 07 08:49:27 2022
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:00

26
adder/adder.tan.summary Normal file
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--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------
Type : Worst-case tpd
Slack : N/A
Required Time : None
Actual Time : 19.344 ns
From : A1
To : CO
From Clock : --
To Clock : --
Failed Paths : 0
Type : Total number of failed paths
Slack :
Required Time :
Actual Time :
From :
To :
From Clock :
To Clock :
Failed Paths : 0
--------------------------------------------------------------------------------------

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adder/db/adder.asm.qmsg Normal file
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 08:49:25 2022 " "Info: Processing started: Mon Mar 07 08:49:25 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off adder -c adder " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off adder -c adder" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "242 " "Info: Peak virtual memory: 242 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 08:49:26 2022 " "Info: Processing ended: Mon Mar 07 08:49:26 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

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adder/db/adder.asm_labs.ddb Normal file
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adder/db/adder.cbx.xml Normal file
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<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="adder">
</PROJECT>
</LOG_ROOT>

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adder/db/adder.cmp.bpm Normal file
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adder/db/adder.cmp.cdb Normal file
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adder/db/adder.cmp.kpt Normal file
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<kpt_db name="adder.cmp" kpt_version="1.1">
<key_points_set type="reference" hier_sep="|">
</key_points_set>
<key_points_set type="transition" hier_sep="|">
</key_points_set>
<key_points_set type="transformed" hier_sep="|">
</key_points_set>
<transformations_set hier_sep="|">
</transformations_set>
</kpt_db>

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adder/db/adder.cmp.logdb Normal file
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v1

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adder/db/adder.cmp.tdb Normal file
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adder/db/adder.cmp_merge.kpt Normal file
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<kpt_db name="adder.cmp_merge" kpt_version="1.1">
<key_points_set type="reference" hier_sep="|">
</key_points_set>
<key_points_set type="transition" hier_sep="|">
</key_points_set>
<key_points_set type="transformed" hier_sep="|">
</key_points_set>
<transformations_set hier_sep="|">
</transformations_set>
</kpt_db>

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adder/db/adder.db_info Normal file
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Quartus_Version = Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Version_Index = 167832322
Creation_Time = Mon Mar 07 08:48:37 2022

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adder/db/adder.eco.cdb Normal file
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adder/db/adder.fit.qmsg Normal file
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adder/db/adder.hier_info Normal file
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|adder
CO <= 7400:inst38.1
A7 => 7400:inst39.3
A7 => 7486:inst36.2
B7 => 7400:inst39.2
B7 => 7486:inst36.3
A6 => 7400:inst34.3
A6 => 7486:inst31.2
B6 => 7400:inst34.2
B6 => 7486:inst31.3
A5 => 7400:inst29.3
A5 => 7486:inst26.2
B5 => 7400:inst29.2
B5 => 7486:inst26.3
A4 => 7400:inst24.3
A4 => 7486:inst21.2
B4 => 7400:inst24.2
B4 => 7486:inst21.3
A3 => 7400:inst19.3
A3 => 7486:inst16.2
B3 => 7400:inst19.2
B3 => 7486:inst16.3
A2 => 7400:inst14.3
A2 => 7486:inst11.2
B2 => 7400:inst14.2
B2 => 7486:inst11.3
A1 => 7400:inst9.3
A1 => 7486:inst6.2
B1 => 7400:inst9.2
B1 => 7486:inst6.3
A0 => 7400:inst4.3
A0 => 7486:inst.2
B0 => 7400:inst4.2
B0 => 7486:inst.3
CI => 7400:inst2.3
CI => 7486:inst5.3
S7 <= 7486:inst40.1
S0 <= 7486:inst5.1
S1 <= 7486:inst10.1
S2 <= 7486:inst15.1
S3 <= 7486:inst20.1
S4 <= 7486:inst25.1
S5 <= 7486:inst30.1
S6 <= 7486:inst35.1
|adder|7400:inst38
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7400:inst39
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7400:inst37
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7400:inst33
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7400:inst34
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7400:inst32
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7400:inst28
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7400:inst29
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7400:inst27
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7400:inst23
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7400:inst24
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7400:inst22
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7400:inst18
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7400:inst19
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7400:inst17
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7400:inst13
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7400:inst14
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7400:inst12
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7400:inst8
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7400:inst9
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7400:inst7
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7400:inst3
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7400:inst4
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7400:inst2
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7486:inst
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7486:inst6
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7486:inst11
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7486:inst16
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7486:inst21
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7486:inst26
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7486:inst31
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7486:inst36
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7486:inst40
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7486:inst5
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7486:inst10
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7486:inst15
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7486:inst20
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7486:inst25
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7486:inst30
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1
|adder|7486:inst35
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1

120
adder/db/adder.hif Normal file
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Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
11
936
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
adder
# storage
db|adder.(0).cnf
db|adder.(0).cnf
# case_insensitive
# source_file
adder.bdf
24315e582bd755b4b98eeb6d569ea2
26
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
|
}
# macro_sequence
# end
# entity
7400
# storage
db|adder.(1).cnf
db|adder.(1).cnf
# case_insensitive
# source_file
..|..|..|altera|90sp2|quartus|libraries|others|maxplus2|7400.bdf
2bbb3be4da5c8a854468ca6be3dac
26
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
7400:inst38
7400:inst39
7400:inst37
7400:inst33
7400:inst34
7400:inst32
7400:inst28
7400:inst29
7400:inst27
7400:inst23
7400:inst24
7400:inst22
7400:inst18
7400:inst19
7400:inst17
7400:inst13
7400:inst14
7400:inst12
7400:inst8
7400:inst9
7400:inst7
7400:inst3
7400:inst4
7400:inst2
}
# macro_sequence
# end
# entity
7486
# storage
db|adder.(2).cnf
db|adder.(2).cnf
# case_insensitive
# source_file
..|..|..|altera|90sp2|quartus|libraries|others|maxplus2|7486.bdf
66760dceba984b0dca8067dd21fcf
26
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
7486:inst
7486:inst6
7486:inst11
7486:inst16
7486:inst21
7486:inst26
7486:inst31
7486:inst36
7486:inst40
7486:inst5
7486:inst10
7486:inst15
7486:inst20
7486:inst25
7486:inst30
7486:inst35
}
# macro_sequence
# end
# complete

18
adder/db/adder.lpc.html Normal file
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<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
</TABLE>

二進制
adder/db/adder.lpc.rdb Normal file
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未顯示二進位檔案。

5
adder/db/adder.lpc.txt Normal file
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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

二進制
adder/db/adder.map.bpm Normal file
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未顯示二進位檔案。

二進制
adder/db/adder.map.cdb Normal file
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未顯示二進位檔案。

二進制
adder/db/adder.map.ecobp Normal file
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未顯示二進位檔案。

二進制
adder/db/adder.map.hdb Normal file
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未顯示二進位檔案。

10
adder/db/adder.map.kpt Normal file
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<kpt_db name="adder.map" kpt_version="1.1">
<key_points_set type="reference" hier_sep="/">
</key_points_set>
<key_points_set type="transition" hier_sep="|">
</key_points_set>
<key_points_set type="transformed" hier_sep="|">
</key_points_set>
<transformations_set hier_sep="|">
</transformations_set>
</kpt_db>

1
adder/db/adder.map.logdb Normal file
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v1

11
adder/db/adder.map.qmsg Normal file
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 07 08:49:21 2022 " "Info: Processing started: Mon Mar 07 08:49:21 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off adder -c adder " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adder -c adder" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adder.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 adder " "Info: Found entity 1: adder" { } { { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "adder " "Info: Elaborating entity \"adder\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7400 7400:inst38 " "Info: Elaborating entity \"7400\" for hierarchy \"7400:inst38\"" { } { { "adder.bdf" "inst38" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 184 432 496 224 "inst38" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "7400:inst38 " "Info: Elaborated megafunction instantiation \"7400:inst38\"" { } { { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 184 432 496 224 "inst38" "" } } } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7486 7486:inst " "Info: Elaborating entity \"7486\" for hierarchy \"7486:inst\"" { } { { "adder.bdf" "inst" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 2096 304 368 2136 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "7486:inst " "Info: Elaborated megafunction instantiation \"7486:inst\"" { } { { "adder.bdf" "" { Schematic "D:/projects/quartus/adder/adder.bdf" { { 2096 304 368 2136 "inst" "" } } } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "47 " "Info: Implemented 47 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "17 " "Info: Implemented 17 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Info: Implemented 9 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "21 " "Info: Implemented 21 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "248 " "Info: Peak virtual memory: 248 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 07 08:49:22 2022 " "Info: Processing ended: Mon Mar 07 08:49:22 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

二進制
adder/db/adder.map_bb.cdb Normal file
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未顯示二進位檔案。

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adder/db/adder.map_bb.hdb Normal file
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未顯示二進位檔案。

1
adder/db/adder.map_bb.logdb Normal file
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v1

二進制
adder/db/adder.pre_map.cdb Normal file
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未顯示二進位檔案。

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adder/db/adder.pre_map.hdb Normal file
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未顯示二進位檔案。

二進制
adder/db/adder.rtlv.hdb Normal file
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未顯示二進位檔案。

二進制
adder/db/adder.rtlv_sg.cdb Normal file
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未顯示二進位檔案。

二進制
adder/db/adder.rtlv_sg_swap.cdb Normal file
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未顯示二進位檔案。

二進制
adder/db/adder.sgdiff.cdb Normal file
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未顯示二進位檔案。

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adder/db/adder.sgdiff.hdb Normal file
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未顯示二進位檔案。

二進制
adder/db/adder.sld_design_entry.sci Normal file
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未顯示二進位檔案。

二進制
adder/db/adder.sld_design_entry_dsc.sci Normal file
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未顯示二進位檔案。

0
adder/db/adder.syn_hier_info Normal file
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6
adder/db/adder.tan.qmsg Normal file
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檔案差異因為一行或多行太長而無法顯示

二進制
adder/db/adder.tis_db_list.ddb Normal file
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未顯示二進位檔案。

11
adder/incremental_db/README Normal file
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This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.

二進制
adder/incremental_db/compiled_partitions/adder.root_partition.cmp.atm Normal file
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未顯示二進位檔案。

二進制
adder/incremental_db/compiled_partitions/adder.root_partition.cmp.dfp Normal file
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未顯示二進位檔案。

二進制
adder/incremental_db/compiled_partitions/adder.root_partition.cmp.hdbx Normal file
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未顯示二進位檔案。

10
adder/incremental_db/compiled_partitions/adder.root_partition.cmp.kpt Normal file
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<kpt_db name="root_partition" kpt_version="1.1">
<key_points_set type="reference" hier_sep="|">
</key_points_set>
<key_points_set type="transition" hier_sep="|">
</key_points_set>
<key_points_set type="transformed" hier_sep="|">
</key_points_set>
<transformations_set hier_sep="|">
</transformations_set>
</kpt_db>

1
adder/incremental_db/compiled_partitions/adder.root_partition.cmp.logdb Normal file
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v1

二進制
adder/incremental_db/compiled_partitions/adder.root_partition.cmp.rcf Normal file
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未顯示二進位檔案。

二進制
adder/incremental_db/compiled_partitions/adder.root_partition.map.atm Normal file
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未顯示二進位檔案。

二進制
adder/incremental_db/compiled_partitions/adder.root_partition.map.dpi Normal file
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未顯示二進位檔案。

二進制
adder/incremental_db/compiled_partitions/adder.root_partition.map.hdbx Normal file
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未顯示二進位檔案。

10
adder/incremental_db/compiled_partitions/adder.root_partition.map.kpt Normal file
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<kpt_db name="adder.map_bb" kpt_version="1.1">
<key_points_set type="reference" hier_sep="/">
</key_points_set>
<key_points_set type="transition" hier_sep="|">
</key_points_set>
<key_points_set type="transformed" hier_sep="|">
</key_points_set>
<transformations_set hier_sep="|">
</transformations_set>
</kpt_db>