set up project of start_circuit and copy it to ram project
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@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP2C8Q208C8
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set_global_assignment -name TOP_LEVEL_ENTITY microprogram_ram
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set_global_assignment -name TOP_LEVEL_ENTITY microprogram_ram
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:35:41 MARCH 17, 2022"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:35:41 MARCH 17, 2022"
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set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2"
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set_global_assignment -name LAST_QUARTUS_VERSION 8.1
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set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
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set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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451
microprogram_ram/start_circuit.bdf
Normal file
451
microprogram_ram/start_circuit.bdf
Normal file
@ -0,0 +1,451 @@
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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 1991-2009 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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applicable agreement for further details.
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*/
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|
(port
|
||||||
|
(pt 48 16)
|
||||||
|
(output)
|
||||||
|
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
|
||||||
|
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
|
||||||
|
(line (pt 39 16)(pt 48 16)(line_width 1))
|
||||||
|
)
|
||||||
|
(drawing
|
||||||
|
(line (pt 13 25)(pt 13 7)(line_width 1))
|
||||||
|
(line (pt 13 7)(pt 31 16)(line_width 1))
|
||||||
|
(line (pt 13 25)(pt 31 16)(line_width 1))
|
||||||
|
(circle (rect 31 12 39 20)(line_width 1))
|
||||||
|
)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 536 160)
|
||||||
|
(pt 536 144)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 504 184)
|
||||||
|
(pt 472 184)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 568 184)
|
||||||
|
(pt 576 184)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 624 96)
|
||||||
|
(pt 624 184)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 640 80)
|
||||||
|
(pt 440 80)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 472 184)
|
||||||
|
(pt 472 96)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 472 96)
|
||||||
|
(pt 624 96)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 624 96)
|
||||||
|
(pt 640 96)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 280 208)
|
||||||
|
(pt 280 200)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 344 184)
|
||||||
|
(pt 344 168)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 280 208)
|
||||||
|
(pt 312 208)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 504 200)
|
||||||
|
(pt 472 200)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 384 192)
|
||||||
|
(pt 408 192)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 376 208)
|
||||||
|
(pt 408 208)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 384 192)
|
||||||
|
(pt 384 136)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 280 136)
|
||||||
|
(pt 384 136)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 280 80)
|
||||||
|
(pt 392 80)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 312 224)
|
||||||
|
(pt 280 224)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 536 240)
|
||||||
|
(pt 536 288)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 536 144)
|
||||||
|
(pt 488 144)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 488 144)
|
||||||
|
(pt 488 288)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 344 264)
|
||||||
|
(pt 344 288)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 296 168)
|
||||||
|
(pt 296 288)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 344 168)
|
||||||
|
(pt 296 168)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 488 288)
|
||||||
|
(pt 536 288)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 280 288)
|
||||||
|
(pt 296 288)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 296 288)
|
||||||
|
(pt 344 288)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 344 288)
|
||||||
|
(pt 488 288)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 704 88)
|
||||||
|
(pt 736 88)
|
||||||
|
)
|
||||||
|
(junction (pt 624 96))
|
||||||
|
(junction (pt 488 288))
|
||||||
|
(junction (pt 344 288))
|
||||||
|
(junction (pt 296 288))
|
||||||
64
microprogram_ram/start_circuit.bsf
Normal file
64
microprogram_ram/start_circuit.bsf
Normal file
@ -0,0 +1,64 @@
|
|||||||
|
/*
|
||||||
|
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||||
|
editor if you plan to continue editing the block that represents it in
|
||||||
|
the Block Editor! File corruption is VERY likely to occur.
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
Copyright (C) 1991-2009 Altera Corporation
|
||||||
|
Your use of Altera Corporation's design tools, logic functions
|
||||||
|
and other software and tools, and its AMPP partner logic
|
||||||
|
functions, and any output files from any of the foregoing
|
||||||
|
(including device programming or simulation files), and any
|
||||||
|
associated documentation or information are expressly subject
|
||||||
|
to the terms and conditions of the Altera Program License
|
||||||
|
Subscription Agreement, Altera MegaCore Function License
|
||||||
|
Agreement, or other applicable license agreement, including,
|
||||||
|
without limitation, that your use is for the sole purpose of
|
||||||
|
programming logic devices manufactured by Altera and sold by
|
||||||
|
Altera or its authorized distributors. Please refer to the
|
||||||
|
applicable agreement for further details.
|
||||||
|
*/
|
||||||
|
(header "symbol" (version "1.1"))
|
||||||
|
(symbol
|
||||||
|
(rect 16 16 112 144)
|
||||||
|
(text "start_circuit" (rect 5 0 72 14)(font "Arial" (font_size 8)))
|
||||||
|
(text "inst" (rect 8 112 25 124)(font "Arial" ))
|
||||||
|
(port
|
||||||
|
(pt 0 32)
|
||||||
|
(input)
|
||||||
|
(text "HALT" (rect 0 0 31 14)(font "Arial" (font_size 8)))
|
||||||
|
(text "HALT" (rect 21 27 52 41)(font "Arial" (font_size 8)))
|
||||||
|
(line (pt 0 32)(pt 16 32)(line_width 1))
|
||||||
|
)
|
||||||
|
(port
|
||||||
|
(pt 0 48)
|
||||||
|
(input)
|
||||||
|
(text "CK_C" (rect 0 0 31 14)(font "Arial" (font_size 8)))
|
||||||
|
(text "CK_C" (rect 21 43 52 57)(font "Arial" (font_size 8)))
|
||||||
|
(line (pt 0 48)(pt 16 48)(line_width 1))
|
||||||
|
)
|
||||||
|
(port
|
||||||
|
(pt 0 64)
|
||||||
|
(input)
|
||||||
|
(text "CK" (rect 0 0 16 14)(font "Arial" (font_size 8)))
|
||||||
|
(text "CK" (rect 21 59 37 73)(font "Arial" (font_size 8)))
|
||||||
|
(line (pt 0 64)(pt 16 64)(line_width 1))
|
||||||
|
)
|
||||||
|
(port
|
||||||
|
(pt 0 80)
|
||||||
|
(input)
|
||||||
|
(text "CLR" (rect 0 0 23 14)(font "Arial" (font_size 8)))
|
||||||
|
(text "CLR" (rect 21 75 44 89)(font "Arial" (font_size 8)))
|
||||||
|
(line (pt 0 80)(pt 16 80)(line_width 1))
|
||||||
|
)
|
||||||
|
(port
|
||||||
|
(pt 96 32)
|
||||||
|
(output)
|
||||||
|
(text "CP" (rect 0 0 15 14)(font "Arial" (font_size 8)))
|
||||||
|
(text "CP" (rect 60 27 75 41)(font "Arial" (font_size 8)))
|
||||||
|
(line (pt 96 32)(pt 80 32)(line_width 1))
|
||||||
|
)
|
||||||
|
(drawing
|
||||||
|
(rectangle (rect 16 16 80 112)(line_width 1))
|
||||||
|
)
|
||||||
|
)
|
||||||
23
start_circuit/start_circuit.qpf
Normal file
23
start_circuit/start_circuit.qpf
Normal file
@ -0,0 +1,23 @@
|
|||||||
|
# Copyright (C) 1991-2008 Altera Corporation
|
||||||
|
# Your use of Altera Corporation's design tools, logic functions
|
||||||
|
# and other software and tools, and its AMPP partner logic
|
||||||
|
# functions, and any output files from any of the foregoing
|
||||||
|
# (including device programming or simulation files), and any
|
||||||
|
# associated documentation or information are expressly subject
|
||||||
|
# to the terms and conditions of the Altera Program License
|
||||||
|
# Subscription Agreement, Altera MegaCore Function License
|
||||||
|
# Agreement, or other applicable license agreement, including,
|
||||||
|
# without limitation, that your use is for the sole purpose of
|
||||||
|
# programming logic devices manufactured by Altera and sold by
|
||||||
|
# Altera or its authorized distributors. Please refer to the
|
||||||
|
# applicable agreement for further details.
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
QUARTUS_VERSION = "8.1"
|
||||||
|
DATE = "20:24:57 March 17, 2022"
|
||||||
|
|
||||||
|
|
||||||
|
# Revisions
|
||||||
|
|
||||||
|
PROJECT_REVISION = "start_circuit"
|
||||||
37
start_circuit/start_circuit.qsf
Normal file
37
start_circuit/start_circuit.qsf
Normal file
@ -0,0 +1,37 @@
|
|||||||
|
# Copyright (C) 1991-2008 Altera Corporation
|
||||||
|
# Your use of Altera Corporation's design tools, logic functions
|
||||||
|
# and other software and tools, and its AMPP partner logic
|
||||||
|
# functions, and any output files from any of the foregoing
|
||||||
|
# (including device programming or simulation files), and any
|
||||||
|
# associated documentation or information are expressly subject
|
||||||
|
# to the terms and conditions of the Altera Program License
|
||||||
|
# Subscription Agreement, Altera MegaCore Function License
|
||||||
|
# Agreement, or other applicable license agreement, including,
|
||||||
|
# without limitation, that your use is for the sole purpose of
|
||||||
|
# programming logic devices manufactured by Altera and sold by
|
||||||
|
# Altera or its authorized distributors. Please refer to the
|
||||||
|
# applicable agreement for further details.
|
||||||
|
|
||||||
|
|
||||||
|
# The default values for assignments are stored in the file
|
||||||
|
# start_circuit_assignment_defaults.qdf
|
||||||
|
# If this file doesn't exist, and for assignments not listed, see file
|
||||||
|
# assignment_defaults.qdf
|
||||||
|
|
||||||
|
# Altera recommends that you do not modify this file. This
|
||||||
|
# file is updated automatically by the Quartus II software
|
||||||
|
# and any changes you make may be lost or overwritten.
|
||||||
|
|
||||||
|
|
||||||
|
set_global_assignment -name FAMILY "Cyclone II"
|
||||||
|
set_global_assignment -name DEVICE EP2C8Q208C7
|
||||||
|
set_global_assignment -name TOP_LEVEL_ENTITY start_circuit
|
||||||
|
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
|
||||||
|
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:24:57 MARCH 17, 2022"
|
||||||
|
set_global_assignment -name LAST_QUARTUS_VERSION 8.1
|
||||||
|
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
|
||||||
|
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
|
||||||
|
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||||
|
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||||
|
set_global_assignment -name BDF_FILE start_circuit.bdf
|
||||||
|
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
|
||||||
載入中…
x
新增問題並參考
Block a user