quartus/shifter_8b/shifter_8b.tan.rpt

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Classic Timing Analyzer report for shifter_8b
Mon Mar 07 10:37:44 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Parallel Compilation
5. tpd
6. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 13.320 ns ; DM ; Y7 ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C8Q208C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Minimum Core Junction Temperature ; 0 ; ; ; ;
; Maximum Core Junction Temperature ; 85 ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; On ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
; Output I/O Timing Endpoint ; Near End ; ; ; ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; 1 processor ; 100.0% ;
; 2-4 processors ; 0.0% ;
+----------------------------+-------------+
+---------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A ; None ; 13.320 ns ; DM ; Y7 ;
; N/A ; None ; 13.225 ns ; DM ; Y4 ;
; N/A ; None ; 13.207 ns ; LM ; Y7 ;
; N/A ; None ; 13.153 ns ; LM ; Y0 ;
; N/A ; None ; 13.128 ns ; LM ; Y4 ;
; N/A ; None ; 13.029 ns ; A0 ; Y1 ;
; N/A ; None ; 13.020 ns ; DM ; Y1 ;
; N/A ; None ; 12.918 ns ; LM ; Y1 ;
; N/A ; None ; 12.906 ns ; A4 ; Y4 ;
; N/A ; None ; 12.900 ns ; DM ; Y2 ;
; N/A ; None ; 12.874 ns ; A0 ; OF ;
; N/A ; None ; 12.848 ns ; A0 ; Y0 ;
; N/A ; None ; 12.834 ns ; DM ; Y0 ;
; N/A ; None ; 12.817 ns ; L ; Y0 ;
; N/A ; None ; 12.816 ns ; LM ; Y6 ;
; N/A ; None ; 12.787 ns ; LM ; Y2 ;
; N/A ; None ; 12.752 ns ; LM ; Y5 ;
; N/A ; None ; 12.542 ns ; A7 ; Y7 ;
; N/A ; None ; 12.524 ns ; DM ; Y3 ;
; N/A ; None ; 12.450 ns ; LM ; OF ;
; N/A ; None ; 12.431 ns ; LM ; Y3 ;
; N/A ; None ; 12.272 ns ; A6 ; Y7 ;
; N/A ; None ; 12.211 ns ; A5 ; Y6 ;
; N/A ; None ; 12.184 ns ; A4 ; Y5 ;
; N/A ; None ; 12.155 ns ; A5 ; Y5 ;
; N/A ; None ; 12.007 ns ; DM ; Y6 ;
; N/A ; None ; 11.961 ns ; A5 ; Y4 ;
; N/A ; None ; 11.952 ns ; DM ; Y5 ;
; N/A ; None ; 11.780 ns ; A7 ; OF ;
; N/A ; None ; 11.520 ns ; A4 ; Y3 ;
; N/A ; None ; 11.436 ns ; A6 ; Y6 ;
; N/A ; None ; 11.309 ns ; R ; Y7 ;
; N/A ; None ; 11.123 ns ; A6 ; Y5 ;
; N/A ; None ; 11.097 ns ; A7 ; Y6 ;
; N/A ; None ; 8.432 ns ; A1 ; Y1 ;
; N/A ; None ; 8.391 ns ; A3 ; Y4 ;
; N/A ; None ; 8.283 ns ; A2 ; Y2 ;
; N/A ; None ; 8.057 ns ; A1 ; Y2 ;
; N/A ; None ; 7.922 ns ; A2 ; Y3 ;
; N/A ; None ; 7.852 ns ; A2 ; Y1 ;
; N/A ; None ; 7.752 ns ; RM ; OF ;
; N/A ; None ; 7.697 ns ; A3 ; Y3 ;
; N/A ; None ; 7.656 ns ; RM ; Y1 ;
; N/A ; None ; 7.645 ns ; RM ; Y0 ;
; N/A ; None ; 7.558 ns ; A1 ; Y0 ;
; N/A ; None ; 7.441 ns ; RM ; Y4 ;
; N/A ; None ; 7.348 ns ; RM ; Y3 ;
; N/A ; None ; 7.270 ns ; A3 ; Y2 ;
; N/A ; None ; 7.067 ns ; RM ; Y5 ;
; N/A ; None ; 7.062 ns ; RM ; Y6 ;
; N/A ; None ; 7.054 ns ; RM ; Y2 ;
; N/A ; None ; 5.826 ns ; RM ; Y7 ;
+-------+-------------------+-----------------+------+----+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Mon Mar 07 10:37:44 2022
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Info: Longest tpd from source pin "DM" to destination pin "Y7" is 13.320 ns
Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_35; Fanout = 8; PIN Node = 'DM'
Info: 2: + IC(6.057 ns) + CELL(0.650 ns) = 7.692 ns; Loc. = LCCOMB_X1_Y14_N20; Fanout = 1; COMB Node = 'triple_selector_8b:inst|inst31~0'
Info: 3: + IC(1.286 ns) + CELL(0.319 ns) = 9.297 ns; Loc. = LCCOMB_X1_Y9_N16; Fanout = 1; COMB Node = 'triple_selector_8b:inst|inst31'
Info: 4: + IC(0.927 ns) + CELL(3.096 ns) = 13.320 ns; Loc. = PIN_33; Fanout = 0; PIN Node = 'Y7'
Info: Total cell delay = 5.050 ns ( 37.91 % )
Info: Total interconnect delay = 8.270 ns ( 62.09 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 212 megabytes
Info: Processing ended: Mon Mar 07 10:37:44 2022
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00