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add data_selector 未设定 pins

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juzeon 2022-03-05 20:52:27 +08:00
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129
data_selector/data_selector.asm.rpt Normal file
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Assembler report for data_selector
Sat Mar 05 20:41:36 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: D:/projects/quartus/data_selector/data_selector.sof
6. Assembler Device Options: D:/projects/quartus/data_selector/data_selector.pof
7. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Sat Mar 05 20:41:36 2022 ;
; Revision Name ; data_selector ;
; Top-level Entity Name ; data_selector ;
; Family ; Cyclone II ;
; Device ; EP2C8Q208C8 ;
+-----------------------+---------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Assembler Settings ;
+-----------------------------------------------------------------------------+----------+---------------+
; Option ; Setting ; Default Value ;
+-----------------------------------------------------------------------------+----------+---------------+
; Use smart compilation ; Off ; Off ;
; Generate compressed bitstreams ; On ; On ;
; Compression mode ; Off ; Off ;
; Clock source for configuration device ; Internal ; Internal ;
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
; Divide clock frequency by ; 1 ; 1 ;
; Auto user code ; Off ; Off ;
; Use configuration device ; On ; On ;
; Configuration device ; Auto ; Auto ;
; Configuration device auto user code ; Off ; Off ;
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
; Hexadecimal Output File start address ; 0 ; 0 ;
; Hexadecimal Output File count direction ; Up ; Up ;
; Release clears before tri-states ; Off ; Off ;
; Auto-restart configuration after error ; On ; On ;
; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ;
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
+-----------------------------------------------------------------------------+----------+---------------+
+-----------------------------------------------------+
; Assembler Generated Files ;
+-----------------------------------------------------+
; File Name ;
+-----------------------------------------------------+
; D:/projects/quartus/data_selector/data_selector.sof ;
; D:/projects/quartus/data_selector/data_selector.pof ;
+-----------------------------------------------------+
+-------------------------------------------------------------------------------+
; Assembler Device Options: D:/projects/quartus/data_selector/data_selector.sof ;
+----------------+--------------------------------------------------------------+
; Option ; Setting ;
+----------------+--------------------------------------------------------------+
; Device ; EP2C8Q208C8 ;
; JTAG usercode ; 0xFFFFFFFF ;
; Checksum ; 0x000C1D58 ;
+----------------+--------------------------------------------------------------+
+-------------------------------------------------------------------------------+
; Assembler Device Options: D:/projects/quartus/data_selector/data_selector.pof ;
+--------------------+----------------------------------------------------------+
; Option ; Setting ;
+--------------------+----------------------------------------------------------+
; Device ; EPCS4 ;
; JTAG usercode ; 0x00000000 ;
; Checksum ; 0x06EFE46F ;
; Compression Ratio ; 3 ;
+--------------------+----------------------------------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Sat Mar 05 20:41:35 2022
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off data_selector -c data_selector
Info: Writing out detailed assembly data for power analysis
Info: Assembler is generating device programming files
Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 241 megabytes
Info: Processing ended: Sat Mar 05 20:41:36 2022
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:00

1819
data_selector/data_selector.bdf Normal file
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data_selector/data_selector.bsf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 112 368)
(text "data_selector" (rect 5 0 82 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 336 25 348)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "a0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "a0" (rect 21 27 35 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "a1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "a1" (rect 21 43 35 57)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "a2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "a2" (rect 21 59 35 73)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 0 80)
(input)
(text "a3" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "a3" (rect 21 75 35 89)(font "Arial" (font_size 8)))
(line (pt 0 80)(pt 16 80)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "a4" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "a4" (rect 21 91 35 105)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 16 96)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "a5" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "a5" (rect 21 107 35 121)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 16 112)(line_width 1))
)
(port
(pt 0 128)
(input)
(text "a6" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "a6" (rect 21 123 35 137)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 16 128)(line_width 1))
)
(port
(pt 0 144)
(input)
(text "a7" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "a7" (rect 21 139 35 153)(font "Arial" (font_size 8)))
(line (pt 0 144)(pt 16 144)(line_width 1))
)
(port
(pt 0 160)
(input)
(text "b0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "b0" (rect 21 155 35 169)(font "Arial" (font_size 8)))
(line (pt 0 160)(pt 16 160)(line_width 1))
)
(port
(pt 0 176)
(input)
(text "b1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "b1" (rect 21 171 35 185)(font "Arial" (font_size 8)))
(line (pt 0 176)(pt 16 176)(line_width 1))
)
(port
(pt 0 192)
(input)
(text "b2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "b2" (rect 21 187 35 201)(font "Arial" (font_size 8)))
(line (pt 0 192)(pt 16 192)(line_width 1))
)
(port
(pt 0 208)
(input)
(text "b3" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "b3" (rect 21 203 35 217)(font "Arial" (font_size 8)))
(line (pt 0 208)(pt 16 208)(line_width 1))
)
(port
(pt 0 224)
(input)
(text "b4" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "b4" (rect 21 219 35 233)(font "Arial" (font_size 8)))
(line (pt 0 224)(pt 16 224)(line_width 1))
)
(port
(pt 0 240)
(input)
(text "b5" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "b5" (rect 21 235 35 249)(font "Arial" (font_size 8)))
(line (pt 0 240)(pt 16 240)(line_width 1))
)
(port
(pt 0 256)
(input)
(text "b6" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "b6" (rect 21 251 35 265)(font "Arial" (font_size 8)))
(line (pt 0 256)(pt 16 256)(line_width 1))
)
(port
(pt 0 272)
(input)
(text "b7" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "b7" (rect 21 267 35 281)(font "Arial" (font_size 8)))
(line (pt 0 272)(pt 16 272)(line_width 1))
)
(port
(pt 0 288)
(input)
(text "AY" (rect 0 0 18 14)(font "Arial" (font_size 8)))
(text "AY" (rect 21 283 39 297)(font "Arial" (font_size 8)))
(line (pt 0 288)(pt 16 288)(line_width 1))
)
(port
(pt 0 304)
(input)
(text "BY" (rect 0 0 17 14)(font "Arial" (font_size 8)))
(text "BY" (rect 21 299 38 313)(font "Arial" (font_size 8)))
(line (pt 0 304)(pt 16 304)(line_width 1))
)
(port
(pt 96 32)
(output)
(text "Y0" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "Y0" (rect 59 27 75 41)(font "Arial" (font_size 8)))
(line (pt 96 32)(pt 80 32)(line_width 1))
)
(port
(pt 96 48)
(output)
(text "Y1" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "Y1" (rect 59 43 75 57)(font "Arial" (font_size 8)))
(line (pt 96 48)(pt 80 48)(line_width 1))
)
(port
(pt 96 64)
(output)
(text "Y2" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "Y2" (rect 59 59 75 73)(font "Arial" (font_size 8)))
(line (pt 96 64)(pt 80 64)(line_width 1))
)
(port
(pt 96 80)
(output)
(text "Y3" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "Y3" (rect 59 75 75 89)(font "Arial" (font_size 8)))
(line (pt 96 80)(pt 80 80)(line_width 1))
)
(port
(pt 96 96)
(output)
(text "Y4" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "Y4" (rect 59 91 75 105)(font "Arial" (font_size 8)))
(line (pt 96 96)(pt 80 96)(line_width 1))
)
(port
(pt 96 112)
(output)
(text "Y5" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "Y5" (rect 59 107 75 121)(font "Arial" (font_size 8)))
(line (pt 96 112)(pt 80 112)(line_width 1))
)
(port
(pt 96 128)
(output)
(text "Y6" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "Y6" (rect 59 123 75 137)(font "Arial" (font_size 8)))
(line (pt 96 128)(pt 80 128)(line_width 1))
)
(port
(pt 96 144)
(output)
(text "Y7" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "Y7" (rect 59 139 75 153)(font "Arial" (font_size 8)))
(line (pt 96 144)(pt 80 144)(line_width 1))
)
(drawing
(rectangle (rect 16 16 80 336)(line_width 1))
)
)

1
data_selector/data_selector.done Normal file
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Sat Mar 05 20:41:37 2022

12
data_selector/data_selector.dpf Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<pin_planner>
<pin_info>
</pin_info>
<buses>
</buses>
<group_file_association>
</group_file_association>
<pin_planner_file_specifies>
</pin_planner_file_specifies>
</pin_planner>

1006
data_selector/data_selector.fit.rpt Normal file
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6
data_selector/data_selector.fit.smsg Normal file
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Extra Info: Performing register packing on registers with non-logic cell location assignments
Extra Info: Completed register packing on registers with non-logic cell location assignments
Extra Info: Started Fast Input/Output/OE register processing
Extra Info: Finished Fast Input/Output/OE register processing
Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks

16
data_selector/data_selector.fit.summary Normal file
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Fitter Status : Successful - Sat Mar 05 20:41:34 2022
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : data_selector
Top-level Entity Name : data_selector
Family : Cyclone II
Device : EP2C8Q208C8
Timing Models : Final
Total logic elements : 8 / 8,256 ( < 1 % )
Total combinational functions : 8 / 8,256 ( < 1 % )
Dedicated logic registers : 0 / 8,256 ( 0 % )
Total registers : 0
Total pins : 26 / 138 ( 19 % )
Total virtual pins : 0
Total memory bits : 0 / 165,888 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )

120
data_selector/data_selector.flow.rpt Normal file
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Flow report for data_selector
Sat Mar 05 20:41:36 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+----------------------------------------------+
; Flow Status ; Successful - Sat Mar 05 20:41:36 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; data_selector ;
; Top-level Entity Name ; data_selector ;
; Family ; Cyclone II ;
; Device ; EP2C8Q208C8 ;
; Timing Models ; Final ;
; Met timing requirements ; Yes ;
; Total logic elements ; 8 / 8,256 ( < 1 % ) ;
; Total combinational functions ; 8 / 8,256 ( < 1 % ) ;
; Dedicated logic registers ; 0 / 8,256 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 26 / 138 ( 19 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 165,888 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
; Total PLLs ; 0 / 2 ( 0 % ) ;
+------------------------------------+----------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 03/05/2022 20:41:32 ;
; Main task ; Compilation ;
; Revision Name ; data_selector ;
+-------------------+---------------------+
+---------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+------------------------------------+---------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+------------------------------------+---------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 220283517943889.164648409201276 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
+------------------------------------+---------------------------------+---------------+-------------+----------------+
+-----------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 245 MB ; 00:00:00 ;
; Fitter ; 00:00:01 ; 1.0 ; 306 MB ; 00:00:01 ;
; Assembler ; 00:00:01 ; 1.0 ; 241 MB ; 00:00:00 ;
; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 198 MB ; 00:00:00 ;
; Total ; 00:00:02 ; -- ; -- ; 00:00:01 ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+------------------------------------------------------------------------------------------+
; Flow OS Summary ;
+-------------------------+------------------+---------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+-------------------------+------------------+---------------+------------+----------------+
; Analysis & Synthesis ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
; Fitter ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
; Assembler ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
; Classic Timing Analyzer ; Polyphony ; Windows Vista ; 6.2 ; x86_64 ;
+-------------------------+------------------+---------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off data_selector -c data_selector
quartus_fit --read_settings_files=off --write_settings_files=off data_selector -c data_selector
quartus_asm --read_settings_files=off --write_settings_files=off data_selector -c data_selector
quartus_tan --read_settings_files=off --write_settings_files=off data_selector -c data_selector --timing_analysis_only

218
data_selector/data_selector.map.rpt Normal file
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Analysis & Synthesis report for data_selector
Sat Mar 05 20:41:32 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. General Register Statistics
8. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sat Mar 05 20:41:32 2022 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; data_selector ;
; Top-level Entity Name ; data_selector ;
; Family ; Cyclone II ;
; Total logic elements ; 8 ;
; Total combinational functions ; 8 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 26 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
+------------------------------------+----------------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------+--------------------+--------------------+
; Device ; EP2C8Q208C8 ; ;
; Top-level entity name ; data_selector ; data_selector ;
; Family name ; Cyclone II ; Stratix II ;
; Use Generated Physical Constraints File ; Off ; ;
; Use smart compilation ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; Off ; Off ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
+--------------------------------------------------------------+--------------------+--------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------+
; data_selector.bdf ; yes ; User Block Diagram/Schematic File ; D:/projects/quartus/data_selector/data_selector.bdf ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------+
+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements ; 8 ;
; ; ;
; Total combinational functions ; 8 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 8 ;
; -- 3 input functions ; 0 ;
; -- <=2 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 8 ;
; -- arithmetic mode ; 0 ;
; ; ;
; Total registers ; 0 ;
; -- Dedicated logic registers ; 0 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 26 ;
; Maximum fan-out node ; AY ;
; Maximum fan-out ; 8 ;
; Total fan-out ; 40 ;
; Average fan-out ; 1.18 ;
+---------------------------------------------+-------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |data_selector ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 26 ; 0 ; |data_selector ; work ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Sat Mar 05 20:41:32 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off data_selector -c data_selector
Info: Found 1 design units, including 1 entities, in source file data_selector.bdf
Info: Found entity 1: data_selector
Info: Elaborating entity "data_selector" for the top level hierarchy
Info: Implemented 34 device resources after synthesis - the final resource count might be different
Info: Implemented 18 input pins
Info: Implemented 8 output pins
Info: Implemented 8 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 248 megabytes
Info: Processing ended: Sat Mar 05 20:41:32 2022
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00

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Analysis & Synthesis Status : Successful - Sat Mar 05 20:41:32 2022
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : data_selector
Top-level Entity Name : data_selector
Family : Cyclone II
Total logic elements : 8
Total combinational functions : 8
Dedicated logic registers : 0
Total registers : 0
Total pins : 26
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0

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-- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
-- Bank 2: 3.3V
-- Bank 3: 3.3V
-- Bank 4: 3.3V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17),
-- connect each pin marked GND* either individually through a 10k Ohm resistor
-- to GND or tie all pins together and connect through a single 10k Ohm resistor
-- to GND.
-- For non-transceiver I/O banks, connect each pin marked GND* directly to GND
-- or leave it unconnected.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
CHIP "data_selector" ASSIGNED TO AN: EP2C8Q208C8
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVTTL : : 1 : N
~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVTTL : : 1 : N
a7 : 3 : input : 3.3-V LVTTL : : 1 : N
RESERVED_INPUT : 4 : : : : 1 :
RESERVED_INPUT : 5 : : : : 1 :
RESERVED_INPUT : 6 : : : : 1 :
VCCIO1 : 7 : power : : 3.3V : 1 :
RESERVED_INPUT : 8 : : : : 1 :
GND : 9 : gnd : : : :
Y4 : 10 : output : 3.3-V LVTTL : : 1 : N
RESERVED_INPUT : 11 : : : : 1 :
a4 : 12 : input : 3.3-V LVTTL : : 1 : N
RESERVED_INPUT : 13 : : : : 1 :
Y2 : 14 : output : 3.3-V LVTTL : : 1 : N
Y3 : 15 : output : 3.3-V LVTTL : : 1 : N
TDO : 16 : output : : : 1 :
TMS : 17 : input : : : 1 :
TCK : 18 : input : : : 1 :
TDI : 19 : input : : : 1 :
DATA0 : 20 : input : : : 1 :
DCLK : 21 : : : : 1 :
nCE : 22 : : : : 1 :
b1 : 23 : input : 3.3-V LVTTL : : 1 : N
a2 : 24 : input : 3.3-V LVTTL : : 1 : N
GND : 25 : gnd : : : :
nCONFIG : 26 : : : : 1 :
b2 : 27 : input : 3.3-V LVTTL : : 1 : N
a3 : 28 : input : 3.3-V LVTTL : : 1 : N
VCCIO1 : 29 : power : : 3.3V : 1 :
Y6 : 30 : output : 3.3-V LVTTL : : 1 : N
a5 : 31 : input : 3.3-V LVTTL : : 1 : N
VCCINT : 32 : power : : 1.2V : :
b7 : 33 : input : 3.3-V LVTTL : : 1 : N
a6 : 34 : input : 3.3-V LVTTL : : 1 : N
Y1 : 35 : output : 3.3-V LVTTL : : 1 : N
GND : 36 : gnd : : : :
a1 : 37 : input : 3.3-V LVTTL : : 1 : N
GND : 38 : gnd : : : :
a0 : 39 : input : 3.3-V LVTTL : : 1 : N
b0 : 40 : input : 3.3-V LVTTL : : 1 : N
b4 : 41 : input : 3.3-V LVTTL : : 1 : N
VCCIO1 : 42 : power : : 3.3V : 1 :
RESERVED_INPUT : 43 : : : : 1 :
BY : 44 : input : 3.3-V LVTTL : : 1 : N
b5 : 45 : input : 3.3-V LVTTL : : 1 : N
RESERVED_INPUT : 46 : : : : 1 :
RESERVED_INPUT : 47 : : : : 1 :
Y7 : 48 : output : 3.3-V LVTTL : : 1 : N
GND : 49 : gnd : : : :
GND_PLL1 : 50 : gnd : : : :
VCCD_PLL1 : 51 : power : : 1.2V : :
GND_PLL1 : 52 : gnd : : : :
VCCA_PLL1 : 53 : power : : 1.2V : :
GNDA_PLL1 : 54 : gnd : : : :
GND : 55 : gnd : : : :
AY : 56 : input : 3.3-V LVTTL : : 4 : N
b6 : 57 : input : 3.3-V LVTTL : : 4 : N
Y0 : 58 : output : 3.3-V LVTTL : : 4 : N
b3 : 59 : input : 3.3-V LVTTL : : 4 : N
RESERVED_INPUT : 60 : : : : 4 :
RESERVED_INPUT : 61 : : : : 4 :
VCCIO4 : 62 : power : : 3.3V : 4 :
RESERVED_INPUT : 63 : : : : 4 :
RESERVED_INPUT : 64 : : : : 4 :
GND : 65 : gnd : : : :
VCCINT : 66 : power : : 1.2V : :
RESERVED_INPUT : 67 : : : : 4 :
RESERVED_INPUT : 68 : : : : 4 :
RESERVED_INPUT : 69 : : : : 4 :
RESERVED_INPUT : 70 : : : : 4 :
VCCIO4 : 71 : power : : 3.3V : 4 :
RESERVED_INPUT : 72 : : : : 4 :
GND : 73 : gnd : : : :
RESERVED_INPUT : 74 : : : : 4 :
RESERVED_INPUT : 75 : : : : 4 :
RESERVED_INPUT : 76 : : : : 4 :
RESERVED_INPUT : 77 : : : : 4 :
GND : 78 : gnd : : : :
VCCINT : 79 : power : : 1.2V : :
RESERVED_INPUT : 80 : : : : 4 :
RESERVED_INPUT : 81 : : : : 4 :
RESERVED_INPUT : 82 : : : : 4 :
VCCIO4 : 83 : power : : 3.3V : 4 :
RESERVED_INPUT : 84 : : : : 4 :
GND : 85 : gnd : : : :
RESERVED_INPUT : 86 : : : : 4 :
RESERVED_INPUT : 87 : : : : 4 :
RESERVED_INPUT : 88 : : : : 4 :
RESERVED_INPUT : 89 : : : : 4 :
RESERVED_INPUT : 90 : : : : 4 :
VCCIO4 : 91 : power : : 3.3V : 4 :
RESERVED_INPUT : 92 : : : : 4 :
GND : 93 : gnd : : : :
RESERVED_INPUT : 94 : : : : 4 :
RESERVED_INPUT : 95 : : : : 4 :
RESERVED_INPUT : 96 : : : : 4 :
RESERVED_INPUT : 97 : : : : 4 :
VCCIO4 : 98 : power : : 3.3V : 4 :
RESERVED_INPUT : 99 : : : : 4 :
GND : 100 : gnd : : : :
RESERVED_INPUT : 101 : : : : 4 :
RESERVED_INPUT : 102 : : : : 4 :
RESERVED_INPUT : 103 : : : : 4 :
RESERVED_INPUT : 104 : : : : 4 :
RESERVED_INPUT : 105 : : : : 3 :
RESERVED_INPUT : 106 : : : : 3 :
RESERVED_INPUT : 107 : : : : 3 :
~LVDS54p/nCEO~ : 108 : output : 3.3-V LVTTL : : 3 : N
VCCIO3 : 109 : power : : 3.3V : 3 :
RESERVED_INPUT : 110 : : : : 3 :
GND : 111 : gnd : : : :
RESERVED_INPUT : 112 : : : : 3 :
RESERVED_INPUT : 113 : : : : 3 :
RESERVED_INPUT : 114 : : : : 3 :
RESERVED_INPUT : 115 : : : : 3 :
RESERVED_INPUT : 116 : : : : 3 :
RESERVED_INPUT : 117 : : : : 3 :
RESERVED_INPUT : 118 : : : : 3 :
GND : 119 : gnd : : : :
VCCINT : 120 : power : : 1.2V : :
nSTATUS : 121 : : : : 3 :
VCCIO3 : 122 : power : : 3.3V : 3 :
CONF_DONE : 123 : : : : 3 :
GND : 124 : gnd : : : :
MSEL1 : 125 : : : : 3 :
MSEL0 : 126 : : : : 3 :
RESERVED_INPUT : 127 : : : : 3 :
RESERVED_INPUT : 128 : : : : 3 :
GND+ : 129 : : : : 3 :
GND+ : 130 : : : : 3 :
GND+ : 131 : : : : 3 :
GND+ : 132 : : : : 3 :
RESERVED_INPUT : 133 : : : : 3 :
RESERVED_INPUT : 134 : : : : 3 :
RESERVED_INPUT : 135 : : : : 3 :
VCCIO3 : 136 : power : : 3.3V : 3 :
RESERVED_INPUT : 137 : : : : 3 :
RESERVED_INPUT : 138 : : : : 3 :
RESERVED_INPUT : 139 : : : : 3 :
GND : 140 : gnd : : : :
RESERVED_INPUT : 141 : : : : 3 :
RESERVED_INPUT : 142 : : : : 3 :
RESERVED_INPUT : 143 : : : : 3 :
RESERVED_INPUT : 144 : : : : 3 :
RESERVED_INPUT : 145 : : : : 3 :
RESERVED_INPUT : 146 : : : : 3 :
RESERVED_INPUT : 147 : : : : 3 :
VCCIO3 : 148 : power : : 3.3V : 3 :
RESERVED_INPUT : 149 : : : : 3 :
RESERVED_INPUT : 150 : : : : 3 :
RESERVED_INPUT : 151 : : : : 3 :
RESERVED_INPUT : 152 : : : : 3 :
GND : 153 : gnd : : : :
GND_PLL2 : 154 : gnd : : : :
VCCD_PLL2 : 155 : power : : 1.2V : :
GND_PLL2 : 156 : gnd : : : :
VCCA_PLL2 : 157 : power : : 1.2V : :
GNDA_PLL2 : 158 : gnd : : : :
GND : 159 : gnd : : : :
RESERVED_INPUT : 160 : : : : 2 :
RESERVED_INPUT : 161 : : : : 2 :
RESERVED_INPUT : 162 : : : : 2 :
RESERVED_INPUT : 163 : : : : 2 :
RESERVED_INPUT : 164 : : : : 2 :
RESERVED_INPUT : 165 : : : : 2 :
VCCIO2 : 166 : power : : 3.3V : 2 :
GND : 167 : gnd : : : :
RESERVED_INPUT : 168 : : : : 2 :
RESERVED_INPUT : 169 : : : : 2 :
RESERVED_INPUT : 170 : : : : 2 :
RESERVED_INPUT : 171 : : : : 2 :
VCCIO2 : 172 : power : : 3.3V : 2 :
RESERVED_INPUT : 173 : : : : 2 :
GND : 174 : gnd : : : :
RESERVED_INPUT : 175 : : : : 2 :
RESERVED_INPUT : 176 : : : : 2 :
GND : 177 : gnd : : : :
VCCINT : 178 : power : : 1.2V : :
RESERVED_INPUT : 179 : : : : 2 :
RESERVED_INPUT : 180 : : : : 2 :
RESERVED_INPUT : 181 : : : : 2 :
RESERVED_INPUT : 182 : : : : 2 :
VCCIO2 : 183 : power : : 3.3V : 2 :
GND : 184 : gnd : : : :
RESERVED_INPUT : 185 : : : : 2 :
GND : 186 : gnd : : : :
RESERVED_INPUT : 187 : : : : 2 :
RESERVED_INPUT : 188 : : : : 2 :
RESERVED_INPUT : 189 : : : : 2 :
VCCINT : 190 : power : : 1.2V : :
RESERVED_INPUT : 191 : : : : 2 :
RESERVED_INPUT : 192 : : : : 2 :
RESERVED_INPUT : 193 : : : : 2 :
VCCIO2 : 194 : power : : 3.3V : 2 :
RESERVED_INPUT : 195 : : : : 2 :
GND : 196 : gnd : : : :
RESERVED_INPUT : 197 : : : : 2 :
RESERVED_INPUT : 198 : : : : 2 :
RESERVED_INPUT : 199 : : : : 2 :
RESERVED_INPUT : 200 : : : : 2 :
RESERVED_INPUT : 201 : : : : 2 :
VCCIO2 : 202 : power : : 3.3V : 2 :
RESERVED_INPUT : 203 : : : : 2 :
GND : 204 : gnd : : : :
RESERVED_INPUT : 205 : : : : 2 :
RESERVED_INPUT : 206 : : : : 2 :
RESERVED_INPUT : 207 : : : : 2 :
Y5 : 208 : output : 3.3-V LVTTL : : 2 : N

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 19:48:38 March 05, 2022
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "9.0"
DATE = "19:48:38 March 05, 2022"
# Revisions
PROJECT_REVISION = "data_selector"

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 19:48:38 March 05, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# data_selector_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C8Q208C8
set_global_assignment -name TOP_LEVEL_ENTITY data_selector
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:48:38 MARCH 05, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name BDF_FILE data_selector.bdf
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name MISC_FILE "D:/projects/quartus/data_selector/data_selector.dpf"

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[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames

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Classic Timing Analyzer report for data_selector
Sat Mar 05 20:41:36 2022
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Parallel Compilation
5. tpd
6. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 12.694 ns ; b5 ; Y5 ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C8Q208C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Minimum Core Junction Temperature ; 0 ; ; ; ;
; Maximum Core Junction Temperature ; 85 ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; On ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
; Output I/O Timing Endpoint ; Near End ; ; ; ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; 1 processor ; 100.0% ;
; 2-4 processors ; 0.0% ;
+----------------------------+-------------+
+---------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A ; None ; 12.694 ns ; b5 ; Y5 ;
; N/A ; None ; 12.565 ns ; BY ; Y7 ;
; N/A ; None ; 12.553 ns ; BY ; Y0 ;
; N/A ; None ; 12.543 ns ; a7 ; Y7 ;
; N/A ; None ; 12.522 ns ; AY ; Y0 ;
; N/A ; None ; 12.477 ns ; BY ; Y5 ;
; N/A ; None ; 12.469 ns ; a4 ; Y4 ;
; N/A ; None ; 12.451 ns ; AY ; Y5 ;
; N/A ; None ; 12.396 ns ; b3 ; Y3 ;
; N/A ; None ; 12.360 ns ; a0 ; Y0 ;
; N/A ; None ; 12.298 ns ; b0 ; Y0 ;
; N/A ; None ; 12.293 ns ; AY ; Y7 ;
; N/A ; None ; 12.239 ns ; a5 ; Y5 ;
; N/A ; None ; 12.214 ns ; b4 ; Y4 ;
; N/A ; None ; 12.099 ns ; AY ; Y1 ;
; N/A ; None ; 12.083 ns ; b7 ; Y7 ;
; N/A ; None ; 12.036 ns ; BY ; Y2 ;
; N/A ; None ; 12.035 ns ; BY ; Y4 ;
; N/A ; None ; 12.030 ns ; BY ; Y3 ;
; N/A ; None ; 12.014 ns ; AY ; Y4 ;
; N/A ; None ; 12.010 ns ; AY ; Y2 ;
; N/A ; None ; 11.998 ns ; AY ; Y3 ;
; N/A ; None ; 11.941 ns ; b6 ; Y6 ;
; N/A ; None ; 11.823 ns ; a1 ; Y1 ;
; N/A ; None ; 11.701 ns ; BY ; Y1 ;
; N/A ; None ; 11.697 ns ; BY ; Y6 ;
; N/A ; None ; 11.670 ns ; AY ; Y6 ;
; N/A ; None ; 11.480 ns ; a6 ; Y6 ;
; N/A ; None ; 6.818 ns ; a3 ; Y3 ;
; N/A ; None ; 6.817 ns ; b2 ; Y2 ;
; N/A ; None ; 6.775 ns ; a2 ; Y2 ;
; N/A ; None ; 6.079 ns ; b1 ; Y1 ;
+-------+-------------------+-----------------+------+----+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Sat Mar 05 20:41:36 2022
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off data_selector -c data_selector --timing_analysis_only
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Info: Longest tpd from source pin "b5" to destination pin "Y5" is 12.694 ns
Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_45; Fanout = 1; PIN Node = 'b5'
Info: 2: + IC(6.147 ns) + CELL(0.624 ns) = 7.766 ns; Loc. = LCCOMB_X1_Y9_N26; Fanout = 1; COMB Node = 'inst6'
Info: 3: + IC(1.642 ns) + CELL(3.286 ns) = 12.694 ns; Loc. = PIN_208; Fanout = 0; PIN Node = 'Y5'
Info: Total cell delay = 4.905 ns ( 38.64 % )
Info: Total interconnect delay = 7.789 ns ( 61.36 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 212 megabytes
Info: Processing ended: Sat Mar 05 20:41:36 2022
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00

26
data_selector/data_selector.tan.summary Normal file
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--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------
Type : Worst-case tpd
Slack : N/A
Required Time : None
Actual Time : 12.694 ns
From : b5
To : Y5
From Clock : --
To Clock : --
Failed Paths : 0
Type : Total number of failed paths
Slack :
Required Time :
Actual Time :
From :
To :
From Clock :
To Clock :
Failed Paths : 0
--------------------------------------------------------------------------------------

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data_selector/db/data_selector.(0).cnf.cdb Normal file
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data_selector/db/data_selector.(0).cnf.hdb Normal file
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data_selector/db/data_selector.asm.qmsg Normal file
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sat Mar 05 20:41:35 2022 " "Info: Processing started: Sat Mar 05 20:41:35 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off data_selector -c data_selector " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off data_selector -c data_selector" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
{ "Info" "IPGMIO_CONDONE_ERROR_CHECKS_DISABLED" "" "Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled" { } { } 0 0 "The Active Serial/Parallel mode CONF_DONE pin error check is disabled" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "241 " "Info: Peak virtual memory: 241 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sat Mar 05 20:41:36 2022 " "Info: Processing ended: Sat Mar 05 20:41:36 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

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data_selector/db/data_selector.asm_labs.ddb Normal file
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data_selector/db/data_selector.cbx.xml Normal file
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<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="data_selector">
</PROJECT>
</LOG_ROOT>

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data_selector/db/data_selector.cmp.bpm Normal file
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data_selector/db/data_selector.cmp.ecobp Normal file
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data_selector/db/data_selector.cmp.kpt Normal file
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<kpt_db name="data_selector.cmp" kpt_version="1.1">
<key_points_set type="reference" hier_sep="|">
</key_points_set>
<key_points_set type="transition" hier_sep="|">
</key_points_set>
<key_points_set type="transformed" hier_sep="|">
</key_points_set>
<transformations_set hier_sep="|">
</transformations_set>
</kpt_db>

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v1

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data_selector/db/data_selector.cmp_merge.kpt Normal file
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<kpt_db name="data_selector.cmp_merge" kpt_version="1.1">
<key_points_set type="reference" hier_sep="|">
</key_points_set>
<key_points_set type="transition" hier_sep="|">
</key_points_set>
<key_points_set type="transformed" hier_sep="|">
</key_points_set>
<transformations_set hier_sep="|">
</transformations_set>
</kpt_db>

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data_selector/db/data_selector.db_info Normal file
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Quartus_Version = Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Version_Index = 167832322
Creation_Time = Sat Mar 05 19:48:38 2022

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data_selector/db/data_selector.eco.cdb Normal file
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data_selector/db/data_selector.fit.qmsg Normal file
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data_selector/db/data_selector.hier_info Normal file
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|data_selector
Y0 <= inst1.DB_MAX_OUTPUT_PORT_TYPE
b0 => inst25.IN0
BY => inst25.IN1
BY => inst26.IN1
BY => inst27.IN1
BY => inst28.IN1
BY => inst29.IN1
BY => inst30.IN1
BY => inst31.IN1
BY => inst32.IN1
a0 => inst24.IN0
AY => inst24.IN1
AY => inst23.IN1
AY => inst22.IN1
AY => inst21.IN1
AY => inst.IN1
AY => inst18.IN1
AY => inst19.IN1
AY => inst20.IN1
Y1 <= inst2.DB_MAX_OUTPUT_PORT_TYPE
b1 => inst26.IN0
a1 => inst23.IN0
Y2 <= inst3.DB_MAX_OUTPUT_PORT_TYPE
b2 => inst27.IN0
a2 => inst22.IN0
Y3 <= inst4.DB_MAX_OUTPUT_PORT_TYPE
b3 => inst28.IN0
a3 => inst21.IN0
Y4 <= inst5.DB_MAX_OUTPUT_PORT_TYPE
b4 => inst29.IN0
a4 => inst.IN0
Y5 <= inst6.DB_MAX_OUTPUT_PORT_TYPE
b5 => inst30.IN0
a5 => inst18.IN0
Y6 <= inst7.DB_MAX_OUTPUT_PORT_TYPE
b6 => inst31.IN0
a6 => inst19.IN0
Y7 <= inst8.DB_MAX_OUTPUT_PORT_TYPE
b7 => inst32.IN0
a7 => inst20.IN0

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data_selector/db/data_selector.hif Normal file
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Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
11
936
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
data_selector
# storage
db|data_selector.(0).cnf
db|data_selector.(0).cnf
# case_insensitive
# source_file
data_selector.bdf
c85a509528fd3f5e5f3854c4318833a1
26
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
|
}
# macro_sequence
# end
# complete

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data_selector/db/data_selector.lpc.html Normal file
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<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
</TABLE>

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data_selector/db/data_selector.lpc.rdb Normal file
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data_selector/db/data_selector.lpc.txt Normal file
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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

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data_selector/db/data_selector.map.bpm Normal file
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data_selector/db/data_selector.map.kpt Normal file
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<kpt_db name="data_selector.map" kpt_version="1.1">
<key_points_set type="reference" hier_sep="/">
</key_points_set>
<key_points_set type="transition" hier_sep="|">
</key_points_set>
<key_points_set type="transformed" hier_sep="|">
</key_points_set>
<transformations_set hier_sep="|">
</transformations_set>
</kpt_db>

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data_selector/db/data_selector.map.logdb Normal file
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v1

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data_selector/db/data_selector.map.qmsg Normal file
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sat Mar 05 20:41:32 2022 " "Info: Processing started: Sat Mar 05 20:41:32 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off data_selector -c data_selector " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off data_selector -c data_selector" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_selector.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file data_selector.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 data_selector " "Info: Found entity 1: data_selector" { } { { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "data_selector " "Info: Elaborating entity \"data_selector\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "34 " "Info: Implemented 34 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "18 " "Info: Implemented 18 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "248 " "Info: Peak virtual memory: 248 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sat Mar 05 20:41:32 2022 " "Info: Processing ended: Sat Mar 05 20:41:32 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

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data_selector/db/data_selector.map_bb.cdb Normal file
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data_selector/db/data_selector.map_bb.hdb Normal file
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data_selector/db/data_selector.map_bb.logdb Normal file
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v1

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data_selector/db/data_selector.pre_map.cdb Normal file
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data_selector/db/data_selector.pre_map.hdb Normal file
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data_selector/db/data_selector.rtlv.hdb Normal file
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data_selector/db/data_selector.rtlv_sg.cdb Normal file
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data_selector/db/data_selector.rtlv_sg_swap.cdb Normal file
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data_selector/db/data_selector.sgdiff.cdb Normal file
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data_selector/db/data_selector.sgdiff.hdb Normal file
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data_selector/db/data_selector.sld_design_entry.sci Normal file
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data_selector/db/data_selector.sld_design_entry_dsc.sci Normal file
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data_selector/db/data_selector.syn_hier_info Normal file
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data_selector/db/data_selector.tan.qmsg Normal file
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sat Mar 05 20:41:36 2022 " "Info: Processing started: Sat Mar 05 20:41:36 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off data_selector -c data_selector --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off data_selector -c data_selector --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TPD_RESULT" "b5 Y5 12.694 ns Longest " "Info: Longest tpd from source pin \"b5\" to destination pin \"Y5\" is 12.694 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns b5 1 PIN PIN_45 1 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_45; Fanout = 1; PIN Node = 'b5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { b5 } "NODE_NAME" } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 432 176 344 448 "b5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.147 ns) + CELL(0.624 ns) 7.766 ns inst6 2 COMB LCCOMB_X1_Y9_N26 1 " "Info: 2: + IC(6.147 ns) + CELL(0.624 ns) = 7.766 ns; Loc. = LCCOMB_X1_Y9_N26; Fanout = 1; COMB Node = 'inst6'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.771 ns" { b5 inst6 } "NODE_NAME" } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 128 776 840 176 "inst6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.642 ns) + CELL(3.286 ns) 12.694 ns Y5 3 PIN PIN_208 0 " "Info: 3: + IC(1.642 ns) + CELL(3.286 ns) = 12.694 ns; Loc. = PIN_208; Fanout = 0; PIN Node = 'Y5'" { } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.928 ns" { inst6 Y5 } "NODE_NAME" } } { "data_selector.bdf" "" { Schematic "D:/projects/quartus/data_selector/data_selector.bdf" { { 144 928 1104 160 "Y5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.905 ns ( 38.64 % ) " "Info: Total cell delay = 4.905 ns ( 38.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "7.789 ns ( 61.36 % ) " "Info: Total interconnect delay = 7.789 ns ( 61.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "12.694 ns" { b5 inst6 Y5 } "NODE_NAME" } } { "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "12.694 ns" { b5 {} b5~combout {} inst6 {} Y5 {} } { 0.000ns 0.000ns 6.147ns 1.642ns } { 0.000ns 0.995ns 0.624ns 3.286ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sat Mar 05 20:41:36 2022 " "Info: Processing ended: Sat Mar 05 20:41:36 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

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data_selector/db/data_selector.tis_db_list.ddb Normal file
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data_selector/db/data_selector.tmw_info Normal file
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start_full_compilation:s:00:00:05
start_analysis_synthesis:s:00:00:01-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:02-start_full_compilation
start_assembler:s:00:00:01-start_full_compilation
start_timing_analyzer:s:00:00:01-start_full_compilation

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data_selector/incremental_db/README Normal file
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This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.

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data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.atm Normal file
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data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.dfp Normal file
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data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.hdbx Normal file
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data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.kpt Normal file
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<kpt_db name="root_partition" kpt_version="1.1">
<key_points_set type="reference" hier_sep="|">
</key_points_set>
<key_points_set type="transition" hier_sep="|">
</key_points_set>
<key_points_set type="transformed" hier_sep="|">
</key_points_set>
<transformations_set hier_sep="|">
</transformations_set>
</kpt_db>

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data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.logdb Normal file
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v1

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data_selector/incremental_db/compiled_partitions/data_selector.root_partition.cmp.rcf Normal file
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data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.atm Normal file
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data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.dpi Normal file
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data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.hdbx Normal file
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data_selector/incremental_db/compiled_partitions/data_selector.root_partition.map.kpt Normal file
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<kpt_db name="data_selector.map_bb" kpt_version="1.1">
<key_points_set type="reference" hier_sep="/">
</key_points_set>
<key_points_set type="transition" hier_sep="|">
</key_points_set>
<key_points_set type="transformed" hier_sep="|">
</key_points_set>
<transformations_set hier_sep="|">
</transformations_set>
</kpt_db>