add triple_selector_8b, shifter_8b
此提交包含在：
178
shifter_8b/shifter_8b.tan.rpt
一般檔案
178
shifter_8b/shifter_8b.tan.rpt
一般檔案
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Classic Timing Analyzer report for shifter_8b
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Mon Mar 07 10:37:44 2022
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Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Timing Analyzer Summary
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3. Timing Analyzer Settings
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4. Parallel Compilation
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5. tpd
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6. Timing Analyzer Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2009 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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applicable agreement for further details.
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+-----------------------------------------------------------------------------------------------------------------------+
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; Timing Analyzer Summary ;
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+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
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; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
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+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
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; Worst-case tpd ; N/A ; None ; 13.320 ns ; DM ; Y7 ; -- ; -- ; 0 ;
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; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
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+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
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+--------------------------------------------------------------------------------------------------------------------+
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; Timing Analyzer Settings ;
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+---------------------------------------------------------------------+--------------------+------+----+-------------+
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; Option ; Setting ; From ; To ; Entity Name ;
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+---------------------------------------------------------------------+--------------------+------+----+-------------+
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; Device Name ; EP2C8Q208C8 ; ; ; ;
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; Timing Models ; Final ; ; ; ;
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; Default hold multicycle ; Same as Multicycle ; ; ; ;
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; Cut paths between unrelated clock domains ; On ; ; ; ;
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; Cut off read during write signal paths ; On ; ; ; ;
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; Cut off feedback from I/O pins ; On ; ; ; ;
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; Report Combined Fast/Slow Timing ; Off ; ; ; ;
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; Ignore Clock Settings ; Off ; ; ; ;
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; Analyze latches as synchronous elements ; On ; ; ; ;
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; Enable Recovery/Removal analysis ; Off ; ; ; ;
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; Enable Clock Latency ; Off ; ; ; ;
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; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
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; Minimum Core Junction Temperature ; 0 ; ; ; ;
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; Maximum Core Junction Temperature ; 85 ; ; ; ;
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; Number of source nodes to report per destination node ; 10 ; ; ; ;
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; Number of destination nodes to report ; 10 ; ; ; ;
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; Number of paths to report ; 200 ; ; ; ;
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; Report Minimum Timing Checks ; Off ; ; ; ;
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; Use Fast Timing Models ; Off ; ; ; ;
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; Report IO Paths Separately ; Off ; ; ; ;
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; Perform Multicorner Analysis ; On ; ; ; ;
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; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
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; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
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; Output I/O Timing Endpoint ; Near End ; ; ; ;
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+---------------------------------------------------------------------+--------------------+------+----+-------------+
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+------------------------------------------+
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; Parallel Compilation ;
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+----------------------------+-------------+
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; Processors ; Number ;
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+----------------------------+-------------+
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; Number detected on machine ; 4 ;
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; Maximum allowed ; 4 ;
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; ; ;
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; Average used ; 1.00 ;
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; Maximum used ; 1 ;
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; ; ;
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; Usage by Processor ; % Time Used ;
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; 1 processor ; 100.0% ;
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; 2-4 processors ; 0.0% ;
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+----------------------------+-------------+
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+---------------------------------------------------------+
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; tpd ;
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+-------+-------------------+-----------------+------+----+
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; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
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+-------+-------------------+-----------------+------+----+
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; N/A ; None ; 13.320 ns ; DM ; Y7 ;
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; N/A ; None ; 13.225 ns ; DM ; Y4 ;
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; N/A ; None ; 13.207 ns ; LM ; Y7 ;
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; N/A ; None ; 13.153 ns ; LM ; Y0 ;
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; N/A ; None ; 13.128 ns ; LM ; Y4 ;
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; N/A ; None ; 13.029 ns ; A0 ; Y1 ;
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; N/A ; None ; 13.020 ns ; DM ; Y1 ;
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; N/A ; None ; 12.918 ns ; LM ; Y1 ;
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; N/A ; None ; 12.906 ns ; A4 ; Y4 ;
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; N/A ; None ; 12.900 ns ; DM ; Y2 ;
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; N/A ; None ; 12.874 ns ; A0 ; OF ;
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; N/A ; None ; 12.848 ns ; A0 ; Y0 ;
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; N/A ; None ; 12.834 ns ; DM ; Y0 ;
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; N/A ; None ; 12.817 ns ; L ; Y0 ;
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; N/A ; None ; 12.816 ns ; LM ; Y6 ;
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; N/A ; None ; 12.787 ns ; LM ; Y2 ;
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; N/A ; None ; 12.752 ns ; LM ; Y5 ;
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; N/A ; None ; 12.542 ns ; A7 ; Y7 ;
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; N/A ; None ; 12.524 ns ; DM ; Y3 ;
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; N/A ; None ; 12.450 ns ; LM ; OF ;
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; N/A ; None ; 12.431 ns ; LM ; Y3 ;
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; N/A ; None ; 12.272 ns ; A6 ; Y7 ;
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; N/A ; None ; 12.211 ns ; A5 ; Y6 ;
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; N/A ; None ; 12.184 ns ; A4 ; Y5 ;
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; N/A ; None ; 12.155 ns ; A5 ; Y5 ;
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; N/A ; None ; 12.007 ns ; DM ; Y6 ;
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; N/A ; None ; 11.961 ns ; A5 ; Y4 ;
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; N/A ; None ; 11.952 ns ; DM ; Y5 ;
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; N/A ; None ; 11.780 ns ; A7 ; OF ;
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; N/A ; None ; 11.520 ns ; A4 ; Y3 ;
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; N/A ; None ; 11.436 ns ; A6 ; Y6 ;
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; N/A ; None ; 11.309 ns ; R ; Y7 ;
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; N/A ; None ; 11.123 ns ; A6 ; Y5 ;
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; N/A ; None ; 11.097 ns ; A7 ; Y6 ;
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; N/A ; None ; 8.432 ns ; A1 ; Y1 ;
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; N/A ; None ; 8.391 ns ; A3 ; Y4 ;
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; N/A ; None ; 8.283 ns ; A2 ; Y2 ;
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; N/A ; None ; 8.057 ns ; A1 ; Y2 ;
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; N/A ; None ; 7.922 ns ; A2 ; Y3 ;
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; N/A ; None ; 7.852 ns ; A2 ; Y1 ;
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; N/A ; None ; 7.752 ns ; RM ; OF ;
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; N/A ; None ; 7.697 ns ; A3 ; Y3 ;
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; N/A ; None ; 7.656 ns ; RM ; Y1 ;
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; N/A ; None ; 7.645 ns ; RM ; Y0 ;
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; N/A ; None ; 7.558 ns ; A1 ; Y0 ;
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; N/A ; None ; 7.441 ns ; RM ; Y4 ;
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; N/A ; None ; 7.348 ns ; RM ; Y3 ;
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; N/A ; None ; 7.270 ns ; A3 ; Y2 ;
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; N/A ; None ; 7.067 ns ; RM ; Y5 ;
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; N/A ; None ; 7.062 ns ; RM ; Y6 ;
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; N/A ; None ; 7.054 ns ; RM ; Y2 ;
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; N/A ; None ; 5.826 ns ; RM ; Y7 ;
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+-------+-------------------+-----------------+------+----+
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+--------------------------+
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; Timing Analyzer Messages ;
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+--------------------------+
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Info: *******************************************************************
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Info: Running Quartus II Classic Timing Analyzer
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Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
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Info: Processing started: Mon Mar 07 10:37:44 2022
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Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off shifter_8b -c shifter_8b --timing_analysis_only
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Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
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Info: Longest tpd from source pin "DM" to destination pin "Y7" is 13.320 ns
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Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_35; Fanout = 8; PIN Node = 'DM'
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Info: 2: + IC(6.057 ns) + CELL(0.650 ns) = 7.692 ns; Loc. = LCCOMB_X1_Y14_N20; Fanout = 1; COMB Node = 'triple_selector_8b:inst|inst31~0'
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Info: 3: + IC(1.286 ns) + CELL(0.319 ns) = 9.297 ns; Loc. = LCCOMB_X1_Y9_N16; Fanout = 1; COMB Node = 'triple_selector_8b:inst|inst31'
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Info: 4: + IC(0.927 ns) + CELL(3.096 ns) = 13.320 ns; Loc. = PIN_33; Fanout = 0; PIN Node = 'Y7'
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Info: Total cell delay = 5.050 ns ( 37.91 % )
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Info: Total interconnect delay = 8.270 ns ( 62.09 % )
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Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
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Info: Peak virtual memory: 212 megabytes
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Info: Processing ended: Mon Mar 07 10:37:44 2022
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Info: Elapsed time: 00:00:00
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Info: Total CPU time (on all processors): 00:00:00
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